Dirk Mueller
0ed966f036
- drop: valgrind-3.9.0-merge.patches.from.Paul.McKenney.patch, valgrind-3.9.0-ppc64le-abiv2.patch - add: VEX-r2803.diff, VEX-r2808.diff, VEX-r2816.diff VEX-r2904.diff, VEX-r2910.diff, VEX-r2914.diff, VEX-r2915.diff, VEX-r2916.diff, r13767.diff, r13770.diff, r14184.diff, r14238.diff, r14239.diff, r14240.diff, r14246.diff OBS-URL: https://build.opensuse.org/package/show/devel:tools/valgrind?expand=0&rev=114
25959 lines
1.7 MiB
25959 lines
1.7 MiB
------------------------------------------------------------------------
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r14240 | carll | 2014-08-08 01:49:27 +0200 (Fr, 08. Aug 2014) | 18 Zeilen
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This commit is for Bugzilla 334836. The Bugzilla contains patch 3 of 3
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to add PPC64 LE support. The other two patches can be found in Bugzillas
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334384 and 334834. Note, there are no VEX changes in this patch.
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PP64 Little Endian test case fixes.
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This patch adds new LE and BE expect files where needed. In other
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cases, the test was fixed to run correctly on LE and BE using based on
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testing to see which platform is being used.
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Where practical, the test cases have been changed so that the output
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produced for BE and LE will be identical. The test cases that require
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a major rewrite to make the output identical for BE and LE simply
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had an additional expect file added.
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Signed-off-by: Carl Love <carll@us.ibm.com>
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------------------------------------------------------------------------
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Index: helgrind/tests/tc11_XCHG.c
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===================================================================
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--- helgrind/tests/tc11_XCHG.c.orig
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+++ helgrind/tests/tc11_XCHG.c
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@@ -14,7 +14,7 @@
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#undef PLAT_x86_linux
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#undef PLAT_amd64_linux
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#undef PLAT_ppc32_linux
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-#undef PLAT_ppc64_linux
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+#undef PLAT_ppc64be_linux
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#undef PLAT_arm_linux
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#undef PLAT_s390x_linux
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#undef PLAT_mips32_linux
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Index: coregrind/launcher-darwin.c
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===================================================================
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--- coregrind/launcher-darwin.c.orig
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+++ coregrind/launcher-darwin.c
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@@ -64,7 +64,6 @@ static struct {
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{ CPU_TYPE_ARM, "arm", "arm" },
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{ CPU_TYPE_POWERPC, "ppc", "ppc32" },
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{ CPU_TYPE_POWERPC64BE, "ppc64be", "ppc64be" },
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- { CPU_TYPE_POWERPC64LE, "ppc64le", "ppc64le" },
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};
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static int valid_archs_count = sizeof(valid_archs)/sizeof(valid_archs[0]);
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Index: none/tests/ppc64/lsw.vgtest
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===================================================================
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--- none/tests/ppc64/lsw.vgtest.orig
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+++ none/tests/ppc64/lsw.vgtest
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@@ -1 +1,2 @@
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+prereq: ../../../tests/is_ppc64_BE
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prog: lsw
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Index: none/tests/ppc64/jm-vmx.stdout.exp-LE
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===================================================================
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--- /dev/null
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+++ none/tests/ppc64/jm-vmx.stdout.exp-LE
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@@ -0,0 +1,3614 @@
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+PPC altivec integer arith insns with three args:
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+ vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
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+ vmhaddshs: => 010403160538076a09ad0c000f970f9a (00000000)
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+ vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
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+ vmhaddshs: => f1f4f406f628f85afa9dfcf00087008a (00000000)
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+ vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
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+ vmhaddshs: => 00e502bb04a10697089d0ab30df00df2 (00000000)
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+ vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
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+ vmhaddshs: => f1d5f3abf591f787f98dfba3fee0fee2 (00000000)
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+ vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
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+ vmhaddshs: => 00e502bb04a10697089d0ab30df00df2 (00000000)
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+ vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
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+ vmhaddshs: => f1d5f3abf591f787f98dfba3fee0fee2 (00000000)
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+ vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
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+ vmhaddshs: => 028d042605cf078909520b2c0e0f0e11 (00000000)
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+ vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
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+ vmhaddshs: => f37df516f6bff879fa42fc1cfeffff01 (00000000)
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+
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+ vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
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+ vmhraddshs: => 010403160538076b09ad0c000f980f9a (00000000)
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+ vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
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+ vmhraddshs: => f1f4f406f628f85bfa9dfcf00088008a (00000000)
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+ vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
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+ vmhraddshs: => 00e602bb04a10697089d0ab30df10df3 (00000000)
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+ vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
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+ vmhraddshs: => f1d6f3abf591f787f98dfba3fee1fee3 (00000000)
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+ vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
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+ vmhraddshs: => 00e602bb04a10697089d0ab30df10df3 (00000000)
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+ vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
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+ vmhraddshs: => f1d6f3abf591f787f98dfba3fee1fee3 (00000000)
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+ vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
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+ vmhraddshs: => 028d042605d0078909530b2c0e0f0e11 (00000000)
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+ vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
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+ vmhraddshs: => f37df516f6c0f879fa43fc1cfeffff01 (00000000)
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+
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+ vmladduhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
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+ vmladduhm: => 05061b14412a7748bd6e139c7ab6b2f0 (00000000)
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+ vmladduhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
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+ vmladduhm: => f5f60c04321a6838ae5e048c6ba6a3e0 (00000000)
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+ vmladduhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
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+ vmladduhm: => d6e6aed496ca8ec896ceaedcd6e6f100 (00000000)
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+ vmladduhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
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+ vmladduhm: => c7d69fc487ba7fb887be9fccc7d6e1f0 (00000000)
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+ vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
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+ vmladduhm: => d6e6aed496ca8ec896ceaedcd6e6f100 (00000000)
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+ vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
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+ vmladduhm: => c7d69fc487ba7fb887be9fccc7d6e1f0 (00000000)
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+ vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
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+ vmladduhm: => 89c62394cd6a8748512e2b1c14161010 (00000000)
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+ vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
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+ vmladduhm: => 7ab61484be5a7838421e1c0c05060100 (00000000)
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+
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+ vmsumubm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
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+ vmsumubm: => 01020322050607b6090a0cca0e0d1121 (00000000)
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+ vmsumubm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
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+ vmsumubm: => f1f2f412f5f6f8a6f9fafdbafefe0211 (00000000)
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+ vmsumubm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
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+ vmsumubm: => 01020c8205062016090a342a0e0d45a1 (00000000)
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+ vmsumubm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
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+ vmsumubm: => f1f2fd72f5f71106f9fb251afefe3691 (00000000)
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+ vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
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+ vmsumubm: => 01020c8205062016090a342a0e0d45a1 (00000000)
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+ vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
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+ vmsumubm: => f1f2fd72f5f71106f9fb251afefe3691 (00000000)
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+ vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
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+ vmsumubm: => 010599e20509bc76090ddf8a0e10fe21 (00000000)
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+ vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
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+ vmsumubm: => f1f68ad2f5faad66f9fed07aff01ef11 (00000000)
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+
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+ vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
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+ vmsumuhm: => 010c1f180550b36c09d5c8000f981f99 (00000000)
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+ vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
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+ vmsumuhm: => f1fd1008f641a45cfac6b8f000891089 (00000000)
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+ vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
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+ vmsumuhm: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000)
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+ vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
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+ vmsumuhm: => f5c675a8019a117c0dae2d901afdaac9 (00000000)
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+ vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
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+ vmsumuhm: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000)
|
|
+ vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
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+ vmsumuhm: => f5c675a8019a117c0dae2d901afdaac9 (00000000)
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+ vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
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+ vmsumuhm: => ce24ac58e1874facf52a73400a071619 (00000000)
|
|
+ vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmsumuhm: => bf159d48d278409ce61b6430faf80709 (00000000)
|
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+
|
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+ vmsumshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmsumshs: => 010c1f180550b36c09d5c8000f981f99 (00000000)
|
|
+ vmsumshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmsumshs: => f1fd1008f641a45cfac6b8f000891089 (00000000)
|
|
+ vmsumshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmsumshs: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000)
|
|
+ vmsumshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmsumshs: => f1c075a8f58c117cf9982d90fee1aac9 (00000000)
|
|
+ vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmsumshs: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000)
|
|
+ vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmsumshs: => f1c075a8f58c117cf9982d90fee1aac9 (00000000)
|
|
+ vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmsumshs: => 0258ac5805ab4fac093e73400e0f1619 (00000000)
|
|
+ vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmsumshs: => f3499d48f69c409cfa2f6430ff000709 (00000000)
|
|
+
|
|
+ vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmsumuhs: => 010c1f180550b36c09d5c8000f981f99 (00000000)
|
|
+ vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmsumuhs: => f1fd1008f641a45cfac6b8f0ffffffff (00000000)
|
|
+ vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmsumuhs: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000)
|
|
+ vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmsumuhs: => f5c675a8ffffffffffffffffffffffff (00000000)
|
|
+ vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmsumuhs: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000)
|
|
+ vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmsumuhs: => f5c675a8ffffffffffffffffffffffff (00000000)
|
|
+ vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmsumuhs: => ffffffffffffffffffffffffffffffff (00000000)
|
|
+ vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmsumuhs: => ffffffffffffffffffffffffffffffff (00000000)
|
|
+
|
|
+ vmsummbm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmsummbm: => 01020322050607b6090a0cca0e0d1121 (00000000)
|
|
+ vmsummbm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmsummbm: => f1f2f412f5f6f8a6f9fafdbafefe0211 (00000000)
|
|
+ vmsummbm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmsummbm: => 01020c8205062016090a342a0e0d45a1 (00000000)
|
|
+ vmsummbm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmsummbm: => f1f2fd72f5f71106f9fb251afefe3691 (00000000)
|
|
+ vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmsummbm: => 0102028205060616090a0a2a0e0d0da1 (00000000)
|
|
+ vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmsummbm: => f1f2f372f5f6f706f9fafb1afefdfe91 (00000000)
|
|
+ vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmsummbm: => 0101cfe20505e2760909f58a0e0d0621 (00000000)
|
|
+ vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmsummbm: => f1f2c0d2f5f6d366f9fae67afefdf711 (00000000)
|
|
+
|
|
+ vmsumshm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmsumshm: => 010c1f180550b36c09d5c8000f981f99 (00000000)
|
|
+ vmsumshm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmsumshm: => f1fd1008f641a45cfac6b8f000891089 (00000000)
|
|
+ vmsumshm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmsumshm: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000)
|
|
+ vmsumshm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmsumshm: => f1c075a8f58c117cf9982d90fee1aac9 (00000000)
|
|
+ vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmsumshm: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000)
|
|
+ vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmsumshm: => f1c075a8f58c117cf9982d90fee1aac9 (00000000)
|
|
+ vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmsumshm: => 0258ac5805ab4fac093e73400e0f1619 (00000000)
|
|
+ vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmsumshm: => f3499d48f69c409cfa2f6430ff000709 (00000000)
|
|
+
|
|
+PPC altivec integer logical insns with three args:
|
|
+ vperm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vperm: => 0d0e0f090a0b0c050607080103020304 (00000000)
|
|
+ vperm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vperm: => 0d0e0f090a0b0c050607080103020304 (00000000)
|
|
+ vperm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vperm: => 0d0e0f090a0b0c050607080103020304 (00000000)
|
|
+ vperm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vperm: => fdfefff9fafbfcf5f6f7f8f1f3f2f3f4 (00000000)
|
|
+ vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vperm: => fdfefff9fafbfcf5f6f7f8f1f3f2f3f4 (00000000)
|
|
+ vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vperm: => 0d0e0f090a0b0c050607080103020304 (00000000)
|
|
+ vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vperm: => fdfefff9fafbfcf5f6f7f8f1f3f2f3f4 (00000000)
|
|
+ vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vperm: => fdfefff9fafbfcf5f6f7f8f1f3f2f3f4 (00000000)
|
|
+
|
|
+ vsel: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000)
|
|
+ vsel: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000)
|
|
+ vsel: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000)
|
|
+ vsel: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000)
|
|
+ vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000)
|
|
+ vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000)
|
|
+ vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000)
|
|
+ vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000)
|
|
+
|
|
+PPC altivec integer arith insns with two args:
|
|
+ vaddubm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vaddubm: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
|
|
+ vaddubm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vaddubm: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000)
|
|
+ vaddubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vaddubm: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000)
|
|
+ vaddubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vaddubm: => e2e4e6e8 eaeceef0 f2f4f6f8 fcfafcfe (00000000)
|
|
+
|
|
+ vadduhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vadduhm: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
|
|
+ vadduhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vadduhm: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000)
|
|
+ vadduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vadduhm: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000)
|
|
+ vadduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vadduhm: => e3e4e7e8 ebeceff0 f3f4f7f8 fdfafdfe (00000000)
|
|
+
|
|
+ vadduwm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vadduwm: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
|
|
+ vadduwm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vadduwm: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000)
|
|
+ vadduwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vadduwm: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000)
|
|
+ vadduwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vadduwm: => e3e5e7e8 ebedeff0 f3f5f7f8 fdfbfdfe (00000000)
|
|
+
|
|
+ vaddubs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vaddubs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
|
|
+ vaddubs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vaddubs: => f2f4f6f8 fafcfeff ffffffff ffffffff (00000000)
|
|
+ vaddubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vaddubs: => f2f4f6f8 fafcfeff ffffffff ffffffff (00000000)
|
|
+ vaddubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vaddubs: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+
|
|
+ vadduhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vadduhs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
|
|
+ vadduhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vadduhs: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000)
|
|
+ vadduhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vadduhs: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000)
|
|
+ vadduhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vadduhs: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+
|
|
+ vadduws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vadduws: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
|
|
+ vadduws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vadduws: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000)
|
|
+ vadduws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vadduws: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000)
|
|
+ vadduws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vadduws: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+
|
|
+ vaddsbs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vaddsbs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
|
|
+ vaddsbs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vaddsbs: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000)
|
|
+ vaddsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vaddsbs: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000)
|
|
+ vaddsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vaddsbs: => e2e4e6e8 eaeceef0 f2f4f6f8 fcfafcfe (00000000)
|
|
+
|
|
+ vaddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vaddshs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
|
|
+ vaddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vaddshs: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000)
|
|
+ vaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vaddshs: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000)
|
|
+ vaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vaddshs: => e3e4e7e8 ebeceff0 f3f4f7f8 fdfafdfe (00000000)
|
|
+
|
|
+ vaddsws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vaddsws: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
|
|
+ vaddsws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vaddsws: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000)
|
|
+ vaddsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vaddsws: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000)
|
|
+ vaddsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vaddsws: => e3e5e7e8 ebedeff0 f3f5f7f8 fdfbfdfe (00000000)
|
|
+
|
|
+ vaddcuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vaddcuw: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vaddcuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vaddcuw: => 00000000 00000000 00000001 00000001 (00000000)
|
|
+ vaddcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vaddcuw: => 00000000 00000000 00000001 00000001 (00000000)
|
|
+ vaddcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vaddcuw: => 00000001 00000001 00000001 00000001 (00000000)
|
|
+
|
|
+ vsububm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsububm: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vsububm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsububm: => 10101010 10101010 10101010 10101010 (00000000)
|
|
+ vsububm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsububm: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
|
|
+ vsububm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsububm: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vsubuhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsubuhm: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vsubuhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsubuhm: => 0f100f10 0f100f10 0f100f10 0f100f10 (00000000)
|
|
+ vsubuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsubuhm: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
|
|
+ vsubuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsubuhm: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vsubuwm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsubuwm: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vsubuwm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsubuwm: => 0f0f0f10 0f0f0f10 0f0f0f10 0f0f0f10 (00000000)
|
|
+ vsubuwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsubuwm: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
|
|
+ vsubuwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsubuwm: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vsububs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsububs: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vsububs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsububs: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vsububs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsububs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
|
|
+ vsububs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsububs: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vsubuhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsubuhs: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vsubuhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsubuhs: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vsubuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsubuhs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
|
|
+ vsubuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsubuhs: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vsubuws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsubuws: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vsubuws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsubuws: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vsubuws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsubuws: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
|
|
+ vsubuws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsubuws: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vsubsbs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsubsbs: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vsubsbs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsubsbs: => 10101010 10101010 10101010 10101010 (00000000)
|
|
+ vsubsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsubsbs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
|
|
+ vsubsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsubsbs: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vsubshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsubshs: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vsubshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsubshs: => 0f100f10 0f100f10 0f100f10 0f100f10 (00000000)
|
|
+ vsubshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsubshs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
|
|
+ vsubshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsubshs: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vsubsws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsubsws: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vsubsws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsubsws: => 0f0f0f10 0f0f0f10 0f0f0f10 0f0f0f10 (00000000)
|
|
+ vsubsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsubsws: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
|
|
+ vsubsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsubsws: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vsubcuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsubcuw: => 00000001 00000001 00000001 00000001 (00000000)
|
|
+ vsubcuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsubcuw: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vsubcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsubcuw: => 00000001 00000001 00000001 00000001 (00000000)
|
|
+ vsubcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsubcuw: => 00000001 00000001 00000001 00000001 (00000000)
|
|
+
|
|
+ vmuloub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmuloub: => 00040010 00240040 00640090 00a900e1 (00000000)
|
|
+ vmuloub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmuloub: => 01e403d0 05c407c0 09c40bd0 0cd90ef1 (00000000)
|
|
+ vmuloub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmuloub: => 01e403d0 05c407c0 09c40bd0 0cd90ef1 (00000000)
|
|
+ vmuloub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmuloub: => e4c4e890 ec64f040 f424f810 fa09fe01 (00000000)
|
|
+
|
|
+ vmulouh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmulouh: => 00091810 00317040 007a0890 00c5a4e1 (00000000)
|
|
+ vmulouh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmulouh: => 02dfabd0 06cf87c0 0adfa3d0 0e00e2f1 (00000000)
|
|
+ vmulouh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmulouh: => 02dfabd0 06cf87c0 0adfa3d0 0e00e2f1 (00000000)
|
|
+ vmulouh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmulouh: => e8792090 f0308040 f8082010 fdff0201 (00000000)
|
|
+
|
|
+ vmulosb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmulosb: => 00040010 00240040 00640090 00a900e1 (00000000)
|
|
+ vmulosb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmulosb: => ffe4ffd0 ffc4ffc0 ffc4ffd0 ffd9fff1 (00000000)
|
|
+ vmulosb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmulosb: => ffe4ffd0 ffc4ffc0 ffc4ffd0 ffd9fff1 (00000000)
|
|
+ vmulosb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmulosb: => 00c40090 00640040 00240010 00090001 (00000000)
|
|
+
|
|
+ vmulosh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmulosh: => 00091810 00317040 007a0890 00c5a4e1 (00000000)
|
|
+ vmulosh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmulosh: => ffdbabd0 ffc787c0 ffd3a3d0 fff1e2f1 (00000000)
|
|
+ vmulosh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmulosh: => ffdbabd0 ffc787c0 ffd3a3d0 fff1e2f1 (00000000)
|
|
+ vmulosh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmulosh: => 00912090 00408040 00102010 00010201 (00000000)
|
|
+
|
|
+ vmuleub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmuleub: => 00010009 00190031 00510079 00c400c4 (00000000)
|
|
+ vmuleub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmuleub: => 00f102d9 04c906c1 08c10ac9 0de40de4 (00000000)
|
|
+ vmuleub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmuleub: => 00f102d9 04c906c1 08c10ac9 0de40de4 (00000000)
|
|
+ vmuleub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmuleub: => e2e1e6a9 ea79ee51 f231f619 fc04fc04 (00000000)
|
|
+
|
|
+ vmuleuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmuleuh: => 00010404 00193c24 0051b464 00c56ca9 (00000000)
|
|
+ vmuleuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmuleuh: => 00f3d5e4 04d391c4 08d38dc4 0dfec8d9 (00000000)
|
|
+ vmuleuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmuleuh: => 00f3d5e4 04d391c4 08d38dc4 0dfec8d9 (00000000)
|
|
+ vmuleuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmuleuh: => e4a988c4 ec50c864 f4184824 fdfb0609 (00000000)
|
|
+
|
|
+ vmulesb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmulesb: => 00010009 00190031 00510079 00c400c4 (00000000)
|
|
+ vmulesb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmulesb: => fff1ffd9 ffc9ffc1 ffc1ffc9 ffe4ffe4 (00000000)
|
|
+ vmulesb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmulesb: => fff1ffd9 ffc9ffc1 ffc1ffc9 ffe4ffe4 (00000000)
|
|
+ vmulesb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmulesb: => 00e100a9 00790051 00310019 00040004 (00000000)
|
|
+
|
|
+ vmulesh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmulesh: => 00010404 00193c24 0051b464 00c56ca9 (00000000)
|
|
+ vmulesh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmulesh: => fff1d5e4 ffcd91c4 ffc98dc4 fff1c8d9 (00000000)
|
|
+ vmulesh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmulesh: => fff1d5e4 ffcd91c4 ffc98dc4 fff1c8d9 (00000000)
|
|
+ vmulesh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmulesh: => 00c588c4 0064c864 00244824 00010609 (00000000)
|
|
+
|
|
+ vsumsws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsumsws: => 1e21262b 00000000 00000000 00000000 (00000000)
|
|
+ vsumsws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsumsws: => 0f12171b 00000000 00000000 00000000 (00000000)
|
|
+ vsumsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsumsws: => e1e4e9eb 00000000 00000000 00000000 (00000000)
|
|
+ vsumsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsumsws: => d2d5dadb 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vsum2sws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsum2sws: => 070a0d10 00000000 20212427 00000000 (00000000)
|
|
+ vsum2sws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsum2sws: => f7fafe00 00000000 11121517 00000000 (00000000)
|
|
+ vsum2sws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsum2sws: => e8ebeef0 00000000 02030607 00000000 (00000000)
|
|
+ vsum2sws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsum2sws: => d9dcdfe0 00000000 f2f3f6f7 00000000 (00000000)
|
|
+
|
|
+ vsum4ubs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsum4ubs: => 0102030e 05060722 090a0b36 0e0d0e47 (00000000)
|
|
+ vsum4ubs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsum4ubs: => f1f2f3fe f5f6f812 f9fafc26 fefdff37 (00000000)
|
|
+ vsum4ubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsum4ubs: => 010206ce 05060ae2 090a0ef6 0e0d1207 (00000000)
|
|
+ vsum4ubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsum4ubs: => f1f2f7be f5f6fbd2 f9faffe6 fefe02f7 (00000000)
|
|
+
|
|
+ vsum4sbs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsum4sbs: => 0102030e 05060722 090a0b36 0e0d0e47 (00000000)
|
|
+ vsum4sbs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsum4sbs: => f1f2f3fe f5f6f812 f9fafc26 fefdff37 (00000000)
|
|
+ vsum4sbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsum4sbs: => 010202ce 050606e2 090a0af6 0e0d0e07 (00000000)
|
|
+ vsum4sbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsum4sbs: => f1f2f3be f5f6f7d2 f9fafbe6 fefdfef7 (00000000)
|
|
+
|
|
+ vsum4shs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsum4shs: => 0102070a 05061316 090a1f22 0e0d2a2b (00000000)
|
|
+ vsum4shs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsum4shs: => f1f2f7fa f5f70406 f9fb1012 fefe1b1b (00000000)
|
|
+ vsum4shs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsum4shs: => 0101e8ea 0505f4f6 090a0102 0e0d0c0b (00000000)
|
|
+ vsum4shs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsum4shs: => f1f2d9da f5f6e5e6 f9faf1f2 fefdfcfb (00000000)
|
|
+
|
|
+ vavgub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vavgub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vavgub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vavgub: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
|
|
+ vavgub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vavgub: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
|
|
+ vavgub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vavgub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+ vavguh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vavguh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vavguh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vavguh: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
|
|
+ vavguh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vavguh: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
|
|
+ vavguh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vavguh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+ vavguw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vavguw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vavguw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vavguw: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
|
|
+ vavguw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vavguw: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
|
|
+ vavguw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vavguw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+ vavgsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vavgsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vavgsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vavgsb: => f9fafbfc fdfeff00 01020304 06050607 (00000000)
|
|
+ vavgsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vavgsb: => f9fafbfc fdfeff00 01020304 06050607 (00000000)
|
|
+ vavgsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vavgsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+ vavgsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vavgsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vavgsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vavgsh: => f97afb7c fd7eff80 01820384 06850687 (00000000)
|
|
+ vavgsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vavgsh: => f97afb7c fd7eff80 01820384 06850687 (00000000)
|
|
+ vavgsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vavgsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+ vavgsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vavgsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vavgsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vavgsw: => f97a7b7c fd7e7f80 01828384 06858687 (00000000)
|
|
+ vavgsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vavgsw: => f97a7b7c fd7e7f80 01828384 06858687 (00000000)
|
|
+ vavgsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vavgsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+ vmaxub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmaxub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vmaxub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmaxub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ vmaxub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmaxub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ vmaxub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmaxub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+ vmaxuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmaxuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vmaxuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmaxuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ vmaxuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmaxuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ vmaxuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmaxuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+ vmaxuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmaxuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vmaxuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmaxuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ vmaxuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmaxuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ vmaxuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmaxuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+ vmaxsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmaxsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vmaxsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmaxsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vmaxsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmaxsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vmaxsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmaxsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+ vmaxsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmaxsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vmaxsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmaxsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vmaxsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmaxsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vmaxsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmaxsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+ vmaxsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmaxsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vmaxsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmaxsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vmaxsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmaxsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vmaxsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmaxsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+ vminub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vminub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vminub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vminub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vminub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vminub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vminub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vminub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+ vminuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vminuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vminuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vminuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vminuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vminuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vminuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vminuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+ vminuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vminuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vminuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vminuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vminuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vminuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vminuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vminuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+ vminsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vminsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vminsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vminsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ vminsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vminsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ vminsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vminsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+ vminsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vminsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vminsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vminsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ vminsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vminsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ vminsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vminsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+ vminsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vminsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vminsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vminsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ vminsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vminsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ vminsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vminsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+PPC altivec integer logical insns with two args:
|
|
+ vand: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vand: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vand: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vand: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vand: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vand: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vand: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vand: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+ vor: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vor: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vor: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vor: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ vor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vor: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ vor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vor: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+ vxor: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vxor: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vxor: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vxor: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
|
|
+ vxor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vxor: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
|
|
+ vxor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vxor: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vandc: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vandc: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vandc: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vandc: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vandc: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vandc: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
|
|
+ vandc: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vandc: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vnor: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vnor: => fefdfcfb faf9f8f7 f6f5f4f3 f1f2f1f0 (00000000)
|
|
+ vnor: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vnor: => 0e0d0c0b 0a090807 06050403 01020100 (00000000)
|
|
+ vnor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vnor: => 0e0d0c0b 0a090807 06050403 01020100 (00000000)
|
|
+ vnor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vnor: => 0e0d0c0b 0a090807 06050403 01020100 (00000000)
|
|
+
|
|
+ vrlb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vrlb: => 02081840 a0818308 122858c0 83a18387 (00000000)
|
|
+ vrlb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vrlb: => 02081840 a0818308 122858c0 83a18387 (00000000)
|
|
+ vrlb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vrlb: => e3cb9f4f bebdfbf8 f3ebdfcf bfbfbfff (00000000)
|
|
+ vrlb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vrlb: => e3cb9f4f bebdfbf8 f3ebdfcf bfbfbfff (00000000)
|
|
+
|
|
+ vrlh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vrlh: => 04083040 41810807 2824c0b0 a1c18707 (00000000)
|
|
+ vrlh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vrlh: => 04083040 41810807 2824c0b0 a1c18707 (00000000)
|
|
+ vrlh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vrlh: => c7cb3f4f 7dbdf8f7 ebe7cfbf bfdfff7f (00000000)
|
|
+ vrlh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vrlh: => c7cb3f4f 7dbdf8f7 ebe7cfbf bfdfff7f (00000000)
|
|
+
|
|
+ vrlw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vrlw: => 10203040 06070805 a0b0c090 87078706 (00000000)
|
|
+ vrlw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vrlw: => 30401020 08050607 c090a0b0 87068707 (00000000)
|
|
+ vrlw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vrlw: => 1f2f3f4f f6f7f8f5 afbfcf9f ff7fff7e (00000000)
|
|
+ vrlw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vrlw: => 3f4f1f2f f8f5f6f7 cf9fafbf ff7eff7f (00000000)
|
|
+
|
|
+ vslb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vslb: => 02081840 a0808008 122858c0 80a08080 (00000000)
|
|
+ vslb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vslb: => 02081840 a0808008 122858c0 80a08080 (00000000)
|
|
+ vslb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vslb: => e2c89840 a08080f8 f2e8d8c0 80a08080 (00000000)
|
|
+ vslb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vslb: => e2c89840 a08080f8 f2e8d8c0 80a08080 (00000000)
|
|
+
|
|
+ vslh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vslh: => 04083040 41800800 2800c000 a0008000 (00000000)
|
|
+ vslh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vslh: => 04083040 41800800 2800c000 a0008000 (00000000)
|
|
+ vslh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vslh: => c7c83f40 7d80f800 e800c000 a0008000 (00000000)
|
|
+ vslh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vslh: => c7c83f40 7d80f800 e800c000 a0008000 (00000000)
|
|
+
|
|
+ vslw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vslw: => 10203040 06070800 a0b0c000 87078000 (00000000)
|
|
+ vslw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vslw: => 30400000 08000000 c0000000 80000000 (00000000)
|
|
+ vslw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vslw: => 1f2f3f40 f6f7f800 afbfc000 ff7f8000 (00000000)
|
|
+ vslw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vslw: => 3f400000 f8000000 c0000000 80000000 (00000000)
|
|
+
|
|
+ vsrb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsrb: => 00000000 00000008 04020100 00000000 (00000000)
|
|
+ vsrb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsrb: => 00000000 00000008 04020100 00000000 (00000000)
|
|
+ vsrb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsrb: => 783c1e0f 070301f8 7c3e1f0f 03070301 (00000000)
|
|
+ vsrb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsrb: => 783c1e0f 070301f8 7c3e1f0f 03070301 (00000000)
|
|
+
|
|
+ vsrh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsrh: => 00400030 00140007 00020000 00000000 (00000000)
|
|
+ vsrh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsrh: => 00400030 00140007 00020000 00000000 (00000000)
|
|
+ vsrh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsrh: => 3c7c0f3f 03d700f7 003e000f 00070001 (00000000)
|
|
+ vsrh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsrh: => 3c7c0f3f 03d700f7 003e000f 00070001 (00000000)
|
|
+
|
|
+ vsrw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsrw: => 00102030 00050607 000090a0 00001c1a (00000000)
|
|
+ vsrw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsrw: => 00000010 00000005 00000000 00000000 (00000000)
|
|
+ vsrw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsrw: => 0f1f2f3f 00f5f6f7 000f9faf 0001fdfb (00000000)
|
|
+ vsrw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsrw: => 00000f1f 000000f5 0000000f 00000001 (00000000)
|
|
+
|
|
+ vsrab: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsrab: => 00000000 00000008 04020100 00000000 (00000000)
|
|
+ vsrab: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsrab: => 00000000 00000008 04020100 00000000 (00000000)
|
|
+ vsrab: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsrab: => f8fcfeff fffffff8 fcfeffff ffffffff (00000000)
|
|
+ vsrab: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsrab: => f8fcfeff fffffff8 fcfeffff ffffffff (00000000)
|
|
+
|
|
+ vsrah: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsrah: => 00400030 00140007 00020000 00000000 (00000000)
|
|
+ vsrah: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsrah: => 00400030 00140007 00020000 00000000 (00000000)
|
|
+ vsrah: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsrah: => fc7cff3f ffd7fff7 fffeffff ffffffff (00000000)
|
|
+ vsrah: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsrah: => fc7cff3f ffd7fff7 fffeffff ffffffff (00000000)
|
|
+
|
|
+ vsraw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsraw: => 00102030 00050607 000090a0 00001c1a (00000000)
|
|
+ vsraw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsraw: => 00000010 00000005 00000000 00000000 (00000000)
|
|
+ vsraw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsraw: => ff1f2f3f fff5f6f7 ffff9faf fffffdfb (00000000)
|
|
+ vsraw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsraw: => ffffff1f fffffff5 ffffffff ffffffff (00000000)
|
|
+
|
|
+ vpkuhum: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vpkuhum: => 06080204 0d0f0a0c 06080204 0d0f0a0c (00000000)
|
|
+ vpkuhum: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vpkuhum: => f6f8f2f4 fdfffafc 06080204 0d0f0a0c (00000000)
|
|
+ vpkuhum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vpkuhum: => 06080204 0d0f0a0c f6f8f2f4 fdfffafc (00000000)
|
|
+ vpkuhum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vpkuhum: => f6f8f2f4 fdfffafc f6f8f2f4 fdfffafc (00000000)
|
|
+
|
|
+ vpkuwum: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vpkuwum: => 07080304 0e0f0b0c 07080304 0e0f0b0c (00000000)
|
|
+ vpkuwum: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vpkuwum: => f7f8f3f4 fefffbfc 07080304 0e0f0b0c (00000000)
|
|
+ vpkuwum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vpkuwum: => 07080304 0e0f0b0c f7f8f3f4 fefffbfc (00000000)
|
|
+ vpkuwum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vpkuwum: => f7f8f3f4 fefffbfc f7f8f3f4 fefffbfc (00000000)
|
|
+
|
|
+ vpkuhus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vpkuhus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vpkuhus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vpkuhus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+
|
|
+ vpkuwus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vpkuwus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vpkuwus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vpkuwus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+
|
|
+ vpkshus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vpkshus: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vpkshus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vpkshus: => 00000000 00000000 ffffffff ffffffff (00000000)
|
|
+ vpkshus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vpkshus: => ffffffff ffffffff 00000000 00000000 (00000000)
|
|
+ vpkshus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vpkshus: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vpkswus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vpkswus: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vpkswus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vpkswus: => 00000000 00000000 ffffffff ffffffff (00000000)
|
|
+ vpkswus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vpkswus: => ffffffff ffffffff 00000000 00000000 (00000000)
|
|
+ vpkswus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vpkswus: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vpkshss: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vpkshss: => 7f7f7f7f 7f7f7f7f 7f7f7f7f 7f7f7f7f (00000000)
|
|
+ vpkshss: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vpkshss: => 80808080 80808080 7f7f7f7f 7f7f7f7f (00000000)
|
|
+ vpkshss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vpkshss: => 7f7f7f7f 7f7f7f7f 80808080 80808080 (00000000)
|
|
+ vpkshss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vpkshss: => 80808080 80808080 80808080 80808080 (00000000)
|
|
+
|
|
+ vpkswss: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vpkswss: => 7fff7fff 7fff7fff 7fff7fff 7fff7fff (00000000)
|
|
+ vpkswss: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vpkswss: => 80008000 80008000 7fff7fff 7fff7fff (00000000)
|
|
+ vpkswss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vpkswss: => 7fff7fff 7fff7fff 80008000 80008000 (00000000)
|
|
+ vpkswss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vpkswss: => 80008000 80008000 80008000 80008000 (00000000)
|
|
+
|
|
+ vpkpx: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vpkpx: => 80018000 04218421 80018000 04218421 (00000000)
|
|
+ vpkpx: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vpkpx: => fbdffbde 7fffffff 80018000 04218421 (00000000)
|
|
+ vpkpx: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vpkpx: => 80018000 04218421 fbdffbde 7fffffff (00000000)
|
|
+ vpkpx: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vpkpx: => fbdffbde 7fffffff fbdffbde 7fffffff (00000000)
|
|
+
|
|
+ vmrghb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmrghb: => 0b0b0c0c 09090a0a 0e0e0f0f 0e0e0d0d (00000000)
|
|
+ vmrghb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmrghb: => 0bfb0cfc 09f90afa 0efe0fff 0efe0dfd (00000000)
|
|
+ vmrghb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmrghb: => fb0bfc0c f909fa0a fe0eff0f fe0efd0d (00000000)
|
|
+ vmrghb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmrghb: => fbfbfcfc f9f9fafa fefeffff fefefdfd (00000000)
|
|
+
|
|
+ vmrghh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmrghh: => 0b0c0b0c 090a090a 0e0f0e0f 0e0d0e0d (00000000)
|
|
+ vmrghh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmrghh: => 0b0cfbfc 090af9fa 0e0ffeff 0e0dfefd (00000000)
|
|
+ vmrghh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmrghh: => fbfc0b0c f9fa090a feff0e0f fefd0e0d (00000000)
|
|
+ vmrghh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmrghh: => fbfcfbfc f9faf9fa fefffeff fefdfefd (00000000)
|
|
+
|
|
+ vmrghw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmrghw: => 090a0b0c 090a0b0c 0e0d0e0f 0e0d0e0f (00000000)
|
|
+ vmrghw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmrghw: => f9fafbfc 090a0b0c fefdfeff 0e0d0e0f (00000000)
|
|
+ vmrghw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmrghw: => 090a0b0c f9fafbfc 0e0d0e0f fefdfeff (00000000)
|
|
+ vmrghw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmrghw: => f9fafbfc f9fafbfc fefdfeff fefdfeff (00000000)
|
|
+
|
|
+ vmrglb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmrglb: => 03030404 01010202 07070808 05050606 (00000000)
|
|
+ vmrglb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmrglb: => 03f304f4 01f102f2 07f708f8 05f506f6 (00000000)
|
|
+ vmrglb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmrglb: => f303f404 f101f202 f707f808 f505f606 (00000000)
|
|
+ vmrglb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmrglb: => f3f3f4f4 f1f1f2f2 f7f7f8f8 f5f5f6f6 (00000000)
|
|
+
|
|
+ vmrglh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmrglh: => 03040304 01020102 07080708 05060506 (00000000)
|
|
+ vmrglh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmrglh: => 0304f3f4 0102f1f2 0708f7f8 0506f5f6 (00000000)
|
|
+ vmrglh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmrglh: => f3f40304 f1f20102 f7f80708 f5f60506 (00000000)
|
|
+ vmrglh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmrglh: => f3f4f3f4 f1f2f1f2 f7f8f7f8 f5f6f5f6 (00000000)
|
|
+
|
|
+ vmrglw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmrglw: => 01020304 01020304 05060708 05060708 (00000000)
|
|
+ vmrglw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmrglw: => f1f2f3f4 01020304 f5f6f7f8 05060708 (00000000)
|
|
+ vmrglw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vmrglw: => 01020304 f1f2f3f4 05060708 f5f6f7f8 (00000000)
|
|
+ vmrglw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vmrglw: => f1f2f3f4 f1f2f3f4 f5f6f7f8 f5f6f7f8 (00000000)
|
|
+
|
|
+ vslo: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vslo: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vslo: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vslo: => 00000000 00000000 00000000 03040000 (00000000)
|
|
+ vslo: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vslo: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ vslo: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vslo: => 00000000 00000000 00000000 f3f40000 (00000000)
|
|
+
|
|
+ vsro: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsro: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vsro: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsro: => 00000e0d 00000000 00000000 00000000 (00000000)
|
|
+ vsro: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vsro: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ vsro: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vsro: => 0000fefd 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+PPC altivec integer logical insns with one arg:
|
|
+ vupkhsb: 01020304 05060708 090a0b0c 0e0d0e0f
|
|
+ vupkhsb: => 000b000c 0009000a 000e000f 000e000d (00000000)
|
|
+ vupkhsb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
|
|
+ vupkhsb: => fffbfffc fff9fffa fffeffff fffefffd (00000000)
|
|
+
|
|
+ vupkhsh: 01020304 05060708 090a0b0c 0e0d0e0f
|
|
+ vupkhsh: => 00000b0c 0000090a 00000e0f 00000e0d (00000000)
|
|
+ vupkhsh: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
|
|
+ vupkhsh: => fffffbfc fffff9fa fffffeff fffffefd (00000000)
|
|
+
|
|
+ vupkhpx: 01020304 05060708 090a0b0c 0e0d0e0f
|
|
+ vupkhpx: => 0002180c 0002080a 0003100f 0003100d (00000000)
|
|
+ vupkhpx: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
|
|
+ vupkhpx: => ff1e1f1c ff1e0f1a ff1f171f ff1f171d (00000000)
|
|
+
|
|
+ vupklsb: 01020304 05060708 090a0b0c 0e0d0e0f
|
|
+ vupklsb: => 00030004 00010002 00070008 00050006 (00000000)
|
|
+ vupklsb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
|
|
+ vupklsb: => fff3fff4 fff1fff2 fff7fff8 fff5fff6 (00000000)
|
|
+
|
|
+ vupklsh: 01020304 05060708 090a0b0c 0e0d0e0f
|
|
+ vupklsh: => 00000304 00000102 00000708 00000506 (00000000)
|
|
+ vupklsh: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
|
|
+ vupklsh: => fffff3f4 fffff1f2 fffff7f8 fffff5f6 (00000000)
|
|
+
|
|
+ vupklpx: 01020304 05060708 090a0b0c 0e0d0e0f
|
|
+ vupklpx: => 00001804 00000802 00011808 00010806 (00000000)
|
|
+ vupklpx: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
|
|
+ vupklpx: => ff1c1f14 ff1c0f12 ff1d1f18 ff1d0f16 (00000000)
|
|
+
|
|
+Altivec integer compare insns:
|
|
+ vcmpgtub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtub: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtub: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtub: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgtub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtub: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vcmpgtuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtuh: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtuh: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtuh: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgtuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtuh: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vcmpgtuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtuw: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtuw: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtuw: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgtuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtuw: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vcmpgtsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtsb: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtsb: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgtsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtsb: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtsb: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vcmpgtsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtsh: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtsh: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgtsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtsh: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtsh: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vcmpgtsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtsw: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtsw: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgtsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtsw: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtsw: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vcmpequb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpequb: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpequb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpequb: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpequb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpequb: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpequb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpequb: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+
|
|
+ vcmpequh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpequh: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpequh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpequh: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpequh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpequh: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpequh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpequh: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+
|
|
+ vcmpequw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpequw: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpequw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpequw: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpequw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpequw: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpequw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpequw: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+
|
|
+Altivec integer compare insns with flags update:
|
|
+ vcmpgtub.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtub.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtub.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtub.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtub.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtub.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgtub.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtub.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+
|
|
+ vcmpgtuh.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtuh.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtuh.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtuh.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtuh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtuh.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgtuh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtuh.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+
|
|
+ vcmpgtuw.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtuw.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtuw.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtuw.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtuw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtuw.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgtuw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtuw.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+
|
|
+ vcmpgtsb.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtsb.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtsb.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtsb.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgtsb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtsb.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtsb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtsb.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+
|
|
+ vcmpgtsh.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtsh.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtsh.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtsh.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgtsh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtsh.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtsh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtsh.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+
|
|
+ vcmpgtsw.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtsw.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtsw.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtsw.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgtsw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpgtsw.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtsw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpgtsw.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+
|
|
+ vcmpequb.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpequb.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpequb.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpequb.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpequb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpequb.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpequb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpequb.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+
|
|
+ vcmpequh.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpequh.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpequh.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpequh.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpequh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpequh.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpequh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpequh.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+
|
|
+ vcmpequw.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpequw.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpequw.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpequw.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpequw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
|
|
+ vcmpequw.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpequw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
|
|
+ vcmpequw.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+
|
|
+Altivec integer special insns:
|
|
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 00000000000000000000000000000000
|
|
+ vsl: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 01010101010101010101010101010101
|
|
+ vsl: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
|
|
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 02020202020202020202020202020202
|
|
+ vsl: => 04080c10 14181c20 24282c30 3834383c (00000000)
|
|
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 03030303030303030303030303030303
|
|
+ vsl: => 08101820 28303840 48505860 70687078 (00000000)
|
|
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 04040404040404040404040404040404
|
|
+ vsl: => 10203040 50607080 90a0b0c0 e0d0e0f0 (00000000)
|
|
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 05050505050505050505050505050505
|
|
+ vsl: => 20406080 a0c0e100 21416180 c1a1c1e1 (00000000)
|
|
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 06060606060606060606060606060606
|
|
+ vsl: => 4080c100 4181c200 4282c301 834383c2 (00000000)
|
|
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 07070707070707070707070707070707
|
|
+ vsl: => 81018200 83038400 85058602 06870784 (00000000)
|
|
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 00000000000000000000000000000000
|
|
+ vsl: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 01010101010101010101010101010101
|
|
+ vsl: => e3e5e7e8 ebedeff1 f3f5f7f9 fdfbfdff (00000000)
|
|
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 02020202020202020202020202020202
|
|
+ vsl: => c7cbcfd0 d7dbdfe3 e7ebeff3 fbf7fbff (00000000)
|
|
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 03030303030303030303030303030303
|
|
+ vsl: => 8f979fa0 afb7bfc7 cfd7dfe7 f7eff7ff (00000000)
|
|
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 04040404040404040404040404040404
|
|
+ vsl: => 1f2f3f40 5f6f7f8f 9fafbfcf efdfefff (00000000)
|
|
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 05050505050505050505050505050505
|
|
+ vsl: => 3e5e7e80 bedeff1e 3f5f7f9e dfbfdfff (00000000)
|
|
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 06060606060606060606060606060606
|
|
+ vsl: => 7cbcfd00 7dbdfe3c 7ebeff3d bf7fbffe (00000000)
|
|
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 07070707070707070707070707070707
|
|
+ vsl: => f979fa00 fb7bfc78 fd7dfe7a 7eff7ffc (00000000)
|
|
+
|
|
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 00000000000000000000000000000000
|
|
+ vsr: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 01010101010101010101010101010101
|
|
+ vsr: => 00810182 02830384 84850586 07068707 (00000000)
|
|
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 02020202020202020202020202020202
|
|
+ vsr: => 004080c1 014181c2 c24282c3 03834383 (00000000)
|
|
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 03030303030303030303030303030303
|
|
+ vsr: => 00204060 80a0c0e1 e1214161 01c1a1c1 (00000000)
|
|
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 04040404040404040404040404040404
|
|
+ vsr: => 80102030 c0506070 f090a0b0 00e0d0e0 (00000000)
|
|
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 05050505050505050505050505050505
|
|
+ vsr: => 40081018 60283038 78485058 00706870 (00000000)
|
|
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 06060606060606060606060606060606
|
|
+ vsr: => 2004080c 3014181c 3c24282c 00383438 (00000000)
|
|
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 07070707070707070707070707070707
|
|
+ vsr: => 10020406 180a0c0e 1e121416 001c1a1c (00000000)
|
|
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 00000000000000000000000000000000
|
|
+ vsr: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 01010101010101010101010101010101
|
|
+ vsr: => 78f979fa 7afb7bfc fcfd7dfe 7f7eff7f (00000000)
|
|
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 02020202020202020202020202020202
|
|
+ vsr: => 3c7cbcfd 3d7dbdfe fe7ebeff 3fbf7fbf (00000000)
|
|
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 03030303030303030303030303030303
|
|
+ vsr: => 1e3e5e7e 9ebedeff ff3f5f7f 1fdfbfdf (00000000)
|
|
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 04040404040404040404040404040404
|
|
+ vsr: => 8f1f2f3f cf5f6f7f ff9fafbf 0fefdfef (00000000)
|
|
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 05050505050505050505050505050505
|
|
+ vsr: => c78f979f e7afb7bf ffcfd7df 07f7eff7 (00000000)
|
|
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 06060606060606060606060606060606
|
|
+ vsr: => e3c7cbcf f3d7dbdf ffe7ebef 03fbf7fb (00000000)
|
|
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 07070707070707070707070707070707
|
|
+ vsr: => f1e3e5e7 f9ebedef fff3f5f7 01fdfbfd (00000000)
|
|
+
|
|
+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 0
|
|
+ vspltb: => 0e0e0e0e 0e0e0e0e 0e0e0e0e 0e0e0e0e (00000000)
|
|
+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 3
|
|
+ vspltb: => 0f0f0f0f 0f0f0f0f 0f0f0f0f 0f0f0f0f (00000000)
|
|
+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 6
|
|
+ vspltb: => 0b0b0b0b 0b0b0b0b 0b0b0b0b 0b0b0b0b (00000000)
|
|
+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 9
|
|
+ vspltb: => 06060606 06060606 06060606 06060606 (00000000)
|
|
+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 12
|
|
+ vspltb: => 01010101 01010101 01010101 01010101 (00000000)
|
|
+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 15
|
|
+ vspltb: => 04040404 04040404 04040404 04040404 (00000000)
|
|
+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 0
|
|
+ vspltb: => fefefefe fefefefe fefefefe fefefefe (00000000)
|
|
+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 3
|
|
+ vspltb: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 6
|
|
+ vspltb: => fbfbfbfb fbfbfbfb fbfbfbfb fbfbfbfb (00000000)
|
|
+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 9
|
|
+ vspltb: => f6f6f6f6 f6f6f6f6 f6f6f6f6 f6f6f6f6 (00000000)
|
|
+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 12
|
|
+ vspltb: => f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1 (00000000)
|
|
+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 15
|
|
+ vspltb: => f4f4f4f4 f4f4f4f4 f4f4f4f4 f4f4f4f4 (00000000)
|
|
+
|
|
+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 0
|
|
+ vsplth: => 0e0d0e0d 0e0d0e0d 0e0d0e0d 0e0d0e0d (00000000)
|
|
+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 3
|
|
+ vsplth: => 0b0c0b0c 0b0c0b0c 0b0c0b0c 0b0c0b0c (00000000)
|
|
+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 6
|
|
+ vsplth: => 01020102 01020102 01020102 01020102 (00000000)
|
|
+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 9
|
|
+ vsplth: => 0e0f0e0f 0e0f0e0f 0e0f0e0f 0e0f0e0f (00000000)
|
|
+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 12
|
|
+ vsplth: => 05060506 05060506 05060506 05060506 (00000000)
|
|
+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 15
|
|
+ vsplth: => 03040304 03040304 03040304 03040304 (00000000)
|
|
+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 0
|
|
+ vsplth: => fefdfefd fefdfefd fefdfefd fefdfefd (00000000)
|
|
+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 3
|
|
+ vsplth: => fbfcfbfc fbfcfbfc fbfcfbfc fbfcfbfc (00000000)
|
|
+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 6
|
|
+ vsplth: => f1f2f1f2 f1f2f1f2 f1f2f1f2 f1f2f1f2 (00000000)
|
|
+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 9
|
|
+ vsplth: => fefffeff fefffeff fefffeff fefffeff (00000000)
|
|
+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 12
|
|
+ vsplth: => f5f6f5f6 f5f6f5f6 f5f6f5f6 f5f6f5f6 (00000000)
|
|
+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 15
|
|
+ vsplth: => f3f4f3f4 f3f4f3f4 f3f4f3f4 f3f4f3f4 (00000000)
|
|
+
|
|
+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 0
|
|
+ vspltw: => 0e0d0e0f 0e0d0e0f 0e0d0e0f 0e0d0e0f (00000000)
|
|
+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 3
|
|
+ vspltw: => 01020304 01020304 01020304 01020304 (00000000)
|
|
+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 6
|
|
+ vspltw: => 05060708 05060708 05060708 05060708 (00000000)
|
|
+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 9
|
|
+ vspltw: => 090a0b0c 090a0b0c 090a0b0c 090a0b0c (00000000)
|
|
+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 12
|
|
+ vspltw: => 0e0d0e0f 0e0d0e0f 0e0d0e0f 0e0d0e0f (00000000)
|
|
+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 15
|
|
+ vspltw: => 01020304 01020304 01020304 01020304 (00000000)
|
|
+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 0
|
|
+ vspltw: => fefdfeff fefdfeff fefdfeff fefdfeff (00000000)
|
|
+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 3
|
|
+ vspltw: => f1f2f3f4 f1f2f3f4 f1f2f3f4 f1f2f3f4 (00000000)
|
|
+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 6
|
|
+ vspltw: => f5f6f7f8 f5f6f7f8 f5f6f7f8 f5f6f7f8 (00000000)
|
|
+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 9
|
|
+ vspltw: => f9fafbfc f9fafbfc f9fafbfc f9fafbfc (00000000)
|
|
+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 12
|
|
+ vspltw: => fefdfeff fefdfeff fefdfeff fefdfeff (00000000)
|
|
+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 15
|
|
+ vspltw: => f1f2f3f4 f1f2f3f4 f1f2f3f4 f1f2f3f4 (00000000)
|
|
+
|
|
+ vspltisb: 0 => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vspltisb: 1 => 01010101 01010101 01010101 01010101 (00000000)
|
|
+ vspltisb: 2 => 02020202 02020202 02020202 02020202 (00000000)
|
|
+ vspltisb: 3 => 03030303 03030303 03030303 03030303 (00000000)
|
|
+ vspltisb: 4 => 04040404 04040404 04040404 04040404 (00000000)
|
|
+ vspltisb: 5 => 05050505 05050505 05050505 05050505 (00000000)
|
|
+ vspltisb: 6 => 06060606 06060606 06060606 06060606 (00000000)
|
|
+ vspltisb: 7 => 07070707 07070707 07070707 07070707 (00000000)
|
|
+ vspltisb: 8 => 08080808 08080808 08080808 08080808 (00000000)
|
|
+ vspltisb: 9 => 09090909 09090909 09090909 09090909 (00000000)
|
|
+ vspltisb: 10 => 0a0a0a0a 0a0a0a0a 0a0a0a0a 0a0a0a0a (00000000)
|
|
+ vspltisb: 11 => 0b0b0b0b 0b0b0b0b 0b0b0b0b 0b0b0b0b (00000000)
|
|
+ vspltisb: 12 => 0c0c0c0c 0c0c0c0c 0c0c0c0c 0c0c0c0c (00000000)
|
|
+ vspltisb: 13 => 0d0d0d0d 0d0d0d0d 0d0d0d0d 0d0d0d0d (00000000)
|
|
+ vspltisb: 14 => 0e0e0e0e 0e0e0e0e 0e0e0e0e 0e0e0e0e (00000000)
|
|
+ vspltisb: 15 => 0f0f0f0f 0f0f0f0f 0f0f0f0f 0f0f0f0f (00000000)
|
|
+ vspltisb: 16 => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
|
|
+ vspltisb: 17 => f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1 (00000000)
|
|
+ vspltisb: 18 => f2f2f2f2 f2f2f2f2 f2f2f2f2 f2f2f2f2 (00000000)
|
|
+ vspltisb: 19 => f3f3f3f3 f3f3f3f3 f3f3f3f3 f3f3f3f3 (00000000)
|
|
+ vspltisb: 20 => f4f4f4f4 f4f4f4f4 f4f4f4f4 f4f4f4f4 (00000000)
|
|
+ vspltisb: 21 => f5f5f5f5 f5f5f5f5 f5f5f5f5 f5f5f5f5 (00000000)
|
|
+ vspltisb: 22 => f6f6f6f6 f6f6f6f6 f6f6f6f6 f6f6f6f6 (00000000)
|
|
+ vspltisb: 23 => f7f7f7f7 f7f7f7f7 f7f7f7f7 f7f7f7f7 (00000000)
|
|
+ vspltisb: 24 => f8f8f8f8 f8f8f8f8 f8f8f8f8 f8f8f8f8 (00000000)
|
|
+ vspltisb: 25 => f9f9f9f9 f9f9f9f9 f9f9f9f9 f9f9f9f9 (00000000)
|
|
+ vspltisb: 26 => fafafafa fafafafa fafafafa fafafafa (00000000)
|
|
+ vspltisb: 27 => fbfbfbfb fbfbfbfb fbfbfbfb fbfbfbfb (00000000)
|
|
+ vspltisb: 28 => fcfcfcfc fcfcfcfc fcfcfcfc fcfcfcfc (00000000)
|
|
+ vspltisb: 29 => fdfdfdfd fdfdfdfd fdfdfdfd fdfdfdfd (00000000)
|
|
+ vspltisb: 30 => fefefefe fefefefe fefefefe fefefefe (00000000)
|
|
+ vspltisb: 31 => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+
|
|
+ vspltish: 0 => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vspltish: 1 => 00010001 00010001 00010001 00010001 (00000000)
|
|
+ vspltish: 2 => 00020002 00020002 00020002 00020002 (00000000)
|
|
+ vspltish: 3 => 00030003 00030003 00030003 00030003 (00000000)
|
|
+ vspltish: 4 => 00040004 00040004 00040004 00040004 (00000000)
|
|
+ vspltish: 5 => 00050005 00050005 00050005 00050005 (00000000)
|
|
+ vspltish: 6 => 00060006 00060006 00060006 00060006 (00000000)
|
|
+ vspltish: 7 => 00070007 00070007 00070007 00070007 (00000000)
|
|
+ vspltish: 8 => 00080008 00080008 00080008 00080008 (00000000)
|
|
+ vspltish: 9 => 00090009 00090009 00090009 00090009 (00000000)
|
|
+ vspltish: 10 => 000a000a 000a000a 000a000a 000a000a (00000000)
|
|
+ vspltish: 11 => 000b000b 000b000b 000b000b 000b000b (00000000)
|
|
+ vspltish: 12 => 000c000c 000c000c 000c000c 000c000c (00000000)
|
|
+ vspltish: 13 => 000d000d 000d000d 000d000d 000d000d (00000000)
|
|
+ vspltish: 14 => 000e000e 000e000e 000e000e 000e000e (00000000)
|
|
+ vspltish: 15 => 000f000f 000f000f 000f000f 000f000f (00000000)
|
|
+ vspltish: 16 => fff0fff0 fff0fff0 fff0fff0 fff0fff0 (00000000)
|
|
+ vspltish: 17 => fff1fff1 fff1fff1 fff1fff1 fff1fff1 (00000000)
|
|
+ vspltish: 18 => fff2fff2 fff2fff2 fff2fff2 fff2fff2 (00000000)
|
|
+ vspltish: 19 => fff3fff3 fff3fff3 fff3fff3 fff3fff3 (00000000)
|
|
+ vspltish: 20 => fff4fff4 fff4fff4 fff4fff4 fff4fff4 (00000000)
|
|
+ vspltish: 21 => fff5fff5 fff5fff5 fff5fff5 fff5fff5 (00000000)
|
|
+ vspltish: 22 => fff6fff6 fff6fff6 fff6fff6 fff6fff6 (00000000)
|
|
+ vspltish: 23 => fff7fff7 fff7fff7 fff7fff7 fff7fff7 (00000000)
|
|
+ vspltish: 24 => fff8fff8 fff8fff8 fff8fff8 fff8fff8 (00000000)
|
|
+ vspltish: 25 => fff9fff9 fff9fff9 fff9fff9 fff9fff9 (00000000)
|
|
+ vspltish: 26 => fffafffa fffafffa fffafffa fffafffa (00000000)
|
|
+ vspltish: 27 => fffbfffb fffbfffb fffbfffb fffbfffb (00000000)
|
|
+ vspltish: 28 => fffcfffc fffcfffc fffcfffc fffcfffc (00000000)
|
|
+ vspltish: 29 => fffdfffd fffdfffd fffdfffd fffdfffd (00000000)
|
|
+ vspltish: 30 => fffefffe fffefffe fffefffe fffefffe (00000000)
|
|
+ vspltish: 31 => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+
|
|
+ vspltisw: 0 => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vspltisw: 1 => 00000001 00000001 00000001 00000001 (00000000)
|
|
+ vspltisw: 2 => 00000002 00000002 00000002 00000002 (00000000)
|
|
+ vspltisw: 3 => 00000003 00000003 00000003 00000003 (00000000)
|
|
+ vspltisw: 4 => 00000004 00000004 00000004 00000004 (00000000)
|
|
+ vspltisw: 5 => 00000005 00000005 00000005 00000005 (00000000)
|
|
+ vspltisw: 6 => 00000006 00000006 00000006 00000006 (00000000)
|
|
+ vspltisw: 7 => 00000007 00000007 00000007 00000007 (00000000)
|
|
+ vspltisw: 8 => 00000008 00000008 00000008 00000008 (00000000)
|
|
+ vspltisw: 9 => 00000009 00000009 00000009 00000009 (00000000)
|
|
+ vspltisw: 10 => 0000000a 0000000a 0000000a 0000000a (00000000)
|
|
+ vspltisw: 11 => 0000000b 0000000b 0000000b 0000000b (00000000)
|
|
+ vspltisw: 12 => 0000000c 0000000c 0000000c 0000000c (00000000)
|
|
+ vspltisw: 13 => 0000000d 0000000d 0000000d 0000000d (00000000)
|
|
+ vspltisw: 14 => 0000000e 0000000e 0000000e 0000000e (00000000)
|
|
+ vspltisw: 15 => 0000000f 0000000f 0000000f 0000000f (00000000)
|
|
+ vspltisw: 16 => fffffff0 fffffff0 fffffff0 fffffff0 (00000000)
|
|
+ vspltisw: 17 => fffffff1 fffffff1 fffffff1 fffffff1 (00000000)
|
|
+ vspltisw: 18 => fffffff2 fffffff2 fffffff2 fffffff2 (00000000)
|
|
+ vspltisw: 19 => fffffff3 fffffff3 fffffff3 fffffff3 (00000000)
|
|
+ vspltisw: 20 => fffffff4 fffffff4 fffffff4 fffffff4 (00000000)
|
|
+ vspltisw: 21 => fffffff5 fffffff5 fffffff5 fffffff5 (00000000)
|
|
+ vspltisw: 22 => fffffff6 fffffff6 fffffff6 fffffff6 (00000000)
|
|
+ vspltisw: 23 => fffffff7 fffffff7 fffffff7 fffffff7 (00000000)
|
|
+ vspltisw: 24 => fffffff8 fffffff8 fffffff8 fffffff8 (00000000)
|
|
+ vspltisw: 25 => fffffff9 fffffff9 fffffff9 fffffff9 (00000000)
|
|
+ vspltisw: 26 => fffffffa fffffffa fffffffa fffffffa (00000000)
|
|
+ vspltisw: 27 => fffffffb fffffffb fffffffb fffffffb (00000000)
|
|
+ vspltisw: 28 => fffffffc fffffffc fffffffc fffffffc (00000000)
|
|
+ vspltisw: 29 => fffffffd fffffffd fffffffd fffffffd (00000000)
|
|
+ vspltisw: 30 => fffffffe fffffffe fffffffe fffffffe (00000000)
|
|
+ vspltisw: 31 => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+
|
|
+ vsldoi: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0
|
|
+ vsldoi: => 01020304 05060708 090a0b0c 0e0d0e0f] (00000000)
|
|
+ vsldoi: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 14
|
|
+ vsldoi: => 07080102 0b0c0506 0e0f090a 03040e0d] (00000000)
|
|
+ vsldoi: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0
|
|
+ vsldoi: => 01020304 05060708 090a0b0c 0e0d0e0f] (00000000)
|
|
+ vsldoi: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 14
|
|
+ vsldoi: => f7f8f1f2 fbfcf5f6 fefff9fa 0304fefd] (00000000)
|
|
+ vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0
|
|
+ vsldoi: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff] (00000000)
|
|
+ vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 14
|
|
+ vsldoi: => 07080102 0b0c0506 0e0f090a f3f40e0d] (00000000)
|
|
+ vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0
|
|
+ vsldoi: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff] (00000000)
|
|
+ vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 14
|
|
+ vsldoi: => f7f8f1f2 fbfcf5f6 fefff9fa f3f4fefd] (00000000)
|
|
+
|
|
+ lvsl 3, 0 => 0x1211100f0e0d0c0b 0x0a09080706050403 (00000000)
|
|
+ lvsl 4, 0 => 0x131211100f0e0d0c 0x0b0a090807060504 (00000000)
|
|
+ lvsl 5, 0 => 0x14131211100f0e0d 0x0c0b0a0908070605 (00000000)
|
|
+ lvsl 6, 0 => 0x1514131211100f0e 0x0d0c0b0a09080706 (00000000)
|
|
+ lvsl 7, 0 => 0x161514131211100f 0x0e0d0c0b0a090807 (00000000)
|
|
+ lvsl 8, 0 => 0x1716151413121110 0x0f0e0d0c0b0a0908 (00000000)
|
|
+ lvsl 9, 0 => 0x1817161514131211 0x100f0e0d0c0b0a09 (00000000)
|
|
+ lvsl a, 0 => 0x1918171615141312 0x11100f0e0d0c0b0a (00000000)
|
|
+ lvsl b, 0 => 0x1a19181716151413 0x1211100f0e0d0c0b (00000000)
|
|
+ lvsl c, 0 => 0x1b1a191817161514 0x131211100f0e0d0c (00000000)
|
|
+ lvsl d, 0 => 0x1c1b1a1918171615 0x14131211100f0e0d (00000000)
|
|
+ lvsl e, 0 => 0x1d1c1b1a19181716 0x1514131211100f0e (00000000)
|
|
+ lvsl f, 0 => 0x1e1d1c1b1a191817 0x161514131211100f (00000000)
|
|
+ lvsl 0, 0 => 0x0f0e0d0c0b0a0908 0x0706050403020100 (00000000)
|
|
+ lvsl 1, 0 => 0x100f0e0d0c0b0a09 0x0807060504030201 (00000000)
|
|
+ lvsl 2, 0 => 0x11100f0e0d0c0b0a 0x0908070605040302 (00000000)
|
|
+ lvsl 3, 0 => 0x1211100f0e0d0c0b 0x0a09080706050403 (00000000)
|
|
+ lvsl 4, 0 => 0x131211100f0e0d0c 0x0b0a090807060504 (00000000)
|
|
+
|
|
+ lvsr 3, 0 => 0x1c1b1a1918171615 0x14131211100f0e0d (00000000)
|
|
+ lvsr 4, 0 => 0x1b1a191817161514 0x131211100f0e0d0c (00000000)
|
|
+ lvsr 5, 0 => 0x1a19181716151413 0x1211100f0e0d0c0b (00000000)
|
|
+ lvsr 6, 0 => 0x1918171615141312 0x11100f0e0d0c0b0a (00000000)
|
|
+ lvsr 7, 0 => 0x1817161514131211 0x100f0e0d0c0b0a09 (00000000)
|
|
+ lvsr 8, 0 => 0x1716151413121110 0x0f0e0d0c0b0a0908 (00000000)
|
|
+ lvsr 9, 0 => 0x161514131211100f 0x0e0d0c0b0a090807 (00000000)
|
|
+ lvsr a, 0 => 0x1514131211100f0e 0x0d0c0b0a09080706 (00000000)
|
|
+ lvsr b, 0 => 0x14131211100f0e0d 0x0c0b0a0908070605 (00000000)
|
|
+ lvsr c, 0 => 0x131211100f0e0d0c 0x0b0a090807060504 (00000000)
|
|
+ lvsr d, 0 => 0x1211100f0e0d0c0b 0x0a09080706050403 (00000000)
|
|
+ lvsr e, 0 => 0x11100f0e0d0c0b0a 0x0908070605040302 (00000000)
|
|
+ lvsr f, 0 => 0x100f0e0d0c0b0a09 0x0807060504030201 (00000000)
|
|
+ lvsr 0, 0 => 0x1f1e1d1c1b1a1918 0x1716151413121110 (00000000)
|
|
+ lvsr 1, 0 => 0x1e1d1c1b1a191817 0x161514131211100f (00000000)
|
|
+ lvsr 2, 0 => 0x1d1c1b1a19181716 0x1514131211100f0e (00000000)
|
|
+ lvsr 3, 0 => 0x1c1b1a1918171615 0x14131211100f0e0d (00000000)
|
|
+ lvsr 4, 0 => 0x1b1a191817161514 0x131211100f0e0d0c (00000000)
|
|
+
|
|
+Altivec load insns with two register args:
|
|
+ lvebx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 00000004 00000000 00000000 00000000 (00000000)
|
|
+ lvebx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 05000000 00000000 00000000 (00000000)
|
|
+ lvebx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 00000000 00000000 000d0000 (00000000)
|
|
+ lvebx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 000000f4 00000000 00000000 00000000 (00000000)
|
|
+ lvebx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 f5000000 00000000 00000000 (00000000)
|
|
+ lvebx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 00000000 00000000 00fd0000 (00000000)
|
|
+
|
|
+ lvehx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 00000304 00000000 00000000 00000000 (00000000)
|
|
+ lvehx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 05060000 00000000 00000000 (00000000)
|
|
+ lvehx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 00000000 00000000 0e0d0000 (00000000)
|
|
+ lvehx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 0000f3f4 00000000 00000000 00000000 (00000000)
|
|
+ lvehx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 f5f60000 00000000 00000000 (00000000)
|
|
+ lvehx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 00000000 00000000 fefd0000 (00000000)
|
|
+
|
|
+ lvewx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 00000000 00000000 00000000 (00000000)
|
|
+ lvewx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 05060708 00000000 00000000 (00000000)
|
|
+ lvewx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 00000000 00000000 0e0d0e0f (00000000)
|
|
+ lvewx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 00000000 00000000 00000000 (00000000)
|
|
+ lvewx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 f5f6f7f8 00000000 00000000 (00000000)
|
|
+ lvewx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 00000000 00000000 fefdfeff (00000000)
|
|
+
|
|
+ lvx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ lvx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ lvx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ lvx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ lvx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ lvx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+ lvxl 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ lvxl 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ lvxl 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ lvxl 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ lvxl 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ lvxl 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+Altivec store insns with three register args:
|
|
+ stvebx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 00000004 00000000 00000000 00000000 (00000000)
|
|
+ stvebx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 00000004 05000000 00000000 00000000 (00000000)
|
|
+ stvebx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 00000004 05000000 00000000 000d0000 (00000000)
|
|
+ stvebx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 000000f4 00000000 00000000 00000000 (00000000)
|
|
+ stvebx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 000000f4 f5000000 00000000 00000000 (00000000)
|
|
+ stvebx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 000000f4 f5000000 00000000 00fd0000 (00000000)
|
|
+
|
|
+ stvehx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 00000304 00000000 00000000 00000000 (00000000)
|
|
+ stvehx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 00000304 05060000 00000000 00000000 (00000000)
|
|
+ stvehx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 00000304 05060000 00000000 0e0d0000 (00000000)
|
|
+ stvehx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 0000f3f4 00000000 00000000 00000000 (00000000)
|
|
+ stvehx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 0000f3f4 f5f60000 00000000 00000000 (00000000)
|
|
+ stvehx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 0000f3f4 f5f60000 00000000 fefd0000 (00000000)
|
|
+
|
|
+ stvewx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 00000000 00000000 00000000 (00000000)
|
|
+ stvewx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 00000000 00000000 (00000000)
|
|
+ stvewx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 00000000 0e0d0e0f (00000000)
|
|
+ stvewx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 00000000 00000000 00000000 (00000000)
|
|
+ stvewx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 00000000 00000000 (00000000)
|
|
+ stvewx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 00000000 fefdfeff (00000000)
|
|
+
|
|
+ stvx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ stvx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ stvx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ stvx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ stvx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ stvx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+ stvxl 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ stvxl 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ stvxl 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
|
|
+ stvxl 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ stvxl 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+ stvxl 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
|
|
+
|
|
+Altivec floating point arith insns with two args:
|
|
+ vaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vaddfp: => 033fffff 033fffff 033fffff 033fffff (00000000)
|
|
+ vaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
|
|
+ vaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vaddfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
|
|
+ vaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vaddfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
|
|
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
|
|
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vaddfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
|
|
+ vaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
|
|
+ vaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vaddfp: => d1bfffff d1bfffff d1bfffff d1bfffff (00000000)
|
|
+ vaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
|
|
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
|
|
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vaddfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
|
|
+ vaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
|
|
+ vaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
|
|
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
|
|
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vaddfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
|
|
+ vaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
|
|
+ vaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
|
|
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
|
|
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
|
|
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
|
|
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
|
|
+ vaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
|
|
+ vaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
|
|
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
|
|
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
|
|
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
|
|
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
|
|
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+
|
|
+ vsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vsubfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
|
|
+ vsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
|
|
+ vsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vsubfp: => 51bfffff 51bfffff 51bfffff 51bfffff (00000000)
|
|
+ vsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
|
|
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
|
|
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vsubfp: => 833fffff 833fffff 833fffff 833fffff (00000000)
|
|
+ vsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
|
|
+ vsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vsubfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
|
|
+ vsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vsubfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
|
|
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
|
|
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vsubfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000)
|
|
+ vsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
|
|
+ vsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
|
|
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
|
|
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vsubfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000)
|
|
+ vsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
|
|
+ vsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
|
|
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
|
|
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
|
|
+ vsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
|
|
+ vsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
|
|
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
|
|
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
|
|
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
|
|
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
|
|
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
|
|
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
|
|
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+
|
|
+ vmaxfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
|
|
+ vmaxfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
|
|
+ vmaxfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vmaxfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vmaxfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaxfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
|
|
+ vmaxfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vmaxfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
|
|
+ vmaxfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
|
|
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vmaxfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
|
|
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vmaxfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
|
|
+ vmaxfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vmaxfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000)
|
|
+ vmaxfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vmaxfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vmaxfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
|
|
+ vmaxfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vmaxfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
|
|
+ vmaxfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
|
|
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vmaxfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
|
|
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vmaxfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
|
|
+ vmaxfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vmaxfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vmaxfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
|
|
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vmaxfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
|
|
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vmaxfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
|
|
+ vmaxfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vmaxfp: => 80000000 80000000 80000000 80000000 (00000000)
|
|
+ vmaxfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
|
|
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vmaxfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
|
|
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vmaxfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vmaxfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vmaxfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
|
|
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vmaxfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
|
|
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vmaxfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
|
|
+ vmaxfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vmaxfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
|
|
+ vmaxfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
|
|
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vmaxfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
|
|
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vmaxfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaxfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaxfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
|
|
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaxfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
|
|
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaxfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vmaxfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vmaxfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
|
|
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vmaxfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
|
|
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vmaxfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaxfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaxfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaxfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaxfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vmaxfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vmaxfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vmaxfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+
|
|
+ vminfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vminfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
|
|
+ vminfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
|
|
+ vminfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vminfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
|
|
+ vminfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vminfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vminfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
|
|
+ vminfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
|
|
+ vminfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
|
|
+ vminfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
|
|
+ vminfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
|
|
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vminfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vminfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000)
|
|
+ vminfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
|
|
+ vminfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vminfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000)
|
|
+ vminfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vminfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
|
|
+ vminfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
|
|
+ vminfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
|
|
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
|
|
+ vminfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
|
|
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vminfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vminfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vminfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
|
|
+ vminfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
|
|
+ vminfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vminfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
|
|
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vminfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vminfp: => 80000000 80000000 80000000 80000000 (00000000)
|
|
+ vminfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
|
|
+ vminfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
|
|
+ vminfp: => 80000000 80000000 80000000 80000000 (00000000)
|
|
+ vminfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
|
|
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vminfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vminfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
|
|
+ vminfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
|
|
+ vminfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
|
|
+ vminfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vminfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
|
|
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vminfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vminfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vminfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vminfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vminfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
|
|
+ vminfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vminfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
|
|
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vminfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vminfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vminfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
|
|
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vminfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
|
|
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vminfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vminfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vminfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
|
|
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vminfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
|
|
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vminfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vminfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vminfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vminfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vminfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vminfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vminfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vminfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+
|
|
+Altivec floating point arith insns with three args:
|
|
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
|
|
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
|
|
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
|
|
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
|
|
+ vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
|
|
+ vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
|
|
+ vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
|
|
+ vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
|
|
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
|
|
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
|
|
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
|
|
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
|
|
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
|
|
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
|
|
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
|
|
+ vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
|
|
+ vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
|
|
+ vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
|
|
+ vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
|
|
+ vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
|
|
+ vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
|
|
+ vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
|
|
+ vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+
|
|
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
|
|
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
|
|
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
|
|
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
|
|
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
|
|
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
|
|
+ vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
|
|
+ vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
|
|
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
|
|
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
|
|
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
|
|
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
|
|
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
|
|
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
|
|
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
|
|
+ vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
|
|
+ vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
|
|
+ vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
|
|
+ vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
|
|
+ vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
|
|
+ vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
|
|
+ vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
|
|
+ vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
|
|
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+
|
|
+Altivec floating point arith insns with one arg:
|
|
+ vrfin: 02bfffff 02bfffff 02bfffff 02bfffff
|
|
+ vrfin: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vrfin: 513fffff 513fffff 513fffff 513fffff
|
|
+ vrfin: => 513fffff 513fffff 513fffff 513fffff (00000000)
|
|
+ vrfin: 82bfffff 82bfffff 82bfffff 82bfffff
|
|
+ vrfin: => 80000000 80000000 80000000 80000000 (00000000)
|
|
+ vrfin: d13fffff d13fffff d13fffff d13fffff
|
|
+ vrfin: => d13fffff d13fffff d13fffff d13fffff (00000000)
|
|
+ vrfin: 00000000 00000000 00000000 00000000
|
|
+ vrfin: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vrfin: 80000000 80000000 80000000 80000000
|
|
+ vrfin: => 80000000 80000000 80000000 80000000 (00000000)
|
|
+ vrfin: 7f800000 7f800000 7f800000 7f800000
|
|
+ vrfin: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vrfin: ff800000 ff800000 ff800000 ff800000
|
|
+ vrfin: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vrfin: 7fffffff 7fffffff 7fffffff 7fffffff
|
|
+ vrfin: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vrfin: ffffffff ffffffff ffffffff ffffffff
|
|
+ vrfin: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vrfin: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
|
|
+ vrfin: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vrfin: ffbfffff ffbfffff ffbfffff ffbfffff
|
|
+ vrfin: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+
|
|
+ vrfiz: 02bfffff 02bfffff 02bfffff 02bfffff
|
|
+ vrfiz: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vrfiz: 513fffff 513fffff 513fffff 513fffff
|
|
+ vrfiz: => 513fffff 513fffff 513fffff 513fffff (00000000)
|
|
+ vrfiz: 82bfffff 82bfffff 82bfffff 82bfffff
|
|
+ vrfiz: => 80000000 80000000 80000000 80000000 (00000000)
|
|
+ vrfiz: d13fffff d13fffff d13fffff d13fffff
|
|
+ vrfiz: => d13fffff d13fffff d13fffff d13fffff (00000000)
|
|
+ vrfiz: 00000000 00000000 00000000 00000000
|
|
+ vrfiz: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vrfiz: 80000000 80000000 80000000 80000000
|
|
+ vrfiz: => 80000000 80000000 80000000 80000000 (00000000)
|
|
+ vrfiz: 7f800000 7f800000 7f800000 7f800000
|
|
+ vrfiz: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vrfiz: ff800000 ff800000 ff800000 ff800000
|
|
+ vrfiz: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vrfiz: 7fffffff 7fffffff 7fffffff 7fffffff
|
|
+ vrfiz: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vrfiz: ffffffff ffffffff ffffffff ffffffff
|
|
+ vrfiz: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vrfiz: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
|
|
+ vrfiz: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vrfiz: ffbfffff ffbfffff ffbfffff ffbfffff
|
|
+ vrfiz: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+
|
|
+ vrfip: 02bfffff 02bfffff 02bfffff 02bfffff
|
|
+ vrfip: => 3f800000 3f800000 3f800000 3f800000 (00000000)
|
|
+ vrfip: 513fffff 513fffff 513fffff 513fffff
|
|
+ vrfip: => 513fffff 513fffff 513fffff 513fffff (00000000)
|
|
+ vrfip: 82bfffff 82bfffff 82bfffff 82bfffff
|
|
+ vrfip: => 80000000 80000000 80000000 80000000 (00000000)
|
|
+ vrfip: d13fffff d13fffff d13fffff d13fffff
|
|
+ vrfip: => d13fffff d13fffff d13fffff d13fffff (00000000)
|
|
+ vrfip: 00000000 00000000 00000000 00000000
|
|
+ vrfip: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vrfip: 80000000 80000000 80000000 80000000
|
|
+ vrfip: => 80000000 80000000 80000000 80000000 (00000000)
|
|
+ vrfip: 7f800000 7f800000 7f800000 7f800000
|
|
+ vrfip: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vrfip: ff800000 ff800000 ff800000 ff800000
|
|
+ vrfip: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vrfip: 7fffffff 7fffffff 7fffffff 7fffffff
|
|
+ vrfip: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vrfip: ffffffff ffffffff ffffffff ffffffff
|
|
+ vrfip: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vrfip: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
|
|
+ vrfip: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vrfip: ffbfffff ffbfffff ffbfffff ffbfffff
|
|
+ vrfip: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+
|
|
+ vrfim: 02bfffff 02bfffff 02bfffff 02bfffff
|
|
+ vrfim: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vrfim: 513fffff 513fffff 513fffff 513fffff
|
|
+ vrfim: => 513fffff 513fffff 513fffff 513fffff (00000000)
|
|
+ vrfim: 82bfffff 82bfffff 82bfffff 82bfffff
|
|
+ vrfim: => bf800000 bf800000 bf800000 bf800000 (00000000)
|
|
+ vrfim: d13fffff d13fffff d13fffff d13fffff
|
|
+ vrfim: => d13fffff d13fffff d13fffff d13fffff (00000000)
|
|
+ vrfim: 00000000 00000000 00000000 00000000
|
|
+ vrfim: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vrfim: 80000000 80000000 80000000 80000000
|
|
+ vrfim: => 80000000 80000000 80000000 80000000 (00000000)
|
|
+ vrfim: 7f800000 7f800000 7f800000 7f800000
|
|
+ vrfim: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vrfim: ff800000 ff800000 ff800000 ff800000
|
|
+ vrfim: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vrfim: 7fffffff 7fffffff 7fffffff 7fffffff
|
|
+ vrfim: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vrfim: ffffffff ffffffff ffffffff ffffffff
|
|
+ vrfim: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vrfim: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
|
|
+ vrfim: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
|
|
+ vrfim: ffbfffff ffbfffff ffbfffff ffbfffff
|
|
+ vrfim: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+
|
|
+ vrefp: 02bfffff 02bfffff 02bfffff 02bfffff
|
|
+ vrefp: => 7c2a8000 7c2a8000 7c2a8000 7c2a8000 (00000000)
|
|
+ vrefp: 513fffff 513fffff 513fffff 513fffff
|
|
+ vrefp: => 2daa8000 2daa8000 2daa8000 2daa8000 (00000000)
|
|
+ vrefp: 82bfffff 82bfffff 82bfffff 82bfffff
|
|
+ vrefp: => fc2a8000 fc2a8000 fc2a8000 fc2a8000 (00000000)
|
|
+ vrefp: d13fffff d13fffff d13fffff d13fffff
|
|
+ vrefp: => adaa8000 adaa8000 adaa8000 adaa8000 (00000000)
|
|
+ vrefp: 00000000 00000000 00000000 00000000
|
|
+ vrefp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vrefp: 80000000 80000000 80000000 80000000
|
|
+ vrefp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vrefp: 7f800000 7f800000 7f800000 7f800000
|
|
+ vrefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vrefp: ff800000 ff800000 ff800000 ff800000
|
|
+ vrefp: => 80000000 80000000 80000000 80000000 (00000000)
|
|
+ vrefp: 7fffffff 7fffffff 7fffffff 7fffffff
|
|
+ vrefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
|
|
+ vrefp: ffffffff ffffffff ffffffff ffffffff
|
|
+ vrefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
|
|
+ vrefp: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
|
|
+ vrefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
|
|
+ vrefp: ffbfffff ffbfffff ffbfffff ffbfffff
|
|
+ vrefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
|
|
+
|
|
+ vrsqrtefp: 02bfffff 02bfffff 02bfffff 02bfffff
|
|
+ vrsqrtefp: => 5dd10000 5dd10000 5dd10000 5dd10000 (00000000)
|
|
+ vrsqrtefp: 513fffff 513fffff 513fffff 513fffff
|
|
+ vrsqrtefp: => 3693c000 3693c000 3693c000 3693c000 (00000000)
|
|
+ vrsqrtefp: 82bfffff 82bfffff 82bfffff 82bfffff
|
|
+ vrsqrtefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
|
|
+ vrsqrtefp: d13fffff d13fffff d13fffff d13fffff
|
|
+ vrsqrtefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
|
|
+ vrsqrtefp: 00000000 00000000 00000000 00000000
|
|
+ vrsqrtefp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
|
|
+ vrsqrtefp: 80000000 80000000 80000000 80000000
|
|
+ vrsqrtefp: => ff800000 ff800000 ff800000 ff800000 (00000000)
|
|
+ vrsqrtefp: 7f800000 7f800000 7f800000 7f800000
|
|
+ vrsqrtefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vrsqrtefp: ff800000 ff800000 ff800000 ff800000
|
|
+ vrsqrtefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
|
|
+ vrsqrtefp: 7fffffff 7fffffff 7fffffff 7fffffff
|
|
+ vrsqrtefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
|
|
+ vrsqrtefp: ffffffff ffffffff ffffffff ffffffff
|
|
+ vrsqrtefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
|
|
+ vrsqrtefp: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
|
|
+ vrsqrtefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
|
|
+ vrsqrtefp: ffbfffff ffbfffff ffbfffff ffbfffff
|
|
+ vrsqrtefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
|
|
+
|
|
+Altivec floating point compare insns:
|
|
+ vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgtfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgtfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgtfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgtfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgtfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgtfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgtfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgtfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vcmpeqfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpeqfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpeqfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpeqfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpeqfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vcmpgefp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgefp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgefp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgefp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgefp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgefp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgefp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgefp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgefp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgefp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgefp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
|
|
+ vcmpgefp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpgefp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+
|
|
+ vcmpbfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpbfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpbfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp: => 80000000 80000000 80000000 80000000 (00000000)
|
|
+ vcmpbfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp: => 80000000 80000000 80000000 80000000 (00000000)
|
|
+ vcmpbfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpbfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpbfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpbfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp: => 40000000 40000000 40000000 40000000 (00000000)
|
|
+ vcmpbfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp: => 40000000 40000000 40000000 40000000 (00000000)
|
|
+ vcmpbfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpbfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpbfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpbfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpbfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpbfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp: => 80000000 80000000 80000000 80000000 (00000000)
|
|
+ vcmpbfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp: => 80000000 80000000 80000000 80000000 (00000000)
|
|
+ vcmpbfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpbfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp: => 40000000 40000000 40000000 40000000 (00000000)
|
|
+ vcmpbfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp: => 40000000 40000000 40000000 40000000 (00000000)
|
|
+ vcmpbfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
|
|
+ vcmpbfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+
|
|
+Altivec floating point compare insns with flags update:
|
|
+ vcmpgtfp.: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgtfp.: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgtfp.: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgtfp.: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgtfp.: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgtfp.: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgtfp.: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgtfp.: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgtfp.: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgtfp.: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+
|
|
+ vcmpeqfp.: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpeqfp.: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpeqfp.: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpeqfp.: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpeqfp.: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+
|
|
+ vcmpgefp.: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgefp.: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgefp.: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgefp.: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgefp.: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgefp.: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgefp.: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgefp.: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgefp.: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgefp.: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgefp.: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
|
|
+ vcmpgefp.: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpgefp.: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+
|
|
+ vcmpbfp.: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpbfp.: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpbfp.: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp.: => 80000000 80000000 80000000 80000000 (00000000)
|
|
+ vcmpbfp.: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp.: => 80000000 80000000 80000000 80000000 (00000000)
|
|
+ vcmpbfp.: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpbfp.: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpbfp.: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpbfp.: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp.: => 40000000 40000000 40000000 40000000 (00000000)
|
|
+ vcmpbfp.: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp.: => 40000000 40000000 40000000 40000000 (00000000)
|
|
+ vcmpbfp.: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpbfp.: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpbfp.: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpbfp.: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpbfp.: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpbfp.: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp.: => 80000000 80000000 80000000 80000000 (00000000)
|
|
+ vcmpbfp.: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp.: => 80000000 80000000 80000000 80000000 (00000000)
|
|
+ vcmpbfp.: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpbfp.: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp.: => 40000000 40000000 40000000 40000000 (00000000)
|
|
+ vcmpbfp.: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp.: => 40000000 40000000 40000000 40000000 (00000000)
|
|
+ vcmpbfp.: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
|
|
+ vcmpbfp.: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+ vcmpbfp.: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
|
|
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
|
|
+
|
|
+Altivec float special insns:
|
|
+ vcfux: 02bfffff ( 2.821186e-37), 0 => 4c300000 ( 4.613734e+07) (00000000)
|
|
+ vcfux: 02bfffff ( 2.821186e-37), 9 => 47b00000 ( 9.011200e+04) (00000000)
|
|
+ vcfux: 02bfffff ( 2.821186e-37), 18 => 43300000 ( 1.760000e+02) (00000000)
|
|
+ vcfux: 02bfffff ( 2.821186e-37), 27 => 3eb00000 ( 3.437500e-01) (00000000)
|
|
+ vcfux: 513fffff ( 5.153960e+10), 0 => 4ea28000 ( 1.363149e+09) (00000000)
|
|
+ vcfux: 513fffff ( 5.153960e+10), 9 => 4a228000 ( 2.662400e+06) (00000000)
|
|
+ vcfux: 513fffff ( 5.153960e+10), 18 => 45a28000 ( 5.200000e+03) (00000000)
|
|
+ vcfux: 513fffff ( 5.153960e+10), 27 => 41228000 ( 1.015625e+01) (00000000)
|
|
+ vcfux: 82bfffff (-2.821186e-37), 0 => 4f02c000 ( 2.193621e+09) (00000000)
|
|
+ vcfux: 82bfffff (-2.821186e-37), 9 => 4a82c000 ( 4.284416e+06) (00000000)
|
|
+ vcfux: 82bfffff (-2.821186e-37), 18 => 4602c000 ( 8.368000e+03) (00000000)
|
|
+ vcfux: 82bfffff (-2.821186e-37), 27 => 4182c000 ( 1.634375e+01) (00000000)
|
|
+ vcfux: d13fffff (-5.153960e+10), 0 => 4f514000 ( 3.510632e+09) (00000000)
|
|
+ vcfux: d13fffff (-5.153960e+10), 9 => 4ad14000 ( 6.856704e+06) (00000000)
|
|
+ vcfux: d13fffff (-5.153960e+10), 18 => 46514000 ( 1.339200e+04) (00000000)
|
|
+ vcfux: d13fffff (-5.153960e+10), 27 => 41d14000 ( 2.615625e+01) (00000000)
|
|
+ vcfux: 00000000 ( 0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vcfux: 00000000 ( 0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vcfux: 00000000 ( 0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vcfux: 00000000 ( 0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vcfux: 80000000 (-0.000000e+00), 0 => 4f000000 ( 2.147484e+09) (00000000)
|
|
+ vcfux: 80000000 (-0.000000e+00), 9 => 4a800000 ( 4.194304e+06) (00000000)
|
|
+ vcfux: 80000000 (-0.000000e+00), 18 => 46000000 ( 8.192000e+03) (00000000)
|
|
+ vcfux: 80000000 (-0.000000e+00), 27 => 41800000 ( 1.600000e+01) (00000000)
|
|
+ vcfux: 7f800000 ( inf), 0 => 4eff0000 ( 2.139095e+09) (00000000)
|
|
+ vcfux: 7f800000 ( inf), 9 => 4a7f0000 ( 4.177920e+06) (00000000)
|
|
+ vcfux: 7f800000 ( inf), 18 => 45ff0000 ( 8.160000e+03) (00000000)
|
|
+ vcfux: 7f800000 ( inf), 27 => 417f0000 ( 1.593750e+01) (00000000)
|
|
+ vcfux: ff800000 ( -inf), 0 => 4f7f8000 ( 4.286579e+09) (00000000)
|
|
+ vcfux: ff800000 ( -inf), 9 => 4aff8000 ( 8.372224e+06) (00000000)
|
|
+ vcfux: ff800000 ( -inf), 18 => 467f8000 ( 1.635200e+04) (00000000)
|
|
+ vcfux: ff800000 ( -inf), 27 => 41ff8000 ( 3.193750e+01) (00000000)
|
|
+ vcfux: 7fffffff ( nan), 0 => 4f000000 ( 2.147484e+09) (00000000)
|
|
+ vcfux: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000)
|
|
+ vcfux: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000)
|
|
+ vcfux: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000)
|
|
+ vcfux: ffffffff ( -nan), 0 => 4f800000 ( 4.294967e+09) (00000000)
|
|
+ vcfux: ffffffff ( -nan), 9 => 4b000000 ( 8.388608e+06) (00000000)
|
|
+ vcfux: ffffffff ( -nan), 18 => 46800000 ( 1.638400e+04) (00000000)
|
|
+ vcfux: ffffffff ( -nan), 27 => 42000000 ( 3.200000e+01) (00000000)
|
|
+ vcfux: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000)
|
|
+ vcfux: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000)
|
|
+ vcfux: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000)
|
|
+ vcfux: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000)
|
|
+ vcfux: ffbfffff ( -nan), 0 => 4f7fc000 ( 4.290773e+09) (00000000)
|
|
+ vcfux: ffbfffff ( -nan), 9 => 4affc000 ( 8.380416e+06) (00000000)
|
|
+ vcfux: ffbfffff ( -nan), 18 => 467fc000 ( 1.636800e+04) (00000000)
|
|
+ vcfux: ffbfffff ( -nan), 27 => 41ffc000 ( 3.196875e+01) (00000000)
|
|
+
|
|
+ vcfsx: 02bfffff ( 2.821186e-37), 0 => 4c300000 ( 4.613734e+07) (00000000)
|
|
+ vcfsx: 02bfffff ( 2.821186e-37), 9 => 47b00000 ( 9.011200e+04) (00000000)
|
|
+ vcfsx: 02bfffff ( 2.821186e-37), 18 => 43300000 ( 1.760000e+02) (00000000)
|
|
+ vcfsx: 02bfffff ( 2.821186e-37), 27 => 3eb00000 ( 3.437500e-01) (00000000)
|
|
+ vcfsx: 513fffff ( 5.153960e+10), 0 => 4ea28000 ( 1.363149e+09) (00000000)
|
|
+ vcfsx: 513fffff ( 5.153960e+10), 9 => 4a228000 ( 2.662400e+06) (00000000)
|
|
+ vcfsx: 513fffff ( 5.153960e+10), 18 => 45a28000 ( 5.200000e+03) (00000000)
|
|
+ vcfsx: 513fffff ( 5.153960e+10), 27 => 41228000 ( 1.015625e+01) (00000000)
|
|
+ vcfsx: 82bfffff (-2.821186e-37), 0 => cefa8000 (-2.101346e+09) (00000000)
|
|
+ vcfsx: 82bfffff (-2.821186e-37), 9 => ca7a8000 (-4.104192e+06) (00000000)
|
|
+ vcfsx: 82bfffff (-2.821186e-37), 18 => c5fa8000 (-8.016000e+03) (00000000)
|
|
+ vcfsx: 82bfffff (-2.821186e-37), 27 => c17a8000 (-1.565625e+01) (00000000)
|
|
+ vcfsx: d13fffff (-5.153960e+10), 0 => ce3b0000 (-7.843348e+08) (00000000)
|
|
+ vcfsx: d13fffff (-5.153960e+10), 9 => c9bb0000 (-1.531904e+06) (00000000)
|
|
+ vcfsx: d13fffff (-5.153960e+10), 18 => c53b0000 (-2.992000e+03) (00000000)
|
|
+ vcfsx: d13fffff (-5.153960e+10), 27 => c0bb0000 (-5.843750e+00) (00000000)
|
|
+ vcfsx: 00000000 ( 0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vcfsx: 00000000 ( 0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vcfsx: 00000000 ( 0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vcfsx: 00000000 ( 0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vcfsx: 80000000 (-0.000000e+00), 0 => cf000000 (-2.147484e+09) (00000000)
|
|
+ vcfsx: 80000000 (-0.000000e+00), 9 => ca800000 (-4.194304e+06) (00000000)
|
|
+ vcfsx: 80000000 (-0.000000e+00), 18 => c6000000 (-8.192000e+03) (00000000)
|
|
+ vcfsx: 80000000 (-0.000000e+00), 27 => c1800000 (-1.600000e+01) (00000000)
|
|
+ vcfsx: 7f800000 ( inf), 0 => 4eff0000 ( 2.139095e+09) (00000000)
|
|
+ vcfsx: 7f800000 ( inf), 9 => 4a7f0000 ( 4.177920e+06) (00000000)
|
|
+ vcfsx: 7f800000 ( inf), 18 => 45ff0000 ( 8.160000e+03) (00000000)
|
|
+ vcfsx: 7f800000 ( inf), 27 => 417f0000 ( 1.593750e+01) (00000000)
|
|
+ vcfsx: ff800000 ( -inf), 0 => cb000000 (-8.388608e+06) (00000000)
|
|
+ vcfsx: ff800000 ( -inf), 9 => c6800000 (-1.638400e+04) (00000000)
|
|
+ vcfsx: ff800000 ( -inf), 18 => c2000000 (-3.200000e+01) (00000000)
|
|
+ vcfsx: ff800000 ( -inf), 27 => bd800000 (-6.250000e-02) (00000000)
|
|
+ vcfsx: 7fffffff ( nan), 0 => 4f000000 ( 2.147484e+09) (00000000)
|
|
+ vcfsx: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000)
|
|
+ vcfsx: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000)
|
|
+ vcfsx: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000)
|
|
+ vcfsx: ffffffff ( -nan), 0 => bf800000 (-1.000000e+00) (00000000)
|
|
+ vcfsx: ffffffff ( -nan), 9 => bb000000 (-1.953125e-03) (00000000)
|
|
+ vcfsx: ffffffff ( -nan), 18 => b6800000 (-3.814697e-06) (00000000)
|
|
+ vcfsx: ffffffff ( -nan), 27 => b2000000 (-7.450581e-09) (00000000)
|
|
+ vcfsx: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000)
|
|
+ vcfsx: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000)
|
|
+ vcfsx: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000)
|
|
+ vcfsx: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000)
|
|
+ vcfsx: ffbfffff ( -nan), 0 => ca800002 (-4.194305e+06) (00000000)
|
|
+ vcfsx: ffbfffff ( -nan), 9 => c6000002 (-8.192002e+03) (00000000)
|
|
+ vcfsx: ffbfffff ( -nan), 18 => c1800002 (-1.600000e+01) (00000000)
|
|
+ vcfsx: ffbfffff ( -nan), 27 => bd000002 (-3.125001e-02) (00000000)
|
|
+
|
|
+ vctuxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 02bfffff ( 2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 02bfffff ( 2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 513fffff ( 5.153960e+10), 0 => ffffffff ( -nan) (00000000)
|
|
+ vctuxs: 513fffff ( 5.153960e+10), 9 => ffffffff ( -nan) (00000000)
|
|
+ vctuxs: 513fffff ( 5.153960e+10), 18 => ffffffff ( -nan) (00000000)
|
|
+ vctuxs: 513fffff ( 5.153960e+10), 27 => ffffffff ( -nan) (00000000)
|
|
+ vctuxs: 82bfffff (-2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 82bfffff (-2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 82bfffff (-2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 82bfffff (-2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: d13fffff (-5.153960e+10), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: d13fffff (-5.153960e+10), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: d13fffff (-5.153960e+10), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: d13fffff (-5.153960e+10), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 00000000 ( 0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 00000000 ( 0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 00000000 ( 0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 00000000 ( 0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 80000000 (-0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 80000000 (-0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 80000000 (-0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 80000000 (-0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 7f800000 ( inf), 0 => ffffffff ( -nan) (00000000)
|
|
+ vctuxs: 7f800000 ( inf), 9 => ffffffff ( -nan) (00000000)
|
|
+ vctuxs: 7f800000 ( inf), 18 => ffffffff ( -nan) (00000000)
|
|
+ vctuxs: 7f800000 ( inf), 27 => ffffffff ( -nan) (00000000)
|
|
+ vctuxs: ff800000 ( -inf), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ff800000 ( -inf), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ff800000 ( -inf), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ff800000 ( -inf), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 7fffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+
|
|
+ vctsxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: 02bfffff ( 2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: 02bfffff ( 2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: 513fffff ( 5.153960e+10), 0 => 7fffffff ( nan) (00000000)
|
|
+ vctsxs: 513fffff ( 5.153960e+10), 9 => 7fffffff ( nan) (00000000)
|
|
+ vctsxs: 513fffff ( 5.153960e+10), 18 => 7fffffff ( nan) (00000000)
|
|
+ vctsxs: 513fffff ( 5.153960e+10), 27 => 7fffffff ( nan) (00000000)
|
|
+ vctsxs: 82bfffff (-2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: 82bfffff (-2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: 82bfffff (-2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: 82bfffff (-2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: d13fffff (-5.153960e+10), 0 => 80000000 (-0.000000e+00) (00000000)
|
|
+ vctsxs: d13fffff (-5.153960e+10), 9 => 80000000 (-0.000000e+00) (00000000)
|
|
+ vctsxs: d13fffff (-5.153960e+10), 18 => 80000000 (-0.000000e+00) (00000000)
|
|
+ vctsxs: d13fffff (-5.153960e+10), 27 => 80000000 (-0.000000e+00) (00000000)
|
|
+ vctsxs: 00000000 ( 0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: 00000000 ( 0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: 00000000 ( 0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: 00000000 ( 0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: 80000000 (-0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: 80000000 (-0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: 80000000 (-0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: 80000000 (-0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: 7f800000 ( inf), 0 => 7fffffff ( nan) (00000000)
|
|
+ vctsxs: 7f800000 ( inf), 9 => 7fffffff ( nan) (00000000)
|
|
+ vctsxs: 7f800000 ( inf), 18 => 7fffffff ( nan) (00000000)
|
|
+ vctsxs: 7f800000 ( inf), 27 => 7fffffff ( nan) (00000000)
|
|
+ vctsxs: ff800000 ( -inf), 0 => 80000000 (-0.000000e+00) (00000000)
|
|
+ vctsxs: ff800000 ( -inf), 9 => 80000000 (-0.000000e+00) (00000000)
|
|
+ vctsxs: ff800000 ( -inf), 18 => 80000000 (-0.000000e+00) (00000000)
|
|
+ vctsxs: ff800000 ( -inf), 27 => 80000000 (-0.000000e+00) (00000000)
|
|
+ vctsxs: 7fffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+
|
|
+All done. Tested 165 different instructions
|
|
Index: none/tests/ppc64/jm-vmx.stdout.exp
|
|
===================================================================
|
|
--- none/tests/ppc64/jm-vmx.stdout.exp.orig
|
|
+++ none/tests/ppc64/jm-vmx.stdout.exp
|
|
@@ -1407,43 +1407,43 @@ Altivec integer special insns:
|
|
vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 14
|
|
vsldoi: => fefff1f2 f3f4f5f6 f7f8f9fa fbfcfefd] (00000000)
|
|
|
|
- lvsl -1, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
|
|
- lvsl 0, 0 => 00010203 04050607 08090a0b 0c0d0e0f (00000000)
|
|
- lvsl 1, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
|
|
- lvsl 2, 0 => 02030405 06070809 0a0b0c0d 0e0f1011 (00000000)
|
|
- lvsl 3, 0 => 03040506 0708090a 0b0c0d0e 0f101112 (00000000)
|
|
- lvsl 4, 0 => 04050607 08090a0b 0c0d0e0f 10111213 (00000000)
|
|
- lvsl 5, 0 => 05060708 090a0b0c 0d0e0f10 11121314 (00000000)
|
|
- lvsl 6, 0 => 06070809 0a0b0c0d 0e0f1011 12131415 (00000000)
|
|
- lvsl 7, 0 => 0708090a 0b0c0d0e 0f101112 13141516 (00000000)
|
|
- lvsl 8, 0 => 08090a0b 0c0d0e0f 10111213 14151617 (00000000)
|
|
- lvsl 9, 0 => 090a0b0c 0d0e0f10 11121314 15161718 (00000000)
|
|
- lvsl 10, 0 => 0a0b0c0d 0e0f1011 12131415 16171819 (00000000)
|
|
- lvsl 11, 0 => 0b0c0d0e 0f101112 13141516 1718191a (00000000)
|
|
- lvsl 12, 0 => 0c0d0e0f 10111213 14151617 18191a1b (00000000)
|
|
- lvsl 13, 0 => 0d0e0f10 11121314 15161718 191a1b1c (00000000)
|
|
- lvsl 14, 0 => 0e0f1011 12131415 16171819 1a1b1c1d (00000000)
|
|
- lvsl 15, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
|
|
- lvsl 16, 0 => 00010203 04050607 08090a0b 0c0d0e0f (00000000)
|
|
-
|
|
- lvsr -1, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
|
|
- lvsr 0, 0 => 10111213 14151617 18191a1b 1c1d1e1f (00000000)
|
|
- lvsr 1, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
|
|
- lvsr 2, 0 => 0e0f1011 12131415 16171819 1a1b1c1d (00000000)
|
|
- lvsr 3, 0 => 0d0e0f10 11121314 15161718 191a1b1c (00000000)
|
|
- lvsr 4, 0 => 0c0d0e0f 10111213 14151617 18191a1b (00000000)
|
|
- lvsr 5, 0 => 0b0c0d0e 0f101112 13141516 1718191a (00000000)
|
|
- lvsr 6, 0 => 0a0b0c0d 0e0f1011 12131415 16171819 (00000000)
|
|
- lvsr 7, 0 => 090a0b0c 0d0e0f10 11121314 15161718 (00000000)
|
|
- lvsr 8, 0 => 08090a0b 0c0d0e0f 10111213 14151617 (00000000)
|
|
- lvsr 9, 0 => 0708090a 0b0c0d0e 0f101112 13141516 (00000000)
|
|
- lvsr 10, 0 => 06070809 0a0b0c0d 0e0f1011 12131415 (00000000)
|
|
- lvsr 11, 0 => 05060708 090a0b0c 0d0e0f10 11121314 (00000000)
|
|
- lvsr 12, 0 => 04050607 08090a0b 0c0d0e0f 10111213 (00000000)
|
|
- lvsr 13, 0 => 03040506 0708090a 0b0c0d0e 0f101112 (00000000)
|
|
- lvsr 14, 0 => 02030405 06070809 0a0b0c0d 0e0f1011 (00000000)
|
|
- lvsr 15, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
|
|
- lvsr 16, 0 => 10111213 14151617 18191a1b 1c1d1e1f (00000000)
|
|
+ lvsl 7, 0 => 0x0708090a0b0c0d0e 0x0f10111213141516 (00000000)
|
|
+ lvsl 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000)
|
|
+ lvsl 9, 0 => 0x090a0b0c0d0e0f10 0x1112131415161718 (00000000)
|
|
+ lvsl a, 0 => 0x0a0b0c0d0e0f1011 0x1213141516171819 (00000000)
|
|
+ lvsl b, 0 => 0x0b0c0d0e0f101112 0x131415161718191a (00000000)
|
|
+ lvsl c, 0 => 0x0c0d0e0f10111213 0x1415161718191a1b (00000000)
|
|
+ lvsl d, 0 => 0x0d0e0f1011121314 0x15161718191a1b1c (00000000)
|
|
+ lvsl e, 0 => 0x0e0f101112131415 0x161718191a1b1c1d (00000000)
|
|
+ lvsl f, 0 => 0x0f10111213141516 0x1718191a1b1c1d1e (00000000)
|
|
+ lvsl 0, 0 => 0x0001020304050607 0x08090a0b0c0d0e0f (00000000)
|
|
+ lvsl 1, 0 => 0x0102030405060708 0x090a0b0c0d0e0f10 (00000000)
|
|
+ lvsl 2, 0 => 0x0203040506070809 0x0a0b0c0d0e0f1011 (00000000)
|
|
+ lvsl 3, 0 => 0x030405060708090a 0x0b0c0d0e0f101112 (00000000)
|
|
+ lvsl 4, 0 => 0x0405060708090a0b 0x0c0d0e0f10111213 (00000000)
|
|
+ lvsl 5, 0 => 0x05060708090a0b0c 0x0d0e0f1011121314 (00000000)
|
|
+ lvsl 6, 0 => 0x060708090a0b0c0d 0x0e0f101112131415 (00000000)
|
|
+ lvsl 7, 0 => 0x0708090a0b0c0d0e 0x0f10111213141516 (00000000)
|
|
+ lvsl 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000)
|
|
+
|
|
+ lvsr 7, 0 => 0x090a0b0c0d0e0f10 0x1112131415161718 (00000000)
|
|
+ lvsr 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000)
|
|
+ lvsr 9, 0 => 0x0708090a0b0c0d0e 0x0f10111213141516 (00000000)
|
|
+ lvsr a, 0 => 0x060708090a0b0c0d 0x0e0f101112131415 (00000000)
|
|
+ lvsr b, 0 => 0x05060708090a0b0c 0x0d0e0f1011121314 (00000000)
|
|
+ lvsr c, 0 => 0x0405060708090a0b 0x0c0d0e0f10111213 (00000000)
|
|
+ lvsr d, 0 => 0x030405060708090a 0x0b0c0d0e0f101112 (00000000)
|
|
+ lvsr e, 0 => 0x0203040506070809 0x0a0b0c0d0e0f1011 (00000000)
|
|
+ lvsr f, 0 => 0x0102030405060708 0x090a0b0c0d0e0f10 (00000000)
|
|
+ lvsr 0, 0 => 0x1011121314151617 0x18191a1b1c1d1e1f (00000000)
|
|
+ lvsr 1, 0 => 0x0f10111213141516 0x1718191a1b1c1d1e (00000000)
|
|
+ lvsr 2, 0 => 0x0e0f101112131415 0x161718191a1b1c1d (00000000)
|
|
+ lvsr 3, 0 => 0x0d0e0f1011121314 0x15161718191a1b1c (00000000)
|
|
+ lvsr 4, 0 => 0x0c0d0e0f10111213 0x1415161718191a1b (00000000)
|
|
+ lvsr 5, 0 => 0x0b0c0d0e0f101112 0x131415161718191a (00000000)
|
|
+ lvsr 6, 0 => 0x0a0b0c0d0e0f1011 0x1213141516171819 (00000000)
|
|
+ lvsr 7, 0 => 0x090a0b0c0d0e0f10 0x1112131415161718 (00000000)
|
|
+ lvsr 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000)
|
|
|
|
Altivec load insns with two register args:
|
|
lvebx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01000000 00000000 00000000 00000000 (00000000)
|
|
@@ -3451,18 +3451,18 @@ Altivec float special insns:
|
|
vcfux: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000)
|
|
vcfux: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000)
|
|
vcfux: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000)
|
|
- vcfux: ffffffff ( nan), 0 => 4f800000 ( 4.294967e+09) (00000000)
|
|
- vcfux: ffffffff ( nan), 9 => 4b000000 ( 8.388608e+06) (00000000)
|
|
- vcfux: ffffffff ( nan), 18 => 46800000 ( 1.638400e+04) (00000000)
|
|
- vcfux: ffffffff ( nan), 27 => 42000000 ( 3.200000e+01) (00000000)
|
|
+ vcfux: ffffffff ( -nan), 0 => 4f800000 ( 4.294967e+09) (00000000)
|
|
+ vcfux: ffffffff ( -nan), 9 => 4b000000 ( 8.388608e+06) (00000000)
|
|
+ vcfux: ffffffff ( -nan), 18 => 46800000 ( 1.638400e+04) (00000000)
|
|
+ vcfux: ffffffff ( -nan), 27 => 42000000 ( 3.200000e+01) (00000000)
|
|
vcfux: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000)
|
|
vcfux: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000)
|
|
vcfux: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000)
|
|
vcfux: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000)
|
|
- vcfux: ffbfffff ( nan), 0 => 4f7fc000 ( 4.290773e+09) (00000000)
|
|
- vcfux: ffbfffff ( nan), 9 => 4affc000 ( 8.380416e+06) (00000000)
|
|
- vcfux: ffbfffff ( nan), 18 => 467fc000 ( 1.636800e+04) (00000000)
|
|
- vcfux: ffbfffff ( nan), 27 => 41ffc000 ( 3.196875e+01) (00000000)
|
|
+ vcfux: ffbfffff ( -nan), 0 => 4f7fc000 ( 4.290773e+09) (00000000)
|
|
+ vcfux: ffbfffff ( -nan), 9 => 4affc000 ( 8.380416e+06) (00000000)
|
|
+ vcfux: ffbfffff ( -nan), 18 => 467fc000 ( 1.636800e+04) (00000000)
|
|
+ vcfux: ffbfffff ( -nan), 27 => 41ffc000 ( 3.196875e+01) (00000000)
|
|
|
|
vcfsx: 02bfffff ( 2.821186e-37), 0 => 4c300000 ( 4.613734e+07) (00000000)
|
|
vcfsx: 02bfffff ( 2.821186e-37), 9 => 47b00000 ( 9.011200e+04) (00000000)
|
|
@@ -3500,27 +3500,27 @@ Altivec float special insns:
|
|
vcfsx: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000)
|
|
vcfsx: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000)
|
|
vcfsx: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000)
|
|
- vcfsx: ffffffff ( nan), 0 => bf800000 (-1.000000e+00) (00000000)
|
|
- vcfsx: ffffffff ( nan), 9 => bb000000 (-1.953125e-03) (00000000)
|
|
- vcfsx: ffffffff ( nan), 18 => b6800000 (-3.814697e-06) (00000000)
|
|
- vcfsx: ffffffff ( nan), 27 => b2000000 (-7.450581e-09) (00000000)
|
|
+ vcfsx: ffffffff ( -nan), 0 => bf800000 (-1.000000e+00) (00000000)
|
|
+ vcfsx: ffffffff ( -nan), 9 => bb000000 (-1.953125e-03) (00000000)
|
|
+ vcfsx: ffffffff ( -nan), 18 => b6800000 (-3.814697e-06) (00000000)
|
|
+ vcfsx: ffffffff ( -nan), 27 => b2000000 (-7.450581e-09) (00000000)
|
|
vcfsx: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000)
|
|
vcfsx: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000)
|
|
vcfsx: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000)
|
|
vcfsx: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000)
|
|
- vcfsx: ffbfffff ( nan), 0 => ca800002 (-4.194305e+06) (00000000)
|
|
- vcfsx: ffbfffff ( nan), 9 => c6000002 (-8.192002e+03) (00000000)
|
|
- vcfsx: ffbfffff ( nan), 18 => c1800002 (-1.600000e+01) (00000000)
|
|
- vcfsx: ffbfffff ( nan), 27 => bd000002 (-3.125001e-02) (00000000)
|
|
+ vcfsx: ffbfffff ( -nan), 0 => ca800002 (-4.194305e+06) (00000000)
|
|
+ vcfsx: ffbfffff ( -nan), 9 => c6000002 (-8.192002e+03) (00000000)
|
|
+ vcfsx: ffbfffff ( -nan), 18 => c1800002 (-1.600000e+01) (00000000)
|
|
+ vcfsx: ffbfffff ( -nan), 27 => bd000002 (-3.125001e-02) (00000000)
|
|
|
|
vctuxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 02bfffff ( 2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 02bfffff ( 2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctuxs: 513fffff ( 5.153960e+10), 0 => ffffffff ( nan) (00000000)
|
|
- vctuxs: 513fffff ( 5.153960e+10), 9 => ffffffff ( nan) (00000000)
|
|
- vctuxs: 513fffff ( 5.153960e+10), 18 => ffffffff ( nan) (00000000)
|
|
- vctuxs: 513fffff ( 5.153960e+10), 27 => ffffffff ( nan) (00000000)
|
|
+ vctuxs: 513fffff ( 5.153960e+10), 0 => ffffffff ( -nan) (00000000)
|
|
+ vctuxs: 513fffff ( 5.153960e+10), 9 => ffffffff ( -nan) (00000000)
|
|
+ vctuxs: 513fffff ( 5.153960e+10), 18 => ffffffff ( -nan) (00000000)
|
|
+ vctuxs: 513fffff ( 5.153960e+10), 27 => ffffffff ( -nan) (00000000)
|
|
vctuxs: 82bfffff (-2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 82bfffff (-2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 82bfffff (-2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
@@ -3537,10 +3537,10 @@ Altivec float special insns:
|
|
vctuxs: 80000000 (-0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 80000000 (-0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 80000000 (-0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctuxs: 7f800000 ( inf), 0 => ffffffff ( nan) (00000000)
|
|
- vctuxs: 7f800000 ( inf), 9 => ffffffff ( nan) (00000000)
|
|
- vctuxs: 7f800000 ( inf), 18 => ffffffff ( nan) (00000000)
|
|
- vctuxs: 7f800000 ( inf), 27 => ffffffff ( nan) (00000000)
|
|
+ vctuxs: 7f800000 ( inf), 0 => ffffffff ( -nan) (00000000)
|
|
+ vctuxs: 7f800000 ( inf), 9 => ffffffff ( -nan) (00000000)
|
|
+ vctuxs: 7f800000 ( inf), 18 => ffffffff ( -nan) (00000000)
|
|
+ vctuxs: 7f800000 ( inf), 27 => ffffffff ( -nan) (00000000)
|
|
vctuxs: ff800000 ( -inf), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: ff800000 ( -inf), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: ff800000 ( -inf), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
@@ -3549,18 +3549,18 @@ Altivec float special insns:
|
|
vctuxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctuxs: ffffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctuxs: ffffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctuxs: ffffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctuxs: ffffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctuxs: ffbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctuxs: ffbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctuxs: ffbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctuxs: ffbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
|
|
vctsxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctsxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
@@ -3598,17 +3598,17 @@ Altivec float special insns:
|
|
vctsxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctsxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctsxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctsxs: ffffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctsxs: ffffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctsxs: ffffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctsxs: ffffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctsxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctsxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctsxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctsxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctsxs: ffbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctsxs: ffbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctsxs: ffbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctsxs: ffbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
|
|
All done. Tested 165 different instructions
|
|
Index: none/tests/ppc64/jm-fp.stdout.exp-BE2
|
|
===================================================================
|
|
--- /dev/null
|
|
+++ none/tests/ppc64/jm-fp.stdout.exp-BE2
|
|
@@ -0,0 +1,1533 @@
|
|
+PPC floating point arith insns with three args:
|
|
+ fsel 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000
|
|
+ fsel 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300
|
|
+ fsel 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
|
|
+ fsel 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000
|
|
+ fsel 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300
|
|
+ fsel 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
|
|
+ fsel bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fsel bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fsel bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fmadd 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100
|
|
+ fmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00
|
|
+ fmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000
|
|
+ fmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100
|
|
+ fmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fmadds 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+
|
|
+ fmsub 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
|
|
+ fmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
|
|
+ fmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00
|
|
+ fmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100
|
|
+ fmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000
|
|
+ fmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00
|
|
+ fmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+
|
|
+ fmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+
|
|
+ fnmadd 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
|
|
+ fnmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
|
|
+ fnmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100
|
|
+ fnmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00
|
|
+ fnmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000
|
|
+ fnmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100
|
|
+ fnmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+
|
|
+ fnmadds 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+
|
|
+ fnmsub 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fnmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fnmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00
|
|
+ fnmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100
|
|
+ fnmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000
|
|
+ fnmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00
|
|
+ fnmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fnmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+
|
|
+PPC floating point arith insns
|
|
+ with three args with flags update:
|
|
+ fsel. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel. 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000
|
|
+ fsel. 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300
|
|
+ fsel. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
|
|
+ fsel. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000
|
|
+ fsel. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300
|
|
+ fsel. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
|
|
+ fsel. bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fsel. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fsel. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100
|
|
+ fmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00
|
|
+ fmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000
|
|
+ fmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100
|
|
+ fmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+
|
|
+ fmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
|
|
+ fmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
|
|
+ fmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00
|
|
+ fmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100
|
|
+ fmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000
|
|
+ fmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00
|
|
+ fmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+
|
|
+ fmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+
|
|
+ fnmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
|
|
+ fnmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
|
|
+ fnmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100
|
|
+ fnmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00
|
|
+ fnmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000
|
|
+ fnmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100
|
|
+ fnmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+
|
|
+ fnmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+
|
|
+ fnmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fnmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fnmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00
|
|
+ fnmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100
|
|
+ fnmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000
|
|
+ fnmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00
|
|
+ fnmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fnmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+
|
|
+PPC floating point arith insns with two args:
|
|
+ fadd 0010000000000001, 0010000000000001 => 0020000000000001
|
|
+ fadd 0010000000000001, 80100094e0000359 => 80000094e0000358
|
|
+ fadd 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadd 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
|
|
+ fadd 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
|
|
+ fadd 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fadd bfe0000000000001, 0010000000000001 => bfe0000000000001
|
|
+ fadd bfe0000000000001, 80100094e0000359 => bfe0000000000001
|
|
+ fadd bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadd 8000000000000000, 0010000000000001 => 0010000000000001
|
|
+ fadd 8000000000000000, 80100094e0000359 => 80100094e0000359
|
|
+ fadd 8000000000000000, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fadd 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fadd 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fadd 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fadd 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fadd fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fadd fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fadd fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fadd fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fadds 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fadds 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fadds 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadds 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
|
|
+ fadds 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
|
|
+ fadds 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fadds bfe0000000000001, 0010000000000001 => bfe0000000000000
|
|
+ fadds bfe0000000000001, 80100094e0000359 => bfe0000000000000
|
|
+ fadds bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadds 8000000000000000, 0010000000000001 => 0000000000000000
|
|
+ fadds 8000000000000000, 80100094e0000359 => 8000000000000000
|
|
+ fadds 8000000000000000, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fadds 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fadds 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fadds 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fadds 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fadds fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fadds fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fadds fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fadds fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fsub 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fsub 0010000000000001, 80100094e0000359 => 0020004a700001ad
|
|
+ fsub 0010000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsub 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsub 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
|
|
+ fsub 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
|
|
+ fsub 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
|
|
+ fsub 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fsub bfe0000000000001, 0010000000000001 => bfe0000000000001
|
|
+ fsub bfe0000000000001, 80100094e0000359 => bfe0000000000001
|
|
+ fsub bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsub bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsub 8000000000000000, 0010000000000001 => 8010000000000001
|
|
+ fsub 8000000000000000, 80100094e0000359 => 00100094e0000359
|
|
+ fsub 8000000000000000, 7ff0000000000000 => fff0000000000000
|
|
+ fsub 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fsub 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fsub 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fsub 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fsub 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fsub fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fsub fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fsub fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fsub fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fsubs 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fsubs 0010000000000001, 80100094e0000359 => 0000000000000000
|
|
+ fsubs 0010000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsubs 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
|
|
+ fsubs 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
|
|
+ fsubs 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fsubs bfe0000000000001, 0010000000000001 => bfe0000000000000
|
|
+ fsubs bfe0000000000001, 80100094e0000359 => bfe0000000000000
|
|
+ fsubs bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsubs 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fsubs 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fsubs 8000000000000000, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fsubs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fsubs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fsubs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fsubs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fsubs fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fsubs fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fsubs fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fsubs fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fmul 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmul 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fmul 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmul 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmul 3fe00094e0000359, 0010000000000001 => 0008004a700001ad
|
|
+ fmul 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179
|
|
+ fmul 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmul 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fmul bfe0000000000001, 0010000000000001 => 8008000000000001
|
|
+ fmul bfe0000000000001, 80100094e0000359 => 0008004a700001ad
|
|
+ fmul bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fmul bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmul 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fmul 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fmul 8000000000000000, 7ff0000000000000 => 7ff8000000000000
|
|
+ fmul 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fmul 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fmul 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fmul 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fmul 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fmul fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fmul fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fmul fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fmul fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fmuls 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmuls 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fmuls 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmuls 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmuls 3fe00094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmuls 3fe00094e0000359, 80100094e0000359 => 8000000000000000
|
|
+ fmuls 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmuls 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fmuls bfe0000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmuls bfe0000000000001, 80100094e0000359 => 0000000000000000
|
|
+ fmuls bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fmuls bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmuls 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fmuls 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fmuls 8000000000000000, 7ff0000000000000 => 7ff8000000000000
|
|
+ fmuls 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fmuls 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fmuls 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fmuls 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fmuls 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fmuls fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fmuls fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fmuls fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fmuls fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fdiv 0010000000000001, 0010000000000001 => 3ff0000000000000
|
|
+ fdiv 0010000000000001, 80100094e0000359 => bfeffed64ad20d22
|
|
+ fdiv 0010000000000001, 7ff0000000000000 => 0000000000000000
|
|
+ fdiv 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdiv 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358
|
|
+ fdiv 3fe00094e0000359, 80100094e0000359 => ffc0000000000000
|
|
+ fdiv 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
|
|
+ fdiv 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fdiv bfe0000000000001, 0010000000000001 => ffc0000000000000
|
|
+ fdiv bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22
|
|
+ fdiv bfe0000000000001, 7ff0000000000000 => 8000000000000000
|
|
+ fdiv bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdiv 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fdiv 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fdiv 8000000000000000, 7ff0000000000000 => 8000000000000000
|
|
+ fdiv 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fdiv 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fdiv 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fdiv 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fdiv 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fdiv fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fdiv fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fdiv fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fdiv fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fdivs 0010000000000001, 0010000000000001 => 3ff0000000000000
|
|
+ fdivs 0010000000000001, 80100094e0000359 => bfeffed640000000
|
|
+ fdivs 0010000000000001, 7ff0000000000000 => 0000000000000000
|
|
+ fdivs 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdivs 3fe00094e0000359, 0010000000000001 => 7ff0000000000000
|
|
+ fdivs 3fe00094e0000359, 80100094e0000359 => fff0000000000000
|
|
+ fdivs 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
|
|
+ fdivs 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fdivs bfe0000000000001, 0010000000000001 => fff0000000000000
|
|
+ fdivs bfe0000000000001, 80100094e0000359 => 7ff0000000000000
|
|
+ fdivs bfe0000000000001, 7ff0000000000000 => 8000000000000000
|
|
+ fdivs bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdivs 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fdivs 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fdivs 8000000000000000, 7ff0000000000000 => 8000000000000000
|
|
+ fdivs 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fdivs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fdivs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fdivs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fdivs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fdivs fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fdivs fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fdivs fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fdivs fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+PPC floating point arith insns
|
|
+ with two args with flags update:
|
|
+ fadd. 0010000000000001, 0010000000000001 => 0020000000000001
|
|
+ fadd. 0010000000000001, 80100094e0000359 => 80000094e0000358
|
|
+ fadd. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadd. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
|
|
+ fadd. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
|
|
+ fadd. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fadd. bfe0000000000001, 0010000000000001 => bfe0000000000001
|
|
+ fadd. bfe0000000000001, 80100094e0000359 => bfe0000000000001
|
|
+ fadd. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadd. 8000000000000000, 0010000000000001 => 0010000000000001
|
|
+ fadd. 8000000000000000, 80100094e0000359 => 80100094e0000359
|
|
+ fadd. 8000000000000000, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fadd. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fadd. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fadd. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fadd. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fadd. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fadd. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fadd. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fadd. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fadds. 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fadds. 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fadds. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadds. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
|
|
+ fadds. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
|
|
+ fadds. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fadds. bfe0000000000001, 0010000000000001 => bfe0000000000000
|
|
+ fadds. bfe0000000000001, 80100094e0000359 => bfe0000000000000
|
|
+ fadds. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadds. 8000000000000000, 0010000000000001 => 0000000000000000
|
|
+ fadds. 8000000000000000, 80100094e0000359 => 8000000000000000
|
|
+ fadds. 8000000000000000, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fadds. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fadds. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fadds. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fadds. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fadds. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fadds. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fadds. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fadds. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fsub. 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fsub. 0010000000000001, 80100094e0000359 => 0020004a700001ad
|
|
+ fsub. 0010000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsub. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsub. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
|
|
+ fsub. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
|
|
+ fsub. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
|
|
+ fsub. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fsub. bfe0000000000001, 0010000000000001 => bfe0000000000001
|
|
+ fsub. bfe0000000000001, 80100094e0000359 => bfe0000000000001
|
|
+ fsub. bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsub. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsub. 8000000000000000, 0010000000000001 => 8010000000000001
|
|
+ fsub. 8000000000000000, 80100094e0000359 => 00100094e0000359
|
|
+ fsub. 8000000000000000, 7ff0000000000000 => fff0000000000000
|
|
+ fsub. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fsub. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fsub. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fsub. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fsub. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fsub. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fsub. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fsub. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fsub. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fsubs. 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fsubs. 0010000000000001, 80100094e0000359 => 0000000000000000
|
|
+ fsubs. 0010000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsubs. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
|
|
+ fsubs. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
|
|
+ fsubs. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fsubs. bfe0000000000001, 0010000000000001 => bfe0000000000000
|
|
+ fsubs. bfe0000000000001, 80100094e0000359 => bfe0000000000000
|
|
+ fsubs. bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsubs. 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fsubs. 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fsubs. 8000000000000000, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fsubs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fsubs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fsubs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fsubs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fsubs. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fsubs. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fsubs. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fsubs. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fmul. 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmul. 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fmul. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmul. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmul. 3fe00094e0000359, 0010000000000001 => 0008004a700001ad
|
|
+ fmul. 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179
|
|
+ fmul. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmul. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fmul. bfe0000000000001, 0010000000000001 => 8008000000000001
|
|
+ fmul. bfe0000000000001, 80100094e0000359 => 0008004a700001ad
|
|
+ fmul. bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fmul. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmul. 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fmul. 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fmul. 8000000000000000, 7ff0000000000000 => 7ff8000000000000
|
|
+ fmul. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fmul. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fmul. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fmul. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fmul. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fmul. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fmul. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fmul. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fmul. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fmuls. 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmuls. 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fmuls. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmuls. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmuls. 3fe00094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmuls. 3fe00094e0000359, 80100094e0000359 => 8000000000000000
|
|
+ fmuls. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmuls. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fmuls. bfe0000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmuls. bfe0000000000001, 80100094e0000359 => 0000000000000000
|
|
+ fmuls. bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fmuls. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmuls. 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fmuls. 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fmuls. 8000000000000000, 7ff0000000000000 => 7ff8000000000000
|
|
+ fmuls. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fmuls. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fmuls. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fmuls. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fmuls. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fmuls. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fmuls. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fmuls. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fmuls. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fdiv. 0010000000000001, 0010000000000001 => 3ff0000000000000
|
|
+ fdiv. 0010000000000001, 80100094e0000359 => bfeffed64ad20d22
|
|
+ fdiv. 0010000000000001, 7ff0000000000000 => 0000000000000000
|
|
+ fdiv. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdiv. 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358
|
|
+ fdiv. 3fe00094e0000359, 80100094e0000359 => ffc0000000000000
|
|
+ fdiv. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
|
|
+ fdiv. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fdiv. bfe0000000000001, 0010000000000001 => ffc0000000000000
|
|
+ fdiv. bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22
|
|
+ fdiv. bfe0000000000001, 7ff0000000000000 => 8000000000000000
|
|
+ fdiv. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdiv. 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fdiv. 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fdiv. 8000000000000000, 7ff0000000000000 => 8000000000000000
|
|
+ fdiv. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fdiv. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fdiv. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fdiv. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fdiv. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fdiv. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fdiv. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fdiv. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fdiv. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fdivs. 0010000000000001, 0010000000000001 => 3ff0000000000000
|
|
+ fdivs. 0010000000000001, 80100094e0000359 => bfeffed640000000
|
|
+ fdivs. 0010000000000001, 7ff0000000000000 => 0000000000000000
|
|
+ fdivs. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdivs. 3fe00094e0000359, 0010000000000001 => 7ff0000000000000
|
|
+ fdivs. 3fe00094e0000359, 80100094e0000359 => fff0000000000000
|
|
+ fdivs. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
|
|
+ fdivs. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fdivs. bfe0000000000001, 0010000000000001 => fff0000000000000
|
|
+ fdivs. bfe0000000000001, 80100094e0000359 => 7ff0000000000000
|
|
+ fdivs. bfe0000000000001, 7ff0000000000000 => 8000000000000000
|
|
+ fdivs. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdivs. 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fdivs. 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fdivs. 8000000000000000, 7ff0000000000000 => 8000000000000000
|
|
+ fdivs. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fdivs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fdivs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fdivs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fdivs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fdivs. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fdivs. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fdivs. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fdivs. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+PPC floating point compare insns (two args):
|
|
+ fcmpo 0010000000000001, 0010000000000001 => fff8000000000000
|
|
+ fcmpo 0010000000000001, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo 0010000000000001, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fcmpo 3fe00094e0000359, 0010000000000001 => fff8000000000000
|
|
+ fcmpo 3fe00094e0000359, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo 3fe00094e0000359, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fcmpo bfe0000000000001, 0010000000000001 => fff8000000000000
|
|
+ fcmpo bfe0000000000001, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo bfe0000000000001, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fcmpo 8000000000000000, 0010000000000001 => fff8000000000000
|
|
+ fcmpo 8000000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo 8000000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fcmpo 7ff7ffffffffffff, 0010000000000001 => fff8000000000000
|
|
+ fcmpo 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo 7ff7ffffffffffff, fff8000000000000 => fff8000000000000
|
|
+ fcmpo fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fcmpo fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fcmpu 0010000000000001, 0010000000000001 => fff8000000000000
|
|
+ fcmpu 0010000000000001, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu 0010000000000001, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fcmpu 3fe00094e0000359, 0010000000000001 => fff8000000000000
|
|
+ fcmpu 3fe00094e0000359, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu 3fe00094e0000359, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fcmpu bfe0000000000001, 0010000000000001 => fff8000000000000
|
|
+ fcmpu bfe0000000000001, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu bfe0000000000001, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fcmpu 8000000000000000, 0010000000000001 => fff8000000000000
|
|
+ fcmpu 8000000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu 8000000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fcmpu 7ff7ffffffffffff, 0010000000000001 => fff8000000000000
|
|
+ fcmpu 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu 7ff7ffffffffffff, fff8000000000000 => fff8000000000000
|
|
+ fcmpu fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fcmpu fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+PPC floating point arith insns with one arg:
|
|
+ fres 0010000000000001 => 7ff0000000000000
|
|
+ fres 00100094e0000359 => 7ff0000000000000
|
|
+ fres 3fe0000000000001 => 4000000000000000
|
|
+ fres 3fe00094e0000359 => 3ffff00000000000
|
|
+ fres 8010000000000001 => fff0000000000000
|
|
+ fres 80100094e0000359 => fff0000000000000
|
|
+ fres bfe0000000000001 => c000000000000000
|
|
+ fres bfe00094e0000359 => bffff00000000000
|
|
+ fres 0000000000000000 => 7ff0000000000000
|
|
+ fres 8000000000000000 => fff0000000000000
|
|
+ fres 7ff0000000000000 => 0000000000000000
|
|
+ fres fff0000000000000 => 8000000000000000
|
|
+ fres 7ff7ffffffffffff => 7ffff00000000000
|
|
+ fres fff7ffffffffffff => fffff00000000000
|
|
+ fres 7ff8000000000000 => 7ff8000000000000
|
|
+ fres fff8000000000000 => fff8000000000000
|
|
+
|
|
+ frsqrte 0010000000000001 => 5fdf000000000000
|
|
+ frsqrte 00100094e0000359 => 5fdf000000000000
|
|
+ frsqrte 3fe0000000000001 => 3ff6000000000000
|
|
+ frsqrte 3fe00094e0000359 => 3ff6000000000000
|
|
+ frsqrte 8010000000000001 => 7ff8000000000000
|
|
+ frsqrte 80100094e0000359 => 7ff8000000000000
|
|
+ frsqrte bfe0000000000001 => 7ff8000000000000
|
|
+ frsqrte bfe00094e0000359 => 7ff8000000000000
|
|
+ frsqrte 0000000000000000 => 7ff0000000000000
|
|
+ frsqrte 8000000000000000 => fff0000000000000
|
|
+ frsqrte 7ff0000000000000 => 0000000000000000
|
|
+ frsqrte fff0000000000000 => 7ff8000000000000
|
|
+ frsqrte 7ff7ffffffffffff => 7fff000000000000
|
|
+ frsqrte fff7ffffffffffff => ffff000000000000
|
|
+ frsqrte 7ff8000000000000 => 7ff8000000000000
|
|
+ frsqrte fff8000000000000 => fff8000000000000
|
|
+
|
|
+ frsp 0010000000000001 => 0000000000000000
|
|
+ frsp 00100094e0000359 => 0000000000000000
|
|
+ frsp 3fe0000000000001 => 3fe0000000000000
|
|
+ frsp 3fe00094e0000359 => 3fe00094e0000000
|
|
+ frsp 8010000000000001 => 8000000000000000
|
|
+ frsp 80100094e0000359 => 8000000000000000
|
|
+ frsp bfe0000000000001 => bfe0000000000000
|
|
+ frsp bfe00094e0000359 => bfe00094e0000000
|
|
+ frsp 0000000000000000 => 0000000000000000
|
|
+ frsp 8000000000000000 => 8000000000000000
|
|
+ frsp 7ff0000000000000 => 7ff0000000000000
|
|
+ frsp fff0000000000000 => fff0000000000000
|
|
+ frsp 7ff7ffffffffffff => 7fffffffe0000000
|
|
+ frsp fff7ffffffffffff => ffffffffe0000000
|
|
+ frsp 7ff8000000000000 => 7ff8000000000000
|
|
+ frsp fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fctiw 0010000000000001 => 0000000000000000
|
|
+ fctiw 00100094e0000359 => 0000000000000000
|
|
+ fctiw 3fe0000000000001 => 0000000000000001
|
|
+ fctiw 3fe00094e0000359 => 0000000000000001
|
|
+ fctiw 8010000000000001 => 0000000000000000
|
|
+ fctiw 80100094e0000359 => 0000000000000000
|
|
+ fctiw bfe0000000000001 => 00000000ffffffff
|
|
+ fctiw bfe00094e0000359 => 00000000ffffffff
|
|
+ fctiw 0000000000000000 => 0000000000000000
|
|
+ fctiw 8000000000000000 => 0000000000000000
|
|
+ fctiw 7ff0000000000000 => 000000007fffffff
|
|
+ fctiw fff0000000000000 => 0000000080000000
|
|
+ fctiw 7ff7ffffffffffff => 0000000080000000
|
|
+ fctiw fff7ffffffffffff => 0000000080000000
|
|
+ fctiw 7ff8000000000000 => 0000000080000000
|
|
+ fctiw fff8000000000000 => 0000000080000000
|
|
+
|
|
+ fctiwz 0010000000000001 => 0000000000000000
|
|
+ fctiwz 00100094e0000359 => 0000000000000000
|
|
+ fctiwz 3fe0000000000001 => 0000000000000000
|
|
+ fctiwz 3fe00094e0000359 => 0000000000000000
|
|
+ fctiwz 8010000000000001 => 0000000000000000
|
|
+ fctiwz 80100094e0000359 => 0000000000000000
|
|
+ fctiwz bfe0000000000001 => 0000000000000000
|
|
+ fctiwz bfe00094e0000359 => 0000000000000000
|
|
+ fctiwz 0000000000000000 => 0000000000000000
|
|
+ fctiwz 8000000000000000 => 0000000000000000
|
|
+ fctiwz 7ff0000000000000 => 000000007fffffff
|
|
+ fctiwz fff0000000000000 => 0000000080000000
|
|
+ fctiwz 7ff7ffffffffffff => 0000000080000000
|
|
+ fctiwz fff7ffffffffffff => 0000000080000000
|
|
+ fctiwz 7ff8000000000000 => 0000000080000000
|
|
+ fctiwz fff8000000000000 => 0000000080000000
|
|
+
|
|
+ fmr 0010000000000001 => 0010000000000001
|
|
+ fmr 00100094e0000359 => 00100094e0000359
|
|
+ fmr 3fe0000000000001 => 3fe0000000000001
|
|
+ fmr 3fe00094e0000359 => 3fe00094e0000359
|
|
+ fmr 8010000000000001 => 8010000000000001
|
|
+ fmr 80100094e0000359 => 80100094e0000359
|
|
+ fmr bfe0000000000001 => bfe0000000000001
|
|
+ fmr bfe00094e0000359 => bfe00094e0000359
|
|
+ fmr 0000000000000000 => 0000000000000000
|
|
+ fmr 8000000000000000 => 8000000000000000
|
|
+ fmr 7ff0000000000000 => 7ff0000000000000
|
|
+ fmr fff0000000000000 => fff0000000000000
|
|
+ fmr 7ff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fmr fff7ffffffffffff => fff7ffffffffffff
|
|
+ fmr 7ff8000000000000 => 7ff8000000000000
|
|
+ fmr fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fneg 0010000000000001 => 8010000000000001
|
|
+ fneg 00100094e0000359 => 80100094e0000359
|
|
+ fneg 3fe0000000000001 => bfe0000000000001
|
|
+ fneg 3fe00094e0000359 => bfe00094e0000359
|
|
+ fneg 8010000000000001 => 0010000000000001
|
|
+ fneg 80100094e0000359 => 00100094e0000359
|
|
+ fneg bfe0000000000001 => 3fe0000000000001
|
|
+ fneg bfe00094e0000359 => 3fe00094e0000359
|
|
+ fneg 0000000000000000 => 8000000000000000
|
|
+ fneg 8000000000000000 => 0000000000000000
|
|
+ fneg 7ff0000000000000 => fff0000000000000
|
|
+ fneg fff0000000000000 => 7ff0000000000000
|
|
+ fneg 7ff7ffffffffffff => fff7ffffffffffff
|
|
+ fneg fff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fneg 7ff8000000000000 => fff8000000000000
|
|
+ fneg fff8000000000000 => 7ff8000000000000
|
|
+
|
|
+ fabs 0010000000000001 => 0010000000000001
|
|
+ fabs 00100094e0000359 => 00100094e0000359
|
|
+ fabs 3fe0000000000001 => 3fe0000000000001
|
|
+ fabs 3fe00094e0000359 => 3fe00094e0000359
|
|
+ fabs 8010000000000001 => 0010000000000001
|
|
+ fabs 80100094e0000359 => 00100094e0000359
|
|
+ fabs bfe0000000000001 => 3fe0000000000001
|
|
+ fabs bfe00094e0000359 => 3fe00094e0000359
|
|
+ fabs 0000000000000000 => 0000000000000000
|
|
+ fabs 8000000000000000 => 0000000000000000
|
|
+ fabs 7ff0000000000000 => 7ff0000000000000
|
|
+ fabs fff0000000000000 => 7ff0000000000000
|
|
+ fabs 7ff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fabs fff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fabs 7ff8000000000000 => 7ff8000000000000
|
|
+ fabs fff8000000000000 => 7ff8000000000000
|
|
+
|
|
+ fnabs 0010000000000001 => 8010000000000001
|
|
+ fnabs 00100094e0000359 => 80100094e0000359
|
|
+ fnabs 3fe0000000000001 => bfe0000000000001
|
|
+ fnabs 3fe00094e0000359 => bfe00094e0000359
|
|
+ fnabs 8010000000000001 => 8010000000000001
|
|
+ fnabs 80100094e0000359 => 80100094e0000359
|
|
+ fnabs bfe0000000000001 => bfe0000000000001
|
|
+ fnabs bfe00094e0000359 => bfe00094e0000359
|
|
+ fnabs 0000000000000000 => 8000000000000000
|
|
+ fnabs 8000000000000000 => 8000000000000000
|
|
+ fnabs 7ff0000000000000 => fff0000000000000
|
|
+ fnabs fff0000000000000 => fff0000000000000
|
|
+ fnabs 7ff7ffffffffffff => fff7ffffffffffff
|
|
+ fnabs fff7ffffffffffff => fff7ffffffffffff
|
|
+ fnabs 7ff8000000000000 => fff8000000000000
|
|
+ fnabs fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fsqrt 0010000000000001 => 2000000000000000
|
|
+ fsqrt 00100094e0000359 => 2000004a6f52dd4a
|
|
+ fsqrt 3fe0000000000001 => 3fe6a09e667f3bcd
|
|
+ fsqrt 3fe00094e0000359 => 3fe6a107aacb50df
|
|
+ fsqrt 8010000000000001 => 7ff8000000000000
|
|
+ fsqrt 80100094e0000359 => 7ff8000000000000
|
|
+ fsqrt bfe0000000000001 => 7ff8000000000000
|
|
+ fsqrt bfe00094e0000359 => 7ff8000000000000
|
|
+ fsqrt 0000000000000000 => 0000000000000000
|
|
+ fsqrt 8000000000000000 => 8000000000000000
|
|
+ fsqrt 7ff0000000000000 => 7ff0000000000000
|
|
+ fsqrt fff0000000000000 => 7ff8000000000000
|
|
+ fsqrt 7ff7ffffffffffff => 7fffffffffffffff
|
|
+ fsqrt fff7ffffffffffff => ffffffffffffffff
|
|
+ fsqrt 7ff8000000000000 => 7ff8000000000000
|
|
+ fsqrt fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fcfid 0010000000000001 => 4330000000000001
|
|
+ fcfid 00100094e0000359 => 43300094e0000359
|
|
+ fcfid 3fe0000000000001 => 43cff00000000000
|
|
+ fcfid 3fe00094e0000359 => 43cff0004a700002
|
|
+ fcfid 8010000000000001 => c3dffc0000000000
|
|
+ fcfid 80100094e0000359 => c3dffbffdac7ffff
|
|
+ fcfid bfe0000000000001 => c3d0080000000000
|
|
+ fcfid bfe00094e0000359 => c3d007ffdac7ffff
|
|
+ fcfid 0000000000000000 => 0000000000000000
|
|
+ fcfid 8000000000000000 => c3e0000000000000
|
|
+ fcfid 7ff0000000000000 => 43dffc0000000000
|
|
+ fcfid fff0000000000000 => c330000000000000
|
|
+ fcfid 7ff7ffffffffffff => 43dffe0000000000
|
|
+ fcfid fff7ffffffffffff => c320000000000002
|
|
+ fcfid 7ff8000000000000 => 43dffe0000000000
|
|
+ fcfid fff8000000000000 => c320000000000000
|
|
+
|
|
+ fctid 0010000000000001 => 0000000000000000
|
|
+ fctid 00100094e0000359 => 0000000000000000
|
|
+ fctid 3fe0000000000001 => 0000000000000001
|
|
+ fctid 3fe00094e0000359 => 0000000000000001
|
|
+ fctid 8010000000000001 => 0000000000000000
|
|
+ fctid 80100094e0000359 => 0000000000000000
|
|
+ fctid bfe0000000000001 => ffffffffffffffff
|
|
+ fctid bfe00094e0000359 => ffffffffffffffff
|
|
+ fctid 0000000000000000 => 0000000000000000
|
|
+ fctid 8000000000000000 => 0000000000000000
|
|
+ fctid 7ff0000000000000 => 7fffffffffffffff
|
|
+ fctid fff0000000000000 => 8000000000000000
|
|
+ fctid 7ff7ffffffffffff => 8000000000000000
|
|
+ fctid fff7ffffffffffff => 8000000000000000
|
|
+ fctid 7ff8000000000000 => 8000000000000000
|
|
+ fctid fff8000000000000 => 8000000000000000
|
|
+
|
|
+ fctidz 0010000000000001 => 0000000000000000
|
|
+ fctidz 00100094e0000359 => 0000000000000000
|
|
+ fctidz 3fe0000000000001 => 0000000000000000
|
|
+ fctidz 3fe00094e0000359 => 0000000000000000
|
|
+ fctidz 8010000000000001 => 0000000000000000
|
|
+ fctidz 80100094e0000359 => 0000000000000000
|
|
+ fctidz bfe0000000000001 => 0000000000000000
|
|
+ fctidz bfe00094e0000359 => 0000000000000000
|
|
+ fctidz 0000000000000000 => 0000000000000000
|
|
+ fctidz 8000000000000000 => 0000000000000000
|
|
+ fctidz 7ff0000000000000 => 7fffffffffffffff
|
|
+ fctidz fff0000000000000 => 8000000000000000
|
|
+ fctidz 7ff7ffffffffffff => 8000000000000000
|
|
+ fctidz fff7ffffffffffff => 8000000000000000
|
|
+ fctidz 7ff8000000000000 => 8000000000000000
|
|
+ fctidz fff8000000000000 => 8000000000000000
|
|
+
|
|
+PPC floating point arith insns
|
|
+ with one arg with flags update:
|
|
+ fres. 0010000000000001 => 7ff0000000000000
|
|
+ fres. 00100094e0000359 => 7ff0000000000000
|
|
+ fres. 3fe0000000000001 => 4000000000000000
|
|
+ fres. 3fe00094e0000359 => 3ffff00000000000
|
|
+ fres. 8010000000000001 => fff0000000000000
|
|
+ fres. 80100094e0000359 => fff0000000000000
|
|
+ fres. bfe0000000000001 => c000000000000000
|
|
+ fres. bfe00094e0000359 => bffff00000000000
|
|
+ fres. 0000000000000000 => 7ff0000000000000
|
|
+ fres. 8000000000000000 => fff0000000000000
|
|
+ fres. 7ff0000000000000 => 0000000000000000
|
|
+ fres. fff0000000000000 => 8000000000000000
|
|
+ fres. 7ff7ffffffffffff => 7ffff00000000000
|
|
+ fres. fff7ffffffffffff => fffff00000000000
|
|
+ fres. 7ff8000000000000 => 7ff8000000000000
|
|
+ fres. fff8000000000000 => fff8000000000000
|
|
+
|
|
+ frsqrte. 0010000000000001 => 5fdf000000000000
|
|
+ frsqrte. 00100094e0000359 => 5fdf000000000000
|
|
+ frsqrte. 3fe0000000000001 => 3ff6000000000000
|
|
+ frsqrte. 3fe00094e0000359 => 3ff6000000000000
|
|
+ frsqrte. 8010000000000001 => 7ff8000000000000
|
|
+ frsqrte. 80100094e0000359 => 7ff8000000000000
|
|
+ frsqrte. bfe0000000000001 => 7ff8000000000000
|
|
+ frsqrte. bfe00094e0000359 => 7ff8000000000000
|
|
+ frsqrte. 0000000000000000 => 7ff0000000000000
|
|
+ frsqrte. 8000000000000000 => fff0000000000000
|
|
+ frsqrte. 7ff0000000000000 => 0000000000000000
|
|
+ frsqrte. fff0000000000000 => 7ff8000000000000
|
|
+ frsqrte. 7ff7ffffffffffff => 7fff000000000000
|
|
+ frsqrte. fff7ffffffffffff => ffff000000000000
|
|
+ frsqrte. 7ff8000000000000 => 7ff8000000000000
|
|
+ frsqrte. fff8000000000000 => fff8000000000000
|
|
+
|
|
+ frsp. 0010000000000001 => 0000000000000000
|
|
+ frsp. 00100094e0000359 => 0000000000000000
|
|
+ frsp. 3fe0000000000001 => 3fe0000000000000
|
|
+ frsp. 3fe00094e0000359 => 3fe00094e0000000
|
|
+ frsp. 8010000000000001 => 8000000000000000
|
|
+ frsp. 80100094e0000359 => 8000000000000000
|
|
+ frsp. bfe0000000000001 => bfe0000000000000
|
|
+ frsp. bfe00094e0000359 => bfe00094e0000000
|
|
+ frsp. 0000000000000000 => 0000000000000000
|
|
+ frsp. 8000000000000000 => 8000000000000000
|
|
+ frsp. 7ff0000000000000 => 7ff0000000000000
|
|
+ frsp. fff0000000000000 => fff0000000000000
|
|
+ frsp. 7ff7ffffffffffff => 7fffffffe0000000
|
|
+ frsp. fff7ffffffffffff => ffffffffe0000000
|
|
+ frsp. 7ff8000000000000 => 7ff8000000000000
|
|
+ frsp. fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fctiw. 0010000000000001 => 0000000000000000
|
|
+ fctiw. 00100094e0000359 => 0000000000000000
|
|
+ fctiw. 3fe0000000000001 => 0000000000000001
|
|
+ fctiw. 3fe00094e0000359 => 0000000000000001
|
|
+ fctiw. 8010000000000001 => 0000000000000000
|
|
+ fctiw. 80100094e0000359 => 0000000000000000
|
|
+ fctiw. bfe0000000000001 => 00000000ffffffff
|
|
+ fctiw. bfe00094e0000359 => 00000000ffffffff
|
|
+ fctiw. 0000000000000000 => 0000000000000000
|
|
+ fctiw. 8000000000000000 => 0000000000000000
|
|
+ fctiw. 7ff0000000000000 => 000000007fffffff
|
|
+ fctiw. fff0000000000000 => 0000000080000000
|
|
+ fctiw. 7ff7ffffffffffff => 0000000080000000
|
|
+ fctiw. fff7ffffffffffff => 0000000080000000
|
|
+ fctiw. 7ff8000000000000 => 0000000080000000
|
|
+ fctiw. fff8000000000000 => 0000000080000000
|
|
+
|
|
+ fctiwz. 0010000000000001 => 0000000000000000
|
|
+ fctiwz. 00100094e0000359 => 0000000000000000
|
|
+ fctiwz. 3fe0000000000001 => 0000000000000000
|
|
+ fctiwz. 3fe00094e0000359 => 0000000000000000
|
|
+ fctiwz. 8010000000000001 => 0000000000000000
|
|
+ fctiwz. 80100094e0000359 => 0000000000000000
|
|
+ fctiwz. bfe0000000000001 => 0000000000000000
|
|
+ fctiwz. bfe00094e0000359 => 0000000000000000
|
|
+ fctiwz. 0000000000000000 => 0000000000000000
|
|
+ fctiwz. 8000000000000000 => 0000000000000000
|
|
+ fctiwz. 7ff0000000000000 => 000000007fffffff
|
|
+ fctiwz. fff0000000000000 => 0000000080000000
|
|
+ fctiwz. 7ff7ffffffffffff => 0000000080000000
|
|
+ fctiwz. fff7ffffffffffff => 0000000080000000
|
|
+ fctiwz. 7ff8000000000000 => 0000000080000000
|
|
+ fctiwz. fff8000000000000 => 0000000080000000
|
|
+
|
|
+ fmr. 0010000000000001 => 0010000000000001
|
|
+ fmr. 00100094e0000359 => 00100094e0000359
|
|
+ fmr. 3fe0000000000001 => 3fe0000000000001
|
|
+ fmr. 3fe00094e0000359 => 3fe00094e0000359
|
|
+ fmr. 8010000000000001 => 8010000000000001
|
|
+ fmr. 80100094e0000359 => 80100094e0000359
|
|
+ fmr. bfe0000000000001 => bfe0000000000001
|
|
+ fmr. bfe00094e0000359 => bfe00094e0000359
|
|
+ fmr. 0000000000000000 => 0000000000000000
|
|
+ fmr. 8000000000000000 => 8000000000000000
|
|
+ fmr. 7ff0000000000000 => 7ff0000000000000
|
|
+ fmr. fff0000000000000 => fff0000000000000
|
|
+ fmr. 7ff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fmr. fff7ffffffffffff => fff7ffffffffffff
|
|
+ fmr. 7ff8000000000000 => 7ff8000000000000
|
|
+ fmr. fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fneg. 0010000000000001 => 8010000000000001
|
|
+ fneg. 00100094e0000359 => 80100094e0000359
|
|
+ fneg. 3fe0000000000001 => bfe0000000000001
|
|
+ fneg. 3fe00094e0000359 => bfe00094e0000359
|
|
+ fneg. 8010000000000001 => 0010000000000001
|
|
+ fneg. 80100094e0000359 => 00100094e0000359
|
|
+ fneg. bfe0000000000001 => 3fe0000000000001
|
|
+ fneg. bfe00094e0000359 => 3fe00094e0000359
|
|
+ fneg. 0000000000000000 => 8000000000000000
|
|
+ fneg. 8000000000000000 => 0000000000000000
|
|
+ fneg. 7ff0000000000000 => fff0000000000000
|
|
+ fneg. fff0000000000000 => 7ff0000000000000
|
|
+ fneg. 7ff7ffffffffffff => fff7ffffffffffff
|
|
+ fneg. fff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fneg. 7ff8000000000000 => fff8000000000000
|
|
+ fneg. fff8000000000000 => 7ff8000000000000
|
|
+
|
|
+ fabs. 0010000000000001 => 0010000000000001
|
|
+ fabs. 00100094e0000359 => 00100094e0000359
|
|
+ fabs. 3fe0000000000001 => 3fe0000000000001
|
|
+ fabs. 3fe00094e0000359 => 3fe00094e0000359
|
|
+ fabs. 8010000000000001 => 0010000000000001
|
|
+ fabs. 80100094e0000359 => 00100094e0000359
|
|
+ fabs. bfe0000000000001 => 3fe0000000000001
|
|
+ fabs. bfe00094e0000359 => 3fe00094e0000359
|
|
+ fabs. 0000000000000000 => 0000000000000000
|
|
+ fabs. 8000000000000000 => 0000000000000000
|
|
+ fabs. 7ff0000000000000 => 7ff0000000000000
|
|
+ fabs. fff0000000000000 => 7ff0000000000000
|
|
+ fabs. 7ff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fabs. fff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fabs. 7ff8000000000000 => 7ff8000000000000
|
|
+ fabs. fff8000000000000 => 7ff8000000000000
|
|
+
|
|
+ fnabs. 0010000000000001 => 8010000000000001
|
|
+ fnabs. 00100094e0000359 => 80100094e0000359
|
|
+ fnabs. 3fe0000000000001 => bfe0000000000001
|
|
+ fnabs. 3fe00094e0000359 => bfe00094e0000359
|
|
+ fnabs. 8010000000000001 => 8010000000000001
|
|
+ fnabs. 80100094e0000359 => 80100094e0000359
|
|
+ fnabs. bfe0000000000001 => bfe0000000000001
|
|
+ fnabs. bfe00094e0000359 => bfe00094e0000359
|
|
+ fnabs. 0000000000000000 => 8000000000000000
|
|
+ fnabs. 8000000000000000 => 8000000000000000
|
|
+ fnabs. 7ff0000000000000 => fff0000000000000
|
|
+ fnabs. fff0000000000000 => fff0000000000000
|
|
+ fnabs. 7ff7ffffffffffff => fff7ffffffffffff
|
|
+ fnabs. fff7ffffffffffff => fff7ffffffffffff
|
|
+ fnabs. 7ff8000000000000 => fff8000000000000
|
|
+ fnabs. fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fcfid. 0010000000000001 => 4330000000000001
|
|
+ fcfid. 00100094e0000359 => 43300094e0000359
|
|
+ fcfid. 3fe0000000000001 => 43cff00000000000
|
|
+ fcfid. 3fe00094e0000359 => 43cff0004a700002
|
|
+ fcfid. 8010000000000001 => c3dffc0000000000
|
|
+ fcfid. 80100094e0000359 => c3dffbffdac7ffff
|
|
+ fcfid. bfe0000000000001 => c3d0080000000000
|
|
+ fcfid. bfe00094e0000359 => c3d007ffdac7ffff
|
|
+ fcfid. 0000000000000000 => 0000000000000000
|
|
+ fcfid. 8000000000000000 => c3e0000000000000
|
|
+ fcfid. 7ff0000000000000 => 43dffc0000000000
|
|
+ fcfid. fff0000000000000 => c330000000000000
|
|
+ fcfid. 7ff7ffffffffffff => 43dffe0000000000
|
|
+ fcfid. fff7ffffffffffff => c320000000000002
|
|
+ fcfid. 7ff8000000000000 => 43dffe0000000000
|
|
+ fcfid. fff8000000000000 => c320000000000000
|
|
+
|
|
+ fctid. 0010000000000001 => 0000000000000000
|
|
+ fctid. 00100094e0000359 => 0000000000000000
|
|
+ fctid. 3fe0000000000001 => 0000000000000001
|
|
+ fctid. 3fe00094e0000359 => 0000000000000001
|
|
+ fctid. 8010000000000001 => 0000000000000000
|
|
+ fctid. 80100094e0000359 => 0000000000000000
|
|
+ fctid. bfe0000000000001 => ffffffffffffffff
|
|
+ fctid. bfe00094e0000359 => ffffffffffffffff
|
|
+ fctid. 0000000000000000 => 0000000000000000
|
|
+ fctid. 8000000000000000 => 0000000000000000
|
|
+ fctid. 7ff0000000000000 => 7fffffffffffffff
|
|
+ fctid. fff0000000000000 => 8000000000000000
|
|
+ fctid. 7ff7ffffffffffff => 8000000000000000
|
|
+ fctid. fff7ffffffffffff => 8000000000000000
|
|
+ fctid. 7ff8000000000000 => 8000000000000000
|
|
+ fctid. fff8000000000000 => 8000000000000000
|
|
+
|
|
+ fctidz. 0010000000000001 => 0000000000000000
|
|
+ fctidz. 00100094e0000359 => 0000000000000000
|
|
+ fctidz. 3fe0000000000001 => 0000000000000000
|
|
+ fctidz. 3fe00094e0000359 => 0000000000000000
|
|
+ fctidz. 8010000000000001 => 0000000000000000
|
|
+ fctidz. 80100094e0000359 => 0000000000000000
|
|
+ fctidz. bfe0000000000001 => 0000000000000000
|
|
+ fctidz. bfe00094e0000359 => 0000000000000000
|
|
+ fctidz. 0000000000000000 => 0000000000000000
|
|
+ fctidz. 8000000000000000 => 0000000000000000
|
|
+ fctidz. 7ff0000000000000 => 7fffffffffffffff
|
|
+ fctidz. fff0000000000000 => 8000000000000000
|
|
+ fctidz. 7ff7ffffffffffff => 8000000000000000
|
|
+ fctidz. fff7ffffffffffff => 8000000000000000
|
|
+ fctidz. 7ff8000000000000 => 8000000000000000
|
|
+ fctidz. fff8000000000000 => 8000000000000000
|
|
+
|
|
+PPC floating point status register manipulation insns:
|
|
+PPC floating point status register manipulation insns
|
|
+ with flags update:
|
|
+PPC float load insns
|
|
+ with one register + one 16 bits immediate args with flags update:
|
|
+ lfs 0010000000000001, 65416 => 37e0000000000000, 0
|
|
+ lfs 00100094e0000359, 65424 => 37e0009400000000, 0
|
|
+ lfs 3fe0000000000001, 65432 => 3ffc000000000000, 0
|
|
+ lfs 3fe00094e0000359, 65440 => 3ffc001280000000, 0
|
|
+ lfs 8010000000000001, 65448 => b7e0000000000000, 0
|
|
+ lfs 80100094e0000359, 65456 => b7e0009400000000, 0
|
|
+ lfs bfe0000000000001, 65464 => bffc000000000000, 0
|
|
+ lfs bfe00094e0000359, 65472 => bffc001280000000, 0
|
|
+ lfs 0000000000000000, 65480 => 0000000000000000, 0
|
|
+ lfs 8000000000000000, 65488 => 8000000000000000, 0
|
|
+ lfs 7ff0000000000000, 65496 => 7ffe000000000000, 0
|
|
+ lfs fff0000000000000, 65504 => fffe000000000000, 0
|
|
+ lfs 7ff7ffffffffffff, 65512 => 7ffeffffe0000000, 0
|
|
+ lfs fff7ffffffffffff, 65520 => fffeffffe0000000, 0
|
|
+ lfs 7ff8000000000000, 65528 => 7fff000000000000, 0
|
|
+ lfs 0010000000000001, 0 => 37e0000000000000, 0
|
|
+ lfs 00100094e0000359, 8 => 37e0009400000000, 0
|
|
+ lfs 3fe0000000000001, 16 => 3ffc000000000000, 0
|
|
+ lfs 3fe00094e0000359, 24 => 3ffc001280000000, 0
|
|
+ lfs 8010000000000001, 32 => b7e0000000000000, 0
|
|
+ lfs 80100094e0000359, 40 => b7e0009400000000, 0
|
|
+ lfs bfe0000000000001, 48 => bffc000000000000, 0
|
|
+ lfs bfe00094e0000359, 56 => bffc001280000000, 0
|
|
+ lfs 0000000000000000, 64 => 0000000000000000, 0
|
|
+ lfs 8000000000000000, 72 => 8000000000000000, 0
|
|
+ lfs 7ff0000000000000, 80 => 7ffe000000000000, 0
|
|
+ lfs fff0000000000000, 88 => fffe000000000000, 0
|
|
+ lfs 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 0
|
|
+ lfs fff7ffffffffffff, 104 => fffeffffe0000000, 0
|
|
+ lfs 7ff8000000000000, 112 => 7fff000000000000, 0
|
|
+ lfs fff8000000000000, 120 => ffff000000000000, 0
|
|
+
|
|
+ lfsu 0010000000000001, 65416 => 37e0000000000000, -120
|
|
+ lfsu 00100094e0000359, 65424 => 37e0009400000000, -112
|
|
+ lfsu 3fe0000000000001, 65432 => 3ffc000000000000, -104
|
|
+ lfsu 3fe00094e0000359, 65440 => 3ffc001280000000, -96
|
|
+ lfsu 8010000000000001, 65448 => b7e0000000000000, -88
|
|
+ lfsu 80100094e0000359, 65456 => b7e0009400000000, -80
|
|
+ lfsu bfe0000000000001, 65464 => bffc000000000000, -72
|
|
+ lfsu bfe00094e0000359, 65472 => bffc001280000000, -64
|
|
+ lfsu 0000000000000000, 65480 => 0000000000000000, -56
|
|
+ lfsu 8000000000000000, 65488 => 8000000000000000, -48
|
|
+ lfsu 7ff0000000000000, 65496 => 7ffe000000000000, -40
|
|
+ lfsu fff0000000000000, 65504 => fffe000000000000, -32
|
|
+ lfsu 7ff7ffffffffffff, 65512 => 7ffeffffe0000000, -24
|
|
+ lfsu fff7ffffffffffff, 65520 => fffeffffe0000000, -16
|
|
+ lfsu 7ff8000000000000, 65528 => 7fff000000000000, -8
|
|
+ lfsu 0010000000000001, 0 => 37e0000000000000, 0
|
|
+ lfsu 00100094e0000359, 8 => 37e0009400000000, 8
|
|
+ lfsu 3fe0000000000001, 16 => 3ffc000000000000, 16
|
|
+ lfsu 3fe00094e0000359, 24 => 3ffc001280000000, 24
|
|
+ lfsu 8010000000000001, 32 => b7e0000000000000, 32
|
|
+ lfsu 80100094e0000359, 40 => b7e0009400000000, 40
|
|
+ lfsu bfe0000000000001, 48 => bffc000000000000, 48
|
|
+ lfsu bfe00094e0000359, 56 => bffc001280000000, 56
|
|
+ lfsu 0000000000000000, 64 => 0000000000000000, 64
|
|
+ lfsu 8000000000000000, 72 => 8000000000000000, 72
|
|
+ lfsu 7ff0000000000000, 80 => 7ffe000000000000, 80
|
|
+ lfsu fff0000000000000, 88 => fffe000000000000, 88
|
|
+ lfsu 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 96
|
|
+ lfsu fff7ffffffffffff, 104 => fffeffffe0000000, 104
|
|
+ lfsu 7ff8000000000000, 112 => 7fff000000000000, 112
|
|
+ lfsu fff8000000000000, 120 => ffff000000000000, 120
|
|
+
|
|
+ lfd 0010000000000001, 65416 => 0010000000000001, 0
|
|
+ lfd 00100094e0000359, 65424 => 00100094e0000359, 0
|
|
+ lfd 3fe0000000000001, 65432 => 3fe0000000000001, 0
|
|
+ lfd 3fe00094e0000359, 65440 => 3fe00094e0000359, 0
|
|
+ lfd 8010000000000001, 65448 => 8010000000000001, 0
|
|
+ lfd 80100094e0000359, 65456 => 80100094e0000359, 0
|
|
+ lfd bfe0000000000001, 65464 => bfe0000000000001, 0
|
|
+ lfd bfe00094e0000359, 65472 => bfe00094e0000359, 0
|
|
+ lfd 0000000000000000, 65480 => 0000000000000000, 0
|
|
+ lfd 8000000000000000, 65488 => 8000000000000000, 0
|
|
+ lfd 7ff0000000000000, 65496 => 7ff0000000000000, 0
|
|
+ lfd fff0000000000000, 65504 => fff0000000000000, 0
|
|
+ lfd 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, 0
|
|
+ lfd fff7ffffffffffff, 65520 => fff7ffffffffffff, 0
|
|
+ lfd 7ff8000000000000, 65528 => 7ff8000000000000, 0
|
|
+ lfd 0010000000000001, 0 => 0010000000000001, 0
|
|
+ lfd 00100094e0000359, 8 => 00100094e0000359, 0
|
|
+ lfd 3fe0000000000001, 16 => 3fe0000000000001, 0
|
|
+ lfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0
|
|
+ lfd 8010000000000001, 32 => 8010000000000001, 0
|
|
+ lfd 80100094e0000359, 40 => 80100094e0000359, 0
|
|
+ lfd bfe0000000000001, 48 => bfe0000000000001, 0
|
|
+ lfd bfe00094e0000359, 56 => bfe00094e0000359, 0
|
|
+ lfd 0000000000000000, 64 => 0000000000000000, 0
|
|
+ lfd 8000000000000000, 72 => 8000000000000000, 0
|
|
+ lfd 7ff0000000000000, 80 => 7ff0000000000000, 0
|
|
+ lfd fff0000000000000, 88 => fff0000000000000, 0
|
|
+ lfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
|
|
+ lfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0
|
|
+ lfd 7ff8000000000000, 112 => 7ff8000000000000, 0
|
|
+ lfd fff8000000000000, 120 => fff8000000000000, 0
|
|
+
|
|
+ lfdu 0010000000000001, 65416 => 0010000000000001, -120
|
|
+ lfdu 00100094e0000359, 65424 => 00100094e0000359, -112
|
|
+ lfdu 3fe0000000000001, 65432 => 3fe0000000000001, -104
|
|
+ lfdu 3fe00094e0000359, 65440 => 3fe00094e0000359, -96
|
|
+ lfdu 8010000000000001, 65448 => 8010000000000001, -88
|
|
+ lfdu 80100094e0000359, 65456 => 80100094e0000359, -80
|
|
+ lfdu bfe0000000000001, 65464 => bfe0000000000001, -72
|
|
+ lfdu bfe00094e0000359, 65472 => bfe00094e0000359, -64
|
|
+ lfdu 0000000000000000, 65480 => 0000000000000000, -56
|
|
+ lfdu 8000000000000000, 65488 => 8000000000000000, -48
|
|
+ lfdu 7ff0000000000000, 65496 => 7ff0000000000000, -40
|
|
+ lfdu fff0000000000000, 65504 => fff0000000000000, -32
|
|
+ lfdu 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, -24
|
|
+ lfdu fff7ffffffffffff, 65520 => fff7ffffffffffff, -16
|
|
+ lfdu 7ff8000000000000, 65528 => 7ff8000000000000, -8
|
|
+ lfdu 0010000000000001, 0 => 0010000000000001, 0
|
|
+ lfdu 00100094e0000359, 8 => 00100094e0000359, 8
|
|
+ lfdu 3fe0000000000001, 16 => 3fe0000000000001, 16
|
|
+ lfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24
|
|
+ lfdu 8010000000000001, 32 => 8010000000000001, 32
|
|
+ lfdu 80100094e0000359, 40 => 80100094e0000359, 40
|
|
+ lfdu bfe0000000000001, 48 => bfe0000000000001, 48
|
|
+ lfdu bfe00094e0000359, 56 => bfe00094e0000359, 56
|
|
+ lfdu 0000000000000000, 64 => 0000000000000000, 64
|
|
+ lfdu 8000000000000000, 72 => 8000000000000000, 72
|
|
+ lfdu 7ff0000000000000, 80 => 7ff0000000000000, 80
|
|
+ lfdu fff0000000000000, 88 => fff0000000000000, 88
|
|
+ lfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
|
|
+ lfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104
|
|
+ lfdu 7ff8000000000000, 112 => 7ff8000000000000, 112
|
|
+ lfdu fff8000000000000, 120 => fff8000000000000, 120
|
|
+
|
|
+PPC float load insns with two register args:
|
|
+ lfsx 0010000000000001, -120 => 37e0000000000000, 0
|
|
+ lfsx 00100094e0000359, -112 => 37e0009400000000, 0
|
|
+ lfsx 3fe0000000000001, -104 => 3ffc000000000000, 0
|
|
+ lfsx 3fe00094e0000359, -96 => 3ffc001280000000, 0
|
|
+ lfsx 8010000000000001, -88 => b7e0000000000000, 0
|
|
+ lfsx 80100094e0000359, -80 => b7e0009400000000, 0
|
|
+ lfsx bfe0000000000001, -72 => bffc000000000000, 0
|
|
+ lfsx bfe00094e0000359, -64 => bffc001280000000, 0
|
|
+ lfsx 0000000000000000, -56 => 0000000000000000, 0
|
|
+ lfsx 8000000000000000, -48 => 8000000000000000, 0
|
|
+ lfsx 7ff0000000000000, -40 => 7ffe000000000000, 0
|
|
+ lfsx fff0000000000000, -32 => fffe000000000000, 0
|
|
+ lfsx 7ff7ffffffffffff, -24 => 7ffeffffe0000000, 0
|
|
+ lfsx fff7ffffffffffff, -16 => fffeffffe0000000, 0
|
|
+ lfsx 7ff8000000000000, -8 => 7fff000000000000, 0
|
|
+ lfsx 0010000000000001, 0 => 37e0000000000000, 0
|
|
+ lfsx 00100094e0000359, 8 => 37e0009400000000, 0
|
|
+ lfsx 3fe0000000000001, 16 => 3ffc000000000000, 0
|
|
+ lfsx 3fe00094e0000359, 24 => 3ffc001280000000, 0
|
|
+ lfsx 8010000000000001, 32 => b7e0000000000000, 0
|
|
+ lfsx 80100094e0000359, 40 => b7e0009400000000, 0
|
|
+ lfsx bfe0000000000001, 48 => bffc000000000000, 0
|
|
+ lfsx bfe00094e0000359, 56 => bffc001280000000, 0
|
|
+ lfsx 0000000000000000, 64 => 0000000000000000, 0
|
|
+ lfsx 8000000000000000, 72 => 8000000000000000, 0
|
|
+ lfsx 7ff0000000000000, 80 => 7ffe000000000000, 0
|
|
+ lfsx fff0000000000000, 88 => fffe000000000000, 0
|
|
+ lfsx 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 0
|
|
+ lfsx fff7ffffffffffff, 104 => fffeffffe0000000, 0
|
|
+ lfsx 7ff8000000000000, 112 => 7fff000000000000, 0
|
|
+ lfsx fff8000000000000, 120 => ffff000000000000, 0
|
|
+
|
|
+ lfsux 0010000000000001, -120 => 37e0000000000000, -120
|
|
+ lfsux 00100094e0000359, -112 => 37e0009400000000, -112
|
|
+ lfsux 3fe0000000000001, -104 => 3ffc000000000000, -104
|
|
+ lfsux 3fe00094e0000359, -96 => 3ffc001280000000, -96
|
|
+ lfsux 8010000000000001, -88 => b7e0000000000000, -88
|
|
+ lfsux 80100094e0000359, -80 => b7e0009400000000, -80
|
|
+ lfsux bfe0000000000001, -72 => bffc000000000000, -72
|
|
+ lfsux bfe00094e0000359, -64 => bffc001280000000, -64
|
|
+ lfsux 0000000000000000, -56 => 0000000000000000, -56
|
|
+ lfsux 8000000000000000, -48 => 8000000000000000, -48
|
|
+ lfsux 7ff0000000000000, -40 => 7ffe000000000000, -40
|
|
+ lfsux fff0000000000000, -32 => fffe000000000000, -32
|
|
+ lfsux 7ff7ffffffffffff, -24 => 7ffeffffe0000000, -24
|
|
+ lfsux fff7ffffffffffff, -16 => fffeffffe0000000, -16
|
|
+ lfsux 7ff8000000000000, -8 => 7fff000000000000, -8
|
|
+ lfsux 0010000000000001, 0 => 37e0000000000000, 0
|
|
+ lfsux 00100094e0000359, 8 => 37e0009400000000, 8
|
|
+ lfsux 3fe0000000000001, 16 => 3ffc000000000000, 16
|
|
+ lfsux 3fe00094e0000359, 24 => 3ffc001280000000, 24
|
|
+ lfsux 8010000000000001, 32 => b7e0000000000000, 32
|
|
+ lfsux 80100094e0000359, 40 => b7e0009400000000, 40
|
|
+ lfsux bfe0000000000001, 48 => bffc000000000000, 48
|
|
+ lfsux bfe00094e0000359, 56 => bffc001280000000, 56
|
|
+ lfsux 0000000000000000, 64 => 0000000000000000, 64
|
|
+ lfsux 8000000000000000, 72 => 8000000000000000, 72
|
|
+ lfsux 7ff0000000000000, 80 => 7ffe000000000000, 80
|
|
+ lfsux fff0000000000000, 88 => fffe000000000000, 88
|
|
+ lfsux 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 96
|
|
+ lfsux fff7ffffffffffff, 104 => fffeffffe0000000, 104
|
|
+ lfsux 7ff8000000000000, 112 => 7fff000000000000, 112
|
|
+ lfsux fff8000000000000, 120 => ffff000000000000, 120
|
|
+
|
|
+ lfdx 0010000000000001, -120 => 0010000000000001, 0
|
|
+ lfdx 00100094e0000359, -112 => 00100094e0000359, 0
|
|
+ lfdx 3fe0000000000001, -104 => 3fe0000000000001, 0
|
|
+ lfdx 3fe00094e0000359, -96 => 3fe00094e0000359, 0
|
|
+ lfdx 8010000000000001, -88 => 8010000000000001, 0
|
|
+ lfdx 80100094e0000359, -80 => 80100094e0000359, 0
|
|
+ lfdx bfe0000000000001, -72 => bfe0000000000001, 0
|
|
+ lfdx bfe00094e0000359, -64 => bfe00094e0000359, 0
|
|
+ lfdx 0000000000000000, -56 => 0000000000000000, 0
|
|
+ lfdx 8000000000000000, -48 => 8000000000000000, 0
|
|
+ lfdx 7ff0000000000000, -40 => 7ff0000000000000, 0
|
|
+ lfdx fff0000000000000, -32 => fff0000000000000, 0
|
|
+ lfdx 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0
|
|
+ lfdx fff7ffffffffffff, -16 => fff7ffffffffffff, 0
|
|
+ lfdx 7ff8000000000000, -8 => 7ff8000000000000, 0
|
|
+ lfdx 0010000000000001, 0 => 0010000000000001, 0
|
|
+ lfdx 00100094e0000359, 8 => 00100094e0000359, 0
|
|
+ lfdx 3fe0000000000001, 16 => 3fe0000000000001, 0
|
|
+ lfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0
|
|
+ lfdx 8010000000000001, 32 => 8010000000000001, 0
|
|
+ lfdx 80100094e0000359, 40 => 80100094e0000359, 0
|
|
+ lfdx bfe0000000000001, 48 => bfe0000000000001, 0
|
|
+ lfdx bfe00094e0000359, 56 => bfe00094e0000359, 0
|
|
+ lfdx 0000000000000000, 64 => 0000000000000000, 0
|
|
+ lfdx 8000000000000000, 72 => 8000000000000000, 0
|
|
+ lfdx 7ff0000000000000, 80 => 7ff0000000000000, 0
|
|
+ lfdx fff0000000000000, 88 => fff0000000000000, 0
|
|
+ lfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
|
|
+ lfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0
|
|
+ lfdx 7ff8000000000000, 112 => 7ff8000000000000, 0
|
|
+ lfdx fff8000000000000, 120 => fff8000000000000, 0
|
|
+
|
|
+ lfdux 0010000000000001, -120 => 0010000000000001, -120
|
|
+ lfdux 00100094e0000359, -112 => 00100094e0000359, -112
|
|
+ lfdux 3fe0000000000001, -104 => 3fe0000000000001, -104
|
|
+ lfdux 3fe00094e0000359, -96 => 3fe00094e0000359, -96
|
|
+ lfdux 8010000000000001, -88 => 8010000000000001, -88
|
|
+ lfdux 80100094e0000359, -80 => 80100094e0000359, -80
|
|
+ lfdux bfe0000000000001, -72 => bfe0000000000001, -72
|
|
+ lfdux bfe00094e0000359, -64 => bfe00094e0000359, -64
|
|
+ lfdux 0000000000000000, -56 => 0000000000000000, -56
|
|
+ lfdux 8000000000000000, -48 => 8000000000000000, -48
|
|
+ lfdux 7ff0000000000000, -40 => 7ff0000000000000, -40
|
|
+ lfdux fff0000000000000, -32 => fff0000000000000, -32
|
|
+ lfdux 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24
|
|
+ lfdux fff7ffffffffffff, -16 => fff7ffffffffffff, -16
|
|
+ lfdux 7ff8000000000000, -8 => 7ff8000000000000, -8
|
|
+ lfdux 0010000000000001, 0 => 0010000000000001, 0
|
|
+ lfdux 00100094e0000359, 8 => 00100094e0000359, 8
|
|
+ lfdux 3fe0000000000001, 16 => 3fe0000000000001, 16
|
|
+ lfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24
|
|
+ lfdux 8010000000000001, 32 => 8010000000000001, 32
|
|
+ lfdux 80100094e0000359, 40 => 80100094e0000359, 40
|
|
+ lfdux bfe0000000000001, 48 => bfe0000000000001, 48
|
|
+ lfdux bfe00094e0000359, 56 => bfe00094e0000359, 56
|
|
+ lfdux 0000000000000000, 64 => 0000000000000000, 64
|
|
+ lfdux 8000000000000000, 72 => 8000000000000000, 72
|
|
+ lfdux 7ff0000000000000, 80 => 7ff0000000000000, 80
|
|
+ lfdux fff0000000000000, 88 => fff0000000000000, 88
|
|
+ lfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
|
|
+ lfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104
|
|
+ lfdux 7ff8000000000000, 112 => 7ff8000000000000, 112
|
|
+ lfdux fff8000000000000, 120 => fff8000000000000, 120
|
|
+
|
|
+PPC float store insns
|
|
+ with one register + one 16 bits immediate args with flags update:
|
|
+ stfs 0010000000000001, -56 => 0000000000000000, 0
|
|
+ stfs 00100094e0000359, -48 => 0000000000000000, 0
|
|
+ stfs 3fe0000000000001, -40 => 3f00000000000000, 0
|
|
+ stfs 3fe00094e0000359, -32 => 3f0004a700000000, 0
|
|
+ stfs 8010000000000001, -24 => 8000000000000000, 0
|
|
+ stfs 80100094e0000359, -16 => 8000000000000000, 0
|
|
+ stfs bfe0000000000001, -8 => bf00000000000000, 0
|
|
+ stfs 0010000000000001, 0 => 0000000000000000, 0
|
|
+ stfs 00100094e0000359, 8 => 0000000000000000, 0
|
|
+ stfs 3fe0000000000001, 16 => 3f00000000000000, 0
|
|
+ stfs 3fe00094e0000359, 24 => 3f0004a700000000, 0
|
|
+ stfs 8010000000000001, 32 => 8000000000000000, 0
|
|
+ stfs 80100094e0000359, 40 => 8000000000000000, 0
|
|
+ stfs bfe0000000000001, 48 => bf00000000000000, 0
|
|
+ stfs bfe00094e0000359, 56 => bf0004a700000000, 0
|
|
+
|
|
+ stfsu 0010000000000001, -56 => 0000000000000000, -56
|
|
+ stfsu 00100094e0000359, -48 => 0000000000000000, -48
|
|
+ stfsu 3fe0000000000001, -40 => 3f00000000000000, -40
|
|
+ stfsu 3fe00094e0000359, -32 => 3f0004a700000000, -32
|
|
+ stfsu 8010000000000001, -24 => 8000000000000000, -24
|
|
+ stfsu 80100094e0000359, -16 => 8000000000000000, -16
|
|
+ stfsu bfe0000000000001, -8 => bf00000000000000, -8
|
|
+ stfsu 0010000000000001, 0 => 0000000000000000, 0
|
|
+ stfsu 00100094e0000359, 8 => 0000000000000000, 8
|
|
+ stfsu 3fe0000000000001, 16 => 3f00000000000000, 16
|
|
+ stfsu 3fe00094e0000359, 24 => 3f0004a700000000, 24
|
|
+ stfsu 8010000000000001, 32 => 8000000000000000, 32
|
|
+ stfsu 80100094e0000359, 40 => 8000000000000000, 40
|
|
+ stfsu bfe0000000000001, 48 => bf00000000000000, 48
|
|
+ stfsu bfe00094e0000359, 56 => bf0004a700000000, 56
|
|
+
|
|
+ stfd 0010000000000001, -120 => 0010000000000001, 0
|
|
+ stfd 00100094e0000359, -112 => 00100094e0000359, 0
|
|
+ stfd 3fe0000000000001, -104 => 3fe0000000000001, 0
|
|
+ stfd 3fe00094e0000359, -96 => 3fe00094e0000359, 0
|
|
+ stfd 8010000000000001, -88 => 8010000000000001, 0
|
|
+ stfd 80100094e0000359, -80 => 80100094e0000359, 0
|
|
+ stfd bfe0000000000001, -72 => bfe0000000000001, 0
|
|
+ stfd bfe00094e0000359, -64 => bfe00094e0000359, 0
|
|
+ stfd 0000000000000000, -56 => 0000000000000000, 0
|
|
+ stfd 8000000000000000, -48 => 8000000000000000, 0
|
|
+ stfd 7ff0000000000000, -40 => 7ff0000000000000, 0
|
|
+ stfd fff0000000000000, -32 => fff0000000000000, 0
|
|
+ stfd 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0
|
|
+ stfd fff7ffffffffffff, -16 => fff7ffffffffffff, 0
|
|
+ stfd 7ff8000000000000, -8 => 7ff8000000000000, 0
|
|
+ stfd 0010000000000001, 0 => 0010000000000001, 0
|
|
+ stfd 00100094e0000359, 8 => 00100094e0000359, 0
|
|
+ stfd 3fe0000000000001, 16 => 3fe0000000000001, 0
|
|
+ stfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0
|
|
+ stfd 8010000000000001, 32 => 8010000000000001, 0
|
|
+ stfd 80100094e0000359, 40 => 80100094e0000359, 0
|
|
+ stfd bfe0000000000001, 48 => bfe0000000000001, 0
|
|
+ stfd bfe00094e0000359, 56 => bfe00094e0000359, 0
|
|
+ stfd 0000000000000000, 64 => 0000000000000000, 0
|
|
+ stfd 8000000000000000, 72 => 8000000000000000, 0
|
|
+ stfd 7ff0000000000000, 80 => 7ff0000000000000, 0
|
|
+ stfd fff0000000000000, 88 => fff0000000000000, 0
|
|
+ stfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
|
|
+ stfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0
|
|
+ stfd 7ff8000000000000, 112 => 7ff8000000000000, 0
|
|
+ stfd fff8000000000000, 120 => fff8000000000000, 0
|
|
+
|
|
+ stfdu 0010000000000001, -120 => 0010000000000001, -120
|
|
+ stfdu 00100094e0000359, -112 => 00100094e0000359, -112
|
|
+ stfdu 3fe0000000000001, -104 => 3fe0000000000001, -104
|
|
+ stfdu 3fe00094e0000359, -96 => 3fe00094e0000359, -96
|
|
+ stfdu 8010000000000001, -88 => 8010000000000001, -88
|
|
+ stfdu 80100094e0000359, -80 => 80100094e0000359, -80
|
|
+ stfdu bfe0000000000001, -72 => bfe0000000000001, -72
|
|
+ stfdu bfe00094e0000359, -64 => bfe00094e0000359, -64
|
|
+ stfdu 0000000000000000, -56 => 0000000000000000, -56
|
|
+ stfdu 8000000000000000, -48 => 8000000000000000, -48
|
|
+ stfdu 7ff0000000000000, -40 => 7ff0000000000000, -40
|
|
+ stfdu fff0000000000000, -32 => fff0000000000000, -32
|
|
+ stfdu 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24
|
|
+ stfdu fff7ffffffffffff, -16 => fff7ffffffffffff, -16
|
|
+ stfdu 7ff8000000000000, -8 => 7ff8000000000000, -8
|
|
+ stfdu 0010000000000001, 0 => 0010000000000001, 0
|
|
+ stfdu 00100094e0000359, 8 => 00100094e0000359, 8
|
|
+ stfdu 3fe0000000000001, 16 => 3fe0000000000001, 16
|
|
+ stfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24
|
|
+ stfdu 8010000000000001, 32 => 8010000000000001, 32
|
|
+ stfdu 80100094e0000359, 40 => 80100094e0000359, 40
|
|
+ stfdu bfe0000000000001, 48 => bfe0000000000001, 48
|
|
+ stfdu bfe00094e0000359, 56 => bfe00094e0000359, 56
|
|
+ stfdu 0000000000000000, 64 => 0000000000000000, 64
|
|
+ stfdu 8000000000000000, 72 => 8000000000000000, 72
|
|
+ stfdu 7ff0000000000000, 80 => 7ff0000000000000, 80
|
|
+ stfdu fff0000000000000, 88 => fff0000000000000, 88
|
|
+ stfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
|
|
+ stfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104
|
|
+ stfdu 7ff8000000000000, 112 => 7ff8000000000000, 112
|
|
+ stfdu fff8000000000000, 120 => fff8000000000000, 120
|
|
+
|
|
+PPC float store insns with three register args:
|
|
+ stfsx 0010000000000001, 0 => 0000000000000000, 0
|
|
+ stfsx 00100094e0000359, 8 => 0000000000000000, 0
|
|
+ stfsx 3fe0000000000001, 16 => 3f00000000000000, 0
|
|
+ stfsx 3fe00094e0000359, 24 => 3f0004a700000000, 0
|
|
+ stfsx 8010000000000001, 32 => 8000000000000000, 0
|
|
+ stfsx 80100094e0000359, 40 => 8000000000000000, 0
|
|
+ stfsx bfe0000000000001, 48 => bf00000000000000, 0
|
|
+ stfsx bfe00094e0000359, 56 => bf0004a700000000, 0
|
|
+
|
|
+ stfsux 0010000000000001, 0 => 0000000000000000, 0
|
|
+ stfsux 00100094e0000359, 8 => 0000000000000000, 8
|
|
+ stfsux 3fe0000000000001, 16 => 3f00000000000000, 16
|
|
+ stfsux 3fe00094e0000359, 24 => 3f0004a700000000, 24
|
|
+ stfsux 8010000000000001, 32 => 8000000000000000, 32
|
|
+ stfsux 80100094e0000359, 40 => 8000000000000000, 40
|
|
+ stfsux bfe0000000000001, 48 => bf00000000000000, 48
|
|
+ stfsux bfe00094e0000359, 56 => bf0004a700000000, 56
|
|
+
|
|
+ stfdx 0010000000000001, 0 => 0010000000000001, 0
|
|
+ stfdx 00100094e0000359, 8 => 00100094e0000359, 0
|
|
+ stfdx 3fe0000000000001, 16 => 3fe0000000000001, 0
|
|
+ stfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0
|
|
+ stfdx 8010000000000001, 32 => 8010000000000001, 0
|
|
+ stfdx 80100094e0000359, 40 => 80100094e0000359, 0
|
|
+ stfdx bfe0000000000001, 48 => bfe0000000000001, 0
|
|
+ stfdx bfe00094e0000359, 56 => bfe00094e0000359, 0
|
|
+ stfdx 0000000000000000, 64 => 0000000000000000, 0
|
|
+ stfdx 8000000000000000, 72 => 8000000000000000, 0
|
|
+ stfdx 7ff0000000000000, 80 => 7ff0000000000000, 0
|
|
+ stfdx fff0000000000000, 88 => fff0000000000000, 0
|
|
+ stfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
|
|
+ stfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0
|
|
+ stfdx 7ff8000000000000, 112 => 7ff8000000000000, 0
|
|
+ stfdx fff8000000000000, 120 => fff8000000000000, 0
|
|
+
|
|
+ stfdux 0010000000000001, 0 => 0010000000000001, 0
|
|
+ stfdux 00100094e0000359, 8 => 00100094e0000359, 8
|
|
+ stfdux 3fe0000000000001, 16 => 3fe0000000000001, 16
|
|
+ stfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24
|
|
+ stfdux 8010000000000001, 32 => 8010000000000001, 32
|
|
+ stfdux 80100094e0000359, 40 => 80100094e0000359, 40
|
|
+ stfdux bfe0000000000001, 48 => bfe0000000000001, 48
|
|
+ stfdux bfe00094e0000359, 56 => bfe00094e0000359, 56
|
|
+ stfdux 0000000000000000, 64 => 0000000000000000, 64
|
|
+ stfdux 8000000000000000, 72 => 8000000000000000, 72
|
|
+ stfdux 7ff0000000000000, 80 => 7ff0000000000000, 80
|
|
+ stfdux fff0000000000000, 88 => fff0000000000000, 88
|
|
+ stfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
|
|
+ stfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104
|
|
+ stfdux 7ff8000000000000, 112 => 7ff8000000000000, 112
|
|
+ stfdux fff8000000000000, 120 => fff8000000000000, 120
|
|
+
|
|
+All done. Tested 77 different instructions
|
|
Index: none/tests/ppc64/round.stdout.exp-RM-fix
|
|
===================================================================
|
|
--- /dev/null
|
|
+++ none/tests/ppc64/round.stdout.exp-RM-fix
|
|
@@ -0,0 +1,2384 @@
|
|
+-------------------------- test denormalized convert --------------------------
|
|
+near:PASSED:(double)(0x1p-148 ) = 0x1.cp-149
|
|
+near:PASSED:(double)(0x1p-149 ) = 0x1.4p-149
|
|
+zero:PASSED:(double)(0x1p-149 ) = 0x1.cp-149
|
|
+zero:PASSED:(double)(0x1p-149 ) = 0x1.4p-149
|
|
++inf:PASSED:(double)(0x1p-148 ) = 0x1.cp-149
|
|
++inf:PASSED:(double)(0x1p-148 ) = 0x1.4p-149
|
|
+-inf:PASSED:(double)(0x1p-149 ) = 0x1.cp-149
|
|
+-inf:PASSED:(double)(0x1p-149 ) = 0x1.4p-149
|
|
+-------------------------- test normalized convert --------------------------
|
|
+near:PASSED:(double)(0x1.000004p-126 ) = 0x1.0000038p-126
|
|
+near:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000028p-126
|
|
+zero:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000038p-126
|
|
+zero:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000028p-126
|
|
++inf:PASSED:(double)(0x1.000004p-126 ) = 0x1.0000038p-126
|
|
++inf:PASSED:(double)(0x1.000004p-126 ) = 0x1.0000028p-126
|
|
+-inf:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000038p-126
|
|
+-inf:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000028p-126
|
|
+-------------------------- test (float)int convert --------------------------
|
|
+near:PASSED:(float)( int) 67047421 = 67047420.0
|
|
+near:PASSED:(float)(long) 67047421 = 67047420.0
|
|
+near:PASSED:(float)( int) 67047423 = 67047424.0
|
|
+near:PASSED:(float)(long) 67047423 = 67047424.0
|
|
+zero:PASSED:(float)( int) 67047421 = 67047420.0
|
|
+zero:PASSED:(float)(long) 67047421 = 67047420.0
|
|
+zero:PASSED:(float)( int) 67047423 = 67047420.0
|
|
+zero:PASSED:(float)(long) 67047423 = 67047420.0
|
|
++inf:PASSED:(float)( int) 67047421 = 67047424.0
|
|
++inf:PASSED:(float)(long) 67047421 = 67047424.0
|
|
++inf:PASSED:(float)( int) 67047423 = 67047424.0
|
|
++inf:PASSED:(float)(long) 67047423 = 67047424.0
|
|
+-inf:PASSED:(float)( int) 67047421 = 67047420.0
|
|
+-inf:PASSED:(float)(long) 67047421 = 67047420.0
|
|
+-inf:PASSED:(float)( int) 67047423 = 67047420.0
|
|
+-inf:PASSED:(float)(long) 67047423 = 67047420.0
|
|
+near:PASSED:(float)( int)-67047421 = -67047420.0
|
|
+near:PASSED:(float)(long)-67047421 = -67047420.0
|
|
+near:PASSED:(float)( int)-67047423 = -67047424.0
|
|
+near:PASSED:(float)(long)-67047423 = -67047424.0
|
|
+zero:PASSED:(float)( int)-67047421 = -67047420.0
|
|
+zero:PASSED:(float)(long)-67047421 = -67047420.0
|
|
+zero:PASSED:(float)( int)-67047423 = -67047420.0
|
|
+zero:PASSED:(float)(long)-67047423 = -67047420.0
|
|
++inf:PASSED:(float)( int)-67047421 = -67047420.0
|
|
++inf:PASSED:(float)(long)-67047421 = -67047420.0
|
|
++inf:PASSED:(float)( int)-67047423 = -67047420.0
|
|
++inf:PASSED:(float)(long)-67047423 = -67047420.0
|
|
+-inf:PASSED:(float)( int)-67047421 = -67047424.0
|
|
+-inf:PASSED:(float)(long)-67047421 = -67047424.0
|
|
+-inf:PASSED:(float)( int)-67047423 = -67047424.0
|
|
+-inf:PASSED:(float)(long)-67047423 = -67047424.0
|
|
+-------------------------- test (float)int convert --------------------------
|
|
+near:PASSED:(float)( int) 67047421 = 67047420.0
|
|
+near:PASSED:(float)(long) 67047421 = 67047420.0
|
|
+near:PASSED:(float)( int) 67047423 = 67047424.0
|
|
+near:PASSED:(float)(long) 67047423 = 67047424.0
|
|
+zero:PASSED:(float)( int) 67047421 = 67047420.0
|
|
+zero:PASSED:(float)(long) 67047421 = 67047420.0
|
|
+zero:PASSED:(float)( int) 67047423 = 67047420.0
|
|
+zero:PASSED:(float)(long) 67047423 = 67047420.0
|
|
++inf:PASSED:(float)( int) 67047421 = 67047424.0
|
|
++inf:PASSED:(float)(long) 67047421 = 67047424.0
|
|
++inf:PASSED:(float)( int) 67047423 = 67047424.0
|
|
++inf:PASSED:(float)(long) 67047423 = 67047424.0
|
|
+-inf:PASSED:(float)( int) 67047421 = 67047420.0
|
|
+-inf:PASSED:(float)(long) 67047421 = 67047420.0
|
|
+-inf:PASSED:(float)( int) 67047423 = 67047420.0
|
|
+-inf:PASSED:(float)(long) 67047423 = 67047420.0
|
|
+near:PASSED:(float)( int)-67047421 = -67047420.0
|
|
+near:PASSED:(float)(long)-67047421 = -67047420.0
|
|
+near:PASSED:(float)( int)-67047423 = -67047424.0
|
|
+near:PASSED:(float)(long)-67047423 = -67047424.0
|
|
+zero:PASSED:(float)( int)-67047421 = -67047420.0
|
|
+zero:PASSED:(float)(long)-67047421 = -67047420.0
|
|
+zero:PASSED:(float)( int)-67047423 = -67047420.0
|
|
+zero:PASSED:(float)(long)-67047423 = -67047420.0
|
|
++inf:PASSED:(float)( int)-67047421 = -67047420.0
|
|
++inf:PASSED:(float)(long)-67047421 = -67047420.0
|
|
++inf:PASSED:(float)( int)-67047423 = -67047420.0
|
|
++inf:PASSED:(float)(long)-67047423 = -67047420.0
|
|
+-inf:PASSED:(float)( int)-67047421 = -67047424.0
|
|
+-inf:PASSED:(float)(long)-67047421 = -67047424.0
|
|
+-inf:PASSED:(float)( int)-67047423 = -67047424.0
|
|
+-inf:PASSED:(float)(long)-67047423 = -67047424.0
|
|
+-------------------------- test (double)long convert --------------------------
|
|
+near:PASSED:(double)( 36012304344547325) = 36012304344547324.0
|
|
+near:PASSED:(double)( 36012304344547327) = 36012304344547328.0
|
|
+zero:PASSED:(double)( 36012304344547325) = 36012304344547324.0
|
|
+zero:PASSED:(double)( 36012304344547327) = 36012304344547324.0
|
|
++inf:PASSED:(double)( 36012304344547325) = 36012304344547328.0
|
|
++inf:PASSED:(double)( 36012304344547327) = 36012304344547328.0
|
|
+-inf:PASSED:(double)( 36012304344547325) = 36012304344547324.0
|
|
+-inf:PASSED:(double)( 36012304344547327) = 36012304344547324.0
|
|
+near:PASSED:(double)(-36012304344547325) = -36012304344547324.0
|
|
+near:PASSED:(double)(-36012304344547327) = -36012304344547328.0
|
|
+zero:PASSED:(double)(-36012304344547325) = -36012304344547324.0
|
|
+zero:PASSED:(double)(-36012304344547327) = -36012304344547324.0
|
|
++inf:PASSED:(double)(-36012304344547325) = -36012304344547324.0
|
|
++inf:PASSED:(double)(-36012304344547327) = -36012304344547324.0
|
|
+-inf:PASSED:(double)(-36012304344547325) = -36012304344547328.0
|
|
+-inf:PASSED:(double)(-36012304344547327) = -36012304344547328.0
|
|
+-------------------------- test rounding of float operators without guard bits --------------------------
|
|
+near:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-149
|
|
+near:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-148
|
|
+near:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-149
|
|
+near:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-148
|
|
+zero:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-149
|
|
+zero:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-149
|
|
+zero:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-149
|
|
+zero:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-149
|
|
++inf:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-149
|
|
++inf:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-149
|
|
++inf:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-148
|
|
++inf:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-148
|
|
+-inf:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-148
|
|
+-inf:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-148
|
|
+-inf:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-149
|
|
+-inf:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-149
|
|
+near:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-149
|
|
+near:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-148
|
|
+near:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-149
|
|
+near:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-148
|
|
+zero:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-149
|
|
+zero:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-149
|
|
+zero:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-149
|
|
+zero:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-149
|
|
++inf:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-149
|
|
++inf:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-149
|
|
++inf:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-148
|
|
++inf:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-148
|
|
+-inf:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-148
|
|
+-inf:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-148
|
|
+-inf:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-149
|
|
+-inf:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-149
|
|
+near:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-149
|
|
+near:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-148
|
|
+near:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-149
|
|
+near:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-148
|
|
+zero:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-149
|
|
+zero:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-149
|
|
+zero:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-149
|
|
+zero:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-149
|
|
++inf:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-149
|
|
++inf:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-149
|
|
++inf:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-148
|
|
++inf:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-148
|
|
+-inf:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-148
|
|
+-inf:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-148
|
|
+-inf:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-149
|
|
+-inf:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-149
|
|
+near:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-149
|
|
+near:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-148
|
|
+near:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-149
|
|
+near:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-148
|
|
+zero:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-149
|
|
+zero:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-149
|
|
+zero:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-149
|
|
+zero:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-149
|
|
++inf:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-149
|
|
++inf:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-149
|
|
++inf:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-148
|
|
++inf:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-148
|
|
+-inf:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-148
|
|
+-inf:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-148
|
|
+-inf:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-149
|
|
+-inf:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-149
|
|
+-------------------------- test rounding of float operators with guard bits --------------------------
|
|
+near:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.2p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.2p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.2p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.2p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.200002p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.200002p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.200002p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200002p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200002p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200002p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200004p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200004p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200004p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200004p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.2p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.2p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.2p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.2p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.200002p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.200002p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.200002p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200002p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200002p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200002p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200004p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200004p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200004p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200004p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.2p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.2p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.2p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.2p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.2p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.2p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.2p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200002p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200002p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200002p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200002p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200002p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200002p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200002p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.2p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.2p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.2p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.2p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.2p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.2p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.2p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200002p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200002p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200002p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200002p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200002p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200002p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200002p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.2p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.2p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.2p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.2p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.2p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.2p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.2p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200002p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200002p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200002p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200002p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200002p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200002p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200002p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.200002p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.200002p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.200002p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.200002p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.200002p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.200002p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.200002p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200004p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200004p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200004p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200004p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200004p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200004p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200004p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.200002p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.200002p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.200002p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.200002p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.200002p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.200002p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.200002p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200004p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200004p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200004p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200004p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200004p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200004p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200004p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200002p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200002p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200002p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200002p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200002p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200002p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200002p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1p-3 ) = -0x1.000004p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.000002p-3) = -0x1.000004p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.000004p-3) = -0x1.000004p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.000006p-3) = -0x1.000004p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.000008p-3) = -0x1.000004p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.00000ap-3) = -0x1.000002p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.00000cp-3) = -0x1.000002p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.00000ep-3) = -0x1.000002p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.00001p-3) = -0x1.000002p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.000012p-3) = -0x1.000002p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.000014p-3) = -0x1.000002p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.000016p-3) = -0x1.000002p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.000018p-3) = -0x1p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000004p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000004p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.000006p-3) = 0x1.000004p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.000008p-3) = 0x1.000004p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.00000ap-3) = 0x1.000002p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.00000cp-3) = 0x1.000002p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.00000ep-3) = 0x1.000002p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.00001p-3 ) = 0x1.000002p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.000012p-3) = 0x1.000002p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.000014p-3) = 0x1.000002p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.000016p-3) = 0x1.000002p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.000018p-3) = 0x1p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.00001ap-3) = 0x1p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.00001cp-3) = 0x1p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1p-3 ) = -0x1.000004p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.000002p-3) = -0x1.000002p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.000004p-3) = -0x1.000002p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.000006p-3) = -0x1.000002p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.000008p-3) = -0x1.000002p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.00000ap-3) = -0x1.000002p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.00000cp-3) = -0x1.000002p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.00000ep-3) = -0x1.000002p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.00001p-3) = -0x1.000002p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.000012p-3) = -0x1p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.000014p-3) = -0x1p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.000016p-3) = -0x1p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.000018p-3) = -0x1p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000002p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000002p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.000006p-3) = 0x1.000002p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.000008p-3) = 0x1.000002p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.00000ap-3) = 0x1.000002p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.00000cp-3) = 0x1.000002p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.00000ep-3) = 0x1.000002p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.00001p-3 ) = 0x1.000002p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.000012p-3) = 0x1p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.000014p-3) = 0x1p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.000016p-3) = 0x1p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.000018p-3) = 0x1p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.00001ap-3) = 0x1p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.00001cp-3) = 0x1p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1p-3 ) = -0x1.000004p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.000002p-3) = -0x1.000002p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.000004p-3) = -0x1.000002p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.000006p-3) = -0x1.000002p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.000008p-3) = -0x1.000002p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.00000ap-3) = -0x1.000002p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.00000cp-3) = -0x1.000002p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.00000ep-3) = -0x1.000002p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.00001p-3) = -0x1.000002p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.000012p-3) = -0x1p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.000014p-3) = -0x1p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.000016p-3) = -0x1p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.000018p-3) = -0x1p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1p-3 ) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000002p-3) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000004p-3) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000006p-3) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000008p-3) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.00000ap-3) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.00000cp-3) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.00000ep-3) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.00001p-3 ) = 0x1.000002p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000012p-3) = 0x1.000002p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000014p-3) = 0x1.000002p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000016p-3) = 0x1.000002p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000018p-3) = 0x1.000002p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.00001ap-3) = 0x1.000002p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.00001cp-3) = 0x1.000002p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.00001ep-3) = 0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1p-3 ) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000002p-3) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000004p-3) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000006p-3) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000008p-3) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.00000ap-3) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.00000cp-3) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.00000ep-3) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.00001p-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000012p-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000014p-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000016p-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000018p-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.00001ap-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.00001cp-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.00001ep-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000002p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000002p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.000006p-3) = 0x1.000002p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.000008p-3) = 0x1.000002p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.00000ap-3) = 0x1.000002p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.00000cp-3) = 0x1.000002p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.00000ep-3) = 0x1.000002p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.00001p-3 ) = 0x1.000002p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.000012p-3) = 0x1p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.000014p-3) = 0x1p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.000016p-3) = 0x1p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.000018p-3) = 0x1p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.00001ap-3) = 0x1p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.00001cp-3) = 0x1p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1p+0
|
|
+near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0
|
|
+near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0
|
|
+near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0
|
|
+near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0
|
|
+near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0
|
|
+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0
|
|
+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0
|
|
+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001p+0
|
|
+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0
|
|
+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0
|
|
+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0
|
|
+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0
|
|
+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0
|
|
+near:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0
|
|
+near:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0
|
|
+near:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200022p+0
|
|
+near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0
|
|
+near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200002p+0
|
|
+near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0
|
|
+near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0
|
|
+near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0
|
|
+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0
|
|
+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0
|
|
+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001p+0
|
|
+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0
|
|
+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0
|
|
+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0
|
|
+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0
|
|
+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0
|
|
+near:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0
|
|
+near:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0
|
|
+near:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200022p+0
|
|
+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0
|
|
+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0
|
|
+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0
|
|
+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0
|
|
+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0
|
|
+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0
|
|
+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000cp+0
|
|
+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ep+0
|
|
+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200012p+0
|
|
+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0
|
|
+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0
|
|
+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0
|
|
+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0
|
|
+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0
|
|
+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ep+0
|
|
+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20002p+0
|
|
+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0
|
|
+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200002p+0
|
|
+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0
|
|
+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0
|
|
+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0
|
|
+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0
|
|
+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000cp+0
|
|
+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ep+0
|
|
+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200012p+0
|
|
+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0
|
|
+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0
|
|
+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0
|
|
+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0
|
|
+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0
|
|
+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ep+0
|
|
+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20002p+0
|
|
++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0
|
|
++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0
|
|
++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0
|
|
++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0
|
|
++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0
|
|
++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0
|
|
++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000cp+0
|
|
++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ep+0
|
|
++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200012p+0
|
|
++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0
|
|
++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0
|
|
++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0
|
|
++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0
|
|
++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0
|
|
++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ep+0
|
|
++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20002p+0
|
|
++inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0
|
|
++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200004p+0
|
|
++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200006p+0
|
|
++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200008p+0
|
|
++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ap+0
|
|
++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0
|
|
++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0
|
|
++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001p+0
|
|
++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0
|
|
++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200016p+0
|
|
++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200018p+0
|
|
++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ap+0
|
|
++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001cp+0
|
|
++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0
|
|
++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0
|
|
++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200022p+0
|
|
+-inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0
|
|
+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200004p+0
|
|
+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200006p+0
|
|
+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200008p+0
|
|
+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ap+0
|
|
+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0
|
|
+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0
|
|
+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001p+0
|
|
+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0
|
|
+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200016p+0
|
|
+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200018p+0
|
|
+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ap+0
|
|
+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001cp+0
|
|
+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0
|
|
+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0
|
|
+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200022p+0
|
|
+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0
|
|
+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200002p+0
|
|
+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0
|
|
+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0
|
|
+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0
|
|
+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0
|
|
+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000cp+0
|
|
+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ep+0
|
|
+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200012p+0
|
|
+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0
|
|
+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0
|
|
+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0
|
|
+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0
|
|
+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0
|
|
+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ep+0
|
|
+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20002p+0
|
|
+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
+near:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0
|
|
+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
+near:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec4p+0
|
|
+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
+near:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745ep+0
|
|
+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
+near:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f6p+0
|
|
+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
+near:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92492p+0
|
|
+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
+near:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f6p+0
|
|
+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148
|
|
+near:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f8p+0
|
|
+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148
|
|
+near:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b14p+0
|
|
+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+near:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f7p+0
|
|
+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+near:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec4p+0
|
|
+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+near:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745ep+0
|
|
+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
+near:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f6p+0
|
|
+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
+near:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92492p+0
|
|
+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
+near:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f6p+0
|
|
+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148
|
|
+near:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f8p+0
|
|
+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148
|
|
+near:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b14p+0
|
|
+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
+zero:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0
|
|
+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
+zero:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec4p+0
|
|
+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
+zero:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745cp+0
|
|
+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
+zero:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f4p+0
|
|
+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
+zero:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92492p+0
|
|
+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
+zero:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f6p+0
|
|
+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
+zero:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f6p+0
|
|
+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
+zero:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b12p+0
|
|
+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+zero:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f7p+0
|
|
+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+zero:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec4p+0
|
|
+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+zero:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745cp+0
|
|
+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+zero:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f4p+0
|
|
+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
+zero:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92492p+0
|
|
+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
+zero:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f6p+0
|
|
+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
+zero:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f6p+0
|
|
+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
+zero:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b12p+0
|
|
++inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
++inf:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0
|
|
++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0
|
|
++inf:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec4p+0
|
|
++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0
|
|
++inf:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745cp+0
|
|
++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0
|
|
++inf:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f4p+0
|
|
++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
|
|
++inf:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92492p+0
|
|
++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
|
|
++inf:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f6p+0
|
|
++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
|
|
++inf:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f6p+0
|
|
++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
|
|
++inf:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b12p+0
|
|
++inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
++inf:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f72p+0
|
|
++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
|
|
++inf:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec6p+0
|
|
++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
|
|
++inf:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745ep+0
|
|
++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
|
|
++inf:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f6p+0
|
|
++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
|
|
++inf:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92494p+0
|
|
++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148
|
|
++inf:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f8p+0
|
|
++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148
|
|
++inf:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f8p+0
|
|
++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148
|
|
++inf:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b14p+0
|
|
+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
+-inf:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f72p+0
|
|
+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
+-inf:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec6p+0
|
|
+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
+-inf:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745ep+0
|
|
+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
+-inf:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f6p+0
|
|
+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
+-inf:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92494p+0
|
|
+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148
|
|
+-inf:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f8p+0
|
|
+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148
|
|
+-inf:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f8p+0
|
|
+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148
|
|
+-inf:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b14p+0
|
|
+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+-inf:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f7p+0
|
|
+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+-inf:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec4p+0
|
|
+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+-inf:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745cp+0
|
|
+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+-inf:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f4p+0
|
|
+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
+-inf:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92492p+0
|
|
+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
+-inf:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f6p+0
|
|
+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
+-inf:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f6p+0
|
|
+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
+-inf:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b12p+0
|
|
+near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
|
|
+near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
+near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
+near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
|
|
+near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
|
+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
|
+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
|
|
+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
+near:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
|
+near:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
+near:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
+near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
|
|
+near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
+near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
+near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
|
|
+near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
|
+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
|
+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
|
|
+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
+near:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
|
+near:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
+near:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
|
|
+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
|
|
+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
|
+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
|
+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
|
+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
|
+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
|
|
+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
|
|
+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
|
+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
|
+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
|
+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
|
+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
|
|
++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
|
|
++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
|
++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
|
++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
|
++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
|
++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
++inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
|
|
++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
|
|
++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
|
++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
|
++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
|
|
++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00024p+0
|
|
+-inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
|
|
+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
|
|
+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
|
+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
|
+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
|
|
+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00024p+0
|
|
+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
|
|
+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
|
|
+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
|
+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
|
+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
|
+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
|
+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
+near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
|
|
+near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
+near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
+near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
|
|
+near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
|
+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
|
+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
|
|
+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
+near:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
|
+near:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
+near:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
+near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
|
|
+near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
+near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
+near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
|
|
+near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
|
+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
|
+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
|
|
+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
+near:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
|
+near:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
+near:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
|
|
+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
|
|
+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
|
+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
|
+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
|
+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
|
+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
|
|
+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
|
|
+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
|
+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
|
+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
|
+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
|
+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
|
|
++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
|
|
++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
|
++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
|
++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
|
++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
|
++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
++inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
|
|
++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
|
|
++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
|
++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
|
++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
|
|
++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00024p+0
|
|
+-inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
|
|
+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
|
|
+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
|
+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
|
+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
|
|
+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00024p+0
|
|
+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
|
|
+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
|
|
+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
|
+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
|
+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
|
+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
|
+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
+near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
|
|
+near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
+near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
+near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
|
|
+near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
|
+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
|
+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
|
|
+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
+near:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
|
+near:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
+near:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
+near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
|
|
+near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
+near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
+near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
|
|
+near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
|
+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
|
+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
|
|
+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
+near:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
|
+near:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
+near:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
|
|
+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
|
|
+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
|
+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
|
+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
|
+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
|
+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
|
|
+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
|
|
+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
|
+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
|
+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
|
+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
|
+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
|
|
++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
|
|
++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
|
++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
|
++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
|
++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
|
++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
++inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
|
|
++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
|
|
++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
|
++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
|
++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
|
|
++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00024p+0
|
|
+-inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
|
|
+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
|
|
+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
|
+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
|
+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
|
|
+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00024p+0
|
|
+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
|
|
+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
|
|
+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
|
+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
|
+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
|
+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
|
+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
+near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
|
|
+near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
+near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
+near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
|
|
+near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
|
+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
|
+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
|
|
+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
+near:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
|
+near:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
+near:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
+near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
|
|
+near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
+near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
+near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
|
|
+near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
|
+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
|
+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
|
|
+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
+near:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
|
+near:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
+near:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
|
|
+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
|
|
+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
|
+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
|
+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
|
+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
|
+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
|
|
+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
|
|
+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
|
+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
|
+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
|
+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
|
+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
|
|
++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
|
|
++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
|
++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
|
++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
|
++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
|
++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
++inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
|
|
++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
|
|
++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
|
++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
|
++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
|
|
++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00024p+0
|
|
+-inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
|
|
+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
|
|
+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
|
+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
|
+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
|
|
+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00024p+0
|
|
+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
|
|
+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
|
|
+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
|
+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
|
+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
|
+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
|
+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
+-------------------------- test rounding of double operators with guard bits --------------------------
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2000000000001p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2000000000001p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2000000000001p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000001p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000001p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000001p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000002p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000002p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000002p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000002p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2000000000001p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2000000000001p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2000000000001p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000001p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000001p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000001p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000002p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000002p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000002p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000002p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000002p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000002p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000002p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000002p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000002p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000002p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000002p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000002p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000002p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000002p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000002p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000002p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000002p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000002p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000001p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000002p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000002p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000002p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000002p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000001p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000001p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000001p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1.0000000000001p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1.0000000000001p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1.0000000000001p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000002p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000002p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000002p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000002p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000001p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000001p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000001p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1.0000000000001p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1.0000000000001p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1.0000000000001p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000002p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000002p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000002p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000002p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000002p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000002p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000002p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000002p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000002p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000002p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000002p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000002p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000002p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000002p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1p+0
|
|
+near:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0
|
|
+near:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000001p+0
|
|
+near:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0
|
|
+near:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0
|
|
+near:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0
|
|
+near:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0
|
|
+near:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0
|
|
+near:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000008p+0
|
|
+near:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0
|
|
+near:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000ap+0
|
|
+near:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000bp+0
|
|
+near:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000cp+0
|
|
+near:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0
|
|
+near:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000fp+0
|
|
+near:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000001p+0
|
|
+near:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.2000000000011p+0
|
|
+near:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0
|
|
+near:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000001p+0
|
|
+near:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0
|
|
+near:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0
|
|
+near:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0
|
|
+near:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0
|
|
+near:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0
|
|
+near:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000008p+0
|
|
+near:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0
|
|
+near:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000ap+0
|
|
+near:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000bp+0
|
|
+near:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000cp+0
|
|
+near:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0
|
|
+near:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000fp+0
|
|
+near:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000001p+0
|
|
+near:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.2000000000011p+0
|
|
+zero:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0
|
|
+zero:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000001p+0
|
|
+zero:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0
|
|
+zero:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0
|
|
+zero:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0
|
|
+zero:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000005p+0
|
|
+zero:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0
|
|
+zero:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0
|
|
+zero:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0
|
|
+zero:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000ap+0
|
|
+zero:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000bp+0
|
|
+zero:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000cp+0
|
|
+zero:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000dp+0
|
|
+zero:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0
|
|
+zero:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000000fp+0
|
|
+zero:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.200000000001p+0
|
|
+zero:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0
|
|
+zero:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000001p+0
|
|
+zero:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0
|
|
+zero:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0
|
|
+zero:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0
|
|
+zero:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000005p+0
|
|
+zero:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0
|
|
+zero:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0
|
|
+zero:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0
|
|
+zero:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000ap+0
|
|
+zero:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000bp+0
|
|
+zero:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000cp+0
|
|
+zero:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000dp+0
|
|
+zero:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0
|
|
+zero:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000000fp+0
|
|
+zero:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.200000000001p+0
|
|
++inf:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0
|
|
++inf:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000001p+0
|
|
++inf:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0
|
|
++inf:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0
|
|
++inf:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0
|
|
++inf:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000005p+0
|
|
++inf:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0
|
|
++inf:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0
|
|
++inf:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0
|
|
++inf:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000ap+0
|
|
++inf:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000bp+0
|
|
++inf:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000cp+0
|
|
++inf:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000dp+0
|
|
++inf:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0
|
|
++inf:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000000fp+0
|
|
++inf:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.200000000001p+0
|
|
++inf:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0
|
|
++inf:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0
|
|
++inf:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0
|
|
++inf:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0
|
|
++inf:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000005p+0
|
|
++inf:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0
|
|
++inf:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0
|
|
++inf:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000008p+0
|
|
++inf:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0
|
|
++inf:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000bp+0
|
|
++inf:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000cp+0
|
|
++inf:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000dp+0
|
|
++inf:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0
|
|
++inf:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000fp+0
|
|
++inf:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000001p+0
|
|
++inf:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.2000000000011p+0
|
|
+-inf:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0
|
|
+-inf:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0
|
|
+-inf:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0
|
|
+-inf:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0
|
|
+-inf:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000005p+0
|
|
+-inf:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0
|
|
+-inf:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0
|
|
+-inf:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000008p+0
|
|
+-inf:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0
|
|
+-inf:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000bp+0
|
|
+-inf:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000cp+0
|
|
+-inf:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000dp+0
|
|
+-inf:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0
|
|
+-inf:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000fp+0
|
|
+-inf:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000001p+0
|
|
+-inf:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.2000000000011p+0
|
|
+-inf:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0
|
|
+-inf:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000001p+0
|
|
+-inf:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0
|
|
+-inf:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0
|
|
+-inf:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0
|
|
+-inf:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000005p+0
|
|
+-inf:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0
|
|
+-inf:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0
|
|
+-inf:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0
|
|
+-inf:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000ap+0
|
|
+-inf:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000bp+0
|
|
+-inf:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000cp+0
|
|
+-inf:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000dp+0
|
|
+-inf:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0
|
|
+-inf:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000000fp+0
|
|
+-inf:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.200000000001p+0
|
|
+-62/62
|
|
+near:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0
|
|
+-64/62
|
|
+near:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421084p+0
|
|
+-66/62
|
|
+near:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842108p+0
|
|
+-100/62
|
|
+near:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cep+0
|
|
+near:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0p+0
|
|
+-102/62
|
|
+near:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a53p+0
|
|
+-106/62
|
|
+near:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5bp+0
|
|
+-108/62
|
|
+near:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdfp+0
|
|
+-108/108
|
|
+near:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0
|
|
+-112/62
|
|
+near:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce7p+0
|
|
+-114/62
|
|
+near:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6bp+0
|
|
+-116/62
|
|
+near:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdefp+0
|
|
+near:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000002p-1022
|
|
+-118/62
|
|
+near:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce74p+0
|
|
+-90/62
|
|
+near:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce73ap+0
|
|
+-92/62
|
|
+near:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bep+0
|
|
+62/62
|
|
+near:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0
|
|
+64/62
|
|
+near:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421084p+0
|
|
+66/62
|
|
+near:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842108p+0
|
|
+100/62
|
|
+near:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cep+0
|
|
+near:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0p+0
|
|
+102/62
|
|
+near:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a53p+0
|
|
+106/62
|
|
+near:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5bp+0
|
|
+108/62
|
|
+near:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdfp+0
|
|
+108/108
|
|
+near:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0
|
|
+112/62
|
|
+near:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce7p+0
|
|
+114/62
|
|
+near:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6bp+0
|
|
+116/62
|
|
+near:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdefp+0
|
|
+near:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000002p-1022
|
|
+118/62
|
|
+near:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce74p+0
|
|
+90/62
|
|
+near:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce73ap+0
|
|
+92/62
|
|
+near:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bep+0
|
|
+-62/62
|
|
+zero:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0
|
|
+-64/62
|
|
+zero:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421084p+0
|
|
+-66/62
|
|
+zero:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842108p+0
|
|
+-100/62
|
|
+zero:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cep+0
|
|
+zero:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0p+0
|
|
+-102/62
|
|
+zero:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a52p+0
|
|
+-106/62
|
|
+zero:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5ap+0
|
|
+-108/62
|
|
+zero:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdep+0
|
|
+-108/108
|
|
+zero:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0
|
|
+-112/62
|
|
+zero:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce7p+0
|
|
+-114/62
|
|
+zero:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6bp+0
|
|
+-116/62
|
|
+zero:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdefp+0
|
|
+zero:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000001p-1022
|
|
+-118/62
|
|
+zero:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce73p+0
|
|
+-90/62
|
|
+zero:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce739p+0
|
|
+-92/62
|
|
+zero:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bdp+0
|
|
+62/62
|
|
+zero:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0
|
|
+64/62
|
|
+zero:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421084p+0
|
|
+66/62
|
|
+zero:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842108p+0
|
|
+100/62
|
|
+zero:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cep+0
|
|
+zero:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0p+0
|
|
+102/62
|
|
+zero:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a52p+0
|
|
+106/62
|
|
+zero:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5ap+0
|
|
+108/62
|
|
+zero:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdep+0
|
|
+108/108
|
|
+zero:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0
|
|
+112/62
|
|
+zero:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce7p+0
|
|
+114/62
|
|
+zero:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6bp+0
|
|
+116/62
|
|
+zero:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdefp+0
|
|
+zero:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000001p-1022
|
|
+118/62
|
|
+zero:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce73p+0
|
|
+90/62
|
|
+zero:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce739p+0
|
|
+92/62
|
|
+zero:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bdp+0
|
|
+-62/62
|
|
++inf:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0
|
|
+-64/62
|
|
++inf:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421084p+0
|
|
+-66/62
|
|
++inf:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842108p+0
|
|
+-100/62
|
|
++inf:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cep+0
|
|
++inf:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0p+0
|
|
+-102/62
|
|
++inf:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a52p+0
|
|
+-106/62
|
|
++inf:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5ap+0
|
|
+-108/62
|
|
++inf:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdep+0
|
|
+-108/108
|
|
++inf:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0
|
|
+-112/62
|
|
++inf:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce7p+0
|
|
+-114/62
|
|
++inf:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6bp+0
|
|
+-116/62
|
|
++inf:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdefp+0
|
|
++inf:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000001p-1022
|
|
+-118/62
|
|
++inf:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce73p+0
|
|
+-90/62
|
|
++inf:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce739p+0
|
|
+-92/62
|
|
++inf:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bdp+0
|
|
+62/62
|
|
++inf:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0
|
|
+64/62
|
|
++inf:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421085p+0
|
|
+66/62
|
|
++inf:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842109p+0
|
|
+100/62
|
|
++inf:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cfp+0
|
|
++inf:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0.0000000000001p-1022
|
|
+102/62
|
|
++inf:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a53p+0
|
|
+106/62
|
|
++inf:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5bp+0
|
|
+108/62
|
|
++inf:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdfp+0
|
|
+108/108
|
|
++inf:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0
|
|
+112/62
|
|
++inf:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce8p+0
|
|
+114/62
|
|
++inf:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6cp+0
|
|
+116/62
|
|
++inf:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdfp+0
|
|
++inf:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000002p-1022
|
|
+118/62
|
|
++inf:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce74p+0
|
|
+90/62
|
|
++inf:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce73ap+0
|
|
+92/62
|
|
++inf:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bep+0
|
|
+-62/62
|
|
+-inf:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0
|
|
+-64/62
|
|
+-inf:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421085p+0
|
|
+-66/62
|
|
+-inf:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842109p+0
|
|
+-100/62
|
|
+-inf:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cfp+0
|
|
+-inf:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0.0000000000001p-1022
|
|
+-102/62
|
|
+-inf:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a53p+0
|
|
+-106/62
|
|
+-inf:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5bp+0
|
|
+-108/62
|
|
+-inf:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdfp+0
|
|
+-108/108
|
|
+-inf:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0
|
|
+-112/62
|
|
+-inf:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce8p+0
|
|
+-114/62
|
|
+-inf:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6cp+0
|
|
+-116/62
|
|
+-inf:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdfp+0
|
|
+-inf:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000002p-1022
|
|
+-118/62
|
|
+-inf:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce74p+0
|
|
+-90/62
|
|
+-inf:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce73ap+0
|
|
+-92/62
|
|
+-inf:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bep+0
|
|
+62/62
|
|
+-inf:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0
|
|
+64/62
|
|
+-inf:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421084p+0
|
|
+66/62
|
|
+-inf:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842108p+0
|
|
+100/62
|
|
+-inf:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cep+0
|
|
+-inf:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0p+0
|
|
+102/62
|
|
+-inf:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a52p+0
|
|
+106/62
|
|
+-inf:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5ap+0
|
|
+108/62
|
|
+-inf:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdep+0
|
|
+108/108
|
|
+-inf:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0
|
|
+112/62
|
|
+-inf:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce7p+0
|
|
+114/62
|
|
+-inf:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6bp+0
|
|
+116/62
|
|
+-inf:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdefp+0
|
|
+-inf:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000001p-1022
|
|
+118/62
|
|
+-inf:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce73p+0
|
|
+90/62
|
|
+-inf:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce739p+0
|
|
+92/62
|
|
+-inf:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bdp+0
|
|
+near:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
|
|
+near:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+near:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+near:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0
|
|
+near:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+near:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
+near:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+near:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+near:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+near:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+near:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+near:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0
|
|
+near:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+near:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
+near:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+near:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
+near:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
|
|
+near:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+near:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+near:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0
|
|
+near:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+near:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
+near:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+near:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+near:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+near:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+near:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+near:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0
|
|
+near:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+near:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
+near:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+near:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
+zero:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
|
|
+zero:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
+zero:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+zero:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+zero:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+zero:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
+zero:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+zero:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+zero:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
+zero:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+zero:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+zero:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+zero:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+zero:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
+zero:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+zero:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
+zero:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
|
|
+zero:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
+zero:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+zero:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+zero:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+zero:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
+zero:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+zero:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+zero:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
+zero:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+zero:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+zero:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+zero:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+zero:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
+zero:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+zero:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
++inf:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
|
|
++inf:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
++inf:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
++inf:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
++inf:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
++inf:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
++inf:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
++inf:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
++inf:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
++inf:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
++inf:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
++inf:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
++inf:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
++inf:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
++inf:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
++inf:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
++inf:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
++inf:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
++inf:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
++inf:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0
|
|
++inf:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
++inf:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
++inf:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
++inf:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
++inf:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
++inf:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
++inf:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
++inf:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0
|
|
++inf:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
++inf:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
++inf:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
++inf:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000012p+0
|
|
+-inf:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
+-inf:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+-inf:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+-inf:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0
|
|
+-inf:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+-inf:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+-inf:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+-inf:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
+-inf:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+-inf:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+-inf:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+-inf:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0
|
|
+-inf:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+-inf:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+-inf:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
+-inf:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000012p+0
|
|
+-inf:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
|
|
+-inf:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
+-inf:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+-inf:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+-inf:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+-inf:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
+-inf:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+-inf:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+-inf:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
+-inf:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+-inf:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+-inf:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+-inf:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+-inf:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
+-inf:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+-inf:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
+near:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
|
|
+near:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+near:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+near:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0
|
|
+near:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+near:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
+near:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+near:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+near:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+near:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+near:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+near:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0
|
|
+near:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+near:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
+near:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+near:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
+near:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
|
|
+near:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+near:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+near:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0
|
|
+near:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+near:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
+near:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+near:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+near:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+near:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+near:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+near:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0
|
|
+near:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+near:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
+near:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+near:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
+zero:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
|
|
+zero:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
+zero:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+zero:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+zero:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+zero:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
+zero:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+zero:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+zero:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
+zero:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+zero:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+zero:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+zero:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+zero:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
+zero:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+zero:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
+zero:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
|
|
+zero:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
+zero:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+zero:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+zero:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+zero:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
+zero:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+zero:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+zero:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
+zero:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+zero:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+zero:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+zero:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+zero:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
+zero:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+zero:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
++inf:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
|
|
++inf:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
++inf:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
++inf:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
++inf:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
++inf:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
++inf:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
++inf:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
++inf:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
++inf:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
++inf:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
++inf:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
++inf:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
++inf:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
++inf:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
++inf:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
++inf:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
++inf:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
++inf:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
++inf:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0
|
|
++inf:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
++inf:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
++inf:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
++inf:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
++inf:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
++inf:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
++inf:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
++inf:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0
|
|
++inf:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
++inf:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
++inf:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
++inf:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000012p+0
|
|
+-inf:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
+-inf:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+-inf:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+-inf:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0
|
|
+-inf:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+-inf:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+-inf:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+-inf:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
+-inf:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+-inf:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+-inf:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+-inf:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0
|
|
+-inf:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+-inf:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+-inf:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
+-inf:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000012p+0
|
|
+-inf:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
|
|
+-inf:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
+-inf:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+-inf:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+-inf:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+-inf:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
+-inf:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+-inf:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+-inf:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
+-inf:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+-inf:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+-inf:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+-inf:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+-inf:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
+-inf:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+-inf:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
+near:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
|
|
+near:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+near:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+near:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0
|
|
+near:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+near:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
+near:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+near:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+near:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+near:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+near:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+near:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0
|
|
+near:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+near:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
+near:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+near:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
+near:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
|
|
+near:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+near:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+near:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0
|
|
+near:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+near:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
+near:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+near:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+near:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+near:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+near:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+near:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0
|
|
+near:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+near:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
+near:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+near:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
+zero:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
|
|
+zero:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
+zero:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+zero:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+zero:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+zero:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
+zero:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+zero:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+zero:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
+zero:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+zero:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+zero:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+zero:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+zero:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
+zero:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+zero:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
+zero:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
|
|
+zero:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
+zero:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+zero:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+zero:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+zero:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
+zero:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+zero:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+zero:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
+zero:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+zero:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+zero:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+zero:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+zero:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
+zero:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+zero:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
++inf:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
|
|
++inf:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
++inf:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
++inf:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
++inf:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
++inf:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
++inf:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
++inf:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
++inf:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
++inf:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
++inf:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
++inf:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
++inf:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
++inf:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
++inf:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
++inf:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
++inf:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
++inf:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
++inf:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
++inf:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0
|
|
++inf:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
++inf:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
++inf:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
++inf:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
++inf:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
++inf:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
++inf:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
++inf:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0
|
|
++inf:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
++inf:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
++inf:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
++inf:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000012p+0
|
|
+-inf:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
+-inf:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+-inf:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+-inf:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0
|
|
+-inf:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+-inf:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+-inf:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+-inf:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
+-inf:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+-inf:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+-inf:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+-inf:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0
|
|
+-inf:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+-inf:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+-inf:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
+-inf:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000012p+0
|
|
+-inf:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
|
|
+-inf:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
+-inf:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+-inf:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+-inf:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+-inf:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
+-inf:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+-inf:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+-inf:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
+-inf:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+-inf:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+-inf:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+-inf:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+-inf:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
+-inf:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+-inf:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
+near:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
|
|
+near:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+near:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+near:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0
|
|
+near:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+near:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
+near:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+near:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+near:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+near:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+near:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+near:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0
|
|
+near:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+near:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
+near:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+near:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
+near:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
|
|
+near:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+near:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+near:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0
|
|
+near:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+near:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
+near:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+near:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+near:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+near:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+near:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+near:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0
|
|
+near:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+near:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
+near:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+near:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
+zero:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
|
|
+zero:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
+zero:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+zero:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+zero:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+zero:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
+zero:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+zero:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+zero:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
+zero:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+zero:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+zero:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+zero:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+zero:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
+zero:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+zero:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
+zero:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
|
|
+zero:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
+zero:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+zero:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+zero:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+zero:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
+zero:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+zero:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+zero:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
+zero:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+zero:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+zero:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+zero:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+zero:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
+zero:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+zero:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
++inf:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
|
|
++inf:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
++inf:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
++inf:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
++inf:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
++inf:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
++inf:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
++inf:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
++inf:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
++inf:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
++inf:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
++inf:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
++inf:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
++inf:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
++inf:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
++inf:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
++inf:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
++inf:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
++inf:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
++inf:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0
|
|
++inf:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
++inf:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
++inf:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
++inf:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
++inf:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
++inf:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
++inf:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
++inf:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0
|
|
++inf:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
++inf:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
++inf:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
++inf:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000012p+0
|
|
+-inf:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
+-inf:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+-inf:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+-inf:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0
|
|
+-inf:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+-inf:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+-inf:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+-inf:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
+-inf:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+-inf:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+-inf:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+-inf:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0
|
|
+-inf:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+-inf:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+-inf:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
+-inf:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000012p+0
|
|
+-inf:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
|
|
+-inf:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
+-inf:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+-inf:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+-inf:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+-inf:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
+-inf:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+-inf:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+-inf:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
+-inf:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+-inf:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+-inf:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+-inf:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+-inf:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
+-inf:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+-inf:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
+near:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049ep-1
|
|
+near:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6dp+0
|
|
+near:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3bfp+0
|
|
+near:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0937p-1
|
|
+near:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b2p+0
|
|
+near:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7483p+0
|
|
+near:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7cp-1
|
|
+near:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9ep+0
|
|
+near:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6cp-1
|
|
+near:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0acp-1
|
|
+near:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e3p+0
|
|
+near:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0b1p-1
|
|
+near:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907afp-1
|
|
+near:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed828p+0
|
|
+zero:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049ep-1
|
|
+zero:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6dp+0
|
|
+zero:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3bfp+0
|
|
+zero:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0937p-1
|
|
+zero:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b2p+0
|
|
+zero:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7483p+0
|
|
+zero:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7cp-1
|
|
+zero:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9dp+0
|
|
+zero:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6bp-1
|
|
+zero:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0abfp-1
|
|
+zero:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e2p+0
|
|
+zero:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0bp-1
|
|
+zero:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907aep-1
|
|
+zero:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed827p+0
|
|
++inf:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049fp-1
|
|
++inf:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6ep+0
|
|
++inf:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3cp+0
|
|
++inf:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0938p-1
|
|
++inf:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b3p+0
|
|
++inf:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7484p+0
|
|
++inf:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7dp-1
|
|
++inf:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9ep+0
|
|
++inf:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6cp-1
|
|
++inf:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0acp-1
|
|
++inf:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e3p+0
|
|
++inf:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0b1p-1
|
|
++inf:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907afp-1
|
|
++inf:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed828p+0
|
|
+-inf:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049ep-1
|
|
+-inf:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6dp+0
|
|
+-inf:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3bfp+0
|
|
+-inf:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0937p-1
|
|
+-inf:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b2p+0
|
|
+-inf:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7483p+0
|
|
+-inf:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7cp-1
|
|
+-inf:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9dp+0
|
|
+-inf:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6bp-1
|
|
+-inf:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0abfp-1
|
|
+-inf:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e2p+0
|
|
+-inf:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0bp-1
|
|
+-inf:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907aep-1
|
|
+-inf:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed827p+0
|
|
Index: none/tests/ppc64/jm-fp.stdout.exp-LE2
|
|
===================================================================
|
|
--- /dev/null
|
|
+++ none/tests/ppc64/jm-fp.stdout.exp-LE2
|
|
@@ -0,0 +1,1533 @@
|
|
+PPC floating point arith insns with three args:
|
|
+ fsel 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000
|
|
+ fsel 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300
|
|
+ fsel 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
|
|
+ fsel 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000
|
|
+ fsel 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300
|
|
+ fsel 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
|
|
+ fsel bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fsel bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fsel bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fmadd 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100
|
|
+ fmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00
|
|
+ fmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000
|
|
+ fmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100
|
|
+ fmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fmadds 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+
|
|
+ fmsub 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
|
|
+ fmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
|
|
+ fmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00
|
|
+ fmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100
|
|
+ fmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000
|
|
+ fmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00
|
|
+ fmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+
|
|
+ fmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+
|
|
+ fnmadd 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
|
|
+ fnmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
|
|
+ fnmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100
|
|
+ fnmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00
|
|
+ fnmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000
|
|
+ fnmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100
|
|
+ fnmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+
|
|
+ fnmadds 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+
|
|
+ fnmsub 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fnmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fnmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00
|
|
+ fnmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100
|
|
+ fnmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000
|
|
+ fnmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00
|
|
+ fnmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fnmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+
|
|
+PPC floating point arith insns
|
|
+ with three args with flags update:
|
|
+ fsel. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel. 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000
|
|
+ fsel. 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300
|
|
+ fsel. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
|
|
+ fsel. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000
|
|
+ fsel. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300
|
|
+ fsel. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
|
|
+ fsel. bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fsel. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fsel. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100
|
|
+ fmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00
|
|
+ fmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000
|
|
+ fmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100
|
|
+ fmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+
|
|
+ fmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
|
|
+ fmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
|
|
+ fmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00
|
|
+ fmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100
|
|
+ fmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000
|
|
+ fmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00
|
|
+ fmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+
|
|
+ fmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+
|
|
+ fnmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
|
|
+ fnmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
|
|
+ fnmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100
|
|
+ fnmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00
|
|
+ fnmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000
|
|
+ fnmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100
|
|
+ fnmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+
|
|
+ fnmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+
|
|
+ fnmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fnmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fnmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00
|
|
+ fnmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100
|
|
+ fnmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000
|
|
+ fnmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00
|
|
+ fnmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fnmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+
|
|
+PPC floating point arith insns with two args:
|
|
+ fadd 0010000000000001, 0010000000000001 => 0020000000000001
|
|
+ fadd 0010000000000001, 80100094e0000359 => 80000094e0000358
|
|
+ fadd 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadd 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
|
|
+ fadd 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
|
|
+ fadd 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fadd bfe0000000000001, 0010000000000001 => bfe0000000000001
|
|
+ fadd bfe0000000000001, 80100094e0000359 => bfe0000000000001
|
|
+ fadd bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadd 8000000000000000, 0010000000000001 => 0010000000000001
|
|
+ fadd 8000000000000000, 80100094e0000359 => 80100094e0000359
|
|
+ fadd 8000000000000000, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fadd 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fadd 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fadd 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fadd 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fadd fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fadd fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fadd fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fadd fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fadds 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fadds 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fadds 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadds 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
|
|
+ fadds 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
|
|
+ fadds 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fadds bfe0000000000001, 0010000000000001 => bfe0000000000000
|
|
+ fadds bfe0000000000001, 80100094e0000359 => bfe0000000000000
|
|
+ fadds bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadds 8000000000000000, 0010000000000001 => 0000000000000000
|
|
+ fadds 8000000000000000, 80100094e0000359 => 8000000000000000
|
|
+ fadds 8000000000000000, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fadds 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fadds 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fadds 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fadds 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fadds fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fadds fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fadds fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fadds fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fsub 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fsub 0010000000000001, 80100094e0000359 => 0020004a700001ad
|
|
+ fsub 0010000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsub 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsub 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
|
|
+ fsub 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
|
|
+ fsub 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
|
|
+ fsub 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fsub bfe0000000000001, 0010000000000001 => bfe0000000000001
|
|
+ fsub bfe0000000000001, 80100094e0000359 => bfe0000000000001
|
|
+ fsub bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsub bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsub 8000000000000000, 0010000000000001 => 8010000000000001
|
|
+ fsub 8000000000000000, 80100094e0000359 => 00100094e0000359
|
|
+ fsub 8000000000000000, 7ff0000000000000 => fff0000000000000
|
|
+ fsub 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fsub 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fsub 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fsub 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fsub 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fsub fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fsub fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fsub fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fsub fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fsubs 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fsubs 0010000000000001, 80100094e0000359 => 0000000000000000
|
|
+ fsubs 0010000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsubs 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
|
|
+ fsubs 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
|
|
+ fsubs 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fsubs bfe0000000000001, 0010000000000001 => bfe0000000000000
|
|
+ fsubs bfe0000000000001, 80100094e0000359 => bfe0000000000000
|
|
+ fsubs bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsubs 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fsubs 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fsubs 8000000000000000, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fsubs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fsubs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fsubs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fsubs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fsubs fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fsubs fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fsubs fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fsubs fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fmul 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmul 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fmul 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmul 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmul 3fe00094e0000359, 0010000000000001 => 0008004a700001ad
|
|
+ fmul 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179
|
|
+ fmul 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmul 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fmul bfe0000000000001, 0010000000000001 => 8008000000000001
|
|
+ fmul bfe0000000000001, 80100094e0000359 => 0008004a700001ad
|
|
+ fmul bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fmul bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmul 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fmul 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fmul 8000000000000000, 7ff0000000000000 => 7ff8000000000000
|
|
+ fmul 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fmul 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fmul 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fmul 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fmul 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fmul fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fmul fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fmul fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fmul fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fmuls 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmuls 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fmuls 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmuls 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmuls 3fe00094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmuls 3fe00094e0000359, 80100094e0000359 => 8000000000000000
|
|
+ fmuls 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmuls 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fmuls bfe0000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmuls bfe0000000000001, 80100094e0000359 => 0000000000000000
|
|
+ fmuls bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fmuls bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmuls 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fmuls 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fmuls 8000000000000000, 7ff0000000000000 => 7ff8000000000000
|
|
+ fmuls 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fmuls 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fmuls 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fmuls 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fmuls 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fmuls fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fmuls fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fmuls fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fmuls fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fdiv 0010000000000001, 0010000000000001 => 3ff0000000000000
|
|
+ fdiv 0010000000000001, 80100094e0000359 => bfeffed64ad20d22
|
|
+ fdiv 0010000000000001, 7ff0000000000000 => 0000000000000000
|
|
+ fdiv 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdiv 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358
|
|
+ fdiv 3fe00094e0000359, 80100094e0000359 => ffc0000000000000
|
|
+ fdiv 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
|
|
+ fdiv 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fdiv bfe0000000000001, 0010000000000001 => ffc0000000000000
|
|
+ fdiv bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22
|
|
+ fdiv bfe0000000000001, 7ff0000000000000 => 8000000000000000
|
|
+ fdiv bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdiv 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fdiv 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fdiv 8000000000000000, 7ff0000000000000 => 8000000000000000
|
|
+ fdiv 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fdiv 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fdiv 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fdiv 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fdiv 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fdiv fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fdiv fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fdiv fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fdiv fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fdivs 0010000000000001, 0010000000000001 => 3ff0000000000000
|
|
+ fdivs 0010000000000001, 80100094e0000359 => bfeffed640000000
|
|
+ fdivs 0010000000000001, 7ff0000000000000 => 0000000000000000
|
|
+ fdivs 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdivs 3fe00094e0000359, 0010000000000001 => 7ff0000000000000
|
|
+ fdivs 3fe00094e0000359, 80100094e0000359 => fff0000000000000
|
|
+ fdivs 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
|
|
+ fdivs 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fdivs bfe0000000000001, 0010000000000001 => fff0000000000000
|
|
+ fdivs bfe0000000000001, 80100094e0000359 => 7ff0000000000000
|
|
+ fdivs bfe0000000000001, 7ff0000000000000 => 8000000000000000
|
|
+ fdivs bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdivs 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fdivs 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fdivs 8000000000000000, 7ff0000000000000 => 8000000000000000
|
|
+ fdivs 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fdivs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fdivs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fdivs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fdivs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fdivs fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fdivs fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fdivs fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fdivs fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+PPC floating point arith insns
|
|
+ with two args with flags update:
|
|
+ fadd. 0010000000000001, 0010000000000001 => 0020000000000001
|
|
+ fadd. 0010000000000001, 80100094e0000359 => 80000094e0000358
|
|
+ fadd. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadd. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
|
|
+ fadd. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
|
|
+ fadd. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fadd. bfe0000000000001, 0010000000000001 => bfe0000000000001
|
|
+ fadd. bfe0000000000001, 80100094e0000359 => bfe0000000000001
|
|
+ fadd. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadd. 8000000000000000, 0010000000000001 => 0010000000000001
|
|
+ fadd. 8000000000000000, 80100094e0000359 => 80100094e0000359
|
|
+ fadd. 8000000000000000, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fadd. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fadd. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fadd. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fadd. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fadd. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fadd. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fadd. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fadd. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fadds. 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fadds. 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fadds. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadds. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
|
|
+ fadds. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
|
|
+ fadds. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fadds. bfe0000000000001, 0010000000000001 => bfe0000000000000
|
|
+ fadds. bfe0000000000001, 80100094e0000359 => bfe0000000000000
|
|
+ fadds. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadds. 8000000000000000, 0010000000000001 => 0000000000000000
|
|
+ fadds. 8000000000000000, 80100094e0000359 => 8000000000000000
|
|
+ fadds. 8000000000000000, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fadds. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fadds. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fadds. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fadds. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fadds. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fadds. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fadds. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fadds. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fsub. 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fsub. 0010000000000001, 80100094e0000359 => 0020004a700001ad
|
|
+ fsub. 0010000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsub. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsub. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
|
|
+ fsub. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
|
|
+ fsub. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
|
|
+ fsub. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fsub. bfe0000000000001, 0010000000000001 => bfe0000000000001
|
|
+ fsub. bfe0000000000001, 80100094e0000359 => bfe0000000000001
|
|
+ fsub. bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsub. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsub. 8000000000000000, 0010000000000001 => 8010000000000001
|
|
+ fsub. 8000000000000000, 80100094e0000359 => 00100094e0000359
|
|
+ fsub. 8000000000000000, 7ff0000000000000 => fff0000000000000
|
|
+ fsub. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fsub. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fsub. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fsub. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fsub. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fsub. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fsub. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fsub. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fsub. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fsubs. 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fsubs. 0010000000000001, 80100094e0000359 => 0000000000000000
|
|
+ fsubs. 0010000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsubs. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
|
|
+ fsubs. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
|
|
+ fsubs. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fsubs. bfe0000000000001, 0010000000000001 => bfe0000000000000
|
|
+ fsubs. bfe0000000000001, 80100094e0000359 => bfe0000000000000
|
|
+ fsubs. bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsubs. 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fsubs. 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fsubs. 8000000000000000, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fsubs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fsubs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fsubs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fsubs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fsubs. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fsubs. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fsubs. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fsubs. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fmul. 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmul. 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fmul. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmul. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmul. 3fe00094e0000359, 0010000000000001 => 0008004a700001ad
|
|
+ fmul. 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179
|
|
+ fmul. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmul. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fmul. bfe0000000000001, 0010000000000001 => 8008000000000001
|
|
+ fmul. bfe0000000000001, 80100094e0000359 => 0008004a700001ad
|
|
+ fmul. bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fmul. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmul. 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fmul. 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fmul. 8000000000000000, 7ff0000000000000 => 7ff8000000000000
|
|
+ fmul. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fmul. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fmul. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fmul. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fmul. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fmul. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fmul. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fmul. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fmul. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fmuls. 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmuls. 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fmuls. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmuls. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmuls. 3fe00094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmuls. 3fe00094e0000359, 80100094e0000359 => 8000000000000000
|
|
+ fmuls. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmuls. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fmuls. bfe0000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmuls. bfe0000000000001, 80100094e0000359 => 0000000000000000
|
|
+ fmuls. bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fmuls. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmuls. 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fmuls. 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fmuls. 8000000000000000, 7ff0000000000000 => 7ff8000000000000
|
|
+ fmuls. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fmuls. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fmuls. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fmuls. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fmuls. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fmuls. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fmuls. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fmuls. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fmuls. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fdiv. 0010000000000001, 0010000000000001 => 3ff0000000000000
|
|
+ fdiv. 0010000000000001, 80100094e0000359 => bfeffed64ad20d22
|
|
+ fdiv. 0010000000000001, 7ff0000000000000 => 0000000000000000
|
|
+ fdiv. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdiv. 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358
|
|
+ fdiv. 3fe00094e0000359, 80100094e0000359 => ffc0000000000000
|
|
+ fdiv. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
|
|
+ fdiv. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fdiv. bfe0000000000001, 0010000000000001 => ffc0000000000000
|
|
+ fdiv. bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22
|
|
+ fdiv. bfe0000000000001, 7ff0000000000000 => 8000000000000000
|
|
+ fdiv. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdiv. 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fdiv. 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fdiv. 8000000000000000, 7ff0000000000000 => 8000000000000000
|
|
+ fdiv. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fdiv. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fdiv. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fdiv. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fdiv. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fdiv. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fdiv. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fdiv. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fdiv. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fdivs. 0010000000000001, 0010000000000001 => 3ff0000000000000
|
|
+ fdivs. 0010000000000001, 80100094e0000359 => bfeffed640000000
|
|
+ fdivs. 0010000000000001, 7ff0000000000000 => 0000000000000000
|
|
+ fdivs. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdivs. 3fe00094e0000359, 0010000000000001 => 7ff0000000000000
|
|
+ fdivs. 3fe00094e0000359, 80100094e0000359 => fff0000000000000
|
|
+ fdivs. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
|
|
+ fdivs. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fdivs. bfe0000000000001, 0010000000000001 => fff0000000000000
|
|
+ fdivs. bfe0000000000001, 80100094e0000359 => 7ff0000000000000
|
|
+ fdivs. bfe0000000000001, 7ff0000000000000 => 8000000000000000
|
|
+ fdivs. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdivs. 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fdivs. 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fdivs. 8000000000000000, 7ff0000000000000 => 8000000000000000
|
|
+ fdivs. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fdivs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fdivs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fdivs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fdivs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fdivs. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fdivs. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fdivs. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fdivs. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+PPC floating point compare insns (two args):
|
|
+ fcmpo 0010000000000001, 0010000000000001 => fff8000000000000
|
|
+ fcmpo 0010000000000001, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo 0010000000000001, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fcmpo 3fe00094e0000359, 0010000000000001 => fff8000000000000
|
|
+ fcmpo 3fe00094e0000359, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo 3fe00094e0000359, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fcmpo bfe0000000000001, 0010000000000001 => fff8000000000000
|
|
+ fcmpo bfe0000000000001, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo bfe0000000000001, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fcmpo 8000000000000000, 0010000000000001 => fff8000000000000
|
|
+ fcmpo 8000000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo 8000000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fcmpo 7ff7ffffffffffff, 0010000000000001 => fff8000000000000
|
|
+ fcmpo 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo 7ff7ffffffffffff, fff8000000000000 => fff8000000000000
|
|
+ fcmpo fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fcmpo fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fcmpu 0010000000000001, 0010000000000001 => fff8000000000000
|
|
+ fcmpu 0010000000000001, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu 0010000000000001, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fcmpu 3fe00094e0000359, 0010000000000001 => fff8000000000000
|
|
+ fcmpu 3fe00094e0000359, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu 3fe00094e0000359, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fcmpu bfe0000000000001, 0010000000000001 => fff8000000000000
|
|
+ fcmpu bfe0000000000001, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu bfe0000000000001, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fcmpu 8000000000000000, 0010000000000001 => fff8000000000000
|
|
+ fcmpu 8000000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu 8000000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fcmpu 7ff7ffffffffffff, 0010000000000001 => fff8000000000000
|
|
+ fcmpu 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu 7ff7ffffffffffff, fff8000000000000 => fff8000000000000
|
|
+ fcmpu fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fcmpu fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+PPC floating point arith insns with one arg:
|
|
+ fres 0010000000000001 => 7ff0000000000000
|
|
+ fres 00100094e0000359 => 7ff0000000000000
|
|
+ fres 3fe0000000000001 => 4000000000000000
|
|
+ fres 3fe00094e0000359 => 3ffff00000000000
|
|
+ fres 8010000000000001 => fff0000000000000
|
|
+ fres 80100094e0000359 => fff0000000000000
|
|
+ fres bfe0000000000001 => c000000000000000
|
|
+ fres bfe00094e0000359 => bffff00000000000
|
|
+ fres 0000000000000000 => 7ff0000000000000
|
|
+ fres 8000000000000000 => fff0000000000000
|
|
+ fres 7ff0000000000000 => 0000000000000000
|
|
+ fres fff0000000000000 => 8000000000000000
|
|
+ fres 7ff7ffffffffffff => 7ffff00000000000
|
|
+ fres fff7ffffffffffff => fffff00000000000
|
|
+ fres 7ff8000000000000 => 7ff8000000000000
|
|
+ fres fff8000000000000 => fff8000000000000
|
|
+
|
|
+ frsqrte 0010000000000001 => 5fdf000000000000
|
|
+ frsqrte 00100094e0000359 => 5fdf000000000000
|
|
+ frsqrte 3fe0000000000001 => 3ff6000000000000
|
|
+ frsqrte 3fe00094e0000359 => 3ff6000000000000
|
|
+ frsqrte 8010000000000001 => 7ff8000000000000
|
|
+ frsqrte 80100094e0000359 => 7ff8000000000000
|
|
+ frsqrte bfe0000000000001 => 7ff8000000000000
|
|
+ frsqrte bfe00094e0000359 => 7ff8000000000000
|
|
+ frsqrte 0000000000000000 => 7ff0000000000000
|
|
+ frsqrte 8000000000000000 => fff0000000000000
|
|
+ frsqrte 7ff0000000000000 => 0000000000000000
|
|
+ frsqrte fff0000000000000 => 7ff8000000000000
|
|
+ frsqrte 7ff7ffffffffffff => 7fff000000000000
|
|
+ frsqrte fff7ffffffffffff => ffff000000000000
|
|
+ frsqrte 7ff8000000000000 => 7ff8000000000000
|
|
+ frsqrte fff8000000000000 => fff8000000000000
|
|
+
|
|
+ frsp 0010000000000001 => 0000000000000000
|
|
+ frsp 00100094e0000359 => 0000000000000000
|
|
+ frsp 3fe0000000000001 => 3fe0000000000000
|
|
+ frsp 3fe00094e0000359 => 3fe00094e0000000
|
|
+ frsp 8010000000000001 => 8000000000000000
|
|
+ frsp 80100094e0000359 => 8000000000000000
|
|
+ frsp bfe0000000000001 => bfe0000000000000
|
|
+ frsp bfe00094e0000359 => bfe00094e0000000
|
|
+ frsp 0000000000000000 => 0000000000000000
|
|
+ frsp 8000000000000000 => 8000000000000000
|
|
+ frsp 7ff0000000000000 => 7ff0000000000000
|
|
+ frsp fff0000000000000 => fff0000000000000
|
|
+ frsp 7ff7ffffffffffff => 7fffffffe0000000
|
|
+ frsp fff7ffffffffffff => ffffffffe0000000
|
|
+ frsp 7ff8000000000000 => 7ff8000000000000
|
|
+ frsp fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fctiw 0010000000000001 => 0000000000000000
|
|
+ fctiw 00100094e0000359 => 0000000000000000
|
|
+ fctiw 3fe0000000000001 => 0000000000000001
|
|
+ fctiw 3fe00094e0000359 => 0000000000000001
|
|
+ fctiw 8010000000000001 => 0000000000000000
|
|
+ fctiw 80100094e0000359 => 0000000000000000
|
|
+ fctiw bfe0000000000001 => 00000000ffffffff
|
|
+ fctiw bfe00094e0000359 => 00000000ffffffff
|
|
+ fctiw 0000000000000000 => 0000000000000000
|
|
+ fctiw 8000000000000000 => 0000000000000000
|
|
+ fctiw 7ff0000000000000 => 000000007fffffff
|
|
+ fctiw fff0000000000000 => 0000000080000000
|
|
+ fctiw 7ff7ffffffffffff => 0000000080000000
|
|
+ fctiw fff7ffffffffffff => 0000000080000000
|
|
+ fctiw 7ff8000000000000 => 0000000080000000
|
|
+ fctiw fff8000000000000 => 0000000080000000
|
|
+
|
|
+ fctiwz 0010000000000001 => 0000000000000000
|
|
+ fctiwz 00100094e0000359 => 0000000000000000
|
|
+ fctiwz 3fe0000000000001 => 0000000000000000
|
|
+ fctiwz 3fe00094e0000359 => 0000000000000000
|
|
+ fctiwz 8010000000000001 => 0000000000000000
|
|
+ fctiwz 80100094e0000359 => 0000000000000000
|
|
+ fctiwz bfe0000000000001 => 0000000000000000
|
|
+ fctiwz bfe00094e0000359 => 0000000000000000
|
|
+ fctiwz 0000000000000000 => 0000000000000000
|
|
+ fctiwz 8000000000000000 => 0000000000000000
|
|
+ fctiwz 7ff0000000000000 => 000000007fffffff
|
|
+ fctiwz fff0000000000000 => 0000000080000000
|
|
+ fctiwz 7ff7ffffffffffff => 0000000080000000
|
|
+ fctiwz fff7ffffffffffff => 0000000080000000
|
|
+ fctiwz 7ff8000000000000 => 0000000080000000
|
|
+ fctiwz fff8000000000000 => 0000000080000000
|
|
+
|
|
+ fmr 0010000000000001 => 0010000000000001
|
|
+ fmr 00100094e0000359 => 00100094e0000359
|
|
+ fmr 3fe0000000000001 => 3fe0000000000001
|
|
+ fmr 3fe00094e0000359 => 3fe00094e0000359
|
|
+ fmr 8010000000000001 => 8010000000000001
|
|
+ fmr 80100094e0000359 => 80100094e0000359
|
|
+ fmr bfe0000000000001 => bfe0000000000001
|
|
+ fmr bfe00094e0000359 => bfe00094e0000359
|
|
+ fmr 0000000000000000 => 0000000000000000
|
|
+ fmr 8000000000000000 => 8000000000000000
|
|
+ fmr 7ff0000000000000 => 7ff0000000000000
|
|
+ fmr fff0000000000000 => fff0000000000000
|
|
+ fmr 7ff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fmr fff7ffffffffffff => fff7ffffffffffff
|
|
+ fmr 7ff8000000000000 => 7ff8000000000000
|
|
+ fmr fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fneg 0010000000000001 => 8010000000000001
|
|
+ fneg 00100094e0000359 => 80100094e0000359
|
|
+ fneg 3fe0000000000001 => bfe0000000000001
|
|
+ fneg 3fe00094e0000359 => bfe00094e0000359
|
|
+ fneg 8010000000000001 => 0010000000000001
|
|
+ fneg 80100094e0000359 => 00100094e0000359
|
|
+ fneg bfe0000000000001 => 3fe0000000000001
|
|
+ fneg bfe00094e0000359 => 3fe00094e0000359
|
|
+ fneg 0000000000000000 => 8000000000000000
|
|
+ fneg 8000000000000000 => 0000000000000000
|
|
+ fneg 7ff0000000000000 => fff0000000000000
|
|
+ fneg fff0000000000000 => 7ff0000000000000
|
|
+ fneg 7ff7ffffffffffff => fff7ffffffffffff
|
|
+ fneg fff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fneg 7ff8000000000000 => fff8000000000000
|
|
+ fneg fff8000000000000 => 7ff8000000000000
|
|
+
|
|
+ fabs 0010000000000001 => 0010000000000001
|
|
+ fabs 00100094e0000359 => 00100094e0000359
|
|
+ fabs 3fe0000000000001 => 3fe0000000000001
|
|
+ fabs 3fe00094e0000359 => 3fe00094e0000359
|
|
+ fabs 8010000000000001 => 0010000000000001
|
|
+ fabs 80100094e0000359 => 00100094e0000359
|
|
+ fabs bfe0000000000001 => 3fe0000000000001
|
|
+ fabs bfe00094e0000359 => 3fe00094e0000359
|
|
+ fabs 0000000000000000 => 0000000000000000
|
|
+ fabs 8000000000000000 => 0000000000000000
|
|
+ fabs 7ff0000000000000 => 7ff0000000000000
|
|
+ fabs fff0000000000000 => 7ff0000000000000
|
|
+ fabs 7ff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fabs fff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fabs 7ff8000000000000 => 7ff8000000000000
|
|
+ fabs fff8000000000000 => 7ff8000000000000
|
|
+
|
|
+ fnabs 0010000000000001 => 8010000000000001
|
|
+ fnabs 00100094e0000359 => 80100094e0000359
|
|
+ fnabs 3fe0000000000001 => bfe0000000000001
|
|
+ fnabs 3fe00094e0000359 => bfe00094e0000359
|
|
+ fnabs 8010000000000001 => 8010000000000001
|
|
+ fnabs 80100094e0000359 => 80100094e0000359
|
|
+ fnabs bfe0000000000001 => bfe0000000000001
|
|
+ fnabs bfe00094e0000359 => bfe00094e0000359
|
|
+ fnabs 0000000000000000 => 8000000000000000
|
|
+ fnabs 8000000000000000 => 8000000000000000
|
|
+ fnabs 7ff0000000000000 => fff0000000000000
|
|
+ fnabs fff0000000000000 => fff0000000000000
|
|
+ fnabs 7ff7ffffffffffff => fff7ffffffffffff
|
|
+ fnabs fff7ffffffffffff => fff7ffffffffffff
|
|
+ fnabs 7ff8000000000000 => fff8000000000000
|
|
+ fnabs fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fsqrt 0010000000000001 => 2000000000000000
|
|
+ fsqrt 00100094e0000359 => 2000004a6f52dd4a
|
|
+ fsqrt 3fe0000000000001 => 3fe6a09e667f3bcd
|
|
+ fsqrt 3fe00094e0000359 => 3fe6a107aacb50df
|
|
+ fsqrt 8010000000000001 => 7ff8000000000000
|
|
+ fsqrt 80100094e0000359 => 7ff8000000000000
|
|
+ fsqrt bfe0000000000001 => 7ff8000000000000
|
|
+ fsqrt bfe00094e0000359 => 7ff8000000000000
|
|
+ fsqrt 0000000000000000 => 0000000000000000
|
|
+ fsqrt 8000000000000000 => 8000000000000000
|
|
+ fsqrt 7ff0000000000000 => 7ff0000000000000
|
|
+ fsqrt fff0000000000000 => 7ff8000000000000
|
|
+ fsqrt 7ff7ffffffffffff => 7fffffffffffffff
|
|
+ fsqrt fff7ffffffffffff => ffffffffffffffff
|
|
+ fsqrt 7ff8000000000000 => 7ff8000000000000
|
|
+ fsqrt fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fcfid 0010000000000001 => 4330000000000001
|
|
+ fcfid 00100094e0000359 => 43300094e0000359
|
|
+ fcfid 3fe0000000000001 => 43cff00000000000
|
|
+ fcfid 3fe00094e0000359 => 43cff0004a700002
|
|
+ fcfid 8010000000000001 => c3dffc0000000000
|
|
+ fcfid 80100094e0000359 => c3dffbffdac7ffff
|
|
+ fcfid bfe0000000000001 => c3d0080000000000
|
|
+ fcfid bfe00094e0000359 => c3d007ffdac7ffff
|
|
+ fcfid 0000000000000000 => 0000000000000000
|
|
+ fcfid 8000000000000000 => c3e0000000000000
|
|
+ fcfid 7ff0000000000000 => 43dffc0000000000
|
|
+ fcfid fff0000000000000 => c330000000000000
|
|
+ fcfid 7ff7ffffffffffff => 43dffe0000000000
|
|
+ fcfid fff7ffffffffffff => c320000000000002
|
|
+ fcfid 7ff8000000000000 => 43dffe0000000000
|
|
+ fcfid fff8000000000000 => c320000000000000
|
|
+
|
|
+ fctid 0010000000000001 => 0000000000000000
|
|
+ fctid 00100094e0000359 => 0000000000000000
|
|
+ fctid 3fe0000000000001 => 0000000000000001
|
|
+ fctid 3fe00094e0000359 => 0000000000000001
|
|
+ fctid 8010000000000001 => 0000000000000000
|
|
+ fctid 80100094e0000359 => 0000000000000000
|
|
+ fctid bfe0000000000001 => ffffffffffffffff
|
|
+ fctid bfe00094e0000359 => ffffffffffffffff
|
|
+ fctid 0000000000000000 => 0000000000000000
|
|
+ fctid 8000000000000000 => 0000000000000000
|
|
+ fctid 7ff0000000000000 => 7fffffffffffffff
|
|
+ fctid fff0000000000000 => 8000000000000000
|
|
+ fctid 7ff7ffffffffffff => 8000000000000000
|
|
+ fctid fff7ffffffffffff => 8000000000000000
|
|
+ fctid 7ff8000000000000 => 8000000000000000
|
|
+ fctid fff8000000000000 => 8000000000000000
|
|
+
|
|
+ fctidz 0010000000000001 => 0000000000000000
|
|
+ fctidz 00100094e0000359 => 0000000000000000
|
|
+ fctidz 3fe0000000000001 => 0000000000000000
|
|
+ fctidz 3fe00094e0000359 => 0000000000000000
|
|
+ fctidz 8010000000000001 => 0000000000000000
|
|
+ fctidz 80100094e0000359 => 0000000000000000
|
|
+ fctidz bfe0000000000001 => 0000000000000000
|
|
+ fctidz bfe00094e0000359 => 0000000000000000
|
|
+ fctidz 0000000000000000 => 0000000000000000
|
|
+ fctidz 8000000000000000 => 0000000000000000
|
|
+ fctidz 7ff0000000000000 => 7fffffffffffffff
|
|
+ fctidz fff0000000000000 => 8000000000000000
|
|
+ fctidz 7ff7ffffffffffff => 8000000000000000
|
|
+ fctidz fff7ffffffffffff => 8000000000000000
|
|
+ fctidz 7ff8000000000000 => 8000000000000000
|
|
+ fctidz fff8000000000000 => 8000000000000000
|
|
+
|
|
+PPC floating point arith insns
|
|
+ with one arg with flags update:
|
|
+ fres. 0010000000000001 => 7ff0000000000000
|
|
+ fres. 00100094e0000359 => 7ff0000000000000
|
|
+ fres. 3fe0000000000001 => 4000000000000000
|
|
+ fres. 3fe00094e0000359 => 3ffff00000000000
|
|
+ fres. 8010000000000001 => fff0000000000000
|
|
+ fres. 80100094e0000359 => fff0000000000000
|
|
+ fres. bfe0000000000001 => c000000000000000
|
|
+ fres. bfe00094e0000359 => bffff00000000000
|
|
+ fres. 0000000000000000 => 7ff0000000000000
|
|
+ fres. 8000000000000000 => fff0000000000000
|
|
+ fres. 7ff0000000000000 => 0000000000000000
|
|
+ fres. fff0000000000000 => 8000000000000000
|
|
+ fres. 7ff7ffffffffffff => 7ffff00000000000
|
|
+ fres. fff7ffffffffffff => fffff00000000000
|
|
+ fres. 7ff8000000000000 => 7ff8000000000000
|
|
+ fres. fff8000000000000 => fff8000000000000
|
|
+
|
|
+ frsqrte. 0010000000000001 => 5fdf000000000000
|
|
+ frsqrte. 00100094e0000359 => 5fdf000000000000
|
|
+ frsqrte. 3fe0000000000001 => 3ff6000000000000
|
|
+ frsqrte. 3fe00094e0000359 => 3ff6000000000000
|
|
+ frsqrte. 8010000000000001 => 7ff8000000000000
|
|
+ frsqrte. 80100094e0000359 => 7ff8000000000000
|
|
+ frsqrte. bfe0000000000001 => 7ff8000000000000
|
|
+ frsqrte. bfe00094e0000359 => 7ff8000000000000
|
|
+ frsqrte. 0000000000000000 => 7ff0000000000000
|
|
+ frsqrte. 8000000000000000 => fff0000000000000
|
|
+ frsqrte. 7ff0000000000000 => 0000000000000000
|
|
+ frsqrte. fff0000000000000 => 7ff8000000000000
|
|
+ frsqrte. 7ff7ffffffffffff => 7fff000000000000
|
|
+ frsqrte. fff7ffffffffffff => ffff000000000000
|
|
+ frsqrte. 7ff8000000000000 => 7ff8000000000000
|
|
+ frsqrte. fff8000000000000 => fff8000000000000
|
|
+
|
|
+ frsp. 0010000000000001 => 0000000000000000
|
|
+ frsp. 00100094e0000359 => 0000000000000000
|
|
+ frsp. 3fe0000000000001 => 3fe0000000000000
|
|
+ frsp. 3fe00094e0000359 => 3fe00094e0000000
|
|
+ frsp. 8010000000000001 => 8000000000000000
|
|
+ frsp. 80100094e0000359 => 8000000000000000
|
|
+ frsp. bfe0000000000001 => bfe0000000000000
|
|
+ frsp. bfe00094e0000359 => bfe00094e0000000
|
|
+ frsp. 0000000000000000 => 0000000000000000
|
|
+ frsp. 8000000000000000 => 8000000000000000
|
|
+ frsp. 7ff0000000000000 => 7ff0000000000000
|
|
+ frsp. fff0000000000000 => fff0000000000000
|
|
+ frsp. 7ff7ffffffffffff => 7fffffffe0000000
|
|
+ frsp. fff7ffffffffffff => ffffffffe0000000
|
|
+ frsp. 7ff8000000000000 => 7ff8000000000000
|
|
+ frsp. fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fctiw. 0010000000000001 => 0000000000000000
|
|
+ fctiw. 00100094e0000359 => 0000000000000000
|
|
+ fctiw. 3fe0000000000001 => 0000000000000001
|
|
+ fctiw. 3fe00094e0000359 => 0000000000000001
|
|
+ fctiw. 8010000000000001 => 0000000000000000
|
|
+ fctiw. 80100094e0000359 => 0000000000000000
|
|
+ fctiw. bfe0000000000001 => 00000000ffffffff
|
|
+ fctiw. bfe00094e0000359 => 00000000ffffffff
|
|
+ fctiw. 0000000000000000 => 0000000000000000
|
|
+ fctiw. 8000000000000000 => 0000000000000000
|
|
+ fctiw. 7ff0000000000000 => 000000007fffffff
|
|
+ fctiw. fff0000000000000 => 0000000080000000
|
|
+ fctiw. 7ff7ffffffffffff => 0000000080000000
|
|
+ fctiw. fff7ffffffffffff => 0000000080000000
|
|
+ fctiw. 7ff8000000000000 => 0000000080000000
|
|
+ fctiw. fff8000000000000 => 0000000080000000
|
|
+
|
|
+ fctiwz. 0010000000000001 => 0000000000000000
|
|
+ fctiwz. 00100094e0000359 => 0000000000000000
|
|
+ fctiwz. 3fe0000000000001 => 0000000000000000
|
|
+ fctiwz. 3fe00094e0000359 => 0000000000000000
|
|
+ fctiwz. 8010000000000001 => 0000000000000000
|
|
+ fctiwz. 80100094e0000359 => 0000000000000000
|
|
+ fctiwz. bfe0000000000001 => 0000000000000000
|
|
+ fctiwz. bfe00094e0000359 => 0000000000000000
|
|
+ fctiwz. 0000000000000000 => 0000000000000000
|
|
+ fctiwz. 8000000000000000 => 0000000000000000
|
|
+ fctiwz. 7ff0000000000000 => 000000007fffffff
|
|
+ fctiwz. fff0000000000000 => 0000000080000000
|
|
+ fctiwz. 7ff7ffffffffffff => 0000000080000000
|
|
+ fctiwz. fff7ffffffffffff => 0000000080000000
|
|
+ fctiwz. 7ff8000000000000 => 0000000080000000
|
|
+ fctiwz. fff8000000000000 => 0000000080000000
|
|
+
|
|
+ fmr. 0010000000000001 => 0010000000000001
|
|
+ fmr. 00100094e0000359 => 00100094e0000359
|
|
+ fmr. 3fe0000000000001 => 3fe0000000000001
|
|
+ fmr. 3fe00094e0000359 => 3fe00094e0000359
|
|
+ fmr. 8010000000000001 => 8010000000000001
|
|
+ fmr. 80100094e0000359 => 80100094e0000359
|
|
+ fmr. bfe0000000000001 => bfe0000000000001
|
|
+ fmr. bfe00094e0000359 => bfe00094e0000359
|
|
+ fmr. 0000000000000000 => 0000000000000000
|
|
+ fmr. 8000000000000000 => 8000000000000000
|
|
+ fmr. 7ff0000000000000 => 7ff0000000000000
|
|
+ fmr. fff0000000000000 => fff0000000000000
|
|
+ fmr. 7ff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fmr. fff7ffffffffffff => fff7ffffffffffff
|
|
+ fmr. 7ff8000000000000 => 7ff8000000000000
|
|
+ fmr. fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fneg. 0010000000000001 => 8010000000000001
|
|
+ fneg. 00100094e0000359 => 80100094e0000359
|
|
+ fneg. 3fe0000000000001 => bfe0000000000001
|
|
+ fneg. 3fe00094e0000359 => bfe00094e0000359
|
|
+ fneg. 8010000000000001 => 0010000000000001
|
|
+ fneg. 80100094e0000359 => 00100094e0000359
|
|
+ fneg. bfe0000000000001 => 3fe0000000000001
|
|
+ fneg. bfe00094e0000359 => 3fe00094e0000359
|
|
+ fneg. 0000000000000000 => 8000000000000000
|
|
+ fneg. 8000000000000000 => 0000000000000000
|
|
+ fneg. 7ff0000000000000 => fff0000000000000
|
|
+ fneg. fff0000000000000 => 7ff0000000000000
|
|
+ fneg. 7ff7ffffffffffff => fff7ffffffffffff
|
|
+ fneg. fff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fneg. 7ff8000000000000 => fff8000000000000
|
|
+ fneg. fff8000000000000 => 7ff8000000000000
|
|
+
|
|
+ fabs. 0010000000000001 => 0010000000000001
|
|
+ fabs. 00100094e0000359 => 00100094e0000359
|
|
+ fabs. 3fe0000000000001 => 3fe0000000000001
|
|
+ fabs. 3fe00094e0000359 => 3fe00094e0000359
|
|
+ fabs. 8010000000000001 => 0010000000000001
|
|
+ fabs. 80100094e0000359 => 00100094e0000359
|
|
+ fabs. bfe0000000000001 => 3fe0000000000001
|
|
+ fabs. bfe00094e0000359 => 3fe00094e0000359
|
|
+ fabs. 0000000000000000 => 0000000000000000
|
|
+ fabs. 8000000000000000 => 0000000000000000
|
|
+ fabs. 7ff0000000000000 => 7ff0000000000000
|
|
+ fabs. fff0000000000000 => 7ff0000000000000
|
|
+ fabs. 7ff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fabs. fff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fabs. 7ff8000000000000 => 7ff8000000000000
|
|
+ fabs. fff8000000000000 => 7ff8000000000000
|
|
+
|
|
+ fnabs. 0010000000000001 => 8010000000000001
|
|
+ fnabs. 00100094e0000359 => 80100094e0000359
|
|
+ fnabs. 3fe0000000000001 => bfe0000000000001
|
|
+ fnabs. 3fe00094e0000359 => bfe00094e0000359
|
|
+ fnabs. 8010000000000001 => 8010000000000001
|
|
+ fnabs. 80100094e0000359 => 80100094e0000359
|
|
+ fnabs. bfe0000000000001 => bfe0000000000001
|
|
+ fnabs. bfe00094e0000359 => bfe00094e0000359
|
|
+ fnabs. 0000000000000000 => 8000000000000000
|
|
+ fnabs. 8000000000000000 => 8000000000000000
|
|
+ fnabs. 7ff0000000000000 => fff0000000000000
|
|
+ fnabs. fff0000000000000 => fff0000000000000
|
|
+ fnabs. 7ff7ffffffffffff => fff7ffffffffffff
|
|
+ fnabs. fff7ffffffffffff => fff7ffffffffffff
|
|
+ fnabs. 7ff8000000000000 => fff8000000000000
|
|
+ fnabs. fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fcfid. 0010000000000001 => 4330000000000001
|
|
+ fcfid. 00100094e0000359 => 43300094e0000359
|
|
+ fcfid. 3fe0000000000001 => 43cff00000000000
|
|
+ fcfid. 3fe00094e0000359 => 43cff0004a700002
|
|
+ fcfid. 8010000000000001 => c3dffc0000000000
|
|
+ fcfid. 80100094e0000359 => c3dffbffdac7ffff
|
|
+ fcfid. bfe0000000000001 => c3d0080000000000
|
|
+ fcfid. bfe00094e0000359 => c3d007ffdac7ffff
|
|
+ fcfid. 0000000000000000 => 0000000000000000
|
|
+ fcfid. 8000000000000000 => c3e0000000000000
|
|
+ fcfid. 7ff0000000000000 => 43dffc0000000000
|
|
+ fcfid. fff0000000000000 => c330000000000000
|
|
+ fcfid. 7ff7ffffffffffff => 43dffe0000000000
|
|
+ fcfid. fff7ffffffffffff => c320000000000002
|
|
+ fcfid. 7ff8000000000000 => 43dffe0000000000
|
|
+ fcfid. fff8000000000000 => c320000000000000
|
|
+
|
|
+ fctid. 0010000000000001 => 0000000000000000
|
|
+ fctid. 00100094e0000359 => 0000000000000000
|
|
+ fctid. 3fe0000000000001 => 0000000000000001
|
|
+ fctid. 3fe00094e0000359 => 0000000000000001
|
|
+ fctid. 8010000000000001 => 0000000000000000
|
|
+ fctid. 80100094e0000359 => 0000000000000000
|
|
+ fctid. bfe0000000000001 => ffffffffffffffff
|
|
+ fctid. bfe00094e0000359 => ffffffffffffffff
|
|
+ fctid. 0000000000000000 => 0000000000000000
|
|
+ fctid. 8000000000000000 => 0000000000000000
|
|
+ fctid. 7ff0000000000000 => 7fffffffffffffff
|
|
+ fctid. fff0000000000000 => 8000000000000000
|
|
+ fctid. 7ff7ffffffffffff => 8000000000000000
|
|
+ fctid. fff7ffffffffffff => 8000000000000000
|
|
+ fctid. 7ff8000000000000 => 8000000000000000
|
|
+ fctid. fff8000000000000 => 8000000000000000
|
|
+
|
|
+ fctidz. 0010000000000001 => 0000000000000000
|
|
+ fctidz. 00100094e0000359 => 0000000000000000
|
|
+ fctidz. 3fe0000000000001 => 0000000000000000
|
|
+ fctidz. 3fe00094e0000359 => 0000000000000000
|
|
+ fctidz. 8010000000000001 => 0000000000000000
|
|
+ fctidz. 80100094e0000359 => 0000000000000000
|
|
+ fctidz. bfe0000000000001 => 0000000000000000
|
|
+ fctidz. bfe00094e0000359 => 0000000000000000
|
|
+ fctidz. 0000000000000000 => 0000000000000000
|
|
+ fctidz. 8000000000000000 => 0000000000000000
|
|
+ fctidz. 7ff0000000000000 => 7fffffffffffffff
|
|
+ fctidz. fff0000000000000 => 8000000000000000
|
|
+ fctidz. 7ff7ffffffffffff => 8000000000000000
|
|
+ fctidz. fff7ffffffffffff => 8000000000000000
|
|
+ fctidz. 7ff8000000000000 => 8000000000000000
|
|
+ fctidz. fff8000000000000 => 8000000000000000
|
|
+
|
|
+PPC floating point status register manipulation insns:
|
|
+PPC floating point status register manipulation insns
|
|
+ with flags update:
|
|
+PPC float load insns
|
|
+ with one register + one 16 bits immediate args with flags update:
|
|
+ lfs 0010000000000001, 65416 => 36a0000000000000, 0
|
|
+ lfs 00100094e0000359, 65424 => c400006b20000000, 0
|
|
+ lfs 3fe0000000000001, 65432 => 36a0000000000000, 0
|
|
+ lfs 3fe00094e0000359, 65440 => c400006b20000000, 0
|
|
+ lfs 8010000000000001, 65448 => 36a0000000000000, 0
|
|
+ lfs 80100094e0000359, 65456 => c400006b20000000, 0
|
|
+ lfs bfe0000000000001, 65464 => 36a0000000000000, 0
|
|
+ lfs bfe00094e0000359, 65472 => c400006b20000000, 0
|
|
+ lfs 0000000000000000, 65480 => 0000000000000000, 0
|
|
+ lfs 8000000000000000, 65488 => 0000000000000000, 0
|
|
+ lfs 7ff0000000000000, 65496 => 0000000000000000, 0
|
|
+ lfs fff0000000000000, 65504 => 0000000000000000, 0
|
|
+ lfs 7ff7ffffffffffff, 65512 => ffffffffe0000000, 0
|
|
+ lfs fff7ffffffffffff, 65520 => ffffffffe0000000, 0
|
|
+ lfs 7ff8000000000000, 65528 => 0000000000000000, 0
|
|
+ lfs 0010000000000001, 0 => 36a0000000000000, 0
|
|
+ lfs 00100094e0000359, 8 => c400006b20000000, 0
|
|
+ lfs 3fe0000000000001, 16 => 36a0000000000000, 0
|
|
+ lfs 3fe00094e0000359, 24 => c400006b20000000, 0
|
|
+ lfs 8010000000000001, 32 => 36a0000000000000, 0
|
|
+ lfs 80100094e0000359, 40 => c400006b20000000, 0
|
|
+ lfs bfe0000000000001, 48 => 36a0000000000000, 0
|
|
+ lfs bfe00094e0000359, 56 => c400006b20000000, 0
|
|
+ lfs 0000000000000000, 64 => 0000000000000000, 0
|
|
+ lfs 8000000000000000, 72 => 0000000000000000, 0
|
|
+ lfs 7ff0000000000000, 80 => 0000000000000000, 0
|
|
+ lfs fff0000000000000, 88 => 0000000000000000, 0
|
|
+ lfs 7ff7ffffffffffff, 96 => ffffffffe0000000, 0
|
|
+ lfs fff7ffffffffffff, 104 => ffffffffe0000000, 0
|
|
+ lfs 7ff8000000000000, 112 => 0000000000000000, 0
|
|
+ lfs fff8000000000000, 120 => 0000000000000000, 0
|
|
+
|
|
+ lfsu 0010000000000001, 65416 => 36a0000000000000, -120
|
|
+ lfsu 00100094e0000359, 65424 => c400006b20000000, -112
|
|
+ lfsu 3fe0000000000001, 65432 => 36a0000000000000, -104
|
|
+ lfsu 3fe00094e0000359, 65440 => c400006b20000000, -96
|
|
+ lfsu 8010000000000001, 65448 => 36a0000000000000, -88
|
|
+ lfsu 80100094e0000359, 65456 => c400006b20000000, -80
|
|
+ lfsu bfe0000000000001, 65464 => 36a0000000000000, -72
|
|
+ lfsu bfe00094e0000359, 65472 => c400006b20000000, -64
|
|
+ lfsu 0000000000000000, 65480 => 0000000000000000, -56
|
|
+ lfsu 8000000000000000, 65488 => 0000000000000000, -48
|
|
+ lfsu 7ff0000000000000, 65496 => 0000000000000000, -40
|
|
+ lfsu fff0000000000000, 65504 => 0000000000000000, -32
|
|
+ lfsu 7ff7ffffffffffff, 65512 => ffffffffe0000000, -24
|
|
+ lfsu fff7ffffffffffff, 65520 => ffffffffe0000000, -16
|
|
+ lfsu 7ff8000000000000, 65528 => 0000000000000000, -8
|
|
+ lfsu 0010000000000001, 0 => 36a0000000000000, 0
|
|
+ lfsu 00100094e0000359, 8 => c400006b20000000, 8
|
|
+ lfsu 3fe0000000000001, 16 => 36a0000000000000, 16
|
|
+ lfsu 3fe00094e0000359, 24 => c400006b20000000, 24
|
|
+ lfsu 8010000000000001, 32 => 36a0000000000000, 32
|
|
+ lfsu 80100094e0000359, 40 => c400006b20000000, 40
|
|
+ lfsu bfe0000000000001, 48 => 36a0000000000000, 48
|
|
+ lfsu bfe00094e0000359, 56 => c400006b20000000, 56
|
|
+ lfsu 0000000000000000, 64 => 0000000000000000, 64
|
|
+ lfsu 8000000000000000, 72 => 0000000000000000, 72
|
|
+ lfsu 7ff0000000000000, 80 => 0000000000000000, 80
|
|
+ lfsu fff0000000000000, 88 => 0000000000000000, 88
|
|
+ lfsu 7ff7ffffffffffff, 96 => ffffffffe0000000, 96
|
|
+ lfsu fff7ffffffffffff, 104 => ffffffffe0000000, 104
|
|
+ lfsu 7ff8000000000000, 112 => 0000000000000000, 112
|
|
+ lfsu fff8000000000000, 120 => 0000000000000000, 120
|
|
+
|
|
+ lfd 0010000000000001, 65416 => 0010000000000001, 0
|
|
+ lfd 00100094e0000359, 65424 => 00100094e0000359, 0
|
|
+ lfd 3fe0000000000001, 65432 => 3fe0000000000001, 0
|
|
+ lfd 3fe00094e0000359, 65440 => 3fe00094e0000359, 0
|
|
+ lfd 8010000000000001, 65448 => 8010000000000001, 0
|
|
+ lfd 80100094e0000359, 65456 => 80100094e0000359, 0
|
|
+ lfd bfe0000000000001, 65464 => bfe0000000000001, 0
|
|
+ lfd bfe00094e0000359, 65472 => bfe00094e0000359, 0
|
|
+ lfd 0000000000000000, 65480 => 0000000000000000, 0
|
|
+ lfd 8000000000000000, 65488 => 8000000000000000, 0
|
|
+ lfd 7ff0000000000000, 65496 => 7ff0000000000000, 0
|
|
+ lfd fff0000000000000, 65504 => fff0000000000000, 0
|
|
+ lfd 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, 0
|
|
+ lfd fff7ffffffffffff, 65520 => fff7ffffffffffff, 0
|
|
+ lfd 7ff8000000000000, 65528 => 7ff8000000000000, 0
|
|
+ lfd 0010000000000001, 0 => 0010000000000001, 0
|
|
+ lfd 00100094e0000359, 8 => 00100094e0000359, 0
|
|
+ lfd 3fe0000000000001, 16 => 3fe0000000000001, 0
|
|
+ lfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0
|
|
+ lfd 8010000000000001, 32 => 8010000000000001, 0
|
|
+ lfd 80100094e0000359, 40 => 80100094e0000359, 0
|
|
+ lfd bfe0000000000001, 48 => bfe0000000000001, 0
|
|
+ lfd bfe00094e0000359, 56 => bfe00094e0000359, 0
|
|
+ lfd 0000000000000000, 64 => 0000000000000000, 0
|
|
+ lfd 8000000000000000, 72 => 8000000000000000, 0
|
|
+ lfd 7ff0000000000000, 80 => 7ff0000000000000, 0
|
|
+ lfd fff0000000000000, 88 => fff0000000000000, 0
|
|
+ lfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
|
|
+ lfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0
|
|
+ lfd 7ff8000000000000, 112 => 7ff8000000000000, 0
|
|
+ lfd fff8000000000000, 120 => fff8000000000000, 0
|
|
+
|
|
+ lfdu 0010000000000001, 65416 => 0010000000000001, -120
|
|
+ lfdu 00100094e0000359, 65424 => 00100094e0000359, -112
|
|
+ lfdu 3fe0000000000001, 65432 => 3fe0000000000001, -104
|
|
+ lfdu 3fe00094e0000359, 65440 => 3fe00094e0000359, -96
|
|
+ lfdu 8010000000000001, 65448 => 8010000000000001, -88
|
|
+ lfdu 80100094e0000359, 65456 => 80100094e0000359, -80
|
|
+ lfdu bfe0000000000001, 65464 => bfe0000000000001, -72
|
|
+ lfdu bfe00094e0000359, 65472 => bfe00094e0000359, -64
|
|
+ lfdu 0000000000000000, 65480 => 0000000000000000, -56
|
|
+ lfdu 8000000000000000, 65488 => 8000000000000000, -48
|
|
+ lfdu 7ff0000000000000, 65496 => 7ff0000000000000, -40
|
|
+ lfdu fff0000000000000, 65504 => fff0000000000000, -32
|
|
+ lfdu 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, -24
|
|
+ lfdu fff7ffffffffffff, 65520 => fff7ffffffffffff, -16
|
|
+ lfdu 7ff8000000000000, 65528 => 7ff8000000000000, -8
|
|
+ lfdu 0010000000000001, 0 => 0010000000000001, 0
|
|
+ lfdu 00100094e0000359, 8 => 00100094e0000359, 8
|
|
+ lfdu 3fe0000000000001, 16 => 3fe0000000000001, 16
|
|
+ lfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24
|
|
+ lfdu 8010000000000001, 32 => 8010000000000001, 32
|
|
+ lfdu 80100094e0000359, 40 => 80100094e0000359, 40
|
|
+ lfdu bfe0000000000001, 48 => bfe0000000000001, 48
|
|
+ lfdu bfe00094e0000359, 56 => bfe00094e0000359, 56
|
|
+ lfdu 0000000000000000, 64 => 0000000000000000, 64
|
|
+ lfdu 8000000000000000, 72 => 8000000000000000, 72
|
|
+ lfdu 7ff0000000000000, 80 => 7ff0000000000000, 80
|
|
+ lfdu fff0000000000000, 88 => fff0000000000000, 88
|
|
+ lfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
|
|
+ lfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104
|
|
+ lfdu 7ff8000000000000, 112 => 7ff8000000000000, 112
|
|
+ lfdu fff8000000000000, 120 => fff8000000000000, 120
|
|
+
|
|
+PPC float load insns with two register args:
|
|
+ lfsx 0010000000000001, -120 => 36a0000000000000, 0
|
|
+ lfsx 00100094e0000359, -112 => c400006b20000000, 0
|
|
+ lfsx 3fe0000000000001, -104 => 36a0000000000000, 0
|
|
+ lfsx 3fe00094e0000359, -96 => c400006b20000000, 0
|
|
+ lfsx 8010000000000001, -88 => 36a0000000000000, 0
|
|
+ lfsx 80100094e0000359, -80 => c400006b20000000, 0
|
|
+ lfsx bfe0000000000001, -72 => 36a0000000000000, 0
|
|
+ lfsx bfe00094e0000359, -64 => c400006b20000000, 0
|
|
+ lfsx 0000000000000000, -56 => 0000000000000000, 0
|
|
+ lfsx 8000000000000000, -48 => 0000000000000000, 0
|
|
+ lfsx 7ff0000000000000, -40 => 0000000000000000, 0
|
|
+ lfsx fff0000000000000, -32 => 0000000000000000, 0
|
|
+ lfsx 7ff7ffffffffffff, -24 => ffffffffe0000000, 0
|
|
+ lfsx fff7ffffffffffff, -16 => ffffffffe0000000, 0
|
|
+ lfsx 7ff8000000000000, -8 => 0000000000000000, 0
|
|
+ lfsx 0010000000000001, 0 => 36a0000000000000, 0
|
|
+ lfsx 00100094e0000359, 8 => c400006b20000000, 0
|
|
+ lfsx 3fe0000000000001, 16 => 36a0000000000000, 0
|
|
+ lfsx 3fe00094e0000359, 24 => c400006b20000000, 0
|
|
+ lfsx 8010000000000001, 32 => 36a0000000000000, 0
|
|
+ lfsx 80100094e0000359, 40 => c400006b20000000, 0
|
|
+ lfsx bfe0000000000001, 48 => 36a0000000000000, 0
|
|
+ lfsx bfe00094e0000359, 56 => c400006b20000000, 0
|
|
+ lfsx 0000000000000000, 64 => 0000000000000000, 0
|
|
+ lfsx 8000000000000000, 72 => 0000000000000000, 0
|
|
+ lfsx 7ff0000000000000, 80 => 0000000000000000, 0
|
|
+ lfsx fff0000000000000, 88 => 0000000000000000, 0
|
|
+ lfsx 7ff7ffffffffffff, 96 => ffffffffe0000000, 0
|
|
+ lfsx fff7ffffffffffff, 104 => ffffffffe0000000, 0
|
|
+ lfsx 7ff8000000000000, 112 => 0000000000000000, 0
|
|
+ lfsx fff8000000000000, 120 => 0000000000000000, 0
|
|
+
|
|
+ lfsux 0010000000000001, -120 => 36a0000000000000, -120
|
|
+ lfsux 00100094e0000359, -112 => c400006b20000000, -112
|
|
+ lfsux 3fe0000000000001, -104 => 36a0000000000000, -104
|
|
+ lfsux 3fe00094e0000359, -96 => c400006b20000000, -96
|
|
+ lfsux 8010000000000001, -88 => 36a0000000000000, -88
|
|
+ lfsux 80100094e0000359, -80 => c400006b20000000, -80
|
|
+ lfsux bfe0000000000001, -72 => 36a0000000000000, -72
|
|
+ lfsux bfe00094e0000359, -64 => c400006b20000000, -64
|
|
+ lfsux 0000000000000000, -56 => 0000000000000000, -56
|
|
+ lfsux 8000000000000000, -48 => 0000000000000000, -48
|
|
+ lfsux 7ff0000000000000, -40 => 0000000000000000, -40
|
|
+ lfsux fff0000000000000, -32 => 0000000000000000, -32
|
|
+ lfsux 7ff7ffffffffffff, -24 => ffffffffe0000000, -24
|
|
+ lfsux fff7ffffffffffff, -16 => ffffffffe0000000, -16
|
|
+ lfsux 7ff8000000000000, -8 => 0000000000000000, -8
|
|
+ lfsux 0010000000000001, 0 => 36a0000000000000, 0
|
|
+ lfsux 00100094e0000359, 8 => c400006b20000000, 8
|
|
+ lfsux 3fe0000000000001, 16 => 36a0000000000000, 16
|
|
+ lfsux 3fe00094e0000359, 24 => c400006b20000000, 24
|
|
+ lfsux 8010000000000001, 32 => 36a0000000000000, 32
|
|
+ lfsux 80100094e0000359, 40 => c400006b20000000, 40
|
|
+ lfsux bfe0000000000001, 48 => 36a0000000000000, 48
|
|
+ lfsux bfe00094e0000359, 56 => c400006b20000000, 56
|
|
+ lfsux 0000000000000000, 64 => 0000000000000000, 64
|
|
+ lfsux 8000000000000000, 72 => 0000000000000000, 72
|
|
+ lfsux 7ff0000000000000, 80 => 0000000000000000, 80
|
|
+ lfsux fff0000000000000, 88 => 0000000000000000, 88
|
|
+ lfsux 7ff7ffffffffffff, 96 => ffffffffe0000000, 96
|
|
+ lfsux fff7ffffffffffff, 104 => ffffffffe0000000, 104
|
|
+ lfsux 7ff8000000000000, 112 => 0000000000000000, 112
|
|
+ lfsux fff8000000000000, 120 => 0000000000000000, 120
|
|
+
|
|
+ lfdx 0010000000000001, -120 => 0010000000000001, 0
|
|
+ lfdx 00100094e0000359, -112 => 00100094e0000359, 0
|
|
+ lfdx 3fe0000000000001, -104 => 3fe0000000000001, 0
|
|
+ lfdx 3fe00094e0000359, -96 => 3fe00094e0000359, 0
|
|
+ lfdx 8010000000000001, -88 => 8010000000000001, 0
|
|
+ lfdx 80100094e0000359, -80 => 80100094e0000359, 0
|
|
+ lfdx bfe0000000000001, -72 => bfe0000000000001, 0
|
|
+ lfdx bfe00094e0000359, -64 => bfe00094e0000359, 0
|
|
+ lfdx 0000000000000000, -56 => 0000000000000000, 0
|
|
+ lfdx 8000000000000000, -48 => 8000000000000000, 0
|
|
+ lfdx 7ff0000000000000, -40 => 7ff0000000000000, 0
|
|
+ lfdx fff0000000000000, -32 => fff0000000000000, 0
|
|
+ lfdx 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0
|
|
+ lfdx fff7ffffffffffff, -16 => fff7ffffffffffff, 0
|
|
+ lfdx 7ff8000000000000, -8 => 7ff8000000000000, 0
|
|
+ lfdx 0010000000000001, 0 => 0010000000000001, 0
|
|
+ lfdx 00100094e0000359, 8 => 00100094e0000359, 0
|
|
+ lfdx 3fe0000000000001, 16 => 3fe0000000000001, 0
|
|
+ lfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0
|
|
+ lfdx 8010000000000001, 32 => 8010000000000001, 0
|
|
+ lfdx 80100094e0000359, 40 => 80100094e0000359, 0
|
|
+ lfdx bfe0000000000001, 48 => bfe0000000000001, 0
|
|
+ lfdx bfe00094e0000359, 56 => bfe00094e0000359, 0
|
|
+ lfdx 0000000000000000, 64 => 0000000000000000, 0
|
|
+ lfdx 8000000000000000, 72 => 8000000000000000, 0
|
|
+ lfdx 7ff0000000000000, 80 => 7ff0000000000000, 0
|
|
+ lfdx fff0000000000000, 88 => fff0000000000000, 0
|
|
+ lfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
|
|
+ lfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0
|
|
+ lfdx 7ff8000000000000, 112 => 7ff8000000000000, 0
|
|
+ lfdx fff8000000000000, 120 => fff8000000000000, 0
|
|
+
|
|
+ lfdux 0010000000000001, -120 => 0010000000000001, -120
|
|
+ lfdux 00100094e0000359, -112 => 00100094e0000359, -112
|
|
+ lfdux 3fe0000000000001, -104 => 3fe0000000000001, -104
|
|
+ lfdux 3fe00094e0000359, -96 => 3fe00094e0000359, -96
|
|
+ lfdux 8010000000000001, -88 => 8010000000000001, -88
|
|
+ lfdux 80100094e0000359, -80 => 80100094e0000359, -80
|
|
+ lfdux bfe0000000000001, -72 => bfe0000000000001, -72
|
|
+ lfdux bfe00094e0000359, -64 => bfe00094e0000359, -64
|
|
+ lfdux 0000000000000000, -56 => 0000000000000000, -56
|
|
+ lfdux 8000000000000000, -48 => 8000000000000000, -48
|
|
+ lfdux 7ff0000000000000, -40 => 7ff0000000000000, -40
|
|
+ lfdux fff0000000000000, -32 => fff0000000000000, -32
|
|
+ lfdux 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24
|
|
+ lfdux fff7ffffffffffff, -16 => fff7ffffffffffff, -16
|
|
+ lfdux 7ff8000000000000, -8 => 7ff8000000000000, -8
|
|
+ lfdux 0010000000000001, 0 => 0010000000000001, 0
|
|
+ lfdux 00100094e0000359, 8 => 00100094e0000359, 8
|
|
+ lfdux 3fe0000000000001, 16 => 3fe0000000000001, 16
|
|
+ lfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24
|
|
+ lfdux 8010000000000001, 32 => 8010000000000001, 32
|
|
+ lfdux 80100094e0000359, 40 => 80100094e0000359, 40
|
|
+ lfdux bfe0000000000001, 48 => bfe0000000000001, 48
|
|
+ lfdux bfe00094e0000359, 56 => bfe00094e0000359, 56
|
|
+ lfdux 0000000000000000, 64 => 0000000000000000, 64
|
|
+ lfdux 8000000000000000, 72 => 8000000000000000, 72
|
|
+ lfdux 7ff0000000000000, 80 => 7ff0000000000000, 80
|
|
+ lfdux fff0000000000000, 88 => fff0000000000000, 88
|
|
+ lfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
|
|
+ lfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104
|
|
+ lfdux 7ff8000000000000, 112 => 7ff8000000000000, 112
|
|
+ lfdux fff8000000000000, 120 => fff8000000000000, 120
|
|
+
|
|
+PPC float store insns
|
|
+ with one register + one 16 bits immediate args with flags update:
|
|
+ stfs 0010000000000001, -56 => 0000000000000000, 0
|
|
+ stfs 00100094e0000359, -48 => 0000000000000000, 0
|
|
+ stfs 3fe0000000000001, -40 => 000000003f000000, 0
|
|
+ stfs 3fe00094e0000359, -32 => 000000003f0004a7, 0
|
|
+ stfs 8010000000000001, -24 => 0000000080000000, 0
|
|
+ stfs 80100094e0000359, -16 => 0000000080000000, 0
|
|
+ stfs bfe0000000000001, -8 => 00000000bf000000, 0
|
|
+ stfs 0010000000000001, 0 => 0000000000000000, 0
|
|
+ stfs 00100094e0000359, 8 => 0000000000000000, 0
|
|
+ stfs 3fe0000000000001, 16 => 000000003f000000, 0
|
|
+ stfs 3fe00094e0000359, 24 => 000000003f0004a7, 0
|
|
+ stfs 8010000000000001, 32 => 0000000080000000, 0
|
|
+ stfs 80100094e0000359, 40 => 0000000080000000, 0
|
|
+ stfs bfe0000000000001, 48 => 00000000bf000000, 0
|
|
+ stfs bfe00094e0000359, 56 => 00000000bf0004a7, 0
|
|
+
|
|
+ stfsu 0010000000000001, -56 => 0000000000000000, -56
|
|
+ stfsu 00100094e0000359, -48 => 0000000000000000, -48
|
|
+ stfsu 3fe0000000000001, -40 => 000000003f000000, -40
|
|
+ stfsu 3fe00094e0000359, -32 => 000000003f0004a7, -32
|
|
+ stfsu 8010000000000001, -24 => 0000000080000000, -24
|
|
+ stfsu 80100094e0000359, -16 => 0000000080000000, -16
|
|
+ stfsu bfe0000000000001, -8 => 00000000bf000000, -8
|
|
+ stfsu 0010000000000001, 0 => 0000000000000000, 0
|
|
+ stfsu 00100094e0000359, 8 => 0000000000000000, 8
|
|
+ stfsu 3fe0000000000001, 16 => 000000003f000000, 16
|
|
+ stfsu 3fe00094e0000359, 24 => 000000003f0004a7, 24
|
|
+ stfsu 8010000000000001, 32 => 0000000080000000, 32
|
|
+ stfsu 80100094e0000359, 40 => 0000000080000000, 40
|
|
+ stfsu bfe0000000000001, 48 => 00000000bf000000, 48
|
|
+ stfsu bfe00094e0000359, 56 => 00000000bf0004a7, 56
|
|
+
|
|
+ stfd 0010000000000001, -120 => 0010000000000001, 0
|
|
+ stfd 00100094e0000359, -112 => 00100094e0000359, 0
|
|
+ stfd 3fe0000000000001, -104 => 3fe0000000000001, 0
|
|
+ stfd 3fe00094e0000359, -96 => 3fe00094e0000359, 0
|
|
+ stfd 8010000000000001, -88 => 8010000000000001, 0
|
|
+ stfd 80100094e0000359, -80 => 80100094e0000359, 0
|
|
+ stfd bfe0000000000001, -72 => bfe0000000000001, 0
|
|
+ stfd bfe00094e0000359, -64 => bfe00094e0000359, 0
|
|
+ stfd 0000000000000000, -56 => 0000000000000000, 0
|
|
+ stfd 8000000000000000, -48 => 8000000000000000, 0
|
|
+ stfd 7ff0000000000000, -40 => 7ff0000000000000, 0
|
|
+ stfd fff0000000000000, -32 => fff0000000000000, 0
|
|
+ stfd 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0
|
|
+ stfd fff7ffffffffffff, -16 => fff7ffffffffffff, 0
|
|
+ stfd 7ff8000000000000, -8 => 7ff8000000000000, 0
|
|
+ stfd 0010000000000001, 0 => 0010000000000001, 0
|
|
+ stfd 00100094e0000359, 8 => 00100094e0000359, 0
|
|
+ stfd 3fe0000000000001, 16 => 3fe0000000000001, 0
|
|
+ stfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0
|
|
+ stfd 8010000000000001, 32 => 8010000000000001, 0
|
|
+ stfd 80100094e0000359, 40 => 80100094e0000359, 0
|
|
+ stfd bfe0000000000001, 48 => bfe0000000000001, 0
|
|
+ stfd bfe00094e0000359, 56 => bfe00094e0000359, 0
|
|
+ stfd 0000000000000000, 64 => 0000000000000000, 0
|
|
+ stfd 8000000000000000, 72 => 8000000000000000, 0
|
|
+ stfd 7ff0000000000000, 80 => 7ff0000000000000, 0
|
|
+ stfd fff0000000000000, 88 => fff0000000000000, 0
|
|
+ stfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
|
|
+ stfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0
|
|
+ stfd 7ff8000000000000, 112 => 7ff8000000000000, 0
|
|
+ stfd fff8000000000000, 120 => fff8000000000000, 0
|
|
+
|
|
+ stfdu 0010000000000001, -120 => 0010000000000001, -120
|
|
+ stfdu 00100094e0000359, -112 => 00100094e0000359, -112
|
|
+ stfdu 3fe0000000000001, -104 => 3fe0000000000001, -104
|
|
+ stfdu 3fe00094e0000359, -96 => 3fe00094e0000359, -96
|
|
+ stfdu 8010000000000001, -88 => 8010000000000001, -88
|
|
+ stfdu 80100094e0000359, -80 => 80100094e0000359, -80
|
|
+ stfdu bfe0000000000001, -72 => bfe0000000000001, -72
|
|
+ stfdu bfe00094e0000359, -64 => bfe00094e0000359, -64
|
|
+ stfdu 0000000000000000, -56 => 0000000000000000, -56
|
|
+ stfdu 8000000000000000, -48 => 8000000000000000, -48
|
|
+ stfdu 7ff0000000000000, -40 => 7ff0000000000000, -40
|
|
+ stfdu fff0000000000000, -32 => fff0000000000000, -32
|
|
+ stfdu 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24
|
|
+ stfdu fff7ffffffffffff, -16 => fff7ffffffffffff, -16
|
|
+ stfdu 7ff8000000000000, -8 => 7ff8000000000000, -8
|
|
+ stfdu 0010000000000001, 0 => 0010000000000001, 0
|
|
+ stfdu 00100094e0000359, 8 => 00100094e0000359, 8
|
|
+ stfdu 3fe0000000000001, 16 => 3fe0000000000001, 16
|
|
+ stfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24
|
|
+ stfdu 8010000000000001, 32 => 8010000000000001, 32
|
|
+ stfdu 80100094e0000359, 40 => 80100094e0000359, 40
|
|
+ stfdu bfe0000000000001, 48 => bfe0000000000001, 48
|
|
+ stfdu bfe00094e0000359, 56 => bfe00094e0000359, 56
|
|
+ stfdu 0000000000000000, 64 => 0000000000000000, 64
|
|
+ stfdu 8000000000000000, 72 => 8000000000000000, 72
|
|
+ stfdu 7ff0000000000000, 80 => 7ff0000000000000, 80
|
|
+ stfdu fff0000000000000, 88 => fff0000000000000, 88
|
|
+ stfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
|
|
+ stfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104
|
|
+ stfdu 7ff8000000000000, 112 => 7ff8000000000000, 112
|
|
+ stfdu fff8000000000000, 120 => fff8000000000000, 120
|
|
+
|
|
+PPC float store insns with three register args:
|
|
+ stfsx 0010000000000001, 0 => 0000000000000000, 0
|
|
+ stfsx 00100094e0000359, 8 => 0000000000000000, 0
|
|
+ stfsx 3fe0000000000001, 16 => 000000003f000000, 0
|
|
+ stfsx 3fe00094e0000359, 24 => 000000003f0004a7, 0
|
|
+ stfsx 8010000000000001, 32 => 0000000080000000, 0
|
|
+ stfsx 80100094e0000359, 40 => 0000000080000000, 0
|
|
+ stfsx bfe0000000000001, 48 => 00000000bf000000, 0
|
|
+ stfsx bfe00094e0000359, 56 => 00000000bf0004a7, 0
|
|
+
|
|
+ stfsux 0010000000000001, 0 => 0000000000000000, 0
|
|
+ stfsux 00100094e0000359, 8 => 0000000000000000, 8
|
|
+ stfsux 3fe0000000000001, 16 => 000000003f000000, 16
|
|
+ stfsux 3fe00094e0000359, 24 => 000000003f0004a7, 24
|
|
+ stfsux 8010000000000001, 32 => 0000000080000000, 32
|
|
+ stfsux 80100094e0000359, 40 => 0000000080000000, 40
|
|
+ stfsux bfe0000000000001, 48 => 00000000bf000000, 48
|
|
+ stfsux bfe00094e0000359, 56 => 00000000bf0004a7, 56
|
|
+
|
|
+ stfdx 0010000000000001, 0 => 0010000000000001, 0
|
|
+ stfdx 00100094e0000359, 8 => 00100094e0000359, 0
|
|
+ stfdx 3fe0000000000001, 16 => 3fe0000000000001, 0
|
|
+ stfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0
|
|
+ stfdx 8010000000000001, 32 => 8010000000000001, 0
|
|
+ stfdx 80100094e0000359, 40 => 80100094e0000359, 0
|
|
+ stfdx bfe0000000000001, 48 => bfe0000000000001, 0
|
|
+ stfdx bfe00094e0000359, 56 => bfe00094e0000359, 0
|
|
+ stfdx 0000000000000000, 64 => 0000000000000000, 0
|
|
+ stfdx 8000000000000000, 72 => 8000000000000000, 0
|
|
+ stfdx 7ff0000000000000, 80 => 7ff0000000000000, 0
|
|
+ stfdx fff0000000000000, 88 => fff0000000000000, 0
|
|
+ stfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
|
|
+ stfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0
|
|
+ stfdx 7ff8000000000000, 112 => 7ff8000000000000, 0
|
|
+ stfdx fff8000000000000, 120 => fff8000000000000, 0
|
|
+
|
|
+ stfdux 0010000000000001, 0 => 0010000000000001, 0
|
|
+ stfdux 00100094e0000359, 8 => 00100094e0000359, 8
|
|
+ stfdux 3fe0000000000001, 16 => 3fe0000000000001, 16
|
|
+ stfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24
|
|
+ stfdux 8010000000000001, 32 => 8010000000000001, 32
|
|
+ stfdux 80100094e0000359, 40 => 80100094e0000359, 40
|
|
+ stfdux bfe0000000000001, 48 => bfe0000000000001, 48
|
|
+ stfdux bfe00094e0000359, 56 => bfe00094e0000359, 56
|
|
+ stfdux 0000000000000000, 64 => 0000000000000000, 64
|
|
+ stfdux 8000000000000000, 72 => 8000000000000000, 72
|
|
+ stfdux 7ff0000000000000, 80 => 7ff0000000000000, 80
|
|
+ stfdux fff0000000000000, 88 => fff0000000000000, 88
|
|
+ stfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
|
|
+ stfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104
|
|
+ stfdux 7ff8000000000000, 112 => 7ff8000000000000, 112
|
|
+ stfdux fff8000000000000, 120 => fff8000000000000, 120
|
|
+
|
|
+All done. Tested 77 different instructions
|
|
Index: none/tests/ppc64/round.c
|
|
===================================================================
|
|
--- none/tests/ppc64/round.c.orig
|
|
+++ none/tests/ppc64/round.c
|
|
@@ -49,19 +49,32 @@ typedef unsigned int fpscr_t;
|
|
typedef union {
|
|
float flt;
|
|
struct {
|
|
+#if defined(VGP_ppc64le_linux)
|
|
+ unsigned int frac:23;
|
|
+ unsigned int exp:8;
|
|
+ unsigned int sign:1;
|
|
+#else
|
|
unsigned int sign:1;
|
|
unsigned int exp:8;
|
|
unsigned int frac:23;
|
|
+#endif
|
|
} layout;
|
|
} flt_overlay;
|
|
|
|
typedef union {
|
|
double dbl;
|
|
struct {
|
|
+#if defined(VGP_ppc64le_linux)
|
|
+ unsigned int frac_lo:32;
|
|
+ unsigned int frac_hi:20;
|
|
+ unsigned int exp:11;
|
|
+ unsigned int sign:1;
|
|
+#else
|
|
unsigned int sign:1;
|
|
unsigned int exp:11;
|
|
unsigned int frac_hi:20;
|
|
unsigned int frac_lo:32;
|
|
+#endif
|
|
} layout;
|
|
struct {
|
|
unsigned int hi;
|
|
@@ -227,7 +240,7 @@ init()
|
|
F.layout.frac = 1;
|
|
denorm_small = F.flt; /* == 2^(-149) */
|
|
if (debug) {
|
|
- print_double("float small", F.flt);
|
|
+ print_single("float small", &F.flt);
|
|
}
|
|
|
|
D.layout.sign = 0;
|
|
Index: none/tests/ppc64/test_isa_2_06_part1.stdout.exp-LE
|
|
===================================================================
|
|
--- /dev/null
|
|
+++ none/tests/ppc64/test_isa_2_06_part1.stdout.exp-LE
|
|
@@ -0,0 +1,1044 @@
|
|
+Test VSX load/store instructions
|
|
+lxsdx: 01234567 89abcdef => 01234567 89abcdef
|
|
+lxsdx: 8899aabb 91929394 => 8899aabb 91929394
|
|
+
|
|
+lxsdx: 01234567 89abcdef => 01234567 89abcdef
|
|
+lxsdx: 89abcdef 00112233 => 89abcdef 00112233
|
|
+lxsdx: 8899aabb 91929394 => 8899aabb 91929394
|
|
+lxsdx: 91929394 a1a2a3a4 => 91929394 a1a2a3a4
|
|
+
|
|
+lxvd2x: 01234567 89abcdef 00112233 44556677 => 00112233 44556677 01234567 89abcdef
|
|
+lxvd2x: 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => a1a2a3a4 b1b2b3b4 8899aabb 91929394
|
|
+
|
|
+lxvd2x: 01234567 89abcdef 00112233 44556677 => 00112233 44556677 01234567 89abcdef
|
|
+lxvd2x: 89abcdef 00112233 44556677 8899aabb => 44556677 8899aabb 89abcdef 00112233
|
|
+lxvd2x: 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => a1a2a3a4 b1b2b3b4 8899aabb 91929394
|
|
+lxvd2x: 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => b1b2b3b4 c1c2c3c4 91929394 a1a2a3a4
|
|
+
|
|
+lxvdsx: 01234567 89abcdef 01234567 89abcdef => 01234567 89abcdef 01234567 89abcdef
|
|
+lxvdsx: 8899aabb 91929394 8899aabb 91929394 => 8899aabb 91929394 8899aabb 91929394
|
|
+
|
|
+lxvdsx: 01234567 89abcdef 01234567 89abcdef => 01234567 89abcdef 01234567 89abcdef
|
|
+lxvdsx: 89abcdef 00112233 89abcdef 00112233 => 89abcdef 00112233 89abcdef 00112233
|
|
+lxvdsx: 8899aabb 91929394 8899aabb 91929394 => 8899aabb 91929394 8899aabb 91929394
|
|
+lxvdsx: 91929394 a1a2a3a4 91929394 a1a2a3a4 => 91929394 a1a2a3a4 91929394 a1a2a3a4
|
|
+
|
|
+lxvw4x: 01234567 89abcdef 00112233 44556677 => 44556677 00112233 89abcdef 01234567
|
|
+lxvw4x: 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => b1b2b3b4 a1a2a3a4 91929394 8899aabb
|
|
+
|
|
+lxvw4x: 01234567 89abcdef 00112233 44556677 => 44556677 00112233 89abcdef 01234567
|
|
+lxvw4x: 89abcdef 00112233 44556677 8899aabb => 8899aabb 44556677 00112233 89abcdef
|
|
+lxvw4x: 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => b1b2b3b4 a1a2a3a4 91929394 8899aabb
|
|
+lxvw4x: 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => c1c2c3c4 b1b2b3b4 a1a2a3a4 91929394
|
|
+
|
|
+stxsdx: 01234567 89abcdef => 00112233 44556677
|
|
+
|
|
+stxsdx: 01234567 89abcdef => 00112233 44556677
|
|
+
|
|
+stxvd2x: 01234567 89abcdef 00112233 44556677 => 00112233 44556677 01234567 89abcdef
|
|
+
|
|
+stxvd2x: 01234567 89abcdef 00112233 44556677 => 00112233 44556677 01234567 89abcdef
|
|
+
|
|
+stxvw4x: 01234567 89abcdef 00112233 44556677 => 44556677 00112233 89abcdef 01234567
|
|
+
|
|
+stxvw4x: 01234567 89abcdef 00112233 44556677 => 44556677 00112233 89abcdef 01234567
|
|
+
|
|
+Test VSX logic instructions
|
|
+xxlxor: 01234567 89abcdef 00112233 44556677 xxlxor 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 89baefdc 18395e7b a1b38197 f5e7d5c3
|
|
+xxlxor: 89abcdef 00112233 44556677 8899aabb xxlxor 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 18395e7b a1b38197 f5e7d5c3 495b697f
|
|
+xxlxor: 00112233 44556677 8899aabb 91929394 xxlxor a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => a1b38197 f5e7d5c3 495b697f 40404040
|
|
+xxlxor: 44556677 8899aabb 91929394 a1a2a3a4 xxlxor b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => f5e7d5c3 495b697f 40404040 dbc9fe9a
|
|
+xxlor: 01234567 89abcdef 00112233 44556677 xxlor 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 89bbefff 99bbdfff a1b3a3b7 f5f7f7f7
|
|
+xxlor: 89abcdef 00112233 44556677 8899aabb xxlor 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 99bbdfff a1b3a3b7 f5f7f7f7 c9dbebff
|
|
+xxlor: 00112233 44556677 8899aabb 91929394 xxlor a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => a1b3a3b7 f5f7f7f7 c9dbebff d1d2d3d4
|
|
+xxlor: 44556677 8899aabb 91929394 a1a2a3a4 xxlor b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => f5f7f7f7 c9dbebff d1d2d3d4 fbebffbe
|
|
+xxlnor: 01234567 89abcdef 00112233 44556677 xxlnor 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 76441000 66442000 5e4c5c48 0a080808
|
|
+xxlnor: 89abcdef 00112233 44556677 8899aabb xxlnor 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 66442000 5e4c5c48 0a080808 36241400
|
|
+xxlnor: 00112233 44556677 8899aabb 91929394 xxlnor a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => 5e4c5c48 0a080808 36241400 2e2d2c2b
|
|
+xxlnor: 44556677 8899aabb 91929394 a1a2a3a4 xxlnor b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => 0a080808 36241400 2e2d2c2b 04140041
|
|
+xxland: 01234567 89abcdef 00112233 44556677 xxland 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 00010023 81828184 00002220 00102234
|
|
+xxland: 89abcdef 00112233 44556677 8899aabb xxland 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 81828184 00002220 00102234 80808280
|
|
+xxland: 00112233 44556677 8899aabb 91929394 xxland a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => 00002220 00102234 80808280 91929394
|
|
+xxland: 44556677 8899aabb 91929394 a1a2a3a4 xxland b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => 00102234 80808280 91929394 20220124
|
|
+xxlandc: 01234567 89abcdef 00112233 44556677 xxlandc 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 01224544 08294c6b 00110013 44454443
|
|
+xxlandc: 89abcdef 00112233 44556677 8899aabb xxlandc 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 08294c6b 00110013 44454443 0819283b
|
|
+xxlandc: 00112233 44556677 8899aabb 91929394 xxlandc a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => 00110013 44454443 0819283b 00000000
|
|
+xxlandc: 44556677 8899aabb 91929394 a1a2a3a4 xxlandc b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => 44454443 0819283b 00000000 8180a280
|
|
+
|
|
+Test ldbrx instruction
|
|
+ldbrx: 67 45 23 01 ef cd ab 89 (reverse) => 89 ab cd ef 01 23 45 67
|
|
+ldbrx: ef cd ab 89 33 22 11 00 (reverse) => 00 11 22 33 89 ab cd ef
|
|
+ldbrx: 33 22 11 00 77 66 55 44 (reverse) => 44 55 66 77 00 11 22 33
|
|
+
|
|
+Test popcntd instruction
|
|
+popcntd: 0x9182736405504536 => 24
|
|
+
|
|
+Test lfiwzx instruction
|
|
+lfiwzx: 19088743 => 19088743.00
|
|
+lfiwzx: 2309737967 => 2309737967.00
|
|
+lfiwzx: 1122867 => 1122867.00
|
|
+
|
|
+Test P7 floating point convert instructions
|
|
+fcfids 0010000000000001 => (raw sp) 59800000)
|
|
+fcfids 00100094e0000359 => (raw sp) 598004a7)
|
|
+fcfids 3fe0000000000001 => (raw sp) 5e7f8000)
|
|
+fcfids 3fe00094e0000359 => (raw sp) 5e7f8002)
|
|
+fcfids 8010000000000001 => (raw sp) deffe000)
|
|
+fcfids 80100094e0000359 => (raw sp) deffdfff)
|
|
+fcfids bfe0000000000001 => (raw sp) de804000)
|
|
+fcfids bfe00094e0000359 => (raw sp) de803fff)
|
|
+fcfids 0020000000000b01 => (raw sp) 5a000000)
|
|
+fcfids 00000000203f0b3d => (raw sp) 4e00fc2d)
|
|
+fcfids 00000000005a203d => (raw sp) 4ab4407a)
|
|
+fcfids 8020000000000b01 => (raw sp) deffc000)
|
|
+fcfids 80000000203f0b3d => (raw sp) df000000)
|
|
+
|
|
+fcfidus 0010000000000001 => (raw sp) 59800000)
|
|
+fcfidus 00100094e0000359 => (raw sp) 598004a7)
|
|
+fcfidus 3fe0000000000001 => (raw sp) 5e7f8000)
|
|
+fcfidus 3fe00094e0000359 => (raw sp) 5e7f8002)
|
|
+fcfidus 8010000000000001 => (raw sp) 5f001000)
|
|
+fcfidus 80100094e0000359 => (raw sp) 5f001001)
|
|
+fcfidus bfe0000000000001 => (raw sp) 5f3fe000)
|
|
+fcfidus bfe00094e0000359 => (raw sp) 5f3fe001)
|
|
+fcfidus 0020000000000b01 => (raw sp) 5a000000)
|
|
+fcfidus 00000000203f0b3d => (raw sp) 4e00fc2d)
|
|
+fcfidus 00000000005a203d => (raw sp) 4ab4407a)
|
|
+fcfidus 8020000000000b01 => (raw sp) 5f002000)
|
|
+fcfidus 80000000203f0b3d => (raw sp) 5f000000)
|
|
+
|
|
+fcfidu 0010000000000001 => (raw sp) 4330000000000001)
|
|
+fcfidu 00100094e0000359 => (raw sp) 43300094e0000359)
|
|
+fcfidu 3fe0000000000001 => (raw sp) 43cff00000000000)
|
|
+fcfidu 3fe00094e0000359 => (raw sp) 43cff0004a700002)
|
|
+fcfidu 8010000000000001 => (raw sp) 43e0020000000000)
|
|
+fcfidu 80100094e0000359 => (raw sp) 43e00200129c0000)
|
|
+fcfidu bfe0000000000001 => (raw sp) 43e7fc0000000000)
|
|
+fcfidu bfe00094e0000359 => (raw sp) 43e7fc00129c0000)
|
|
+fcfidu 0020000000000b01 => (raw sp) 4340000000000580)
|
|
+fcfidu 00000000203f0b3d => (raw sp) 41c01f859e800000)
|
|
+fcfidu 00000000005a203d => (raw sp) 4156880f40000000)
|
|
+fcfidu 8020000000000b01 => (raw sp) 43e0040000000001)
|
|
+fcfidu 80000000203f0b3d => (raw sp) 43e00000000407e1)
|
|
+
|
|
+Test ftdiv instruction
|
|
+ftdiv: 3fd8000000000000 <=> 404f000000000000 ? 8 (CRx)
|
|
+ftdiv: 7ff7ffffffffffff <=> 404f000000000000 ? a (CRx)
|
|
+ftdiv: 404f000000000000 <=> fff8000000000000 ? a (CRx)
|
|
+ftdiv: 3fd8000000000000 <=> 0018000000b77501 ? a (CRx)
|
|
+ftdiv: 404f000000000000 <=> 7fe800000000051b ? a (CRx)
|
|
+ftdiv: 7fe800000000051b <=> 3fd8000000000000 ? a (CRx)
|
|
+ftdiv: 3fd8000000000000 <=> 7fe800000000051b ? a (CRx)
|
|
+ftdiv: 0123214569900000 <=> 3fd8000000000000 ? a (CRx)
|
|
+ftdiv: 7ff0000000000000 <=> 404f000000000000 ? e (CRx)
|
|
+ftdiv: fff0000000000000 <=> 404f000000000000 ? e (CRx)
|
|
+ftdiv: 404f000000000000 <=> 7ff0000000000000 ? e (CRx)
|
|
+ftdiv: 3fd8000000000000 <=> 8008340000078000 ? e (CRx)
|
|
+ftdiv: 0000000000000000 <=> 0000000000000000 ? e (CRx)
|
|
+ftdiv: 0000000000000000 <=> 8000000000000000 ? e (CRx)
|
|
+
|
|
+Test VSX move instructions
|
|
+xsabsdp: X[B]: 0011223344556677 => 0011223344556677
|
|
+xsabsdp: X[B]: a1a2a3a4b1b2b3b4 => 21a2a3a4b1b2b3b4
|
|
+xsabsdp: X[B]: 7a6b5d3efc032778 => 7a6b5d3efc032778
|
|
+
|
|
+xscpsgndp: X[A]: 0011223344556677 X[B]: 0011223344556677 => 0011223344556677
|
|
+xscpsgndp: X[A]: a1a2a3a4b1b2b3b4 X[B]: 0011223344556677 => 8011223344556677
|
|
+xscpsgndp: X[A]: 7a6b5d3efc032778 X[B]: 0011223344556677 => 0011223344556677
|
|
+xscpsgndp: X[A]: 0011223344556677 X[B]: a1a2a3a4b1b2b3b4 => 21a2a3a4b1b2b3b4
|
|
+xscpsgndp: X[A]: a1a2a3a4b1b2b3b4 X[B]: a1a2a3a4b1b2b3b4 => a1a2a3a4b1b2b3b4
|
|
+xscpsgndp: X[A]: 7a6b5d3efc032778 X[B]: a1a2a3a4b1b2b3b4 => 21a2a3a4b1b2b3b4
|
|
+xscpsgndp: X[A]: 0011223344556677 X[B]: 7a6b5d3efc032778 => 7a6b5d3efc032778
|
|
+xscpsgndp: X[A]: a1a2a3a4b1b2b3b4 X[B]: 7a6b5d3efc032778 => fa6b5d3efc032778
|
|
+xscpsgndp: X[A]: 7a6b5d3efc032778 X[B]: 7a6b5d3efc032778 => 7a6b5d3efc032778
|
|
+
|
|
+xsnabsdp: X[B]: 0011223344556677 => 8011223344556677
|
|
+xsnabsdp: X[B]: a1a2a3a4b1b2b3b4 => a1a2a3a4b1b2b3b4
|
|
+xsnabsdp: X[B]: 7a6b5d3efc032778 => fa6b5d3efc032778
|
|
+
|
|
+xsnegdp: X[B]: 0011223344556677 => 8011223344556677
|
|
+xsnegdp: X[B]: a1a2a3a4b1b2b3b4 => 21a2a3a4b1b2b3b4
|
|
+xsnegdp: X[B]: 7a6b5d3efc032778 => fa6b5d3efc032778
|
|
+
|
|
+Test VSX permute instructions
|
|
+xxmrghw:
|
|
+ XA[11111111,22222222,33333333,44444444]
|
|
+ XB[55555555,66666666,77777777,88888888]
|
|
+ => XT[77777777,33333333,88888888,44444444]
|
|
+xxmrghw:
|
|
+ XA[00112233,44556677,8899aabb,ccddeeff]
|
|
+ XB[11111111,22222222,33333333,44444444]
|
|
+ => XT[33333333,8899aabb,44444444,ccddeeff]
|
|
+xxmrglw:
|
|
+ XA[11111111,22222222,33333333,44444444]
|
|
+ XB[55555555,66666666,77777777,88888888]
|
|
+ => XT[55555555,11111111,66666666,22222222]
|
|
+xxmrglw:
|
|
+ XA[00112233,44556677,8899aabb,ccddeeff]
|
|
+ XB[11111111,22222222,33333333,44444444]
|
|
+ => XT[11111111,00112233,22222222,44556677]
|
|
+xxpermdi DM=00:
|
|
+ XA[11111111,22222222,33333333,44444444]
|
|
+ XB[55555555,66666666,77777777,88888888]
|
|
+ => XT[77777777,88888888,33333333,44444444]
|
|
+xxpermdi DM=01:
|
|
+ XA[11111111,22222222,33333333,44444444]
|
|
+ XB[55555555,66666666,77777777,88888888]
|
|
+ => XT[55555555,66666666,33333333,44444444]
|
|
+xxpermdi DM=10:
|
|
+ XA[11111111,22222222,33333333,44444444]
|
|
+ XB[55555555,66666666,77777777,88888888]
|
|
+ => XT[77777777,88888888,11111111,22222222]
|
|
+xxpermdi DM=11:
|
|
+ XA[11111111,22222222,33333333,44444444]
|
|
+ XB[55555555,66666666,77777777,88888888]
|
|
+ => XT[55555555,66666666,11111111,22222222]
|
|
+xxsldwi SHW=0:
|
|
+ XA[11111111,22222222,33333333,44444444]
|
|
+ XB[55555555,66666666,77777777,88888888]
|
|
+ => XT[11111111,22222222,33333333,44444444]
|
|
+xxsldwi SHW=1:
|
|
+ XA[11111111,22222222,33333333,44444444]
|
|
+ XB[55555555,66666666,77777777,88888888]
|
|
+ => XT[88888888,11111111,22222222,33333333]
|
|
+xxsldwi SHW=2:
|
|
+ XA[11111111,22222222,33333333,44444444]
|
|
+ XB[55555555,66666666,77777777,88888888]
|
|
+ => XT[77777777,88888888,11111111,22222222]
|
|
+xxsldwi SHW=3:
|
|
+ XA[11111111,22222222,33333333,44444444]
|
|
+ XB[55555555,66666666,77777777,88888888]
|
|
+ => XT[66666666,77777777,88888888,11111111]
|
|
+
|
|
+Test VSX floating point instructions
|
|
+#0: xscmpudp fff0000000000000 <=> fff0000000000000 ? 2 (CRx)
|
|
+#1: xscmpudp fff0000000000000 <=> c0d0650f5a07b353 ? 8 (CRx)
|
|
+#2: xscmpudp fff0000000000000 <=> 8000000000000000 ? 8 (CRx)
|
|
+#3: xscmpudp fff0000000000000 <=> 0000000000000000 ? 8 (CRx)
|
|
+#4: xscmpudp fff0000000000000 <=> 0123214569900000 ? 8 (CRx)
|
|
+#5: xscmpudp fff0000000000000 <=> 7ff0000000000000 ? 8 (CRx)
|
|
+#6: xscmpudp fff0000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
|
|
+#7: xscmpudp fff0000000000000 <=> 7ff8000000000000 ? 1 (CRx)
|
|
+#8: xscmpudp c0d0650f5a07b353 <=> fff0000000000000 ? 4 (CRx)
|
|
+#9: xscmpudp c0d0650f5a07b353 <=> c0d0650f5a07b353 ? 2 (CRx)
|
|
+#10: xscmpudp c0d0650f5a07b353 <=> 8000000000000000 ? 8 (CRx)
|
|
+#11: xscmpudp c0d0650f5a07b353 <=> 0000000000000000 ? 8 (CRx)
|
|
+#12: xscmpudp c0d0650f5a07b353 <=> 0123214569900000 ? 8 (CRx)
|
|
+#13: xscmpudp c0d0650f5a07b353 <=> 7ff0000000000000 ? 8 (CRx)
|
|
+#14: xscmpudp c0d0650f5a07b353 <=> 7ff7ffffffffffff ? 1 (CRx)
|
|
+#15: xscmpudp c0d0650f5a07b353 <=> 7ff8000000000000 ? 1 (CRx)
|
|
+#16: xscmpudp 8000000000000000 <=> fff0000000000000 ? 4 (CRx)
|
|
+#17: xscmpudp 8000000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
|
|
+#18: xscmpudp 8000000000000000 <=> 8000000000000000 ? 2 (CRx)
|
|
+#19: xscmpudp 8000000000000000 <=> 0000000000000000 ? 2 (CRx)
|
|
+#20: xscmpudp 8000000000000000 <=> 0123214569900000 ? 8 (CRx)
|
|
+#21: xscmpudp 8000000000000000 <=> 7ff0000000000000 ? 8 (CRx)
|
|
+#22: xscmpudp 8000000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
|
|
+#23: xscmpudp 8000000000000000 <=> 7ff8000000000000 ? 1 (CRx)
|
|
+#24: xscmpudp 0000000000000000 <=> fff0000000000000 ? 4 (CRx)
|
|
+#25: xscmpudp 0000000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
|
|
+#26: xscmpudp 0000000000000000 <=> 8000000000000000 ? 2 (CRx)
|
|
+#27: xscmpudp 0000000000000000 <=> 0000000000000000 ? 2 (CRx)
|
|
+#28: xscmpudp 0000000000000000 <=> 0123214569900000 ? 8 (CRx)
|
|
+#29: xscmpudp 0000000000000000 <=> 7ff0000000000000 ? 8 (CRx)
|
|
+#30: xscmpudp 0000000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
|
|
+#31: xscmpudp 0000000000000000 <=> 7ff8000000000000 ? 1 (CRx)
|
|
+#32: xscmpudp 0123214569900000 <=> fff0000000000000 ? 4 (CRx)
|
|
+#33: xscmpudp 0123214569900000 <=> c0d0650f5a07b353 ? 4 (CRx)
|
|
+#34: xscmpudp 0123214569900000 <=> 8000000000000000 ? 4 (CRx)
|
|
+#35: xscmpudp 0123214569900000 <=> 0000000000000000 ? 4 (CRx)
|
|
+#36: xscmpudp 0123214569900000 <=> 404f000000000000 ? 8 (CRx)
|
|
+#37: xscmpudp 0123214569900000 <=> 7ff0000000000000 ? 8 (CRx)
|
|
+#38: xscmpudp 0123214569900000 <=> 7ff7ffffffffffff ? 1 (CRx)
|
|
+#39: xscmpudp 0123214569900000 <=> 7ff8000000000000 ? 1 (CRx)
|
|
+#40: xscmpudp 7ff0000000000000 <=> fff0000000000000 ? 4 (CRx)
|
|
+#41: xscmpudp 7ff0000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
|
|
+#42: xscmpudp 7ff0000000000000 <=> 8000000000000000 ? 4 (CRx)
|
|
+#43: xscmpudp 7ff0000000000000 <=> 0000000000000000 ? 4 (CRx)
|
|
+#44: xscmpudp 7ff0000000000000 <=> 0123214569900000 ? 4 (CRx)
|
|
+#45: xscmpudp 7ff0000000000000 <=> 7ff0000000000000 ? 2 (CRx)
|
|
+#46: xscmpudp 7ff0000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
|
|
+#47: xscmpudp 7ff0000000000000 <=> 7ff8000000000000 ? 1 (CRx)
|
|
+#48: xscmpudp fff7ffffffffffff <=> fff0000000000000 ? 1 (CRx)
|
|
+#49: xscmpudp fff7ffffffffffff <=> c0d0650f5a07b353 ? 1 (CRx)
|
|
+#50: xscmpudp fff7ffffffffffff <=> 8000000000000000 ? 1 (CRx)
|
|
+#51: xscmpudp fff7ffffffffffff <=> 0000000000000000 ? 1 (CRx)
|
|
+#52: xscmpudp fff7ffffffffffff <=> 0123214569900000 ? 1 (CRx)
|
|
+#53: xscmpudp fff7ffffffffffff <=> 7ff0000000000000 ? 1 (CRx)
|
|
+#54: xscmpudp fff7ffffffffffff <=> 7ff7ffffffffffff ? 1 (CRx)
|
|
+#55: xscmpudp fff7ffffffffffff <=> 7ff8000000000000 ? 1 (CRx)
|
|
+#56: xscmpudp fff8000000000000 <=> fff0000000000000 ? 1 (CRx)
|
|
+#57: xscmpudp fff8000000000000 <=> c0d0650f5a07b353 ? 1 (CRx)
|
|
+#58: xscmpudp fff8000000000000 <=> 8000000000000000 ? 1 (CRx)
|
|
+#59: xscmpudp fff8000000000000 <=> 0000000000000000 ? 1 (CRx)
|
|
+#60: xscmpudp fff8000000000000 <=> 0123214569900000 ? 1 (CRx)
|
|
+#61: xscmpudp fff8000000000000 <=> 7ff0000000000000 ? 1 (CRx)
|
|
+#62: xscmpudp fff8000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
|
|
+#63: xscmpudp fff8000000000000 <=> 7ff8000000000000 ? 1 (CRx)
|
|
+
|
|
+#0: xscmpodp fff0000000000000 <=> fff0000000000000 ? 2 (CRx)
|
|
+#1: xscmpodp fff0000000000000 <=> c0d0650f5a07b353 ? 8 (CRx)
|
|
+#2: xscmpodp fff0000000000000 <=> 8000000000000000 ? 8 (CRx)
|
|
+#3: xscmpodp fff0000000000000 <=> 0000000000000000 ? 8 (CRx)
|
|
+#4: xscmpodp fff0000000000000 <=> 0123214569900000 ? 8 (CRx)
|
|
+#5: xscmpodp fff0000000000000 <=> 7ff0000000000000 ? 8 (CRx)
|
|
+#6: xscmpodp fff0000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
|
|
+#7: xscmpodp fff0000000000000 <=> 7ff8000000000000 ? 1 (CRx)
|
|
+#8: xscmpodp c0d0650f5a07b353 <=> fff0000000000000 ? 4 (CRx)
|
|
+#9: xscmpodp c0d0650f5a07b353 <=> c0d0650f5a07b353 ? 2 (CRx)
|
|
+#10: xscmpodp c0d0650f5a07b353 <=> 8000000000000000 ? 8 (CRx)
|
|
+#11: xscmpodp c0d0650f5a07b353 <=> 0000000000000000 ? 8 (CRx)
|
|
+#12: xscmpodp c0d0650f5a07b353 <=> 0123214569900000 ? 8 (CRx)
|
|
+#13: xscmpodp c0d0650f5a07b353 <=> 7ff0000000000000 ? 8 (CRx)
|
|
+#14: xscmpodp c0d0650f5a07b353 <=> 7ff7ffffffffffff ? 1 (CRx)
|
|
+#15: xscmpodp c0d0650f5a07b353 <=> 7ff8000000000000 ? 1 (CRx)
|
|
+#16: xscmpodp 8000000000000000 <=> fff0000000000000 ? 4 (CRx)
|
|
+#17: xscmpodp 8000000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
|
|
+#18: xscmpodp 8000000000000000 <=> 8000000000000000 ? 2 (CRx)
|
|
+#19: xscmpodp 8000000000000000 <=> 0000000000000000 ? 2 (CRx)
|
|
+#20: xscmpodp 8000000000000000 <=> 0123214569900000 ? 8 (CRx)
|
|
+#21: xscmpodp 8000000000000000 <=> 7ff0000000000000 ? 8 (CRx)
|
|
+#22: xscmpodp 8000000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
|
|
+#23: xscmpodp 8000000000000000 <=> 7ff8000000000000 ? 1 (CRx)
|
|
+#24: xscmpodp 0000000000000000 <=> fff0000000000000 ? 4 (CRx)
|
|
+#25: xscmpodp 0000000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
|
|
+#26: xscmpodp 0000000000000000 <=> 8000000000000000 ? 2 (CRx)
|
|
+#27: xscmpodp 0000000000000000 <=> 0000000000000000 ? 2 (CRx)
|
|
+#28: xscmpodp 0000000000000000 <=> 0123214569900000 ? 8 (CRx)
|
|
+#29: xscmpodp 0000000000000000 <=> 7ff0000000000000 ? 8 (CRx)
|
|
+#30: xscmpodp 0000000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
|
|
+#31: xscmpodp 0000000000000000 <=> 7ff8000000000000 ? 1 (CRx)
|
|
+#32: xscmpodp 0123214569900000 <=> fff0000000000000 ? 4 (CRx)
|
|
+#33: xscmpodp 0123214569900000 <=> c0d0650f5a07b353 ? 4 (CRx)
|
|
+#34: xscmpodp 0123214569900000 <=> 8000000000000000 ? 4 (CRx)
|
|
+#35: xscmpodp 0123214569900000 <=> 0000000000000000 ? 4 (CRx)
|
|
+#36: xscmpodp 0123214569900000 <=> 404f000000000000 ? 8 (CRx)
|
|
+#37: xscmpodp 0123214569900000 <=> 7ff0000000000000 ? 8 (CRx)
|
|
+#38: xscmpodp 0123214569900000 <=> 7ff7ffffffffffff ? 1 (CRx)
|
|
+#39: xscmpodp 0123214569900000 <=> 7ff8000000000000 ? 1 (CRx)
|
|
+#40: xscmpodp 7ff0000000000000 <=> fff0000000000000 ? 4 (CRx)
|
|
+#41: xscmpodp 7ff0000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
|
|
+#42: xscmpodp 7ff0000000000000 <=> 8000000000000000 ? 4 (CRx)
|
|
+#43: xscmpodp 7ff0000000000000 <=> 0000000000000000 ? 4 (CRx)
|
|
+#44: xscmpodp 7ff0000000000000 <=> 0123214569900000 ? 4 (CRx)
|
|
+#45: xscmpodp 7ff0000000000000 <=> 7ff0000000000000 ? 2 (CRx)
|
|
+#46: xscmpodp 7ff0000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
|
|
+#47: xscmpodp 7ff0000000000000 <=> 7ff8000000000000 ? 1 (CRx)
|
|
+#48: xscmpodp fff7ffffffffffff <=> fff0000000000000 ? 1 (CRx)
|
|
+#49: xscmpodp fff7ffffffffffff <=> c0d0650f5a07b353 ? 1 (CRx)
|
|
+#50: xscmpodp fff7ffffffffffff <=> 8000000000000000 ? 1 (CRx)
|
|
+#51: xscmpodp fff7ffffffffffff <=> 0000000000000000 ? 1 (CRx)
|
|
+#52: xscmpodp fff7ffffffffffff <=> 0123214569900000 ? 1 (CRx)
|
|
+#53: xscmpodp fff7ffffffffffff <=> 7ff0000000000000 ? 1 (CRx)
|
|
+#54: xscmpodp fff7ffffffffffff <=> 7ff7ffffffffffff ? 1 (CRx)
|
|
+#55: xscmpodp fff7ffffffffffff <=> 7ff8000000000000 ? 1 (CRx)
|
|
+#56: xscmpodp fff8000000000000 <=> fff0000000000000 ? 1 (CRx)
|
|
+#57: xscmpodp fff8000000000000 <=> c0d0650f5a07b353 ? 1 (CRx)
|
|
+#58: xscmpodp fff8000000000000 <=> 8000000000000000 ? 1 (CRx)
|
|
+#59: xscmpodp fff8000000000000 <=> 0000000000000000 ? 1 (CRx)
|
|
+#60: xscmpodp fff8000000000000 <=> 0123214569900000 ? 1 (CRx)
|
|
+#61: xscmpodp fff8000000000000 <=> 7ff0000000000000 ? 1 (CRx)
|
|
+#62: xscmpodp fff8000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
|
|
+#63: xscmpodp fff8000000000000 <=> 7ff8000000000000 ? 1 (CRx)
|
|
+
|
|
+#0: xsadddp fff0000000000000 fff0000000000000 = fff0000000000000
|
|
+#1: xsadddp fff0000000000000 c0d0650f5a07b353 = fff0000000000000
|
|
+#2: xsadddp fff0000000000000 8000000000000000 = fff0000000000000
|
|
+#3: xsadddp fff0000000000000 0000000000000000 = fff0000000000000
|
|
+#4: xsadddp fff0000000000000 0123214569900000 = fff0000000000000
|
|
+#5: xsadddp fff0000000000000 7ff0000000000000 = 7ff8000000000000
|
|
+#6: xsadddp fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#7: xsadddp fff0000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#8: xsadddp c0d0650f5a07b353 fff0000000000000 = fff0000000000000
|
|
+#9: xsadddp c0d0650f5a07b353 c0d0650f5a07b353 = c0e0650f5a07b353
|
|
+#10: xsadddp c0d0650f5a07b353 8000000000000000 = c0d0650f5a07b353
|
|
+#11: xsadddp c0d0650f5a07b353 0000000000000000 = c0d0650f5a07b353
|
|
+#12: xsadddp c0d0650f5a07b353 0123214569900000 = c0d0650f5a07b353
|
|
+#13: xsadddp c0d0650f5a07b353 7ff0000000000000 = 7ff0000000000000
|
|
+#14: xsadddp c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#15: xsadddp c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
|
|
+#16: xsadddp 8000000000000000 fff0000000000000 = fff0000000000000
|
|
+#17: xsadddp 8000000000000000 c0d0650f5a07b353 = c0d0650f5a07b353
|
|
+#18: xsadddp 8000000000000000 8000000000000000 = 8000000000000000
|
|
+#19: xsadddp 8000000000000000 0000000000000000 = 0000000000000000
|
|
+#20: xsadddp 8000000000000000 0123214569900000 = 0123214569900000
|
|
+#21: xsadddp 8000000000000000 7ff0000000000000 = 7ff0000000000000
|
|
+#22: xsadddp 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#23: xsadddp 8000000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#24: xsadddp 0000000000000000 fff0000000000000 = fff0000000000000
|
|
+#25: xsadddp 0000000000000000 c0d0650f5a07b353 = c0d0650f5a07b353
|
|
+#26: xsadddp 0000000000000000 8000000000000000 = 0000000000000000
|
|
+#27: xsadddp 0000000000000000 0000000000000000 = 0000000000000000
|
|
+#28: xsadddp 0000000000000000 0123214569900000 = 0123214569900000
|
|
+#29: xsadddp 0000000000000000 7ff0000000000000 = 7ff0000000000000
|
|
+#30: xsadddp 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#31: xsadddp 0000000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#32: xsadddp 0123214569900000 fff0000000000000 = fff0000000000000
|
|
+#33: xsadddp 0123214569900000 c0d0650f5a07b353 = c0d0650f5a07b353
|
|
+#34: xsadddp 0123214569900000 8000000000000000 = 0123214569900000
|
|
+#35: xsadddp 0123214569900000 0000000000000000 = 0123214569900000
|
|
+#36: xsadddp 0123214569900000 404f000000000000 = 404f000000000000
|
|
+#37: xsadddp 0123214569900000 7ff0000000000000 = 7ff0000000000000
|
|
+#38: xsadddp 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#39: xsadddp 0123214569900000 7ff8000000000000 = 7ff8000000000000
|
|
+#40: xsadddp 7ff0000000000000 fff0000000000000 = 7ff8000000000000
|
|
+#41: xsadddp 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#42: xsadddp 7ff0000000000000 8000000000000000 = 7ff0000000000000
|
|
+#43: xsadddp 7ff0000000000000 0000000000000000 = 7ff0000000000000
|
|
+#44: xsadddp 7ff0000000000000 0123214569900000 = 7ff0000000000000
|
|
+#45: xsadddp 7ff0000000000000 7ff0000000000000 = 7ff0000000000000
|
|
+#46: xsadddp 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#47: xsadddp 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#48: xsadddp fff7ffffffffffff fff0000000000000 = ffffffffffffffff
|
|
+#49: xsadddp fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
|
|
+#50: xsadddp fff7ffffffffffff 8000000000000000 = ffffffffffffffff
|
|
+#51: xsadddp fff7ffffffffffff 0000000000000000 = ffffffffffffffff
|
|
+#52: xsadddp fff7ffffffffffff 0123214569900000 = ffffffffffffffff
|
|
+#53: xsadddp fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
|
|
+#54: xsadddp fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
|
|
+#55: xsadddp fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
|
|
+#56: xsadddp fff8000000000000 fff0000000000000 = fff8000000000000
|
|
+#57: xsadddp fff8000000000000 c0d0650f5a07b353 = fff8000000000000
|
|
+#58: xsadddp fff8000000000000 8000000000000000 = fff8000000000000
|
|
+#59: xsadddp fff8000000000000 0000000000000000 = fff8000000000000
|
|
+#60: xsadddp fff8000000000000 0123214569900000 = fff8000000000000
|
|
+#61: xsadddp fff8000000000000 7ff0000000000000 = fff8000000000000
|
|
+#62: xsadddp fff8000000000000 7ff7ffffffffffff = fff8000000000000
|
|
+#63: xsadddp fff8000000000000 7ff8000000000000 = fff8000000000000
|
|
+
|
|
+#0: xsdivdp fff0000000000000 fff0000000000000 = 7ff8000000000000
|
|
+#1: xsdivdp fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#2: xsdivdp fff0000000000000 8000000000000000 = 7ff0000000000000
|
|
+#3: xsdivdp fff0000000000000 0000000000000000 = fff0000000000000
|
|
+#4: xsdivdp fff0000000000000 0123214569900000 = fff0000000000000
|
|
+#5: xsdivdp fff0000000000000 7ff0000000000000 = 7ff8000000000000
|
|
+#6: xsdivdp fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#7: xsdivdp fff0000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#8: xsdivdp c0d0650f5a07b353 fff0000000000000 = 0000000000000000
|
|
+#9: xsdivdp c0d0650f5a07b353 c0d0650f5a07b353 = 3ff0000000000000
|
|
+#10: xsdivdp c0d0650f5a07b353 8000000000000000 = 7ff0000000000000
|
|
+#11: xsdivdp c0d0650f5a07b353 0000000000000000 = fff0000000000000
|
|
+#12: xsdivdp c0d0650f5a07b353 0123214569900000 = ff9b6cb57ca13c00
|
|
+#13: xsdivdp c0d0650f5a07b353 7ff0000000000000 = 8000000000000000
|
|
+#14: xsdivdp c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#15: xsdivdp c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
|
|
+#16: xsdivdp 8000000000000000 fff0000000000000 = 0000000000000000
|
|
+#17: xsdivdp 8000000000000000 c0d0650f5a07b353 = 0000000000000000
|
|
+#18: xsdivdp 8000000000000000 8000000000000000 = 7ff8000000000000
|
|
+#19: xsdivdp 8000000000000000 0000000000000000 = 7ff8000000000000
|
|
+#20: xsdivdp 8000000000000000 0123214569900000 = 8000000000000000
|
|
+#21: xsdivdp 8000000000000000 7ff0000000000000 = 8000000000000000
|
|
+#22: xsdivdp 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#23: xsdivdp 8000000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#24: xsdivdp 0000000000000000 fff0000000000000 = 8000000000000000
|
|
+#25: xsdivdp 0000000000000000 c0d0650f5a07b353 = 8000000000000000
|
|
+#26: xsdivdp 0000000000000000 8000000000000000 = 7ff8000000000000
|
|
+#27: xsdivdp 0000000000000000 0000000000000000 = 7ff8000000000000
|
|
+#28: xsdivdp 0000000000000000 0123214569900000 = 0000000000000000
|
|
+#29: xsdivdp 0000000000000000 7ff0000000000000 = 0000000000000000
|
|
+#30: xsdivdp 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#31: xsdivdp 0000000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#32: xsdivdp 0123214569900000 fff0000000000000 = 8000000000000000
|
|
+#33: xsdivdp 0123214569900000 c0d0650f5a07b353 = 8042ab59d8b6ec87
|
|
+#34: xsdivdp 0123214569900000 8000000000000000 = fff0000000000000
|
|
+#35: xsdivdp 0123214569900000 0000000000000000 = 7ff0000000000000
|
|
+#36: xsdivdp 0123214569900000 404f000000000000 = 00c3bf3f64b5ad6b
|
|
+#37: xsdivdp 0123214569900000 7ff0000000000000 = 0000000000000000
|
|
+#38: xsdivdp 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#39: xsdivdp 0123214569900000 7ff8000000000000 = 7ff8000000000000
|
|
+#40: xsdivdp 7ff0000000000000 fff0000000000000 = 7ff8000000000000
|
|
+#41: xsdivdp 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
|
|
+#42: xsdivdp 7ff0000000000000 8000000000000000 = fff0000000000000
|
|
+#43: xsdivdp 7ff0000000000000 0000000000000000 = 7ff0000000000000
|
|
+#44: xsdivdp 7ff0000000000000 0123214569900000 = 7ff0000000000000
|
|
+#45: xsdivdp 7ff0000000000000 7ff0000000000000 = 7ff8000000000000
|
|
+#46: xsdivdp 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#47: xsdivdp 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#48: xsdivdp fff7ffffffffffff fff0000000000000 = ffffffffffffffff
|
|
+#49: xsdivdp fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
|
|
+#50: xsdivdp fff7ffffffffffff 8000000000000000 = ffffffffffffffff
|
|
+#51: xsdivdp fff7ffffffffffff 0000000000000000 = ffffffffffffffff
|
|
+#52: xsdivdp fff7ffffffffffff 0123214569900000 = ffffffffffffffff
|
|
+#53: xsdivdp fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
|
|
+#54: xsdivdp fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
|
|
+#55: xsdivdp fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
|
|
+#56: xsdivdp fff8000000000000 fff0000000000000 = fff8000000000000
|
|
+#57: xsdivdp fff8000000000000 c0d0650f5a07b353 = fff8000000000000
|
|
+#58: xsdivdp fff8000000000000 8000000000000000 = fff8000000000000
|
|
+#59: xsdivdp fff8000000000000 0000000000000000 = fff8000000000000
|
|
+#60: xsdivdp fff8000000000000 0123214569900000 = fff8000000000000
|
|
+#61: xsdivdp fff8000000000000 7ff0000000000000 = fff8000000000000
|
|
+#62: xsdivdp fff8000000000000 7ff7ffffffffffff = fff8000000000000
|
|
+#63: xsdivdp fff8000000000000 7ff8000000000000 = fff8000000000000
|
|
+
|
|
+#0: xsmaddadp fff0000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff8000000000000
|
|
+#1: xsmaddadp c0d0650f5a07b353 fff0000000000000 0123214569900000 = fff0000000000000
|
|
+#2: xsmaddadp 8000000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#3: xsmaddadp 0000000000000000 fff0000000000000 0123214569900000 = fff0000000000000
|
|
+#4: xsmaddadp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#5: xsmaddadp 7ff0000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000
|
|
+#6: xsmaddadp 7ff7ffffffffffff fff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
|
|
+#7: xsmaddadp 7ff8000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000
|
|
+#8: xsmaddadp fff0000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = fff0000000000000
|
|
+#9: xsmaddadp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = c0d0650f5a07b353
|
|
+#10: xsmaddadp 8000000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7
|
|
+#11: xsmaddadp 0000000000000000 c0d0650f5a07b353 0123214569900000 = 82039a19ca8fcb5f
|
|
+#12: xsmaddadp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7
|
|
+#13: xsmaddadp 7ff0000000000000 c0d0650f5a07b353 0123214569900000 = 7ff0000000000000
|
|
+#14: xsmaddadp 7ff7ffffffffffff c0d0650f5a07b353 c0d0650f5a07b353 = 7fffffffffffffff
|
|
+#15: xsmaddadp 7ff8000000000000 c0d0650f5a07b353 0123214569900000 = 7ff8000000000000
|
|
+#16: xsmaddadp fff0000000000000 8000000000000000 c0d0650f5a07b353 = fff0000000000000
|
|
+#17: xsmaddadp c0d0650f5a07b353 8000000000000000 0123214569900000 = c0d0650f5a07b353
|
|
+#18: xsmaddadp 8000000000000000 8000000000000000 c0d0650f5a07b353 = 0000000000000000
|
|
+#19: xsmaddadp 0000000000000000 8000000000000000 0123214569900000 = 0000000000000000
|
|
+#20: xsmaddadp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 0123214569900000
|
|
+#21: xsmaddadp 7ff0000000000000 8000000000000000 0123214569900000 = 7ff0000000000000
|
|
+#22: xsmaddadp 7ff7ffffffffffff 8000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
|
|
+#23: xsmaddadp 7ff8000000000000 8000000000000000 0123214569900000 = 7ff8000000000000
|
|
+#24: xsmaddadp fff0000000000000 0000000000000000 c0d0650f5a07b353 = fff0000000000000
|
|
+#25: xsmaddadp c0d0650f5a07b353 0000000000000000 0123214569900000 = c0d0650f5a07b353
|
|
+#26: xsmaddadp 8000000000000000 0000000000000000 c0d0650f5a07b353 = 8000000000000000
|
|
+#27: xsmaddadp 0000000000000000 0000000000000000 0123214569900000 = 0000000000000000
|
|
+#28: xsmaddadp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 0123214569900000
|
|
+#29: xsmaddadp 7ff0000000000000 0000000000000000 0123214569900000 = 7ff0000000000000
|
|
+#30: xsmaddadp 7ff7ffffffffffff 0000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
|
|
+#31: xsmaddadp 7ff8000000000000 0000000000000000 0123214569900000 = 7ff8000000000000
|
|
+#32: xsmaddadp fff0000000000000 0123214569900000 c0d0650f5a07b353 = fff0000000000000
|
|
+#33: xsmaddadp c0d0650f5a07b353 0123214569900000 0123214569900000 = c0d0650f5a07b353
|
|
+#34: xsmaddadp 8000000000000000 0123214569900000 c0d0650f5a07b353 = 82039a19ca8fcb5f
|
|
+#35: xsmaddadp 0000000000000000 0123214569900000 0123214569900000 = 0000000000000000
|
|
+#36: xsmaddadp 404f000000000000 0123214569900000 c0d0650f5a07b353 = 404f000000000000
|
|
+#37: xsmaddadp 7ff0000000000000 0123214569900000 0123214569900000 = 7ff0000000000000
|
|
+#38: xsmaddadp 7ff7ffffffffffff 0123214569900000 c0d0650f5a07b353 = 7fffffffffffffff
|
|
+#39: xsmaddadp 7ff8000000000000 0123214569900000 0123214569900000 = 7ff8000000000000
|
|
+#40: xsmaddadp fff0000000000000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
|
|
+#41: xsmaddadp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = 7ff0000000000000
|
|
+#42: xsmaddadp 8000000000000000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
|
|
+#43: xsmaddadp 0000000000000000 7ff0000000000000 0123214569900000 = 7ff0000000000000
|
|
+#44: xsmaddadp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
|
|
+#45: xsmaddadp 7ff0000000000000 7ff0000000000000 0123214569900000 = 7ff0000000000000
|
|
+#46: xsmaddadp 7ff7ffffffffffff 7ff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
|
|
+#47: xsmaddadp 7ff8000000000000 7ff0000000000000 0123214569900000 = 7ff8000000000000
|
|
+#48: xsmaddadp fff0000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
|
|
+#49: xsmaddadp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
|
|
+#50: xsmaddadp 8000000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
|
|
+#51: xsmaddadp 0000000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
|
|
+#52: xsmaddadp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
|
|
+#53: xsmaddadp 7ff0000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
|
|
+#54: xsmaddadp 7ff7ffffffffffff fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
|
|
+#55: xsmaddadp 7ff8000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
|
|
+#56: xsmaddadp fff0000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
|
|
+#57: xsmaddadp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
|
|
+#58: xsmaddadp 8000000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
|
|
+#59: xsmaddadp 0000000000000000 fff8000000000000 0123214569900000 = fff8000000000000
|
|
+#60: xsmaddadp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
|
|
+#61: xsmaddadp 7ff0000000000000 fff8000000000000 0123214569900000 = fff8000000000000
|
|
+#62: xsmaddadp 7ff7ffffffffffff fff8000000000000 c0d0650f5a07b353 = fff8000000000000
|
|
+#63: xsmaddadp 7ff8000000000000 fff8000000000000 0123214569900000 = fff8000000000000
|
|
+
|
|
+#0: xsmaddmdp c0d0650f5a07b353 fff0000000000000 fff0000000000000 = 7ff8000000000000
|
|
+#1: xsmaddmdp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = fff0000000000000
|
|
+#2: xsmaddmdp c0d0650f5a07b353 fff0000000000000 8000000000000000 = 7ff0000000000000
|
|
+#3: xsmaddmdp 0123214569900000 fff0000000000000 0000000000000000 = fff0000000000000
|
|
+#4: xsmaddmdp c0d0650f5a07b353 fff0000000000000 0123214569900000 = 7ff0000000000000
|
|
+#5: xsmaddmdp 0123214569900000 fff0000000000000 7ff0000000000000 = 7ff8000000000000
|
|
+#6: xsmaddmdp c0d0650f5a07b353 fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#7: xsmaddmdp 0123214569900000 fff0000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#8: xsmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 fff0000000000000 = fff0000000000000
|
|
+#9: xsmaddmdp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = c0d0650f5a07b353
|
|
+#10: xsmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 8000000000000000 = 41b0cc9d05eec2a7
|
|
+#11: xsmaddmdp 0123214569900000 c0d0650f5a07b353 0000000000000000 = 82039a19ca8fcb5f
|
|
+#12: xsmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = 41b0cc9d05eec2a7
|
|
+#13: xsmaddmdp 0123214569900000 c0d0650f5a07b353 7ff0000000000000 = 7ff0000000000000
|
|
+#14: xsmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#15: xsmaddmdp 0123214569900000 c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
|
|
+#16: xsmaddmdp c0d0650f5a07b353 8000000000000000 fff0000000000000 = fff0000000000000
|
|
+#17: xsmaddmdp 0123214569900000 8000000000000000 c0d0650f5a07b353 = c0d0650f5a07b353
|
|
+#18: xsmaddmdp c0d0650f5a07b353 8000000000000000 8000000000000000 = 0000000000000000
|
|
+#19: xsmaddmdp 0123214569900000 8000000000000000 0000000000000000 = 0000000000000000
|
|
+#20: xsmaddmdp c0d0650f5a07b353 8000000000000000 0123214569900000 = 0123214569900000
|
|
+#21: xsmaddmdp 0123214569900000 8000000000000000 7ff0000000000000 = 7ff0000000000000
|
|
+#22: xsmaddmdp c0d0650f5a07b353 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#23: xsmaddmdp 0123214569900000 8000000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#24: xsmaddmdp c0d0650f5a07b353 0000000000000000 fff0000000000000 = fff0000000000000
|
|
+#25: xsmaddmdp 0123214569900000 0000000000000000 c0d0650f5a07b353 = c0d0650f5a07b353
|
|
+#26: xsmaddmdp c0d0650f5a07b353 0000000000000000 8000000000000000 = 8000000000000000
|
|
+#27: xsmaddmdp 0123214569900000 0000000000000000 0000000000000000 = 0000000000000000
|
|
+#28: xsmaddmdp c0d0650f5a07b353 0000000000000000 0123214569900000 = 0123214569900000
|
|
+#29: xsmaddmdp 0123214569900000 0000000000000000 7ff0000000000000 = 7ff0000000000000
|
|
+#30: xsmaddmdp c0d0650f5a07b353 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#31: xsmaddmdp 0123214569900000 0000000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#32: xsmaddmdp c0d0650f5a07b353 0123214569900000 fff0000000000000 = fff0000000000000
|
|
+#33: xsmaddmdp 0123214569900000 0123214569900000 c0d0650f5a07b353 = c0d0650f5a07b353
|
|
+#34: xsmaddmdp c0d0650f5a07b353 0123214569900000 8000000000000000 = 82039a19ca8fcb5f
|
|
+#35: xsmaddmdp 0123214569900000 0123214569900000 0000000000000000 = 0000000000000000
|
|
+#36: xsmaddmdp c0d0650f5a07b353 0123214569900000 404f000000000000 = 404f000000000000
|
|
+#37: xsmaddmdp 0123214569900000 0123214569900000 7ff0000000000000 = 7ff0000000000000
|
|
+#38: xsmaddmdp c0d0650f5a07b353 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#39: xsmaddmdp 0123214569900000 0123214569900000 7ff8000000000000 = 7ff8000000000000
|
|
+#40: xsmaddmdp c0d0650f5a07b353 7ff0000000000000 fff0000000000000 = fff0000000000000
|
|
+#41: xsmaddmdp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#42: xsmaddmdp c0d0650f5a07b353 7ff0000000000000 8000000000000000 = fff0000000000000
|
|
+#43: xsmaddmdp 0123214569900000 7ff0000000000000 0000000000000000 = 7ff0000000000000
|
|
+#44: xsmaddmdp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = fff0000000000000
|
|
+#45: xsmaddmdp 0123214569900000 7ff0000000000000 7ff0000000000000 = 7ff0000000000000
|
|
+#46: xsmaddmdp c0d0650f5a07b353 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#47: xsmaddmdp 0123214569900000 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#48: xsmaddmdp c0d0650f5a07b353 fff7ffffffffffff fff0000000000000 = ffffffffffffffff
|
|
+#49: xsmaddmdp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
|
|
+#50: xsmaddmdp c0d0650f5a07b353 fff7ffffffffffff 8000000000000000 = ffffffffffffffff
|
|
+#51: xsmaddmdp 0123214569900000 fff7ffffffffffff 0000000000000000 = ffffffffffffffff
|
|
+#52: xsmaddmdp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
|
|
+#53: xsmaddmdp 0123214569900000 fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
|
|
+#54: xsmaddmdp c0d0650f5a07b353 fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
|
|
+#55: xsmaddmdp 0123214569900000 fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
|
|
+#56: xsmaddmdp c0d0650f5a07b353 fff8000000000000 fff0000000000000 = fff8000000000000
|
|
+#57: xsmaddmdp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
|
|
+#58: xsmaddmdp c0d0650f5a07b353 fff8000000000000 8000000000000000 = fff8000000000000
|
|
+#59: xsmaddmdp 0123214569900000 fff8000000000000 0000000000000000 = fff8000000000000
|
|
+#60: xsmaddmdp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
|
|
+#61: xsmaddmdp 0123214569900000 fff8000000000000 7ff0000000000000 = fff8000000000000
|
|
+#62: xsmaddmdp c0d0650f5a07b353 fff8000000000000 7ff7ffffffffffff = fff8000000000000
|
|
+#63: xsmaddmdp 0123214569900000 fff8000000000000 7ff8000000000000 = fff8000000000000
|
|
+
|
|
+#0: xsmsubadp fff0000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#1: xsmsubadp c0d0650f5a07b353 fff0000000000000 0123214569900000 = fff0000000000000
|
|
+#2: xsmsubadp 8000000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#3: xsmsubadp 0000000000000000 fff0000000000000 0123214569900000 = fff0000000000000
|
|
+#4: xsmsubadp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#5: xsmsubadp 7ff0000000000000 fff0000000000000 0123214569900000 = fff0000000000000
|
|
+#6: xsmsubadp 7ff7ffffffffffff fff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
|
|
+#7: xsmsubadp 7ff8000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000
|
|
+#8: xsmsubadp fff0000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#9: xsmsubadp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = 40d0650f5a07b353
|
|
+#10: xsmsubadp 8000000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7
|
|
+#11: xsmsubadp 0000000000000000 c0d0650f5a07b353 0123214569900000 = 82039a19ca8fcb5f
|
|
+#12: xsmsubadp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7
|
|
+#13: xsmsubadp 7ff0000000000000 c0d0650f5a07b353 0123214569900000 = fff0000000000000
|
|
+#14: xsmsubadp 7ff7ffffffffffff c0d0650f5a07b353 c0d0650f5a07b353 = 7fffffffffffffff
|
|
+#15: xsmsubadp 7ff8000000000000 c0d0650f5a07b353 0123214569900000 = 7ff8000000000000
|
|
+#16: xsmsubadp fff0000000000000 8000000000000000 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#17: xsmsubadp c0d0650f5a07b353 8000000000000000 0123214569900000 = 40d0650f5a07b353
|
|
+#18: xsmsubadp 8000000000000000 8000000000000000 c0d0650f5a07b353 = 0000000000000000
|
|
+#19: xsmsubadp 0000000000000000 8000000000000000 0123214569900000 = 8000000000000000
|
|
+#20: xsmsubadp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 8123214569900000
|
|
+#21: xsmsubadp 7ff0000000000000 8000000000000000 0123214569900000 = fff0000000000000
|
|
+#22: xsmsubadp 7ff7ffffffffffff 8000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
|
|
+#23: xsmsubadp 7ff8000000000000 8000000000000000 0123214569900000 = 7ff8000000000000
|
|
+#24: xsmsubadp fff0000000000000 0000000000000000 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#25: xsmsubadp c0d0650f5a07b353 0000000000000000 0123214569900000 = 40d0650f5a07b353
|
|
+#26: xsmsubadp 8000000000000000 0000000000000000 c0d0650f5a07b353 = 0000000000000000
|
|
+#27: xsmsubadp 0000000000000000 0000000000000000 0123214569900000 = 0000000000000000
|
|
+#28: xsmsubadp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 8123214569900000
|
|
+#29: xsmsubadp 7ff0000000000000 0000000000000000 0123214569900000 = fff0000000000000
|
|
+#30: xsmsubadp 7ff7ffffffffffff 0000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
|
|
+#31: xsmsubadp 7ff8000000000000 0000000000000000 0123214569900000 = 7ff8000000000000
|
|
+#32: xsmsubadp fff0000000000000 0123214569900000 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#33: xsmsubadp c0d0650f5a07b353 0123214569900000 0123214569900000 = 40d0650f5a07b353
|
|
+#34: xsmsubadp 8000000000000000 0123214569900000 c0d0650f5a07b353 = 82039a19ca8fcb5f
|
|
+#35: xsmsubadp 0000000000000000 0123214569900000 0123214569900000 = 0000000000000000
|
|
+#36: xsmsubadp 404f000000000000 0123214569900000 c0d0650f5a07b353 = c04f000000000000
|
|
+#37: xsmsubadp 7ff0000000000000 0123214569900000 0123214569900000 = fff0000000000000
|
|
+#38: xsmsubadp 7ff7ffffffffffff 0123214569900000 c0d0650f5a07b353 = 7fffffffffffffff
|
|
+#39: xsmsubadp 7ff8000000000000 0123214569900000 0123214569900000 = 7ff8000000000000
|
|
+#40: xsmsubadp fff0000000000000 7ff0000000000000 c0d0650f5a07b353 = 7ff8000000000000
|
|
+#41: xsmsubadp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = 7ff0000000000000
|
|
+#42: xsmsubadp 8000000000000000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
|
|
+#43: xsmsubadp 0000000000000000 7ff0000000000000 0123214569900000 = 7ff0000000000000
|
|
+#44: xsmsubadp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
|
|
+#45: xsmsubadp 7ff0000000000000 7ff0000000000000 0123214569900000 = 7ff8000000000000
|
|
+#46: xsmsubadp 7ff7ffffffffffff 7ff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
|
|
+#47: xsmsubadp 7ff8000000000000 7ff0000000000000 0123214569900000 = 7ff8000000000000
|
|
+#48: xsmsubadp fff0000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
|
|
+#49: xsmsubadp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
|
|
+#50: xsmsubadp 8000000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
|
|
+#51: xsmsubadp 0000000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
|
|
+#52: xsmsubadp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
|
|
+#53: xsmsubadp 7ff0000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
|
|
+#54: xsmsubadp 7ff7ffffffffffff fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
|
|
+#55: xsmsubadp 7ff8000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
|
|
+#56: xsmsubadp fff0000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
|
|
+#57: xsmsubadp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
|
|
+#58: xsmsubadp 8000000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
|
|
+#59: xsmsubadp 0000000000000000 fff8000000000000 0123214569900000 = fff8000000000000
|
|
+#60: xsmsubadp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
|
|
+#61: xsmsubadp 7ff0000000000000 fff8000000000000 0123214569900000 = fff8000000000000
|
|
+#62: xsmsubadp 7ff7ffffffffffff fff8000000000000 c0d0650f5a07b353 = fff8000000000000
|
|
+#63: xsmsubadp 7ff8000000000000 fff8000000000000 0123214569900000 = fff8000000000000
|
|
+
|
|
+#0: xsmsubmdp c0d0650f5a07b353 fff0000000000000 fff0000000000000 = 7ff0000000000000
|
|
+#1: xsmsubmdp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = fff0000000000000
|
|
+#2: xsmsubmdp c0d0650f5a07b353 fff0000000000000 8000000000000000 = 7ff0000000000000
|
|
+#3: xsmsubmdp 0123214569900000 fff0000000000000 0000000000000000 = fff0000000000000
|
|
+#4: xsmsubmdp c0d0650f5a07b353 fff0000000000000 0123214569900000 = 7ff0000000000000
|
|
+#5: xsmsubmdp 0123214569900000 fff0000000000000 7ff0000000000000 = fff0000000000000
|
|
+#6: xsmsubmdp c0d0650f5a07b353 fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#7: xsmsubmdp 0123214569900000 fff0000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#8: xsmsubmdp c0d0650f5a07b353 c0d0650f5a07b353 fff0000000000000 = 7ff0000000000000
|
|
+#9: xsmsubmdp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = 40d0650f5a07b353
|
|
+#10: xsmsubmdp c0d0650f5a07b353 c0d0650f5a07b353 8000000000000000 = 41b0cc9d05eec2a7
|
|
+#11: xsmsubmdp 0123214569900000 c0d0650f5a07b353 0000000000000000 = 82039a19ca8fcb5f
|
|
+#12: xsmsubmdp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = 41b0cc9d05eec2a7
|
|
+#13: xsmsubmdp 0123214569900000 c0d0650f5a07b353 7ff0000000000000 = fff0000000000000
|
|
+#14: xsmsubmdp c0d0650f5a07b353 c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#15: xsmsubmdp 0123214569900000 c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
|
|
+#16: xsmsubmdp c0d0650f5a07b353 8000000000000000 fff0000000000000 = 7ff0000000000000
|
|
+#17: xsmsubmdp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
|
|
+#18: xsmsubmdp c0d0650f5a07b353 8000000000000000 8000000000000000 = 0000000000000000
|
|
+#19: xsmsubmdp 0123214569900000 8000000000000000 0000000000000000 = 8000000000000000
|
|
+#20: xsmsubmdp c0d0650f5a07b353 8000000000000000 0123214569900000 = 8123214569900000
|
|
+#21: xsmsubmdp 0123214569900000 8000000000000000 7ff0000000000000 = fff0000000000000
|
|
+#22: xsmsubmdp c0d0650f5a07b353 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#23: xsmsubmdp 0123214569900000 8000000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#24: xsmsubmdp c0d0650f5a07b353 0000000000000000 fff0000000000000 = 7ff0000000000000
|
|
+#25: xsmsubmdp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
|
|
+#26: xsmsubmdp c0d0650f5a07b353 0000000000000000 8000000000000000 = 0000000000000000
|
|
+#27: xsmsubmdp 0123214569900000 0000000000000000 0000000000000000 = 0000000000000000
|
|
+#28: xsmsubmdp c0d0650f5a07b353 0000000000000000 0123214569900000 = 8123214569900000
|
|
+#29: xsmsubmdp 0123214569900000 0000000000000000 7ff0000000000000 = fff0000000000000
|
|
+#30: xsmsubmdp c0d0650f5a07b353 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#31: xsmsubmdp 0123214569900000 0000000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#32: xsmsubmdp c0d0650f5a07b353 0123214569900000 fff0000000000000 = 7ff0000000000000
|
|
+#33: xsmsubmdp 0123214569900000 0123214569900000 c0d0650f5a07b353 = 40d0650f5a07b353
|
|
+#34: xsmsubmdp c0d0650f5a07b353 0123214569900000 8000000000000000 = 82039a19ca8fcb5f
|
|
+#35: xsmsubmdp 0123214569900000 0123214569900000 0000000000000000 = 0000000000000000
|
|
+#36: xsmsubmdp c0d0650f5a07b353 0123214569900000 404f000000000000 = c04f000000000000
|
|
+#37: xsmsubmdp 0123214569900000 0123214569900000 7ff0000000000000 = fff0000000000000
|
|
+#38: xsmsubmdp c0d0650f5a07b353 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#39: xsmsubmdp 0123214569900000 0123214569900000 7ff8000000000000 = 7ff8000000000000
|
|
+#40: xsmsubmdp c0d0650f5a07b353 7ff0000000000000 fff0000000000000 = 7ff8000000000000
|
|
+#41: xsmsubmdp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#42: xsmsubmdp c0d0650f5a07b353 7ff0000000000000 8000000000000000 = fff0000000000000
|
|
+#43: xsmsubmdp 0123214569900000 7ff0000000000000 0000000000000000 = 7ff0000000000000
|
|
+#44: xsmsubmdp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = fff0000000000000
|
|
+#45: xsmsubmdp 0123214569900000 7ff0000000000000 7ff0000000000000 = 7ff8000000000000
|
|
+#46: xsmsubmdp c0d0650f5a07b353 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#47: xsmsubmdp 0123214569900000 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#48: xsmsubmdp c0d0650f5a07b353 fff7ffffffffffff fff0000000000000 = ffffffffffffffff
|
|
+#49: xsmsubmdp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
|
|
+#50: xsmsubmdp c0d0650f5a07b353 fff7ffffffffffff 8000000000000000 = ffffffffffffffff
|
|
+#51: xsmsubmdp 0123214569900000 fff7ffffffffffff 0000000000000000 = ffffffffffffffff
|
|
+#52: xsmsubmdp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
|
|
+#53: xsmsubmdp 0123214569900000 fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
|
|
+#54: xsmsubmdp c0d0650f5a07b353 fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
|
|
+#55: xsmsubmdp 0123214569900000 fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
|
|
+#56: xsmsubmdp c0d0650f5a07b353 fff8000000000000 fff0000000000000 = fff8000000000000
|
|
+#57: xsmsubmdp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
|
|
+#58: xsmsubmdp c0d0650f5a07b353 fff8000000000000 8000000000000000 = fff8000000000000
|
|
+#59: xsmsubmdp 0123214569900000 fff8000000000000 0000000000000000 = fff8000000000000
|
|
+#60: xsmsubmdp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
|
|
+#61: xsmsubmdp 0123214569900000 fff8000000000000 7ff0000000000000 = fff8000000000000
|
|
+#62: xsmsubmdp c0d0650f5a07b353 fff8000000000000 7ff7ffffffffffff = fff8000000000000
|
|
+#63: xsmsubmdp 0123214569900000 fff8000000000000 7ff8000000000000 = fff8000000000000
|
|
+
|
|
+#0: xsnmaddadp fff0000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff8000000000000
|
|
+#1: xsnmaddadp c0d0650f5a07b353 fff0000000000000 0123214569900000 = 7ff0000000000000
|
|
+#2: xsnmaddadp 8000000000000000 fff0000000000000 c0d0650f5a07b353 = fff0000000000000
|
|
+#3: xsnmaddadp 0000000000000000 fff0000000000000 0123214569900000 = 7ff0000000000000
|
|
+#4: xsnmaddadp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = fff0000000000000
|
|
+#5: xsnmaddadp 7ff0000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000
|
|
+#6: xsnmaddadp 7ff7ffffffffffff fff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
|
|
+#7: xsnmaddadp 7ff8000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000
|
|
+#8: xsnmaddadp fff0000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#9: xsnmaddadp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = 40d0650f5a07b353
|
|
+#10: xsnmaddadp 8000000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = c1b0cc9d05eec2a7
|
|
+#11: xsnmaddadp 0000000000000000 c0d0650f5a07b353 0123214569900000 = 02039a19ca8fcb5f
|
|
+#12: xsnmaddadp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = c1b0cc9d05eec2a7
|
|
+#13: xsnmaddadp 7ff0000000000000 c0d0650f5a07b353 0123214569900000 = fff0000000000000
|
|
+#14: xsnmaddadp 7ff7ffffffffffff c0d0650f5a07b353 c0d0650f5a07b353 = 7fffffffffffffff
|
|
+#15: xsnmaddadp 7ff8000000000000 c0d0650f5a07b353 0123214569900000 = 7ff8000000000000
|
|
+#16: xsnmaddadp fff0000000000000 8000000000000000 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#17: xsnmaddadp c0d0650f5a07b353 8000000000000000 0123214569900000 = 40d0650f5a07b353
|
|
+#18: xsnmaddadp 8000000000000000 8000000000000000 c0d0650f5a07b353 = 8000000000000000
|
|
+#19: xsnmaddadp 0000000000000000 8000000000000000 0123214569900000 = 8000000000000000
|
|
+#20: xsnmaddadp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 8123214569900000
|
|
+#21: xsnmaddadp 7ff0000000000000 8000000000000000 0123214569900000 = fff0000000000000
|
|
+#22: xsnmaddadp 7ff7ffffffffffff 8000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
|
|
+#23: xsnmaddadp 7ff8000000000000 8000000000000000 0123214569900000 = 7ff8000000000000
|
|
+#24: xsnmaddadp fff0000000000000 0000000000000000 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#25: xsnmaddadp c0d0650f5a07b353 0000000000000000 0123214569900000 = 40d0650f5a07b353
|
|
+#26: xsnmaddadp 8000000000000000 0000000000000000 c0d0650f5a07b353 = 0000000000000000
|
|
+#27: xsnmaddadp 0000000000000000 0000000000000000 0123214569900000 = 8000000000000000
|
|
+#28: xsnmaddadp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 8123214569900000
|
|
+#29: xsnmaddadp 7ff0000000000000 0000000000000000 0123214569900000 = fff0000000000000
|
|
+#30: xsnmaddadp 7ff7ffffffffffff 0000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
|
|
+#31: xsnmaddadp 7ff8000000000000 0000000000000000 0123214569900000 = 7ff8000000000000
|
|
+#32: xsnmaddadp fff0000000000000 0123214569900000 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#33: xsnmaddadp c0d0650f5a07b353 0123214569900000 0123214569900000 = 40d0650f5a07b353
|
|
+#34: xsnmaddadp 8000000000000000 0123214569900000 c0d0650f5a07b353 = 02039a19ca8fcb5f
|
|
+#35: xsnmaddadp 0000000000000000 0123214569900000 0123214569900000 = 8000000000000000
|
|
+#36: xsnmaddadp 404f000000000000 0123214569900000 c0d0650f5a07b353 = c04f000000000000
|
|
+#37: xsnmaddadp 7ff0000000000000 0123214569900000 0123214569900000 = fff0000000000000
|
|
+#38: xsnmaddadp 7ff7ffffffffffff 0123214569900000 c0d0650f5a07b353 = 7fffffffffffffff
|
|
+#39: xsnmaddadp 7ff8000000000000 0123214569900000 0123214569900000 = 7ff8000000000000
|
|
+#40: xsnmaddadp fff0000000000000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#41: xsnmaddadp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = fff0000000000000
|
|
+#42: xsnmaddadp 8000000000000000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#43: xsnmaddadp 0000000000000000 7ff0000000000000 0123214569900000 = fff0000000000000
|
|
+#44: xsnmaddadp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#45: xsnmaddadp 7ff0000000000000 7ff0000000000000 0123214569900000 = fff0000000000000
|
|
+#46: xsnmaddadp 7ff7ffffffffffff 7ff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
|
|
+#47: xsnmaddadp 7ff8000000000000 7ff0000000000000 0123214569900000 = 7ff8000000000000
|
|
+#48: xsnmaddadp fff0000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
|
|
+#49: xsnmaddadp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
|
|
+#50: xsnmaddadp 8000000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
|
|
+#51: xsnmaddadp 0000000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
|
|
+#52: xsnmaddadp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
|
|
+#53: xsnmaddadp 7ff0000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
|
|
+#54: xsnmaddadp 7ff7ffffffffffff fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
|
|
+#55: xsnmaddadp 7ff8000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
|
|
+#56: xsnmaddadp fff0000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
|
|
+#57: xsnmaddadp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
|
|
+#58: xsnmaddadp 8000000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
|
|
+#59: xsnmaddadp 0000000000000000 fff8000000000000 0123214569900000 = fff8000000000000
|
|
+#60: xsnmaddadp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
|
|
+#61: xsnmaddadp 7ff0000000000000 fff8000000000000 0123214569900000 = fff8000000000000
|
|
+#62: xsnmaddadp 7ff7ffffffffffff fff8000000000000 c0d0650f5a07b353 = fff8000000000000
|
|
+#63: xsnmaddadp 7ff8000000000000 fff8000000000000 0123214569900000 = fff8000000000000
|
|
+
|
|
+#0: xsnmaddmdp c0d0650f5a07b353 fff0000000000000 fff0000000000000 = 7ff8000000000000
|
|
+#1: xsnmaddmdp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#2: xsnmaddmdp c0d0650f5a07b353 fff0000000000000 8000000000000000 = fff0000000000000
|
|
+#3: xsnmaddmdp 0123214569900000 fff0000000000000 0000000000000000 = 7ff0000000000000
|
|
+#4: xsnmaddmdp c0d0650f5a07b353 fff0000000000000 0123214569900000 = fff0000000000000
|
|
+#5: xsnmaddmdp 0123214569900000 fff0000000000000 7ff0000000000000 = 7ff8000000000000
|
|
+#6: xsnmaddmdp c0d0650f5a07b353 fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#7: xsnmaddmdp 0123214569900000 fff0000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#8: xsnmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 fff0000000000000 = 7ff0000000000000
|
|
+#9: xsnmaddmdp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = 40d0650f5a07b353
|
|
+#10: xsnmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 8000000000000000 = c1b0cc9d05eec2a7
|
|
+#11: xsnmaddmdp 0123214569900000 c0d0650f5a07b353 0000000000000000 = 02039a19ca8fcb5f
|
|
+#12: xsnmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = c1b0cc9d05eec2a7
|
|
+#13: xsnmaddmdp 0123214569900000 c0d0650f5a07b353 7ff0000000000000 = fff0000000000000
|
|
+#14: xsnmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#15: xsnmaddmdp 0123214569900000 c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
|
|
+#16: xsnmaddmdp c0d0650f5a07b353 8000000000000000 fff0000000000000 = 7ff0000000000000
|
|
+#17: xsnmaddmdp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
|
|
+#18: xsnmaddmdp c0d0650f5a07b353 8000000000000000 8000000000000000 = 8000000000000000
|
|
+#19: xsnmaddmdp 0123214569900000 8000000000000000 0000000000000000 = 8000000000000000
|
|
+#20: xsnmaddmdp c0d0650f5a07b353 8000000000000000 0123214569900000 = 8123214569900000
|
|
+#21: xsnmaddmdp 0123214569900000 8000000000000000 7ff0000000000000 = fff0000000000000
|
|
+#22: xsnmaddmdp c0d0650f5a07b353 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#23: xsnmaddmdp 0123214569900000 8000000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#24: xsnmaddmdp c0d0650f5a07b353 0000000000000000 fff0000000000000 = 7ff0000000000000
|
|
+#25: xsnmaddmdp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
|
|
+#26: xsnmaddmdp c0d0650f5a07b353 0000000000000000 8000000000000000 = 0000000000000000
|
|
+#27: xsnmaddmdp 0123214569900000 0000000000000000 0000000000000000 = 8000000000000000
|
|
+#28: xsnmaddmdp c0d0650f5a07b353 0000000000000000 0123214569900000 = 8123214569900000
|
|
+#29: xsnmaddmdp 0123214569900000 0000000000000000 7ff0000000000000 = fff0000000000000
|
|
+#30: xsnmaddmdp c0d0650f5a07b353 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#31: xsnmaddmdp 0123214569900000 0000000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#32: xsnmaddmdp c0d0650f5a07b353 0123214569900000 fff0000000000000 = 7ff0000000000000
|
|
+#33: xsnmaddmdp 0123214569900000 0123214569900000 c0d0650f5a07b353 = 40d0650f5a07b353
|
|
+#34: xsnmaddmdp c0d0650f5a07b353 0123214569900000 8000000000000000 = 02039a19ca8fcb5f
|
|
+#35: xsnmaddmdp 0123214569900000 0123214569900000 0000000000000000 = 8000000000000000
|
|
+#36: xsnmaddmdp c0d0650f5a07b353 0123214569900000 404f000000000000 = c04f000000000000
|
|
+#37: xsnmaddmdp 0123214569900000 0123214569900000 7ff0000000000000 = fff0000000000000
|
|
+#38: xsnmaddmdp c0d0650f5a07b353 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#39: xsnmaddmdp 0123214569900000 0123214569900000 7ff8000000000000 = 7ff8000000000000
|
|
+#40: xsnmaddmdp c0d0650f5a07b353 7ff0000000000000 fff0000000000000 = 7ff0000000000000
|
|
+#41: xsnmaddmdp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
|
|
+#42: xsnmaddmdp c0d0650f5a07b353 7ff0000000000000 8000000000000000 = 7ff0000000000000
|
|
+#43: xsnmaddmdp 0123214569900000 7ff0000000000000 0000000000000000 = fff0000000000000
|
|
+#44: xsnmaddmdp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = 7ff0000000000000
|
|
+#45: xsnmaddmdp 0123214569900000 7ff0000000000000 7ff0000000000000 = fff0000000000000
|
|
+#46: xsnmaddmdp c0d0650f5a07b353 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#47: xsnmaddmdp 0123214569900000 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#48: xsnmaddmdp c0d0650f5a07b353 fff7ffffffffffff fff0000000000000 = ffffffffffffffff
|
|
+#49: xsnmaddmdp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
|
|
+#50: xsnmaddmdp c0d0650f5a07b353 fff7ffffffffffff 8000000000000000 = ffffffffffffffff
|
|
+#51: xsnmaddmdp 0123214569900000 fff7ffffffffffff 0000000000000000 = ffffffffffffffff
|
|
+#52: xsnmaddmdp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
|
|
+#53: xsnmaddmdp 0123214569900000 fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
|
|
+#54: xsnmaddmdp c0d0650f5a07b353 fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
|
|
+#55: xsnmaddmdp 0123214569900000 fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
|
|
+#56: xsnmaddmdp c0d0650f5a07b353 fff8000000000000 fff0000000000000 = fff8000000000000
|
|
+#57: xsnmaddmdp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
|
|
+#58: xsnmaddmdp c0d0650f5a07b353 fff8000000000000 8000000000000000 = fff8000000000000
|
|
+#59: xsnmaddmdp 0123214569900000 fff8000000000000 0000000000000000 = fff8000000000000
|
|
+#60: xsnmaddmdp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
|
|
+#61: xsnmaddmdp 0123214569900000 fff8000000000000 7ff0000000000000 = fff8000000000000
|
|
+#62: xsnmaddmdp c0d0650f5a07b353 fff8000000000000 7ff7ffffffffffff = fff8000000000000
|
|
+#63: xsnmaddmdp 0123214569900000 fff8000000000000 7ff8000000000000 = fff8000000000000
|
|
+
|
|
+#0: xsmuldp fff0000000000000 fff0000000000000 = 7ff0000000000000
|
|
+#1: xsmuldp fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#2: xsmuldp fff0000000000000 8000000000000000 = 7ff8000000000000
|
|
+#3: xsmuldp fff0000000000000 0000000000000000 = 7ff8000000000000
|
|
+#4: xsmuldp fff0000000000000 0123214569900000 = fff0000000000000
|
|
+#5: xsmuldp fff0000000000000 7ff0000000000000 = fff0000000000000
|
|
+#6: xsmuldp fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#7: xsmuldp fff0000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#8: xsmuldp c0d0650f5a07b353 fff0000000000000 = 7ff0000000000000
|
|
+#9: xsmuldp c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7
|
|
+#10: xsmuldp c0d0650f5a07b353 8000000000000000 = 0000000000000000
|
|
+#11: xsmuldp c0d0650f5a07b353 0000000000000000 = 8000000000000000
|
|
+#12: xsmuldp c0d0650f5a07b353 0123214569900000 = 82039a19ca8fcb5f
|
|
+#13: xsmuldp c0d0650f5a07b353 7ff0000000000000 = fff0000000000000
|
|
+#14: xsmuldp c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#15: xsmuldp c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
|
|
+#16: xsmuldp 8000000000000000 fff0000000000000 = 7ff8000000000000
|
|
+#17: xsmuldp 8000000000000000 c0d0650f5a07b353 = 0000000000000000
|
|
+#18: xsmuldp 8000000000000000 8000000000000000 = 0000000000000000
|
|
+#19: xsmuldp 8000000000000000 0000000000000000 = 8000000000000000
|
|
+#20: xsmuldp 8000000000000000 0123214569900000 = 8000000000000000
|
|
+#21: xsmuldp 8000000000000000 7ff0000000000000 = 7ff8000000000000
|
|
+#22: xsmuldp 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#23: xsmuldp 8000000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#24: xsmuldp 0000000000000000 fff0000000000000 = 7ff8000000000000
|
|
+#25: xsmuldp 0000000000000000 c0d0650f5a07b353 = 8000000000000000
|
|
+#26: xsmuldp 0000000000000000 8000000000000000 = 8000000000000000
|
|
+#27: xsmuldp 0000000000000000 0000000000000000 = 0000000000000000
|
|
+#28: xsmuldp 0000000000000000 0123214569900000 = 0000000000000000
|
|
+#29: xsmuldp 0000000000000000 7ff0000000000000 = 7ff8000000000000
|
|
+#30: xsmuldp 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#31: xsmuldp 0000000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#32: xsmuldp 0123214569900000 fff0000000000000 = fff0000000000000
|
|
+#33: xsmuldp 0123214569900000 c0d0650f5a07b353 = 82039a19ca8fcb5f
|
|
+#34: xsmuldp 0123214569900000 8000000000000000 = 8000000000000000
|
|
+#35: xsmuldp 0123214569900000 0000000000000000 = 0000000000000000
|
|
+#36: xsmuldp 0123214569900000 404f000000000000 = 0182883b3e438000
|
|
+#37: xsmuldp 0123214569900000 7ff0000000000000 = 7ff0000000000000
|
|
+#38: xsmuldp 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#39: xsmuldp 0123214569900000 7ff8000000000000 = 7ff8000000000000
|
|
+#40: xsmuldp 7ff0000000000000 fff0000000000000 = fff0000000000000
|
|
+#41: xsmuldp 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
|
|
+#42: xsmuldp 7ff0000000000000 8000000000000000 = 7ff8000000000000
|
|
+#43: xsmuldp 7ff0000000000000 0000000000000000 = 7ff8000000000000
|
|
+#44: xsmuldp 7ff0000000000000 0123214569900000 = 7ff0000000000000
|
|
+#45: xsmuldp 7ff0000000000000 7ff0000000000000 = 7ff0000000000000
|
|
+#46: xsmuldp 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#47: xsmuldp 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#48: xsmuldp fff7ffffffffffff fff0000000000000 = ffffffffffffffff
|
|
+#49: xsmuldp fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
|
|
+#50: xsmuldp fff7ffffffffffff 8000000000000000 = ffffffffffffffff
|
|
+#51: xsmuldp fff7ffffffffffff 0000000000000000 = ffffffffffffffff
|
|
+#52: xsmuldp fff7ffffffffffff 0123214569900000 = ffffffffffffffff
|
|
+#53: xsmuldp fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
|
|
+#54: xsmuldp fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
|
|
+#55: xsmuldp fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
|
|
+#56: xsmuldp fff8000000000000 fff0000000000000 = fff8000000000000
|
|
+#57: xsmuldp fff8000000000000 c0d0650f5a07b353 = fff8000000000000
|
|
+#58: xsmuldp fff8000000000000 8000000000000000 = fff8000000000000
|
|
+#59: xsmuldp fff8000000000000 0000000000000000 = fff8000000000000
|
|
+#60: xsmuldp fff8000000000000 0123214569900000 = fff8000000000000
|
|
+#61: xsmuldp fff8000000000000 7ff0000000000000 = fff8000000000000
|
|
+#62: xsmuldp fff8000000000000 7ff7ffffffffffff = fff8000000000000
|
|
+#63: xsmuldp fff8000000000000 7ff8000000000000 = fff8000000000000
|
|
+
|
|
+#0: xssubdp fff0000000000000 fff0000000000000 = 7ff8000000000000
|
|
+#1: xssubdp fff0000000000000 c0d0650f5a07b353 = fff0000000000000
|
|
+#2: xssubdp fff0000000000000 8000000000000000 = fff0000000000000
|
|
+#3: xssubdp fff0000000000000 0000000000000000 = fff0000000000000
|
|
+#4: xssubdp fff0000000000000 0123214569900000 = fff0000000000000
|
|
+#5: xssubdp fff0000000000000 7ff0000000000000 = fff0000000000000
|
|
+#6: xssubdp fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#7: xssubdp fff0000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#8: xssubdp c0d0650f5a07b353 fff0000000000000 = 7ff0000000000000
|
|
+#9: xssubdp c0d0650f5a07b353 c0d0650f5a07b353 = 0000000000000000
|
|
+#10: xssubdp c0d0650f5a07b353 8000000000000000 = c0d0650f5a07b353
|
|
+#11: xssubdp c0d0650f5a07b353 0000000000000000 = c0d0650f5a07b353
|
|
+#12: xssubdp c0d0650f5a07b353 0123214569900000 = c0d0650f5a07b353
|
|
+#13: xssubdp c0d0650f5a07b353 7ff0000000000000 = fff0000000000000
|
|
+#14: xssubdp c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#15: xssubdp c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
|
|
+#16: xssubdp 8000000000000000 fff0000000000000 = 7ff0000000000000
|
|
+#17: xssubdp 8000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
|
|
+#18: xssubdp 8000000000000000 8000000000000000 = 0000000000000000
|
|
+#19: xssubdp 8000000000000000 0000000000000000 = 8000000000000000
|
|
+#20: xssubdp 8000000000000000 0123214569900000 = 8123214569900000
|
|
+#21: xssubdp 8000000000000000 7ff0000000000000 = fff0000000000000
|
|
+#22: xssubdp 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#23: xssubdp 8000000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#24: xssubdp 0000000000000000 fff0000000000000 = 7ff0000000000000
|
|
+#25: xssubdp 0000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
|
|
+#26: xssubdp 0000000000000000 8000000000000000 = 0000000000000000
|
|
+#27: xssubdp 0000000000000000 0000000000000000 = 0000000000000000
|
|
+#28: xssubdp 0000000000000000 0123214569900000 = 8123214569900000
|
|
+#29: xssubdp 0000000000000000 7ff0000000000000 = fff0000000000000
|
|
+#30: xssubdp 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#31: xssubdp 0000000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#32: xssubdp 0123214569900000 fff0000000000000 = 7ff0000000000000
|
|
+#33: xssubdp 0123214569900000 c0d0650f5a07b353 = 40d0650f5a07b353
|
|
+#34: xssubdp 0123214569900000 8000000000000000 = 0123214569900000
|
|
+#35: xssubdp 0123214569900000 0000000000000000 = 0123214569900000
|
|
+#36: xssubdp 0123214569900000 404f000000000000 = c04f000000000000
|
|
+#37: xssubdp 0123214569900000 7ff0000000000000 = fff0000000000000
|
|
+#38: xssubdp 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#39: xssubdp 0123214569900000 7ff8000000000000 = 7ff8000000000000
|
|
+#40: xssubdp 7ff0000000000000 fff0000000000000 = 7ff0000000000000
|
|
+#41: xssubdp 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
|
|
+#42: xssubdp 7ff0000000000000 8000000000000000 = 7ff0000000000000
|
|
+#43: xssubdp 7ff0000000000000 0000000000000000 = 7ff0000000000000
|
|
+#44: xssubdp 7ff0000000000000 0123214569900000 = 7ff0000000000000
|
|
+#45: xssubdp 7ff0000000000000 7ff0000000000000 = 7ff8000000000000
|
|
+#46: xssubdp 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
|
|
+#47: xssubdp 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
|
|
+#48: xssubdp fff7ffffffffffff fff0000000000000 = ffffffffffffffff
|
|
+#49: xssubdp fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
|
|
+#50: xssubdp fff7ffffffffffff 8000000000000000 = ffffffffffffffff
|
|
+#51: xssubdp fff7ffffffffffff 0000000000000000 = ffffffffffffffff
|
|
+#52: xssubdp fff7ffffffffffff 0123214569900000 = ffffffffffffffff
|
|
+#53: xssubdp fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
|
|
+#54: xssubdp fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
|
|
+#55: xssubdp fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
|
|
+#56: xssubdp fff8000000000000 fff0000000000000 = fff8000000000000
|
|
+#57: xssubdp fff8000000000000 c0d0650f5a07b353 = fff8000000000000
|
|
+#58: xssubdp fff8000000000000 8000000000000000 = fff8000000000000
|
|
+#59: xssubdp fff8000000000000 0000000000000000 = fff8000000000000
|
|
+#60: xssubdp fff8000000000000 0123214569900000 = fff8000000000000
|
|
+#61: xssubdp fff8000000000000 7ff0000000000000 = fff8000000000000
|
|
+#62: xssubdp fff8000000000000 7ff7ffffffffffff = fff8000000000000
|
|
+#63: xssubdp fff8000000000000 7ff8000000000000 = fff8000000000000
|
|
+
|
|
+
|
|
+Test VSX scalar integer conversion instructions
|
|
+#0: xscvdpsxds 3fd8000000000000 => 0000000000000000
|
|
+#1: xscvdpsxds 404f000000000000 => 000000000000003e
|
|
+#2: xscvdpsxds 0018000000b77501 => 0000000000000000
|
|
+#3: xscvdpsxds 7fe800000000051b => 7fffffffffffffff
|
|
+#4: xscvdpsxds 0123214569900000 => 0000000000000000
|
|
+#5: xscvdpsxds 0000000000000000 => 0000000000000000
|
|
+#6: xscvdpsxds 8000000000000000 => 0000000000000000
|
|
+#7: xscvdpsxds 7ff0000000000000 => 7fffffffffffffff
|
|
+#8: xscvdpsxds fff0000000000000 => 8000000000000000
|
|
+#9: xscvdpsxds 7ff7ffffffffffff => 8000000000000000
|
|
+#10: xscvdpsxds fff7ffffffffffff => 8000000000000000
|
|
+#11: xscvdpsxds 7ff8000000000000 => 8000000000000000
|
|
+#12: xscvdpsxds fff8000000000000 => 8000000000000000
|
|
+#13: xscvdpsxds 8008340000078000 => 0000000000000000
|
|
+#14: xscvdpsxds c0d0650f5a07b353 => ffffffffffffbe6c
|
|
+
|
|
+#0: xscvsxddp 3fd8000000000000 => 43cfec0000000000
|
|
+#1: xscvsxddp 404f000000000000 => 43d013c000000000
|
|
+#2: xscvsxddp 0018000000b77501 => 4338000000b77501
|
|
+#3: xscvsxddp 7fe800000000051b => 43dffa0000000001
|
|
+#4: xscvsxddp 0123214569900000 => 4372321456990000
|
|
+#5: xscvsxddp 0000000000000000 => 0000000000000000
|
|
+#6: xscvsxddp 8000000000000000 => c3e0000000000000
|
|
+#7: xscvsxddp 7ff0000000000000 => 43dffc0000000000
|
|
+#8: xscvsxddp fff0000000000000 => c330000000000000
|
|
+#9: xscvsxddp 7ff7ffffffffffff => 43dffe0000000000
|
|
+#10: xscvsxddp fff7ffffffffffff => c320000000000002
|
|
+#11: xscvsxddp 7ff8000000000000 => 43dffe0000000000
|
|
+#12: xscvsxddp fff8000000000000 => c320000000000000
|
|
+#13: xscvsxddp 8008340000078000 => c3dffdf2fffffe20
|
|
+#14: xscvsxddp c0d0650f5a07b353 => c3cf97cd7852fc26
|
|
+
|
|
+#0: xscvuxddp 3fd8000000000000 => 43cfec0000000000
|
|
+#1: xscvuxddp 404f000000000000 => 43d013c000000000
|
|
+#2: xscvuxddp 0018000000b77501 => 4338000000b77501
|
|
+#3: xscvuxddp 7fe800000000051b => 43dffa0000000001
|
|
+#4: xscvuxddp 0123214569900000 => 4372321456990000
|
|
+#5: xscvuxddp 0000000000000000 => 0000000000000000
|
|
+#6: xscvuxddp 8000000000000000 => 43e0000000000000
|
|
+#7: xscvuxddp 7ff0000000000000 => 43dffc0000000000
|
|
+#8: xscvuxddp fff0000000000000 => 43effe0000000000
|
|
+#9: xscvuxddp 7ff7ffffffffffff => 43dffe0000000000
|
|
+#10: xscvuxddp fff7ffffffffffff => 43efff0000000000
|
|
+#11: xscvuxddp 7ff8000000000000 => 43dffe0000000000
|
|
+#12: xscvuxddp fff8000000000000 => 43efff0000000000
|
|
+#13: xscvuxddp 8008340000078000 => 43e00106800000f0
|
|
+#14: xscvuxddp c0d0650f5a07b353 => 43e81a0ca1eb40f6
|
|
+
|
|
+
|
|
Index: none/tests/ppc64/jm-fp.stdout.exp
|
|
===================================================================
|
|
--- none/tests/ppc64/jm-fp.stdout.exp.orig
|
|
+++ none/tests/ppc64/jm-fp.stdout.exp
|
|
@@ -692,11 +692,11 @@ PPC floating point compare insns (two ar
|
|
PPC floating point arith insns with one arg:
|
|
fres 0010000000000001 => 7ff0000000000000
|
|
fres 00100094e0000359 => 7ff0000000000000
|
|
- fres 3fe0000000000001 => 4000000000000000
|
|
+ fres 3fe0000000000001 => 3ffff00000000000
|
|
fres 3fe00094e0000359 => 3ffff00000000000
|
|
fres 8010000000000001 => fff0000000000000
|
|
fres 80100094e0000359 => fff0000000000000
|
|
- fres bfe0000000000001 => c000000000000000
|
|
+ fres bfe0000000000001 => bffff00000000000
|
|
fres bfe00094e0000359 => bffff00000000000
|
|
fres 0000000000000000 => 7ff0000000000000
|
|
fres 8000000000000000 => fff0000000000000
|
|
@@ -915,11 +915,11 @@ PPC floating point arith insns
|
|
with one arg with flags update:
|
|
fres. 0010000000000001 => 7ff0000000000000
|
|
fres. 00100094e0000359 => 7ff0000000000000
|
|
- fres. 3fe0000000000001 => 4000000000000000
|
|
+ fres. 3fe0000000000001 => 3ffff00000000000
|
|
fres. 3fe00094e0000359 => 3ffff00000000000
|
|
fres. 8010000000000001 => fff0000000000000
|
|
fres. 80100094e0000359 => fff0000000000000
|
|
- fres. bfe0000000000001 => c000000000000000
|
|
+ fres. bfe0000000000001 => bffff00000000000
|
|
fres. bfe00094e0000359 => bffff00000000000
|
|
fres. 0000000000000000 => 7ff0000000000000
|
|
fres. 8000000000000000 => fff0000000000000
|
|
@@ -1122,21 +1122,21 @@ PPC floating point status register manip
|
|
with flags update:
|
|
PPC float load insns
|
|
with one register + one 16 bits immediate args with flags update:
|
|
- lfs 0010000000000001, -120 => 37e0000000000000, 0
|
|
- lfs 00100094e0000359, -112 => 37e0009400000000, 0
|
|
- lfs 3fe0000000000001, -104 => 3ffc000000000000, 0
|
|
- lfs 3fe00094e0000359, -96 => 3ffc001280000000, 0
|
|
- lfs 8010000000000001, -88 => b7e0000000000000, 0
|
|
- lfs 80100094e0000359, -80 => b7e0009400000000, 0
|
|
- lfs bfe0000000000001, -72 => bffc000000000000, 0
|
|
- lfs bfe00094e0000359, -64 => bffc001280000000, 0
|
|
- lfs 0000000000000000, -56 => 0000000000000000, 0
|
|
- lfs 8000000000000000, -48 => 8000000000000000, 0
|
|
- lfs 7ff0000000000000, -40 => 7ffe000000000000, 0
|
|
- lfs fff0000000000000, -32 => fffe000000000000, 0
|
|
- lfs 7ff7ffffffffffff, -24 => 7ffeffffe0000000, 0
|
|
- lfs fff7ffffffffffff, -16 => fffeffffe0000000, 0
|
|
- lfs 7ff8000000000000, -8 => 7fff000000000000, 0
|
|
+ lfs 0010000000000001, 65416 => 37e0000000000000, 0
|
|
+ lfs 00100094e0000359, 65424 => 37e0009400000000, 0
|
|
+ lfs 3fe0000000000001, 65432 => 3ffc000000000000, 0
|
|
+ lfs 3fe00094e0000359, 65440 => 3ffc001280000000, 0
|
|
+ lfs 8010000000000001, 65448 => b7e0000000000000, 0
|
|
+ lfs 80100094e0000359, 65456 => b7e0009400000000, 0
|
|
+ lfs bfe0000000000001, 65464 => bffc000000000000, 0
|
|
+ lfs bfe00094e0000359, 65472 => bffc001280000000, 0
|
|
+ lfs 0000000000000000, 65480 => 0000000000000000, 0
|
|
+ lfs 8000000000000000, 65488 => 8000000000000000, 0
|
|
+ lfs 7ff0000000000000, 65496 => 7ffe000000000000, 0
|
|
+ lfs fff0000000000000, 65504 => fffe000000000000, 0
|
|
+ lfs 7ff7ffffffffffff, 65512 => 7ffeffffe0000000, 0
|
|
+ lfs fff7ffffffffffff, 65520 => fffeffffe0000000, 0
|
|
+ lfs 7ff8000000000000, 65528 => 7fff000000000000, 0
|
|
lfs 0010000000000001, 0 => 37e0000000000000, 0
|
|
lfs 00100094e0000359, 8 => 37e0009400000000, 0
|
|
lfs 3fe0000000000001, 16 => 3ffc000000000000, 0
|
|
@@ -1154,21 +1154,21 @@ PPC float load insns
|
|
lfs 7ff8000000000000, 112 => 7fff000000000000, 0
|
|
lfs fff8000000000000, 120 => ffff000000000000, 0
|
|
|
|
- lfsu 0010000000000001, -120 => 37e0000000000000, -120
|
|
- lfsu 00100094e0000359, -112 => 37e0009400000000, -112
|
|
- lfsu 3fe0000000000001, -104 => 3ffc000000000000, -104
|
|
- lfsu 3fe00094e0000359, -96 => 3ffc001280000000, -96
|
|
- lfsu 8010000000000001, -88 => b7e0000000000000, -88
|
|
- lfsu 80100094e0000359, -80 => b7e0009400000000, -80
|
|
- lfsu bfe0000000000001, -72 => bffc000000000000, -72
|
|
- lfsu bfe00094e0000359, -64 => bffc001280000000, -64
|
|
- lfsu 0000000000000000, -56 => 0000000000000000, -56
|
|
- lfsu 8000000000000000, -48 => 8000000000000000, -48
|
|
- lfsu 7ff0000000000000, -40 => 7ffe000000000000, -40
|
|
- lfsu fff0000000000000, -32 => fffe000000000000, -32
|
|
- lfsu 7ff7ffffffffffff, -24 => 7ffeffffe0000000, -24
|
|
- lfsu fff7ffffffffffff, -16 => fffeffffe0000000, -16
|
|
- lfsu 7ff8000000000000, -8 => 7fff000000000000, -8
|
|
+ lfsu 0010000000000001, 65416 => 37e0000000000000, -120
|
|
+ lfsu 00100094e0000359, 65424 => 37e0009400000000, -112
|
|
+ lfsu 3fe0000000000001, 65432 => 3ffc000000000000, -104
|
|
+ lfsu 3fe00094e0000359, 65440 => 3ffc001280000000, -96
|
|
+ lfsu 8010000000000001, 65448 => b7e0000000000000, -88
|
|
+ lfsu 80100094e0000359, 65456 => b7e0009400000000, -80
|
|
+ lfsu bfe0000000000001, 65464 => bffc000000000000, -72
|
|
+ lfsu bfe00094e0000359, 65472 => bffc001280000000, -64
|
|
+ lfsu 0000000000000000, 65480 => 0000000000000000, -56
|
|
+ lfsu 8000000000000000, 65488 => 8000000000000000, -48
|
|
+ lfsu 7ff0000000000000, 65496 => 7ffe000000000000, -40
|
|
+ lfsu fff0000000000000, 65504 => fffe000000000000, -32
|
|
+ lfsu 7ff7ffffffffffff, 65512 => 7ffeffffe0000000, -24
|
|
+ lfsu fff7ffffffffffff, 65520 => fffeffffe0000000, -16
|
|
+ lfsu 7ff8000000000000, 65528 => 7fff000000000000, -8
|
|
lfsu 0010000000000001, 0 => 37e0000000000000, 0
|
|
lfsu 00100094e0000359, 8 => 37e0009400000000, 8
|
|
lfsu 3fe0000000000001, 16 => 3ffc000000000000, 16
|
|
@@ -1186,21 +1186,21 @@ PPC float load insns
|
|
lfsu 7ff8000000000000, 112 => 7fff000000000000, 112
|
|
lfsu fff8000000000000, 120 => ffff000000000000, 120
|
|
|
|
- lfd 0010000000000001, -120 => 0010000000000001, 0
|
|
- lfd 00100094e0000359, -112 => 00100094e0000359, 0
|
|
- lfd 3fe0000000000001, -104 => 3fe0000000000001, 0
|
|
- lfd 3fe00094e0000359, -96 => 3fe00094e0000359, 0
|
|
- lfd 8010000000000001, -88 => 8010000000000001, 0
|
|
- lfd 80100094e0000359, -80 => 80100094e0000359, 0
|
|
- lfd bfe0000000000001, -72 => bfe0000000000001, 0
|
|
- lfd bfe00094e0000359, -64 => bfe00094e0000359, 0
|
|
- lfd 0000000000000000, -56 => 0000000000000000, 0
|
|
- lfd 8000000000000000, -48 => 8000000000000000, 0
|
|
- lfd 7ff0000000000000, -40 => 7ff0000000000000, 0
|
|
- lfd fff0000000000000, -32 => fff0000000000000, 0
|
|
- lfd 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0
|
|
- lfd fff7ffffffffffff, -16 => fff7ffffffffffff, 0
|
|
- lfd 7ff8000000000000, -8 => 7ff8000000000000, 0
|
|
+ lfd 0010000000000001, 65416 => 0010000000000001, 0
|
|
+ lfd 00100094e0000359, 65424 => 00100094e0000359, 0
|
|
+ lfd 3fe0000000000001, 65432 => 3fe0000000000001, 0
|
|
+ lfd 3fe00094e0000359, 65440 => 3fe00094e0000359, 0
|
|
+ lfd 8010000000000001, 65448 => 8010000000000001, 0
|
|
+ lfd 80100094e0000359, 65456 => 80100094e0000359, 0
|
|
+ lfd bfe0000000000001, 65464 => bfe0000000000001, 0
|
|
+ lfd bfe00094e0000359, 65472 => bfe00094e0000359, 0
|
|
+ lfd 0000000000000000, 65480 => 0000000000000000, 0
|
|
+ lfd 8000000000000000, 65488 => 8000000000000000, 0
|
|
+ lfd 7ff0000000000000, 65496 => 7ff0000000000000, 0
|
|
+ lfd fff0000000000000, 65504 => fff0000000000000, 0
|
|
+ lfd 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, 0
|
|
+ lfd fff7ffffffffffff, 65520 => fff7ffffffffffff, 0
|
|
+ lfd 7ff8000000000000, 65528 => 7ff8000000000000, 0
|
|
lfd 0010000000000001, 0 => 0010000000000001, 0
|
|
lfd 00100094e0000359, 8 => 00100094e0000359, 0
|
|
lfd 3fe0000000000001, 16 => 3fe0000000000001, 0
|
|
@@ -1218,21 +1218,21 @@ PPC float load insns
|
|
lfd 7ff8000000000000, 112 => 7ff8000000000000, 0
|
|
lfd fff8000000000000, 120 => fff8000000000000, 0
|
|
|
|
- lfdu 0010000000000001, -120 => 0010000000000001, -120
|
|
- lfdu 00100094e0000359, -112 => 00100094e0000359, -112
|
|
- lfdu 3fe0000000000001, -104 => 3fe0000000000001, -104
|
|
- lfdu 3fe00094e0000359, -96 => 3fe00094e0000359, -96
|
|
- lfdu 8010000000000001, -88 => 8010000000000001, -88
|
|
- lfdu 80100094e0000359, -80 => 80100094e0000359, -80
|
|
- lfdu bfe0000000000001, -72 => bfe0000000000001, -72
|
|
- lfdu bfe00094e0000359, -64 => bfe00094e0000359, -64
|
|
- lfdu 0000000000000000, -56 => 0000000000000000, -56
|
|
- lfdu 8000000000000000, -48 => 8000000000000000, -48
|
|
- lfdu 7ff0000000000000, -40 => 7ff0000000000000, -40
|
|
- lfdu fff0000000000000, -32 => fff0000000000000, -32
|
|
- lfdu 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24
|
|
- lfdu fff7ffffffffffff, -16 => fff7ffffffffffff, -16
|
|
- lfdu 7ff8000000000000, -8 => 7ff8000000000000, -8
|
|
+ lfdu 0010000000000001, 65416 => 0010000000000001, -120
|
|
+ lfdu 00100094e0000359, 65424 => 00100094e0000359, -112
|
|
+ lfdu 3fe0000000000001, 65432 => 3fe0000000000001, -104
|
|
+ lfdu 3fe00094e0000359, 65440 => 3fe00094e0000359, -96
|
|
+ lfdu 8010000000000001, 65448 => 8010000000000001, -88
|
|
+ lfdu 80100094e0000359, 65456 => 80100094e0000359, -80
|
|
+ lfdu bfe0000000000001, 65464 => bfe0000000000001, -72
|
|
+ lfdu bfe00094e0000359, 65472 => bfe00094e0000359, -64
|
|
+ lfdu 0000000000000000, 65480 => 0000000000000000, -56
|
|
+ lfdu 8000000000000000, 65488 => 8000000000000000, -48
|
|
+ lfdu 7ff0000000000000, 65496 => 7ff0000000000000, -40
|
|
+ lfdu fff0000000000000, 65504 => fff0000000000000, -32
|
|
+ lfdu 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, -24
|
|
+ lfdu fff7ffffffffffff, 65520 => fff7ffffffffffff, -16
|
|
+ lfdu 7ff8000000000000, 65528 => 7ff8000000000000, -8
|
|
lfdu 0010000000000001, 0 => 0010000000000001, 0
|
|
lfdu 00100094e0000359, 8 => 00100094e0000359, 8
|
|
lfdu 3fe0000000000001, 16 => 3fe0000000000001, 16
|
|
Index: none/tests/ppc64/test_isa_2_07_part2.c
|
|
===================================================================
|
|
--- none/tests/ppc64/test_isa_2_07_part2.c.orig
|
|
+++ none/tests/ppc64/test_isa_2_07_part2.c
|
|
@@ -40,6 +40,12 @@ typedef uint32_t HWord_t;
|
|
typedef uint64_t HWord_t;
|
|
#endif /* __powerpc64__ */
|
|
|
|
+#ifdef VGP_ppc64le_linux
|
|
+#define isLE 1
|
|
+#else
|
|
+#define isLE 0
|
|
+#endif
|
|
+
|
|
register HWord_t r14 __asm__ ("r14");
|
|
register HWord_t r15 __asm__ ("r15");
|
|
register HWord_t r16 __asm__ ("r16");
|
|
@@ -341,6 +347,16 @@ static unsigned int viargs[] __attribute
|
|
#define NUM_VIARGS_INTS (sizeof viargs/sizeof viargs[0])
|
|
#define NUM_VIARGS_VECS (NUM_VIARGS_INTS/4)
|
|
|
|
+
|
|
+static unsigned long long vdargs[] __attribute__ ((aligned (16))) = {
|
|
+ 0x0102030405060708ULL,
|
|
+ 0x090A0B0C0E0D0E0FULL,
|
|
+ 0xF1F2F3F4F5F6F7F8ULL,
|
|
+ 0xF9FAFBFCFEFDFEFFULL
|
|
+};
|
|
+#define NUM_VDARGS_INTS (sizeof vdargs/sizeof vdargs[0])
|
|
+#define NUM_VDARGS_VECS (NUM_VDARGS_INTS/2)
|
|
+
|
|
typedef void (*test_func_t)(void);
|
|
|
|
struct test_table
|
|
@@ -727,7 +743,7 @@ static vx_fp_test_basic_t vx_fp_tests[]
|
|
|
|
static vx_fp_test2_t
|
|
vsx_one_fp_arg_tests[] = {
|
|
- { &test_xscvdpspn, "xscvdpspn", NULL, 20, SINGLE_TEST_SINGLE_RES, VX_SCALAR_SP_TO_VECTOR_SP, "conv"},
|
|
+ { &test_xscvdpspn, "xscvdpspn", NULL, 20, DOUBLE_TEST_SINGLE_RES, VX_SCALAR_SP_TO_VECTOR_SP, "conv"},
|
|
{ &test_xscvspdpn, "xscvspdpn", NULL, 20, SINGLE_TEST, VX_DEFAULT, "conv"},
|
|
{ &test_xsresp, "xsresp", NULL, 20, DOUBLE_TEST, VX_ESTIMATE, "1/x"},
|
|
{ &test_xsrsp, "xsrsp", NULL, 20, DOUBLE_TEST, VX_DEFAULT, "round"},
|
|
@@ -749,7 +765,7 @@ ldst_tests[] = {
|
|
{ &test_stxsspx, "stxsspx", DOUBLE_TEST_SINGLE_RES, vstg, 0, VSX_STORE },
|
|
{ &test_stxsiwx, "stxsiwx", SINGLE_TEST_SINGLE_RES, vstg, 4, VSX_STORE },
|
|
{ &test_lxsiwax, "lxsiwax", SINGLE_TEST, viargs, 0, VSX_LOAD },
|
|
- { &test_lxsiwzx, "lxsiwzx", SINGLE_TEST, viargs, 1, VSX_LOAD },
|
|
+ { &test_lxsiwzx, "lxsiwzx", SINGLE_TEST, viargs, 4, VSX_LOAD },
|
|
{ &test_lxsspx, "lxsspx", SINGLE_TEST, NULL, 0, VSX_LOAD },
|
|
{ NULL, NULL, 0, NULL, 0, 0 } };
|
|
|
|
@@ -881,8 +897,19 @@ static void test_vx_fp_ops(void)
|
|
test_func_t func;
|
|
int k;
|
|
char * test_name = (char *)malloc(20);
|
|
- k = 0;
|
|
+ void * vecA_void_ptr, * vecB_void_ptr, * vecOut_void_ptr;
|
|
+
|
|
+ if (isLE) {
|
|
+ vecA_void_ptr = (void *)&vec_inA + 8;
|
|
+ vecB_void_ptr = (void *)&vec_inB + 8;
|
|
+ vecOut_void_ptr = (void *)&vec_out + 8;
|
|
+ } else {
|
|
+ vecA_void_ptr = (void *)&vec_inA;
|
|
+ vecB_void_ptr = (void *)&vec_inB;
|
|
+ vecOut_void_ptr = (void *)&vec_out;
|
|
+ }
|
|
|
|
+ k = 0;
|
|
build_special_fargs_table();
|
|
while ((func = vx_fp_tests[k].test_func)) {
|
|
int i, repeat = 0;
|
|
@@ -932,8 +959,8 @@ again:
|
|
pv = (unsigned int *)&vec_out;
|
|
|
|
// Only need to copy one doubleword into each vector's element 0
|
|
- memcpy(&vec_inA, inA, 8);
|
|
- memcpy(&vec_inB, inB, 8);
|
|
+ memcpy(vecA_void_ptr, inA, 8);
|
|
+ memcpy(vecB_void_ptr, inB, 8);
|
|
|
|
// clear vec_out
|
|
for (idx = 0; idx < 4; idx++, pv++)
|
|
@@ -963,18 +990,20 @@ again:
|
|
* src2 <= VSX[XT]
|
|
* src3 <= VSX[XB]
|
|
*/
|
|
- memcpy(&vec_out, inB, 8); // src2
|
|
- memcpy(&vec_inB, &spec_fargs[extra_arg_idx], 8); //src3
|
|
+ memcpy(vecOut_void_ptr, inB, 8); // src2
|
|
+ memcpy(vecB_void_ptr, &spec_fargs[extra_arg_idx], 8); //src3
|
|
frbp = (unsigned long long *)&spec_fargs[extra_arg_idx];
|
|
} else {
|
|
// Don't need to init src2, as it's done before the switch()
|
|
- memcpy(&vec_out, &spec_fargs[extra_arg_idx], 8); //src3
|
|
+ memcpy(vecOut_void_ptr, &spec_fargs[extra_arg_idx], 8); //src3
|
|
}
|
|
- memcpy(&vsr_XT, &vec_out, 8);
|
|
+ memcpy(&vsr_XT, vecOut_void_ptr, 8);
|
|
}
|
|
|
|
(*func)();
|
|
dst = (unsigned long long *) &vec_out;
|
|
+ if (isLE)
|
|
+ dst++;
|
|
|
|
if (test_type == VX_FP_OTHER)
|
|
printf("#%d: %s %016llx %016llx = %016llx\n", i, test_name,
|
|
@@ -1033,6 +1062,8 @@ static void test_vsx_one_fp_arg(void)
|
|
{
|
|
test_func_t func;
|
|
int k;
|
|
+ void * vecB_void_ptr;
|
|
+
|
|
k = 0;
|
|
build_special_fargs_table();
|
|
|
|
@@ -1047,26 +1078,13 @@ static void test_vsx_one_fp_arg(void)
|
|
/* size of result */
|
|
Bool dp_res = IS_DP_RESULT(test_group.precision);
|
|
Bool is_sqrt = (strstr(test_group.name, "sqrt")) ? True : False;
|
|
- Bool is_scalar = (strstr(test_group.name, "xs")) ? True : False;
|
|
- Bool sparse_sp = False;
|
|
- int stride = dp ? 2 : 4;
|
|
- int loops = is_scalar ? 1 : stride;
|
|
- stride = is_scalar ? 1: stride;
|
|
-
|
|
- /* For conversions of single to double, the 128-bit input register is sparsely populated:
|
|
- * |___ SP___|_Unused_|___SP___|__Unused__| // for vector op
|
|
- * or
|
|
- * |___ SP___|_Unused_|_Unused_|__Unused__| // for scalar op
|
|
- *
|
|
- * For the vector op case, we need to adjust stride from '4' to '2', since
|
|
- * we'll only be loading two values per loop into the input register.
|
|
- */
|
|
- if (!dp && !is_scalar && test_group.test_type == VX_CONV_TO_DOUBLE) {
|
|
- sparse_sp = True;
|
|
- stride = 2;
|
|
+
|
|
+ vecB_void_ptr = (void *)&vec_inB;
|
|
+ if (isLE) {
|
|
+ vecB_void_ptr += dp? 8 : 12;
|
|
}
|
|
|
|
- for (i = 0; i < test_group.num_tests; i+=stride) {
|
|
+ for (i = 0; i < test_group.num_tests; i++) {
|
|
unsigned int * pv;
|
|
void * inB;
|
|
|
|
@@ -1076,13 +1094,26 @@ static void test_vsx_one_fp_arg(void)
|
|
*pv = 0;
|
|
|
|
if (dp) {
|
|
- int j;
|
|
+ int vec_out_idx;
|
|
unsigned long long * frB_dp;
|
|
- for (j = 0; j < loops; j++) {
|
|
- inB = (void *)&spec_fargs[i + j];
|
|
- // copy double precision FP into vector element i
|
|
- memcpy(((void *)&vec_inB) + (j * 8), inB, 8);
|
|
+ if (isLE)
|
|
+ vec_out_idx = dp_res ? 1 : 3;
|
|
+ else
|
|
+ vec_out_idx = 0;
|
|
+
|
|
+ if (test_group.test_type == VX_SCALAR_SP_TO_VECTOR_SP) {
|
|
+ /* Take a single-precision value stored in double word element 0
|
|
+ * of src in double-precision format and convert to single-
|
|
+ * precision and store in word element 0 of dst.
|
|
+ */
|
|
+ double input = spec_sp_fargs[i];
|
|
+ memcpy(vecB_void_ptr, (void *)&input, 8);
|
|
+ } else {
|
|
+ inB = (void *)&spec_fargs[i];
|
|
+ // copy double precision FP into input vector element 0
|
|
+ memcpy(vecB_void_ptr, inB, 8);
|
|
}
|
|
+
|
|
// execute test insn
|
|
(*func)();
|
|
if (dp_res)
|
|
@@ -1090,56 +1121,34 @@ static void test_vsx_one_fp_arg(void)
|
|
else
|
|
dst_sp = (unsigned int *) &vec_out;
|
|
|
|
- printf("#%d: %s ", i/stride, test_group.name);
|
|
- for (j = 0; j < loops; j++) {
|
|
- if (j)
|
|
- printf("; ");
|
|
- frB_dp = (unsigned long long *)&spec_fargs[i + j];
|
|
- printf("%s(%016llx)", test_group.op, *frB_dp);
|
|
- if (test_group.test_type == VX_ESTIMATE)
|
|
- {
|
|
- Bool res;
|
|
- res = check_reciprocal_estimate(is_sqrt, i + j, j);
|
|
- printf(" ==> %s)", res ? "PASS" : "FAIL");
|
|
- } else if (dp_res) {
|
|
- printf(" = %016llx", dst_dp[j]);
|
|
- } else {
|
|
- printf(" = %08x", dst_sp[j]);
|
|
- }
|
|
+ printf("#%d: %s ", i, test_group.name);
|
|
+ frB_dp = (unsigned long long *)&spec_fargs[i];
|
|
+ printf("%s(%016llx)", test_group.op, *frB_dp);
|
|
+ if (test_group.test_type == VX_ESTIMATE)
|
|
+ {
|
|
+ Bool res;
|
|
+ res = check_reciprocal_estimate(is_sqrt, i, vec_out_idx);
|
|
+ printf(" ==> %s)", res ? "PASS" : "FAIL");
|
|
+ } else if (dp_res) {
|
|
+ printf(" = %016llx", dst_dp[vec_out_idx]);
|
|
+ } else {
|
|
+ printf(" = %08x", dst_sp[vec_out_idx]);
|
|
}
|
|
+
|
|
printf("\n");
|
|
} else { // single precision test type
|
|
- int j;
|
|
+ int vec_out_idx;
|
|
+ if (isLE)
|
|
+ vec_out_idx = dp_res ? 1 : 3;
|
|
+ else
|
|
+ vec_out_idx = 0;
|
|
// Clear input vector
|
|
pv = (unsigned int *)&vec_inB;
|
|
for (idx = 0; idx < 4; idx++, pv++)
|
|
*pv = 0;
|
|
-
|
|
- if (test_group.test_type == VX_SCALAR_SP_TO_VECTOR_SP) {
|
|
- /* Take a single-precision value stored in double word element 0
|
|
- * of src in double-precision format and convert to single-
|
|
- * precision and store in word element 0 of dst.
|
|
- */
|
|
- double input = spec_sp_fargs[i];
|
|
- memcpy(((void *)&vec_inB), (void *)&input, 8);
|
|
- } else {
|
|
- int skip_slot;
|
|
- if (sparse_sp) {
|
|
- skip_slot = 1;
|
|
- loops = 2;
|
|
- } else {
|
|
- skip_slot = 0;
|
|
- }
|
|
- for (j = 0; j < loops; j++) {
|
|
- inB = (void *)&spec_sp_fargs[i + j];
|
|
- // copy single precision FP into vector element i
|
|
-
|
|
- if (skip_slot && j > 0)
|
|
- memcpy(((void *)&vec_inB) + ((j + j) * 4), inB, 4);
|
|
- else
|
|
- memcpy(((void *)&vec_inB) + (j * 4), inB, 4);
|
|
- }
|
|
- }
|
|
+ inB = (void *)&spec_sp_fargs[i];
|
|
+ // copy single precision FP into input vector element i
|
|
+ memcpy(vecB_void_ptr, inB, 4);
|
|
// execute test insn
|
|
(*func)();
|
|
if (dp_res)
|
|
@@ -1147,16 +1156,13 @@ static void test_vsx_one_fp_arg(void)
|
|
else
|
|
dst_sp = (unsigned int *) &vec_out;
|
|
// print result
|
|
- printf("#%d: %s ", i/stride, test_group.name);
|
|
- for (j = 0; j < loops; j++) {
|
|
- if (j)
|
|
- printf("; ");
|
|
- printf("%s(%08x)", test_group.op, *((unsigned int *)&spec_sp_fargs[i + j]));
|
|
+ printf("#%d: %s ", i, test_group.name);
|
|
+ printf("%s(%08x)", test_group.op, *((unsigned int *)&spec_sp_fargs[i]));
|
|
if (dp_res)
|
|
- printf(" = %016llx", dst_dp[j]);
|
|
+ printf(" = %016llx", dst_dp[vec_out_idx]);
|
|
else
|
|
- printf(" = %08x", dst_sp[j]);
|
|
- }
|
|
+ printf(" = %08x", dst_sp[vec_out_idx]);
|
|
+
|
|
printf("\n");
|
|
}
|
|
}
|
|
@@ -1170,6 +1176,15 @@ static void test_vsx_two_fp_arg(void)
|
|
{
|
|
test_func_t func;
|
|
int k = 0;
|
|
+ void * vecA_void_ptr, * vecB_void_ptr;
|
|
+
|
|
+ if (isLE) {
|
|
+ vecA_void_ptr = (void *)&vec_inA + 8;
|
|
+ vecB_void_ptr = (void *)&vec_inB + 8;
|
|
+ } else {
|
|
+ vecA_void_ptr = (void *)&vec_inA;
|
|
+ vecB_void_ptr = (void *)&vec_inB;
|
|
+ }
|
|
|
|
build_special_fargs_table();
|
|
while ((func = vx_simple_scalar_fp_tests[k].test_func)) {
|
|
@@ -1191,10 +1206,12 @@ static void test_vsx_two_fp_arg(void)
|
|
frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
|
|
frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
|
|
// Only need to copy one doubleword into each vector's element 0
|
|
- memcpy(&vec_inA, inA, 8);
|
|
- memcpy(&vec_inB, inB, 8);
|
|
+ memcpy(vecA_void_ptr, inA, 8);
|
|
+ memcpy(vecB_void_ptr, inB, 8);
|
|
(*func)();
|
|
dst = (unsigned long long *) &vec_out;
|
|
+ if (isLE)
|
|
+ dst++;
|
|
printf("#%d: %s %016llx,%016llx => %016llx\n", i, test_group.name,
|
|
*frap, *frbp, *dst);
|
|
}
|
|
@@ -1214,84 +1231,91 @@ static void _do_store_test (ldst_test_t
|
|
unsigned int *dst32;
|
|
unsigned int i, idx;
|
|
unsigned int * pv = (unsigned int *) storeTest.base_addr;
|
|
+ void * vecA_void_ptr;
|
|
+
|
|
+ if (isLE) {
|
|
+ if (storeTest.precision == SINGLE_TEST_SINGLE_RES)
|
|
+ vecA_void_ptr = (void *)&vec_inA + 8;
|
|
+ } else {
|
|
+ if (storeTest.precision == SINGLE_TEST_SINGLE_RES)
|
|
+ vecA_void_ptr = (void *)&vec_inA + 4;
|
|
+ else
|
|
+ vecA_void_ptr = (void *)&vec_inA;
|
|
+ }
|
|
|
|
func = storeTest.test_func;
|
|
r14 = (HWord_t) storeTest.base_addr;
|
|
r15 = (HWord_t) storeTest.offset;
|
|
|
|
- if (storeTest.precision == DOUBLE_TEST_SINGLE_RES) {
|
|
- /* source is single precision stored in double precision format */
|
|
- /* test some of the pre-defined single precision values */
|
|
- for (i = 0; i < nb_special_fargs; i+=3) {
|
|
- // clear out storage destination
|
|
- for (idx = 0; idx < 4; idx++)
|
|
- *(pv + idx) = 0;
|
|
-
|
|
- printf( "%s:", storeTest.name );
|
|
+ /* test some of the pre-defined single precision values */
|
|
+ for (i = 0; i < nb_special_fargs; i+=3) {
|
|
+ // clear out storage destination
|
|
+ for (idx = 0; idx < 4; idx++)
|
|
+ *(pv + idx) = 0;
|
|
+
|
|
+ printf( "%s:", storeTest.name );
|
|
+ if (storeTest.precision == SINGLE_TEST_SINGLE_RES)
|
|
+ {
|
|
+ unsigned int * arg_ptr = (unsigned int *)&spec_sp_fargs[i];
|
|
+ memcpy(vecA_void_ptr, arg_ptr, sizeof(unsigned int));
|
|
+ printf(" %08x ==> ", *arg_ptr);
|
|
+ } else {
|
|
unsigned long long * dp;
|
|
double input = spec_sp_fargs[i];
|
|
dp = (unsigned long long *)&input;
|
|
- memcpy(&vec_inA, dp, sizeof(unsigned long long));
|
|
+ memcpy(vecA_void_ptr, dp, sizeof(unsigned long long));
|
|
printf(" %016llx ==> ", *dp);
|
|
-
|
|
- // execute test insn
|
|
- (*func)();
|
|
- dst32 = (unsigned int*)(storeTest.base_addr + storeTest.offset);
|
|
- printf( "%08x\n", *dst32);
|
|
}
|
|
- } else {
|
|
- // source is an integer word
|
|
- for (i = 0; i < NUM_VIARGS_INTS; i++) {
|
|
- // clear out storage destination
|
|
- for (idx = 0; idx < 4; idx++)
|
|
- *(pv + idx) = 0;
|
|
- printf( "%s:", storeTest.name );
|
|
- unsigned int * pi = (unsigned int *)&vec_inA;
|
|
- memcpy(pi + 1, &viargs[i], sizeof(unsigned int));
|
|
- printf(" %08x ==> ", *(pi + 1));
|
|
|
|
- // execute test insn
|
|
- (*func)();
|
|
- dst32 = (unsigned int*)(storeTest.base_addr + storeTest.offset);
|
|
- printf( "%08x\n", *dst32);
|
|
- }
|
|
+ // execute test insn
|
|
+ (*func)();
|
|
+ dst32 = (unsigned int*)(storeTest.base_addr);
|
|
+ dst32 += (storeTest.offset/sizeof(int));
|
|
+ printf( "%08x\n", *dst32);
|
|
}
|
|
+
|
|
printf("\n");
|
|
}
|
|
|
|
-static void _do_load_test(ldst_test_t storeTest)
|
|
+static void _do_load_test(ldst_test_t loadTest)
|
|
{
|
|
test_func_t func;
|
|
unsigned int i;
|
|
unsigned long long * dst_dp;
|
|
|
|
- func = storeTest.test_func;
|
|
- r15 = (HWord_t) storeTest.offset;
|
|
+ func = loadTest.test_func;
|
|
+ r15 = (HWord_t) loadTest.offset;
|
|
|
|
- if (storeTest.base_addr == NULL) {
|
|
+ if (loadTest.base_addr == NULL) {
|
|
/* Test lxsspx: source is single precision value, so let's */
|
|
/* test some of the pre-defined single precision values. */
|
|
- for (i = 0; i + storeTest.offset < nb_special_fargs; i+=3) {
|
|
- unsigned int * sp = (unsigned int *)&spec_sp_fargs[i + storeTest.offset];
|
|
- printf( "%s:", storeTest.name );
|
|
+ int num_loops = (loadTest.offset == 0) ? nb_special_fargs : (nb_special_fargs - (loadTest.offset/sizeof(int)));
|
|
+ for (i = 0; i < num_loops; i+=3) {
|
|
+ unsigned int * sp = (unsigned int *)&spec_sp_fargs[i + (loadTest.offset/sizeof(int))];
|
|
+ printf( "%s:", loadTest.name );
|
|
printf(" %08x ==> ", *sp);
|
|
r14 = (HWord_t)&spec_sp_fargs[i];
|
|
|
|
// execute test insn
|
|
(*func)();
|
|
dst_dp = (unsigned long long *) &vec_out;
|
|
+ if (isLE)
|
|
+ dst_dp++;
|
|
printf("%016llx\n", *dst_dp);
|
|
}
|
|
} else {
|
|
// source is an integer word
|
|
- for (i = 0; i < NUM_VIARGS_INTS; i++) {
|
|
- printf( "%s:", storeTest.name );
|
|
- r14 = (HWord_t)&viargs[i + storeTest.offset];
|
|
- printf(" %08x ==> ", viargs[i + storeTest.offset]);
|
|
+ int num_loops = (loadTest.offset == 0) ? NUM_VIARGS_INTS : (NUM_VIARGS_INTS - (loadTest.offset/sizeof(int)));
|
|
+ for (i = 0; i < num_loops; i++) {
|
|
+ printf( "%s:", loadTest.name );
|
|
+ r14 = (HWord_t)&viargs[i];
|
|
+ printf(" %08x ==> ", viargs[i + (loadTest.offset/sizeof(int))]);
|
|
|
|
// execute test insn
|
|
(*func)();
|
|
dst_dp = (unsigned long long *) &vec_out;
|
|
+ if (isLE)
|
|
+ dst_dp++;
|
|
printf("%016llx\n", *dst_dp);
|
|
}
|
|
}
|
|
@@ -1318,24 +1342,32 @@ static void test_xs_conv_ops(void)
|
|
|
|
test_func_t func;
|
|
int k = 0;
|
|
+ void * vecB_void_ptr;
|
|
+
|
|
+ if (isLE)
|
|
+ vecB_void_ptr = (void *)&vec_inB + 8;
|
|
+ else
|
|
+ vecB_void_ptr = (void *)&vec_inB;
|
|
|
|
build_special_fargs_table();
|
|
while ((func = xs_conv_tests[k].test_func)) {
|
|
int i;
|
|
unsigned long long * dst;
|
|
xs_conv_test_t test_group = xs_conv_tests[k];
|
|
- for (i = 0; i < NUM_VIARGS_INTS; i++) {
|
|
- unsigned int * inB, * pv;
|
|
+ for (i = 0; i < NUM_VDARGS_INTS; i++) {
|
|
+ unsigned long long * inB, * pv;
|
|
int idx;
|
|
- inB = (unsigned int *)&viargs[i];
|
|
- memcpy(&vec_inB, inB, 4);
|
|
- pv = (unsigned int *)&vec_out;
|
|
+ inB = (unsigned long long *)&vdargs[i];
|
|
+ memcpy(vecB_void_ptr, inB, 8);
|
|
+ pv = (unsigned long long *)&vec_out;
|
|
// clear vec_out
|
|
- for (idx = 0; idx < 4; idx++, pv++)
|
|
- *pv = 0;
|
|
+ for (idx = 0; idx < 2; idx++, pv++)
|
|
+ *pv = 0ULL;
|
|
(*func)();
|
|
dst = (unsigned long long *) &vec_out;
|
|
- printf("#%d: %s %08x => %016llx\n", i, test_group.name, viargs[i], *dst);
|
|
+ if (isLE)
|
|
+ dst++;
|
|
+ printf("#%d: %s %016llx => %016llx\n", i, test_group.name, vdargs[i], *dst);
|
|
}
|
|
k++;
|
|
printf("\n");
|
|
Index: none/tests/ppc64/jm_vec_isa_2_07.stdout.exp
|
|
===================================================================
|
|
--- none/tests/ppc64/jm_vec_isa_2_07.stdout.exp.orig
|
|
+++ none/tests/ppc64/jm_vec_isa_2_07.stdout.exp
|
|
@@ -443,9 +443,9 @@ vsubuqm: 0102030405060708090a0b0c0e0d0e0
|
|
vsubuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0
|
|
vsubuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
|
|
|
|
-vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 0000000000000000000000000000020a
|
|
+vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 000000000000020a0000000000000000
|
|
vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
|
|
-vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> 0000000000000000000000000000e3ea
|
|
+vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> 000000000000e3ea0000000000000000
|
|
vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
|
|
|
|
vaddecuq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> 00000000000000000000000000000000
|
|
Index: none/tests/ppc64/jm-fp.stdout.exp-LE
|
|
===================================================================
|
|
--- /dev/null
|
|
+++ none/tests/ppc64/jm-fp.stdout.exp-LE
|
|
@@ -0,0 +1,1533 @@
|
|
+PPC floating point arith insns with three args:
|
|
+ fsel 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000
|
|
+ fsel 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300
|
|
+ fsel 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
|
|
+ fsel 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000
|
|
+ fsel 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300
|
|
+ fsel 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
|
|
+ fsel bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fsel bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fsel bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fmadd 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100
|
|
+ fmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00
|
|
+ fmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000
|
|
+ fmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100
|
|
+ fmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fmadds 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+
|
|
+ fmsub 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
|
|
+ fmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
|
|
+ fmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00
|
|
+ fmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100
|
|
+ fmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000
|
|
+ fmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00
|
|
+ fmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+
|
|
+ fmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+
|
|
+ fnmadd 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
|
|
+ fnmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
|
|
+ fnmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100
|
|
+ fnmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00
|
|
+ fnmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000
|
|
+ fnmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100
|
|
+ fnmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+
|
|
+ fnmadds 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+
|
|
+ fnmsub 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fnmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fnmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00
|
|
+ fnmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100
|
|
+ fnmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000
|
|
+ fnmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00
|
|
+ fnmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fnmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+
|
|
+PPC floating point arith insns
|
|
+ with three args with flags update:
|
|
+ fsel. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel. 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000
|
|
+ fsel. 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300
|
|
+ fsel. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
|
|
+ fsel. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000
|
|
+ fsel. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300
|
|
+ fsel. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
|
|
+ fsel. bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fsel. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fsel. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100
|
|
+ fmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00
|
|
+ fmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000
|
|
+ fmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100
|
|
+ fmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+
|
|
+ fmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
|
|
+ fmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
|
|
+ fmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00
|
|
+ fmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100
|
|
+ fmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000
|
|
+ fmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00
|
|
+ fmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+
|
|
+ fmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+
|
|
+ fnmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
|
|
+ fnmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
|
|
+ fnmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100
|
|
+ fnmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00
|
|
+ fnmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000
|
|
+ fnmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100
|
|
+ fnmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+
|
|
+ fnmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+
|
|
+ fnmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fnmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fnmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00
|
|
+ fnmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100
|
|
+ fnmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000
|
|
+ fnmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00
|
|
+ fnmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fnmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+
|
|
+PPC floating point arith insns with two args:
|
|
+ fadd 0010000000000001, 0010000000000001 => 0020000000000001
|
|
+ fadd 0010000000000001, 80100094e0000359 => 80000094e0000358
|
|
+ fadd 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadd 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
|
|
+ fadd 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
|
|
+ fadd 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fadd bfe0000000000001, 0010000000000001 => bfe0000000000001
|
|
+ fadd bfe0000000000001, 80100094e0000359 => bfe0000000000001
|
|
+ fadd bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadd 8000000000000000, 0010000000000001 => 0010000000000001
|
|
+ fadd 8000000000000000, 80100094e0000359 => 80100094e0000359
|
|
+ fadd 8000000000000000, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fadd 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fadd 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fadd 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fadd 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fadd fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fadd fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fadd fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fadd fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fadds 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fadds 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fadds 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadds 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
|
|
+ fadds 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
|
|
+ fadds 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fadds bfe0000000000001, 0010000000000001 => bfe0000000000000
|
|
+ fadds bfe0000000000001, 80100094e0000359 => bfe0000000000000
|
|
+ fadds bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadds 8000000000000000, 0010000000000001 => 0000000000000000
|
|
+ fadds 8000000000000000, 80100094e0000359 => 8000000000000000
|
|
+ fadds 8000000000000000, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fadds 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fadds 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fadds 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fadds 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fadds fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fadds fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fadds fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fadds fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fsub 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fsub 0010000000000001, 80100094e0000359 => 0020004a700001ad
|
|
+ fsub 0010000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsub 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsub 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
|
|
+ fsub 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
|
|
+ fsub 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
|
|
+ fsub 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fsub bfe0000000000001, 0010000000000001 => bfe0000000000001
|
|
+ fsub bfe0000000000001, 80100094e0000359 => bfe0000000000001
|
|
+ fsub bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsub bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsub 8000000000000000, 0010000000000001 => 8010000000000001
|
|
+ fsub 8000000000000000, 80100094e0000359 => 00100094e0000359
|
|
+ fsub 8000000000000000, 7ff0000000000000 => fff0000000000000
|
|
+ fsub 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fsub 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fsub 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fsub 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fsub 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fsub fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fsub fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fsub fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fsub fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fsubs 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fsubs 0010000000000001, 80100094e0000359 => 0000000000000000
|
|
+ fsubs 0010000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsubs 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
|
|
+ fsubs 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
|
|
+ fsubs 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fsubs bfe0000000000001, 0010000000000001 => bfe0000000000000
|
|
+ fsubs bfe0000000000001, 80100094e0000359 => bfe0000000000000
|
|
+ fsubs bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsubs 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fsubs 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fsubs 8000000000000000, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fsubs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fsubs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fsubs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fsubs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fsubs fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fsubs fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fsubs fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fsubs fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fmul 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmul 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fmul 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmul 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmul 3fe00094e0000359, 0010000000000001 => 0008004a700001ad
|
|
+ fmul 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179
|
|
+ fmul 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmul 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fmul bfe0000000000001, 0010000000000001 => 8008000000000001
|
|
+ fmul bfe0000000000001, 80100094e0000359 => 0008004a700001ad
|
|
+ fmul bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fmul bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmul 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fmul 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fmul 8000000000000000, 7ff0000000000000 => 7ff8000000000000
|
|
+ fmul 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fmul 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fmul 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fmul 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fmul 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fmul fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fmul fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fmul fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fmul fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fmuls 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmuls 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fmuls 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmuls 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmuls 3fe00094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmuls 3fe00094e0000359, 80100094e0000359 => 8000000000000000
|
|
+ fmuls 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmuls 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fmuls bfe0000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmuls bfe0000000000001, 80100094e0000359 => 0000000000000000
|
|
+ fmuls bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fmuls bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmuls 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fmuls 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fmuls 8000000000000000, 7ff0000000000000 => 7ff8000000000000
|
|
+ fmuls 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fmuls 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fmuls 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fmuls 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fmuls 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fmuls fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fmuls fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fmuls fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fmuls fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fdiv 0010000000000001, 0010000000000001 => 3ff0000000000000
|
|
+ fdiv 0010000000000001, 80100094e0000359 => bfeffed64ad20d22
|
|
+ fdiv 0010000000000001, 7ff0000000000000 => 0000000000000000
|
|
+ fdiv 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdiv 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358
|
|
+ fdiv 3fe00094e0000359, 80100094e0000359 => ffc0000000000000
|
|
+ fdiv 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
|
|
+ fdiv 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fdiv bfe0000000000001, 0010000000000001 => ffc0000000000000
|
|
+ fdiv bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22
|
|
+ fdiv bfe0000000000001, 7ff0000000000000 => 8000000000000000
|
|
+ fdiv bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdiv 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fdiv 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fdiv 8000000000000000, 7ff0000000000000 => 8000000000000000
|
|
+ fdiv 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fdiv 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fdiv 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fdiv 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fdiv 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fdiv fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fdiv fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fdiv fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fdiv fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fdivs 0010000000000001, 0010000000000001 => 3ff0000000000000
|
|
+ fdivs 0010000000000001, 80100094e0000359 => bfeffed640000000
|
|
+ fdivs 0010000000000001, 7ff0000000000000 => 0000000000000000
|
|
+ fdivs 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdivs 3fe00094e0000359, 0010000000000001 => 7ff0000000000000
|
|
+ fdivs 3fe00094e0000359, 80100094e0000359 => fff0000000000000
|
|
+ fdivs 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
|
|
+ fdivs 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fdivs bfe0000000000001, 0010000000000001 => fff0000000000000
|
|
+ fdivs bfe0000000000001, 80100094e0000359 => 7ff0000000000000
|
|
+ fdivs bfe0000000000001, 7ff0000000000000 => 8000000000000000
|
|
+ fdivs bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdivs 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fdivs 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fdivs 8000000000000000, 7ff0000000000000 => 8000000000000000
|
|
+ fdivs 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fdivs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fdivs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fdivs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fdivs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fdivs fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fdivs fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fdivs fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fdivs fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+PPC floating point arith insns
|
|
+ with two args with flags update:
|
|
+ fadd. 0010000000000001, 0010000000000001 => 0020000000000001
|
|
+ fadd. 0010000000000001, 80100094e0000359 => 80000094e0000358
|
|
+ fadd. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadd. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
|
|
+ fadd. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
|
|
+ fadd. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fadd. bfe0000000000001, 0010000000000001 => bfe0000000000001
|
|
+ fadd. bfe0000000000001, 80100094e0000359 => bfe0000000000001
|
|
+ fadd. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadd. 8000000000000000, 0010000000000001 => 0010000000000001
|
|
+ fadd. 8000000000000000, 80100094e0000359 => 80100094e0000359
|
|
+ fadd. 8000000000000000, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fadd. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fadd. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fadd. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fadd. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fadd. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fadd. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fadd. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fadd. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fadds. 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fadds. 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fadds. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadds. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
|
|
+ fadds. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
|
|
+ fadds. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fadds. bfe0000000000001, 0010000000000001 => bfe0000000000000
|
|
+ fadds. bfe0000000000001, 80100094e0000359 => bfe0000000000000
|
|
+ fadds. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadds. 8000000000000000, 0010000000000001 => 0000000000000000
|
|
+ fadds. 8000000000000000, 80100094e0000359 => 8000000000000000
|
|
+ fadds. 8000000000000000, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fadds. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fadds. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fadds. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fadds. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fadds. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fadds. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fadds. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fadds. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fsub. 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fsub. 0010000000000001, 80100094e0000359 => 0020004a700001ad
|
|
+ fsub. 0010000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsub. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsub. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
|
|
+ fsub. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
|
|
+ fsub. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
|
|
+ fsub. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fsub. bfe0000000000001, 0010000000000001 => bfe0000000000001
|
|
+ fsub. bfe0000000000001, 80100094e0000359 => bfe0000000000001
|
|
+ fsub. bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsub. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsub. 8000000000000000, 0010000000000001 => 8010000000000001
|
|
+ fsub. 8000000000000000, 80100094e0000359 => 00100094e0000359
|
|
+ fsub. 8000000000000000, 7ff0000000000000 => fff0000000000000
|
|
+ fsub. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fsub. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fsub. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fsub. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fsub. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fsub. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fsub. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fsub. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fsub. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fsubs. 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fsubs. 0010000000000001, 80100094e0000359 => 0000000000000000
|
|
+ fsubs. 0010000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsubs. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
|
|
+ fsubs. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
|
|
+ fsubs. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fsubs. bfe0000000000001, 0010000000000001 => bfe0000000000000
|
|
+ fsubs. bfe0000000000001, 80100094e0000359 => bfe0000000000000
|
|
+ fsubs. bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsubs. 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fsubs. 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fsubs. 8000000000000000, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fsubs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fsubs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fsubs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fsubs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fsubs. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fsubs. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fsubs. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fsubs. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fmul. 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmul. 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fmul. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmul. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmul. 3fe00094e0000359, 0010000000000001 => 0008004a700001ad
|
|
+ fmul. 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179
|
|
+ fmul. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmul. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fmul. bfe0000000000001, 0010000000000001 => 8008000000000001
|
|
+ fmul. bfe0000000000001, 80100094e0000359 => 0008004a700001ad
|
|
+ fmul. bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fmul. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmul. 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fmul. 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fmul. 8000000000000000, 7ff0000000000000 => 7ff8000000000000
|
|
+ fmul. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fmul. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fmul. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fmul. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fmul. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fmul. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fmul. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fmul. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fmul. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fmuls. 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmuls. 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fmuls. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmuls. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmuls. 3fe00094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmuls. 3fe00094e0000359, 80100094e0000359 => 8000000000000000
|
|
+ fmuls. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmuls. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fmuls. bfe0000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmuls. bfe0000000000001, 80100094e0000359 => 0000000000000000
|
|
+ fmuls. bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fmuls. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmuls. 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fmuls. 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fmuls. 8000000000000000, 7ff0000000000000 => 7ff8000000000000
|
|
+ fmuls. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fmuls. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fmuls. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fmuls. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fmuls. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fmuls. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fmuls. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fmuls. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fmuls. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fdiv. 0010000000000001, 0010000000000001 => 3ff0000000000000
|
|
+ fdiv. 0010000000000001, 80100094e0000359 => bfeffed64ad20d22
|
|
+ fdiv. 0010000000000001, 7ff0000000000000 => 0000000000000000
|
|
+ fdiv. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdiv. 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358
|
|
+ fdiv. 3fe00094e0000359, 80100094e0000359 => ffc0000000000000
|
|
+ fdiv. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
|
|
+ fdiv. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fdiv. bfe0000000000001, 0010000000000001 => ffc0000000000000
|
|
+ fdiv. bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22
|
|
+ fdiv. bfe0000000000001, 7ff0000000000000 => 8000000000000000
|
|
+ fdiv. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdiv. 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fdiv. 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fdiv. 8000000000000000, 7ff0000000000000 => 8000000000000000
|
|
+ fdiv. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fdiv. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fdiv. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fdiv. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fdiv. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fdiv. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fdiv. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fdiv. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fdiv. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fdivs. 0010000000000001, 0010000000000001 => 3ff0000000000000
|
|
+ fdivs. 0010000000000001, 80100094e0000359 => bfeffed640000000
|
|
+ fdivs. 0010000000000001, 7ff0000000000000 => 0000000000000000
|
|
+ fdivs. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdivs. 3fe00094e0000359, 0010000000000001 => 7ff0000000000000
|
|
+ fdivs. 3fe00094e0000359, 80100094e0000359 => fff0000000000000
|
|
+ fdivs. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
|
|
+ fdivs. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fdivs. bfe0000000000001, 0010000000000001 => fff0000000000000
|
|
+ fdivs. bfe0000000000001, 80100094e0000359 => 7ff0000000000000
|
|
+ fdivs. bfe0000000000001, 7ff0000000000000 => 8000000000000000
|
|
+ fdivs. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdivs. 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fdivs. 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fdivs. 8000000000000000, 7ff0000000000000 => 8000000000000000
|
|
+ fdivs. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fdivs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fdivs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fdivs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fdivs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fdivs. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fdivs. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fdivs. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fdivs. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+PPC floating point compare insns (two args):
|
|
+ fcmpo 0010000000000001, 0010000000000001 => fff8000000000000
|
|
+ fcmpo 0010000000000001, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo 0010000000000001, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fcmpo 3fe00094e0000359, 0010000000000001 => fff8000000000000
|
|
+ fcmpo 3fe00094e0000359, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo 3fe00094e0000359, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fcmpo bfe0000000000001, 0010000000000001 => fff8000000000000
|
|
+ fcmpo bfe0000000000001, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo bfe0000000000001, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fcmpo 8000000000000000, 0010000000000001 => fff8000000000000
|
|
+ fcmpo 8000000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo 8000000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fcmpo 7ff7ffffffffffff, 0010000000000001 => fff8000000000000
|
|
+ fcmpo 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo 7ff7ffffffffffff, fff8000000000000 => fff8000000000000
|
|
+ fcmpo fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fcmpo fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fcmpu 0010000000000001, 0010000000000001 => fff8000000000000
|
|
+ fcmpu 0010000000000001, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu 0010000000000001, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fcmpu 3fe00094e0000359, 0010000000000001 => fff8000000000000
|
|
+ fcmpu 3fe00094e0000359, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu 3fe00094e0000359, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fcmpu bfe0000000000001, 0010000000000001 => fff8000000000000
|
|
+ fcmpu bfe0000000000001, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu bfe0000000000001, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fcmpu 8000000000000000, 0010000000000001 => fff8000000000000
|
|
+ fcmpu 8000000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu 8000000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fcmpu 7ff7ffffffffffff, 0010000000000001 => fff8000000000000
|
|
+ fcmpu 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu 7ff7ffffffffffff, fff8000000000000 => fff8000000000000
|
|
+ fcmpu fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fcmpu fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+PPC floating point arith insns with one arg:
|
|
+ fres 0010000000000001 => 7ff0000000000000
|
|
+ fres 00100094e0000359 => 7ff0000000000000
|
|
+ fres 3fe0000000000001 => 3ffff00000000000
|
|
+ fres 3fe00094e0000359 => 3ffff00000000000
|
|
+ fres 8010000000000001 => fff0000000000000
|
|
+ fres 80100094e0000359 => fff0000000000000
|
|
+ fres bfe0000000000001 => bffff00000000000
|
|
+ fres bfe00094e0000359 => bffff00000000000
|
|
+ fres 0000000000000000 => 7ff0000000000000
|
|
+ fres 8000000000000000 => fff0000000000000
|
|
+ fres 7ff0000000000000 => 0000000000000000
|
|
+ fres fff0000000000000 => 8000000000000000
|
|
+ fres 7ff7ffffffffffff => 7ffff00000000000
|
|
+ fres fff7ffffffffffff => fffff00000000000
|
|
+ fres 7ff8000000000000 => 7ff8000000000000
|
|
+ fres fff8000000000000 => fff8000000000000
|
|
+
|
|
+ frsqrte 0010000000000001 => 5fdf000000000000
|
|
+ frsqrte 00100094e0000359 => 5fdf000000000000
|
|
+ frsqrte 3fe0000000000001 => 3ff6000000000000
|
|
+ frsqrte 3fe00094e0000359 => 3ff6000000000000
|
|
+ frsqrte 8010000000000001 => 7ff8000000000000
|
|
+ frsqrte 80100094e0000359 => 7ff8000000000000
|
|
+ frsqrte bfe0000000000001 => 7ff8000000000000
|
|
+ frsqrte bfe00094e0000359 => 7ff8000000000000
|
|
+ frsqrte 0000000000000000 => 7ff0000000000000
|
|
+ frsqrte 8000000000000000 => fff0000000000000
|
|
+ frsqrte 7ff0000000000000 => 0000000000000000
|
|
+ frsqrte fff0000000000000 => 7ff8000000000000
|
|
+ frsqrte 7ff7ffffffffffff => 7fff000000000000
|
|
+ frsqrte fff7ffffffffffff => ffff000000000000
|
|
+ frsqrte 7ff8000000000000 => 7ff8000000000000
|
|
+ frsqrte fff8000000000000 => fff8000000000000
|
|
+
|
|
+ frsp 0010000000000001 => 0000000000000000
|
|
+ frsp 00100094e0000359 => 0000000000000000
|
|
+ frsp 3fe0000000000001 => 3fe0000000000000
|
|
+ frsp 3fe00094e0000359 => 3fe00094e0000000
|
|
+ frsp 8010000000000001 => 8000000000000000
|
|
+ frsp 80100094e0000359 => 8000000000000000
|
|
+ frsp bfe0000000000001 => bfe0000000000000
|
|
+ frsp bfe00094e0000359 => bfe00094e0000000
|
|
+ frsp 0000000000000000 => 0000000000000000
|
|
+ frsp 8000000000000000 => 8000000000000000
|
|
+ frsp 7ff0000000000000 => 7ff0000000000000
|
|
+ frsp fff0000000000000 => fff0000000000000
|
|
+ frsp 7ff7ffffffffffff => 7fffffffe0000000
|
|
+ frsp fff7ffffffffffff => ffffffffe0000000
|
|
+ frsp 7ff8000000000000 => 7ff8000000000000
|
|
+ frsp fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fctiw 0010000000000001 => 0000000000000000
|
|
+ fctiw 00100094e0000359 => 0000000000000000
|
|
+ fctiw 3fe0000000000001 => 0000000000000001
|
|
+ fctiw 3fe00094e0000359 => 0000000000000001
|
|
+ fctiw 8010000000000001 => 0000000000000000
|
|
+ fctiw 80100094e0000359 => 0000000000000000
|
|
+ fctiw bfe0000000000001 => 00000000ffffffff
|
|
+ fctiw bfe00094e0000359 => 00000000ffffffff
|
|
+ fctiw 0000000000000000 => 0000000000000000
|
|
+ fctiw 8000000000000000 => 0000000000000000
|
|
+ fctiw 7ff0000000000000 => 000000007fffffff
|
|
+ fctiw fff0000000000000 => 0000000080000000
|
|
+ fctiw 7ff7ffffffffffff => 0000000080000000
|
|
+ fctiw fff7ffffffffffff => 0000000080000000
|
|
+ fctiw 7ff8000000000000 => 0000000080000000
|
|
+ fctiw fff8000000000000 => 0000000080000000
|
|
+
|
|
+ fctiwz 0010000000000001 => 0000000000000000
|
|
+ fctiwz 00100094e0000359 => 0000000000000000
|
|
+ fctiwz 3fe0000000000001 => 0000000000000000
|
|
+ fctiwz 3fe00094e0000359 => 0000000000000000
|
|
+ fctiwz 8010000000000001 => 0000000000000000
|
|
+ fctiwz 80100094e0000359 => 0000000000000000
|
|
+ fctiwz bfe0000000000001 => 0000000000000000
|
|
+ fctiwz bfe00094e0000359 => 0000000000000000
|
|
+ fctiwz 0000000000000000 => 0000000000000000
|
|
+ fctiwz 8000000000000000 => 0000000000000000
|
|
+ fctiwz 7ff0000000000000 => 000000007fffffff
|
|
+ fctiwz fff0000000000000 => 0000000080000000
|
|
+ fctiwz 7ff7ffffffffffff => 0000000080000000
|
|
+ fctiwz fff7ffffffffffff => 0000000080000000
|
|
+ fctiwz 7ff8000000000000 => 0000000080000000
|
|
+ fctiwz fff8000000000000 => 0000000080000000
|
|
+
|
|
+ fmr 0010000000000001 => 0010000000000001
|
|
+ fmr 00100094e0000359 => 00100094e0000359
|
|
+ fmr 3fe0000000000001 => 3fe0000000000001
|
|
+ fmr 3fe00094e0000359 => 3fe00094e0000359
|
|
+ fmr 8010000000000001 => 8010000000000001
|
|
+ fmr 80100094e0000359 => 80100094e0000359
|
|
+ fmr bfe0000000000001 => bfe0000000000001
|
|
+ fmr bfe00094e0000359 => bfe00094e0000359
|
|
+ fmr 0000000000000000 => 0000000000000000
|
|
+ fmr 8000000000000000 => 8000000000000000
|
|
+ fmr 7ff0000000000000 => 7ff0000000000000
|
|
+ fmr fff0000000000000 => fff0000000000000
|
|
+ fmr 7ff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fmr fff7ffffffffffff => fff7ffffffffffff
|
|
+ fmr 7ff8000000000000 => 7ff8000000000000
|
|
+ fmr fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fneg 0010000000000001 => 8010000000000001
|
|
+ fneg 00100094e0000359 => 80100094e0000359
|
|
+ fneg 3fe0000000000001 => bfe0000000000001
|
|
+ fneg 3fe00094e0000359 => bfe00094e0000359
|
|
+ fneg 8010000000000001 => 0010000000000001
|
|
+ fneg 80100094e0000359 => 00100094e0000359
|
|
+ fneg bfe0000000000001 => 3fe0000000000001
|
|
+ fneg bfe00094e0000359 => 3fe00094e0000359
|
|
+ fneg 0000000000000000 => 8000000000000000
|
|
+ fneg 8000000000000000 => 0000000000000000
|
|
+ fneg 7ff0000000000000 => fff0000000000000
|
|
+ fneg fff0000000000000 => 7ff0000000000000
|
|
+ fneg 7ff7ffffffffffff => fff7ffffffffffff
|
|
+ fneg fff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fneg 7ff8000000000000 => fff8000000000000
|
|
+ fneg fff8000000000000 => 7ff8000000000000
|
|
+
|
|
+ fabs 0010000000000001 => 0010000000000001
|
|
+ fabs 00100094e0000359 => 00100094e0000359
|
|
+ fabs 3fe0000000000001 => 3fe0000000000001
|
|
+ fabs 3fe00094e0000359 => 3fe00094e0000359
|
|
+ fabs 8010000000000001 => 0010000000000001
|
|
+ fabs 80100094e0000359 => 00100094e0000359
|
|
+ fabs bfe0000000000001 => 3fe0000000000001
|
|
+ fabs bfe00094e0000359 => 3fe00094e0000359
|
|
+ fabs 0000000000000000 => 0000000000000000
|
|
+ fabs 8000000000000000 => 0000000000000000
|
|
+ fabs 7ff0000000000000 => 7ff0000000000000
|
|
+ fabs fff0000000000000 => 7ff0000000000000
|
|
+ fabs 7ff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fabs fff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fabs 7ff8000000000000 => 7ff8000000000000
|
|
+ fabs fff8000000000000 => 7ff8000000000000
|
|
+
|
|
+ fnabs 0010000000000001 => 8010000000000001
|
|
+ fnabs 00100094e0000359 => 80100094e0000359
|
|
+ fnabs 3fe0000000000001 => bfe0000000000001
|
|
+ fnabs 3fe00094e0000359 => bfe00094e0000359
|
|
+ fnabs 8010000000000001 => 8010000000000001
|
|
+ fnabs 80100094e0000359 => 80100094e0000359
|
|
+ fnabs bfe0000000000001 => bfe0000000000001
|
|
+ fnabs bfe00094e0000359 => bfe00094e0000359
|
|
+ fnabs 0000000000000000 => 8000000000000000
|
|
+ fnabs 8000000000000000 => 8000000000000000
|
|
+ fnabs 7ff0000000000000 => fff0000000000000
|
|
+ fnabs fff0000000000000 => fff0000000000000
|
|
+ fnabs 7ff7ffffffffffff => fff7ffffffffffff
|
|
+ fnabs fff7ffffffffffff => fff7ffffffffffff
|
|
+ fnabs 7ff8000000000000 => fff8000000000000
|
|
+ fnabs fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fsqrt 0010000000000001 => 2000000000000000
|
|
+ fsqrt 00100094e0000359 => 2000004a6f52dd4a
|
|
+ fsqrt 3fe0000000000001 => 3fe6a09e667f3bcd
|
|
+ fsqrt 3fe00094e0000359 => 3fe6a107aacb50df
|
|
+ fsqrt 8010000000000001 => 7ff8000000000000
|
|
+ fsqrt 80100094e0000359 => 7ff8000000000000
|
|
+ fsqrt bfe0000000000001 => 7ff8000000000000
|
|
+ fsqrt bfe00094e0000359 => 7ff8000000000000
|
|
+ fsqrt 0000000000000000 => 0000000000000000
|
|
+ fsqrt 8000000000000000 => 8000000000000000
|
|
+ fsqrt 7ff0000000000000 => 7ff0000000000000
|
|
+ fsqrt fff0000000000000 => 7ff8000000000000
|
|
+ fsqrt 7ff7ffffffffffff => 7fffffffffffffff
|
|
+ fsqrt fff7ffffffffffff => ffffffffffffffff
|
|
+ fsqrt 7ff8000000000000 => 7ff8000000000000
|
|
+ fsqrt fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fcfid 0010000000000001 => 4330000000000001
|
|
+ fcfid 00100094e0000359 => 43300094e0000359
|
|
+ fcfid 3fe0000000000001 => 43cff00000000000
|
|
+ fcfid 3fe00094e0000359 => 43cff0004a700002
|
|
+ fcfid 8010000000000001 => c3dffc0000000000
|
|
+ fcfid 80100094e0000359 => c3dffbffdac7ffff
|
|
+ fcfid bfe0000000000001 => c3d0080000000000
|
|
+ fcfid bfe00094e0000359 => c3d007ffdac7ffff
|
|
+ fcfid 0000000000000000 => 0000000000000000
|
|
+ fcfid 8000000000000000 => c3e0000000000000
|
|
+ fcfid 7ff0000000000000 => 43dffc0000000000
|
|
+ fcfid fff0000000000000 => c330000000000000
|
|
+ fcfid 7ff7ffffffffffff => 43dffe0000000000
|
|
+ fcfid fff7ffffffffffff => c320000000000002
|
|
+ fcfid 7ff8000000000000 => 43dffe0000000000
|
|
+ fcfid fff8000000000000 => c320000000000000
|
|
+
|
|
+ fctid 0010000000000001 => 0000000000000000
|
|
+ fctid 00100094e0000359 => 0000000000000000
|
|
+ fctid 3fe0000000000001 => 0000000000000001
|
|
+ fctid 3fe00094e0000359 => 0000000000000001
|
|
+ fctid 8010000000000001 => 0000000000000000
|
|
+ fctid 80100094e0000359 => 0000000000000000
|
|
+ fctid bfe0000000000001 => ffffffffffffffff
|
|
+ fctid bfe00094e0000359 => ffffffffffffffff
|
|
+ fctid 0000000000000000 => 0000000000000000
|
|
+ fctid 8000000000000000 => 0000000000000000
|
|
+ fctid 7ff0000000000000 => 7fffffffffffffff
|
|
+ fctid fff0000000000000 => 8000000000000000
|
|
+ fctid 7ff7ffffffffffff => 8000000000000000
|
|
+ fctid fff7ffffffffffff => 8000000000000000
|
|
+ fctid 7ff8000000000000 => 8000000000000000
|
|
+ fctid fff8000000000000 => 8000000000000000
|
|
+
|
|
+ fctidz 0010000000000001 => 0000000000000000
|
|
+ fctidz 00100094e0000359 => 0000000000000000
|
|
+ fctidz 3fe0000000000001 => 0000000000000000
|
|
+ fctidz 3fe00094e0000359 => 0000000000000000
|
|
+ fctidz 8010000000000001 => 0000000000000000
|
|
+ fctidz 80100094e0000359 => 0000000000000000
|
|
+ fctidz bfe0000000000001 => 0000000000000000
|
|
+ fctidz bfe00094e0000359 => 0000000000000000
|
|
+ fctidz 0000000000000000 => 0000000000000000
|
|
+ fctidz 8000000000000000 => 0000000000000000
|
|
+ fctidz 7ff0000000000000 => 7fffffffffffffff
|
|
+ fctidz fff0000000000000 => 8000000000000000
|
|
+ fctidz 7ff7ffffffffffff => 8000000000000000
|
|
+ fctidz fff7ffffffffffff => 8000000000000000
|
|
+ fctidz 7ff8000000000000 => 8000000000000000
|
|
+ fctidz fff8000000000000 => 8000000000000000
|
|
+
|
|
+PPC floating point arith insns
|
|
+ with one arg with flags update:
|
|
+ fres. 0010000000000001 => 7ff0000000000000
|
|
+ fres. 00100094e0000359 => 7ff0000000000000
|
|
+ fres. 3fe0000000000001 => 3ffff00000000000
|
|
+ fres. 3fe00094e0000359 => 3ffff00000000000
|
|
+ fres. 8010000000000001 => fff0000000000000
|
|
+ fres. 80100094e0000359 => fff0000000000000
|
|
+ fres. bfe0000000000001 => bffff00000000000
|
|
+ fres. bfe00094e0000359 => bffff00000000000
|
|
+ fres. 0000000000000000 => 7ff0000000000000
|
|
+ fres. 8000000000000000 => fff0000000000000
|
|
+ fres. 7ff0000000000000 => 0000000000000000
|
|
+ fres. fff0000000000000 => 8000000000000000
|
|
+ fres. 7ff7ffffffffffff => 7ffff00000000000
|
|
+ fres. fff7ffffffffffff => fffff00000000000
|
|
+ fres. 7ff8000000000000 => 7ff8000000000000
|
|
+ fres. fff8000000000000 => fff8000000000000
|
|
+
|
|
+ frsqrte. 0010000000000001 => 5fdf000000000000
|
|
+ frsqrte. 00100094e0000359 => 5fdf000000000000
|
|
+ frsqrte. 3fe0000000000001 => 3ff6000000000000
|
|
+ frsqrte. 3fe00094e0000359 => 3ff6000000000000
|
|
+ frsqrte. 8010000000000001 => 7ff8000000000000
|
|
+ frsqrte. 80100094e0000359 => 7ff8000000000000
|
|
+ frsqrte. bfe0000000000001 => 7ff8000000000000
|
|
+ frsqrte. bfe00094e0000359 => 7ff8000000000000
|
|
+ frsqrte. 0000000000000000 => 7ff0000000000000
|
|
+ frsqrte. 8000000000000000 => fff0000000000000
|
|
+ frsqrte. 7ff0000000000000 => 0000000000000000
|
|
+ frsqrte. fff0000000000000 => 7ff8000000000000
|
|
+ frsqrte. 7ff7ffffffffffff => 7fff000000000000
|
|
+ frsqrte. fff7ffffffffffff => ffff000000000000
|
|
+ frsqrte. 7ff8000000000000 => 7ff8000000000000
|
|
+ frsqrte. fff8000000000000 => fff8000000000000
|
|
+
|
|
+ frsp. 0010000000000001 => 0000000000000000
|
|
+ frsp. 00100094e0000359 => 0000000000000000
|
|
+ frsp. 3fe0000000000001 => 3fe0000000000000
|
|
+ frsp. 3fe00094e0000359 => 3fe00094e0000000
|
|
+ frsp. 8010000000000001 => 8000000000000000
|
|
+ frsp. 80100094e0000359 => 8000000000000000
|
|
+ frsp. bfe0000000000001 => bfe0000000000000
|
|
+ frsp. bfe00094e0000359 => bfe00094e0000000
|
|
+ frsp. 0000000000000000 => 0000000000000000
|
|
+ frsp. 8000000000000000 => 8000000000000000
|
|
+ frsp. 7ff0000000000000 => 7ff0000000000000
|
|
+ frsp. fff0000000000000 => fff0000000000000
|
|
+ frsp. 7ff7ffffffffffff => 7fffffffe0000000
|
|
+ frsp. fff7ffffffffffff => ffffffffe0000000
|
|
+ frsp. 7ff8000000000000 => 7ff8000000000000
|
|
+ frsp. fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fctiw. 0010000000000001 => 0000000000000000
|
|
+ fctiw. 00100094e0000359 => 0000000000000000
|
|
+ fctiw. 3fe0000000000001 => 0000000000000001
|
|
+ fctiw. 3fe00094e0000359 => 0000000000000001
|
|
+ fctiw. 8010000000000001 => 0000000000000000
|
|
+ fctiw. 80100094e0000359 => 0000000000000000
|
|
+ fctiw. bfe0000000000001 => 00000000ffffffff
|
|
+ fctiw. bfe00094e0000359 => 00000000ffffffff
|
|
+ fctiw. 0000000000000000 => 0000000000000000
|
|
+ fctiw. 8000000000000000 => 0000000000000000
|
|
+ fctiw. 7ff0000000000000 => 000000007fffffff
|
|
+ fctiw. fff0000000000000 => 0000000080000000
|
|
+ fctiw. 7ff7ffffffffffff => 0000000080000000
|
|
+ fctiw. fff7ffffffffffff => 0000000080000000
|
|
+ fctiw. 7ff8000000000000 => 0000000080000000
|
|
+ fctiw. fff8000000000000 => 0000000080000000
|
|
+
|
|
+ fctiwz. 0010000000000001 => 0000000000000000
|
|
+ fctiwz. 00100094e0000359 => 0000000000000000
|
|
+ fctiwz. 3fe0000000000001 => 0000000000000000
|
|
+ fctiwz. 3fe00094e0000359 => 0000000000000000
|
|
+ fctiwz. 8010000000000001 => 0000000000000000
|
|
+ fctiwz. 80100094e0000359 => 0000000000000000
|
|
+ fctiwz. bfe0000000000001 => 0000000000000000
|
|
+ fctiwz. bfe00094e0000359 => 0000000000000000
|
|
+ fctiwz. 0000000000000000 => 0000000000000000
|
|
+ fctiwz. 8000000000000000 => 0000000000000000
|
|
+ fctiwz. 7ff0000000000000 => 000000007fffffff
|
|
+ fctiwz. fff0000000000000 => 0000000080000000
|
|
+ fctiwz. 7ff7ffffffffffff => 0000000080000000
|
|
+ fctiwz. fff7ffffffffffff => 0000000080000000
|
|
+ fctiwz. 7ff8000000000000 => 0000000080000000
|
|
+ fctiwz. fff8000000000000 => 0000000080000000
|
|
+
|
|
+ fmr. 0010000000000001 => 0010000000000001
|
|
+ fmr. 00100094e0000359 => 00100094e0000359
|
|
+ fmr. 3fe0000000000001 => 3fe0000000000001
|
|
+ fmr. 3fe00094e0000359 => 3fe00094e0000359
|
|
+ fmr. 8010000000000001 => 8010000000000001
|
|
+ fmr. 80100094e0000359 => 80100094e0000359
|
|
+ fmr. bfe0000000000001 => bfe0000000000001
|
|
+ fmr. bfe00094e0000359 => bfe00094e0000359
|
|
+ fmr. 0000000000000000 => 0000000000000000
|
|
+ fmr. 8000000000000000 => 8000000000000000
|
|
+ fmr. 7ff0000000000000 => 7ff0000000000000
|
|
+ fmr. fff0000000000000 => fff0000000000000
|
|
+ fmr. 7ff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fmr. fff7ffffffffffff => fff7ffffffffffff
|
|
+ fmr. 7ff8000000000000 => 7ff8000000000000
|
|
+ fmr. fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fneg. 0010000000000001 => 8010000000000001
|
|
+ fneg. 00100094e0000359 => 80100094e0000359
|
|
+ fneg. 3fe0000000000001 => bfe0000000000001
|
|
+ fneg. 3fe00094e0000359 => bfe00094e0000359
|
|
+ fneg. 8010000000000001 => 0010000000000001
|
|
+ fneg. 80100094e0000359 => 00100094e0000359
|
|
+ fneg. bfe0000000000001 => 3fe0000000000001
|
|
+ fneg. bfe00094e0000359 => 3fe00094e0000359
|
|
+ fneg. 0000000000000000 => 8000000000000000
|
|
+ fneg. 8000000000000000 => 0000000000000000
|
|
+ fneg. 7ff0000000000000 => fff0000000000000
|
|
+ fneg. fff0000000000000 => 7ff0000000000000
|
|
+ fneg. 7ff7ffffffffffff => fff7ffffffffffff
|
|
+ fneg. fff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fneg. 7ff8000000000000 => fff8000000000000
|
|
+ fneg. fff8000000000000 => 7ff8000000000000
|
|
+
|
|
+ fabs. 0010000000000001 => 0010000000000001
|
|
+ fabs. 00100094e0000359 => 00100094e0000359
|
|
+ fabs. 3fe0000000000001 => 3fe0000000000001
|
|
+ fabs. 3fe00094e0000359 => 3fe00094e0000359
|
|
+ fabs. 8010000000000001 => 0010000000000001
|
|
+ fabs. 80100094e0000359 => 00100094e0000359
|
|
+ fabs. bfe0000000000001 => 3fe0000000000001
|
|
+ fabs. bfe00094e0000359 => 3fe00094e0000359
|
|
+ fabs. 0000000000000000 => 0000000000000000
|
|
+ fabs. 8000000000000000 => 0000000000000000
|
|
+ fabs. 7ff0000000000000 => 7ff0000000000000
|
|
+ fabs. fff0000000000000 => 7ff0000000000000
|
|
+ fabs. 7ff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fabs. fff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fabs. 7ff8000000000000 => 7ff8000000000000
|
|
+ fabs. fff8000000000000 => 7ff8000000000000
|
|
+
|
|
+ fnabs. 0010000000000001 => 8010000000000001
|
|
+ fnabs. 00100094e0000359 => 80100094e0000359
|
|
+ fnabs. 3fe0000000000001 => bfe0000000000001
|
|
+ fnabs. 3fe00094e0000359 => bfe00094e0000359
|
|
+ fnabs. 8010000000000001 => 8010000000000001
|
|
+ fnabs. 80100094e0000359 => 80100094e0000359
|
|
+ fnabs. bfe0000000000001 => bfe0000000000001
|
|
+ fnabs. bfe00094e0000359 => bfe00094e0000359
|
|
+ fnabs. 0000000000000000 => 8000000000000000
|
|
+ fnabs. 8000000000000000 => 8000000000000000
|
|
+ fnabs. 7ff0000000000000 => fff0000000000000
|
|
+ fnabs. fff0000000000000 => fff0000000000000
|
|
+ fnabs. 7ff7ffffffffffff => fff7ffffffffffff
|
|
+ fnabs. fff7ffffffffffff => fff7ffffffffffff
|
|
+ fnabs. 7ff8000000000000 => fff8000000000000
|
|
+ fnabs. fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fcfid. 0010000000000001 => 4330000000000001
|
|
+ fcfid. 00100094e0000359 => 43300094e0000359
|
|
+ fcfid. 3fe0000000000001 => 43cff00000000000
|
|
+ fcfid. 3fe00094e0000359 => 43cff0004a700002
|
|
+ fcfid. 8010000000000001 => c3dffc0000000000
|
|
+ fcfid. 80100094e0000359 => c3dffbffdac7ffff
|
|
+ fcfid. bfe0000000000001 => c3d0080000000000
|
|
+ fcfid. bfe00094e0000359 => c3d007ffdac7ffff
|
|
+ fcfid. 0000000000000000 => 0000000000000000
|
|
+ fcfid. 8000000000000000 => c3e0000000000000
|
|
+ fcfid. 7ff0000000000000 => 43dffc0000000000
|
|
+ fcfid. fff0000000000000 => c330000000000000
|
|
+ fcfid. 7ff7ffffffffffff => 43dffe0000000000
|
|
+ fcfid. fff7ffffffffffff => c320000000000002
|
|
+ fcfid. 7ff8000000000000 => 43dffe0000000000
|
|
+ fcfid. fff8000000000000 => c320000000000000
|
|
+
|
|
+ fctid. 0010000000000001 => 0000000000000000
|
|
+ fctid. 00100094e0000359 => 0000000000000000
|
|
+ fctid. 3fe0000000000001 => 0000000000000001
|
|
+ fctid. 3fe00094e0000359 => 0000000000000001
|
|
+ fctid. 8010000000000001 => 0000000000000000
|
|
+ fctid. 80100094e0000359 => 0000000000000000
|
|
+ fctid. bfe0000000000001 => ffffffffffffffff
|
|
+ fctid. bfe00094e0000359 => ffffffffffffffff
|
|
+ fctid. 0000000000000000 => 0000000000000000
|
|
+ fctid. 8000000000000000 => 0000000000000000
|
|
+ fctid. 7ff0000000000000 => 7fffffffffffffff
|
|
+ fctid. fff0000000000000 => 8000000000000000
|
|
+ fctid. 7ff7ffffffffffff => 8000000000000000
|
|
+ fctid. fff7ffffffffffff => 8000000000000000
|
|
+ fctid. 7ff8000000000000 => 8000000000000000
|
|
+ fctid. fff8000000000000 => 8000000000000000
|
|
+
|
|
+ fctidz. 0010000000000001 => 0000000000000000
|
|
+ fctidz. 00100094e0000359 => 0000000000000000
|
|
+ fctidz. 3fe0000000000001 => 0000000000000000
|
|
+ fctidz. 3fe00094e0000359 => 0000000000000000
|
|
+ fctidz. 8010000000000001 => 0000000000000000
|
|
+ fctidz. 80100094e0000359 => 0000000000000000
|
|
+ fctidz. bfe0000000000001 => 0000000000000000
|
|
+ fctidz. bfe00094e0000359 => 0000000000000000
|
|
+ fctidz. 0000000000000000 => 0000000000000000
|
|
+ fctidz. 8000000000000000 => 0000000000000000
|
|
+ fctidz. 7ff0000000000000 => 7fffffffffffffff
|
|
+ fctidz. fff0000000000000 => 8000000000000000
|
|
+ fctidz. 7ff7ffffffffffff => 8000000000000000
|
|
+ fctidz. fff7ffffffffffff => 8000000000000000
|
|
+ fctidz. 7ff8000000000000 => 8000000000000000
|
|
+ fctidz. fff8000000000000 => 8000000000000000
|
|
+
|
|
+PPC floating point status register manipulation insns:
|
|
+PPC floating point status register manipulation insns
|
|
+ with flags update:
|
|
+PPC float load insns
|
|
+ with one register + one 16 bits immediate args with flags update:
|
|
+ lfs 0010000000000001, 65416 => 36a0000000000000, 0
|
|
+ lfs 00100094e0000359, 65424 => c400006b20000000, 0
|
|
+ lfs 3fe0000000000001, 65432 => 36a0000000000000, 0
|
|
+ lfs 3fe00094e0000359, 65440 => c400006b20000000, 0
|
|
+ lfs 8010000000000001, 65448 => 36a0000000000000, 0
|
|
+ lfs 80100094e0000359, 65456 => c400006b20000000, 0
|
|
+ lfs bfe0000000000001, 65464 => 36a0000000000000, 0
|
|
+ lfs bfe00094e0000359, 65472 => c400006b20000000, 0
|
|
+ lfs 0000000000000000, 65480 => 0000000000000000, 0
|
|
+ lfs 8000000000000000, 65488 => 0000000000000000, 0
|
|
+ lfs 7ff0000000000000, 65496 => 0000000000000000, 0
|
|
+ lfs fff0000000000000, 65504 => 0000000000000000, 0
|
|
+ lfs 7ff7ffffffffffff, 65512 => ffffffffe0000000, 0
|
|
+ lfs fff7ffffffffffff, 65520 => ffffffffe0000000, 0
|
|
+ lfs 7ff8000000000000, 65528 => 0000000000000000, 0
|
|
+ lfs 0010000000000001, 0 => 36a0000000000000, 0
|
|
+ lfs 00100094e0000359, 8 => c400006b20000000, 0
|
|
+ lfs 3fe0000000000001, 16 => 36a0000000000000, 0
|
|
+ lfs 3fe00094e0000359, 24 => c400006b20000000, 0
|
|
+ lfs 8010000000000001, 32 => 36a0000000000000, 0
|
|
+ lfs 80100094e0000359, 40 => c400006b20000000, 0
|
|
+ lfs bfe0000000000001, 48 => 36a0000000000000, 0
|
|
+ lfs bfe00094e0000359, 56 => c400006b20000000, 0
|
|
+ lfs 0000000000000000, 64 => 0000000000000000, 0
|
|
+ lfs 8000000000000000, 72 => 0000000000000000, 0
|
|
+ lfs 7ff0000000000000, 80 => 0000000000000000, 0
|
|
+ lfs fff0000000000000, 88 => 0000000000000000, 0
|
|
+ lfs 7ff7ffffffffffff, 96 => ffffffffe0000000, 0
|
|
+ lfs fff7ffffffffffff, 104 => ffffffffe0000000, 0
|
|
+ lfs 7ff8000000000000, 112 => 0000000000000000, 0
|
|
+ lfs fff8000000000000, 120 => 0000000000000000, 0
|
|
+
|
|
+ lfsu 0010000000000001, 65416 => 36a0000000000000, -120
|
|
+ lfsu 00100094e0000359, 65424 => c400006b20000000, -112
|
|
+ lfsu 3fe0000000000001, 65432 => 36a0000000000000, -104
|
|
+ lfsu 3fe00094e0000359, 65440 => c400006b20000000, -96
|
|
+ lfsu 8010000000000001, 65448 => 36a0000000000000, -88
|
|
+ lfsu 80100094e0000359, 65456 => c400006b20000000, -80
|
|
+ lfsu bfe0000000000001, 65464 => 36a0000000000000, -72
|
|
+ lfsu bfe00094e0000359, 65472 => c400006b20000000, -64
|
|
+ lfsu 0000000000000000, 65480 => 0000000000000000, -56
|
|
+ lfsu 8000000000000000, 65488 => 0000000000000000, -48
|
|
+ lfsu 7ff0000000000000, 65496 => 0000000000000000, -40
|
|
+ lfsu fff0000000000000, 65504 => 0000000000000000, -32
|
|
+ lfsu 7ff7ffffffffffff, 65512 => ffffffffe0000000, -24
|
|
+ lfsu fff7ffffffffffff, 65520 => ffffffffe0000000, -16
|
|
+ lfsu 7ff8000000000000, 65528 => 0000000000000000, -8
|
|
+ lfsu 0010000000000001, 0 => 36a0000000000000, 0
|
|
+ lfsu 00100094e0000359, 8 => c400006b20000000, 8
|
|
+ lfsu 3fe0000000000001, 16 => 36a0000000000000, 16
|
|
+ lfsu 3fe00094e0000359, 24 => c400006b20000000, 24
|
|
+ lfsu 8010000000000001, 32 => 36a0000000000000, 32
|
|
+ lfsu 80100094e0000359, 40 => c400006b20000000, 40
|
|
+ lfsu bfe0000000000001, 48 => 36a0000000000000, 48
|
|
+ lfsu bfe00094e0000359, 56 => c400006b20000000, 56
|
|
+ lfsu 0000000000000000, 64 => 0000000000000000, 64
|
|
+ lfsu 8000000000000000, 72 => 0000000000000000, 72
|
|
+ lfsu 7ff0000000000000, 80 => 0000000000000000, 80
|
|
+ lfsu fff0000000000000, 88 => 0000000000000000, 88
|
|
+ lfsu 7ff7ffffffffffff, 96 => ffffffffe0000000, 96
|
|
+ lfsu fff7ffffffffffff, 104 => ffffffffe0000000, 104
|
|
+ lfsu 7ff8000000000000, 112 => 0000000000000000, 112
|
|
+ lfsu fff8000000000000, 120 => 0000000000000000, 120
|
|
+
|
|
+ lfd 0010000000000001, 65416 => 0010000000000001, 0
|
|
+ lfd 00100094e0000359, 65424 => 00100094e0000359, 0
|
|
+ lfd 3fe0000000000001, 65432 => 3fe0000000000001, 0
|
|
+ lfd 3fe00094e0000359, 65440 => 3fe00094e0000359, 0
|
|
+ lfd 8010000000000001, 65448 => 8010000000000001, 0
|
|
+ lfd 80100094e0000359, 65456 => 80100094e0000359, 0
|
|
+ lfd bfe0000000000001, 65464 => bfe0000000000001, 0
|
|
+ lfd bfe00094e0000359, 65472 => bfe00094e0000359, 0
|
|
+ lfd 0000000000000000, 65480 => 0000000000000000, 0
|
|
+ lfd 8000000000000000, 65488 => 8000000000000000, 0
|
|
+ lfd 7ff0000000000000, 65496 => 7ff0000000000000, 0
|
|
+ lfd fff0000000000000, 65504 => fff0000000000000, 0
|
|
+ lfd 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, 0
|
|
+ lfd fff7ffffffffffff, 65520 => fff7ffffffffffff, 0
|
|
+ lfd 7ff8000000000000, 65528 => 7ff8000000000000, 0
|
|
+ lfd 0010000000000001, 0 => 0010000000000001, 0
|
|
+ lfd 00100094e0000359, 8 => 00100094e0000359, 0
|
|
+ lfd 3fe0000000000001, 16 => 3fe0000000000001, 0
|
|
+ lfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0
|
|
+ lfd 8010000000000001, 32 => 8010000000000001, 0
|
|
+ lfd 80100094e0000359, 40 => 80100094e0000359, 0
|
|
+ lfd bfe0000000000001, 48 => bfe0000000000001, 0
|
|
+ lfd bfe00094e0000359, 56 => bfe00094e0000359, 0
|
|
+ lfd 0000000000000000, 64 => 0000000000000000, 0
|
|
+ lfd 8000000000000000, 72 => 8000000000000000, 0
|
|
+ lfd 7ff0000000000000, 80 => 7ff0000000000000, 0
|
|
+ lfd fff0000000000000, 88 => fff0000000000000, 0
|
|
+ lfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
|
|
+ lfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0
|
|
+ lfd 7ff8000000000000, 112 => 7ff8000000000000, 0
|
|
+ lfd fff8000000000000, 120 => fff8000000000000, 0
|
|
+
|
|
+ lfdu 0010000000000001, 65416 => 0010000000000001, -120
|
|
+ lfdu 00100094e0000359, 65424 => 00100094e0000359, -112
|
|
+ lfdu 3fe0000000000001, 65432 => 3fe0000000000001, -104
|
|
+ lfdu 3fe00094e0000359, 65440 => 3fe00094e0000359, -96
|
|
+ lfdu 8010000000000001, 65448 => 8010000000000001, -88
|
|
+ lfdu 80100094e0000359, 65456 => 80100094e0000359, -80
|
|
+ lfdu bfe0000000000001, 65464 => bfe0000000000001, -72
|
|
+ lfdu bfe00094e0000359, 65472 => bfe00094e0000359, -64
|
|
+ lfdu 0000000000000000, 65480 => 0000000000000000, -56
|
|
+ lfdu 8000000000000000, 65488 => 8000000000000000, -48
|
|
+ lfdu 7ff0000000000000, 65496 => 7ff0000000000000, -40
|
|
+ lfdu fff0000000000000, 65504 => fff0000000000000, -32
|
|
+ lfdu 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, -24
|
|
+ lfdu fff7ffffffffffff, 65520 => fff7ffffffffffff, -16
|
|
+ lfdu 7ff8000000000000, 65528 => 7ff8000000000000, -8
|
|
+ lfdu 0010000000000001, 0 => 0010000000000001, 0
|
|
+ lfdu 00100094e0000359, 8 => 00100094e0000359, 8
|
|
+ lfdu 3fe0000000000001, 16 => 3fe0000000000001, 16
|
|
+ lfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24
|
|
+ lfdu 8010000000000001, 32 => 8010000000000001, 32
|
|
+ lfdu 80100094e0000359, 40 => 80100094e0000359, 40
|
|
+ lfdu bfe0000000000001, 48 => bfe0000000000001, 48
|
|
+ lfdu bfe00094e0000359, 56 => bfe00094e0000359, 56
|
|
+ lfdu 0000000000000000, 64 => 0000000000000000, 64
|
|
+ lfdu 8000000000000000, 72 => 8000000000000000, 72
|
|
+ lfdu 7ff0000000000000, 80 => 7ff0000000000000, 80
|
|
+ lfdu fff0000000000000, 88 => fff0000000000000, 88
|
|
+ lfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
|
|
+ lfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104
|
|
+ lfdu 7ff8000000000000, 112 => 7ff8000000000000, 112
|
|
+ lfdu fff8000000000000, 120 => fff8000000000000, 120
|
|
+
|
|
+PPC float load insns with two register args:
|
|
+ lfsx 0010000000000001, -120 => 36a0000000000000, 0
|
|
+ lfsx 00100094e0000359, -112 => c400006b20000000, 0
|
|
+ lfsx 3fe0000000000001, -104 => 36a0000000000000, 0
|
|
+ lfsx 3fe00094e0000359, -96 => c400006b20000000, 0
|
|
+ lfsx 8010000000000001, -88 => 36a0000000000000, 0
|
|
+ lfsx 80100094e0000359, -80 => c400006b20000000, 0
|
|
+ lfsx bfe0000000000001, -72 => 36a0000000000000, 0
|
|
+ lfsx bfe00094e0000359, -64 => c400006b20000000, 0
|
|
+ lfsx 0000000000000000, -56 => 0000000000000000, 0
|
|
+ lfsx 8000000000000000, -48 => 0000000000000000, 0
|
|
+ lfsx 7ff0000000000000, -40 => 0000000000000000, 0
|
|
+ lfsx fff0000000000000, -32 => 0000000000000000, 0
|
|
+ lfsx 7ff7ffffffffffff, -24 => ffffffffe0000000, 0
|
|
+ lfsx fff7ffffffffffff, -16 => ffffffffe0000000, 0
|
|
+ lfsx 7ff8000000000000, -8 => 0000000000000000, 0
|
|
+ lfsx 0010000000000001, 0 => 36a0000000000000, 0
|
|
+ lfsx 00100094e0000359, 8 => c400006b20000000, 0
|
|
+ lfsx 3fe0000000000001, 16 => 36a0000000000000, 0
|
|
+ lfsx 3fe00094e0000359, 24 => c400006b20000000, 0
|
|
+ lfsx 8010000000000001, 32 => 36a0000000000000, 0
|
|
+ lfsx 80100094e0000359, 40 => c400006b20000000, 0
|
|
+ lfsx bfe0000000000001, 48 => 36a0000000000000, 0
|
|
+ lfsx bfe00094e0000359, 56 => c400006b20000000, 0
|
|
+ lfsx 0000000000000000, 64 => 0000000000000000, 0
|
|
+ lfsx 8000000000000000, 72 => 0000000000000000, 0
|
|
+ lfsx 7ff0000000000000, 80 => 0000000000000000, 0
|
|
+ lfsx fff0000000000000, 88 => 0000000000000000, 0
|
|
+ lfsx 7ff7ffffffffffff, 96 => ffffffffe0000000, 0
|
|
+ lfsx fff7ffffffffffff, 104 => ffffffffe0000000, 0
|
|
+ lfsx 7ff8000000000000, 112 => 0000000000000000, 0
|
|
+ lfsx fff8000000000000, 120 => 0000000000000000, 0
|
|
+
|
|
+ lfsux 0010000000000001, -120 => 36a0000000000000, -120
|
|
+ lfsux 00100094e0000359, -112 => c400006b20000000, -112
|
|
+ lfsux 3fe0000000000001, -104 => 36a0000000000000, -104
|
|
+ lfsux 3fe00094e0000359, -96 => c400006b20000000, -96
|
|
+ lfsux 8010000000000001, -88 => 36a0000000000000, -88
|
|
+ lfsux 80100094e0000359, -80 => c400006b20000000, -80
|
|
+ lfsux bfe0000000000001, -72 => 36a0000000000000, -72
|
|
+ lfsux bfe00094e0000359, -64 => c400006b20000000, -64
|
|
+ lfsux 0000000000000000, -56 => 0000000000000000, -56
|
|
+ lfsux 8000000000000000, -48 => 0000000000000000, -48
|
|
+ lfsux 7ff0000000000000, -40 => 0000000000000000, -40
|
|
+ lfsux fff0000000000000, -32 => 0000000000000000, -32
|
|
+ lfsux 7ff7ffffffffffff, -24 => ffffffffe0000000, -24
|
|
+ lfsux fff7ffffffffffff, -16 => ffffffffe0000000, -16
|
|
+ lfsux 7ff8000000000000, -8 => 0000000000000000, -8
|
|
+ lfsux 0010000000000001, 0 => 36a0000000000000, 0
|
|
+ lfsux 00100094e0000359, 8 => c400006b20000000, 8
|
|
+ lfsux 3fe0000000000001, 16 => 36a0000000000000, 16
|
|
+ lfsux 3fe00094e0000359, 24 => c400006b20000000, 24
|
|
+ lfsux 8010000000000001, 32 => 36a0000000000000, 32
|
|
+ lfsux 80100094e0000359, 40 => c400006b20000000, 40
|
|
+ lfsux bfe0000000000001, 48 => 36a0000000000000, 48
|
|
+ lfsux bfe00094e0000359, 56 => c400006b20000000, 56
|
|
+ lfsux 0000000000000000, 64 => 0000000000000000, 64
|
|
+ lfsux 8000000000000000, 72 => 0000000000000000, 72
|
|
+ lfsux 7ff0000000000000, 80 => 0000000000000000, 80
|
|
+ lfsux fff0000000000000, 88 => 0000000000000000, 88
|
|
+ lfsux 7ff7ffffffffffff, 96 => ffffffffe0000000, 96
|
|
+ lfsux fff7ffffffffffff, 104 => ffffffffe0000000, 104
|
|
+ lfsux 7ff8000000000000, 112 => 0000000000000000, 112
|
|
+ lfsux fff8000000000000, 120 => 0000000000000000, 120
|
|
+
|
|
+ lfdx 0010000000000001, -120 => 0010000000000001, 0
|
|
+ lfdx 00100094e0000359, -112 => 00100094e0000359, 0
|
|
+ lfdx 3fe0000000000001, -104 => 3fe0000000000001, 0
|
|
+ lfdx 3fe00094e0000359, -96 => 3fe00094e0000359, 0
|
|
+ lfdx 8010000000000001, -88 => 8010000000000001, 0
|
|
+ lfdx 80100094e0000359, -80 => 80100094e0000359, 0
|
|
+ lfdx bfe0000000000001, -72 => bfe0000000000001, 0
|
|
+ lfdx bfe00094e0000359, -64 => bfe00094e0000359, 0
|
|
+ lfdx 0000000000000000, -56 => 0000000000000000, 0
|
|
+ lfdx 8000000000000000, -48 => 8000000000000000, 0
|
|
+ lfdx 7ff0000000000000, -40 => 7ff0000000000000, 0
|
|
+ lfdx fff0000000000000, -32 => fff0000000000000, 0
|
|
+ lfdx 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0
|
|
+ lfdx fff7ffffffffffff, -16 => fff7ffffffffffff, 0
|
|
+ lfdx 7ff8000000000000, -8 => 7ff8000000000000, 0
|
|
+ lfdx 0010000000000001, 0 => 0010000000000001, 0
|
|
+ lfdx 00100094e0000359, 8 => 00100094e0000359, 0
|
|
+ lfdx 3fe0000000000001, 16 => 3fe0000000000001, 0
|
|
+ lfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0
|
|
+ lfdx 8010000000000001, 32 => 8010000000000001, 0
|
|
+ lfdx 80100094e0000359, 40 => 80100094e0000359, 0
|
|
+ lfdx bfe0000000000001, 48 => bfe0000000000001, 0
|
|
+ lfdx bfe00094e0000359, 56 => bfe00094e0000359, 0
|
|
+ lfdx 0000000000000000, 64 => 0000000000000000, 0
|
|
+ lfdx 8000000000000000, 72 => 8000000000000000, 0
|
|
+ lfdx 7ff0000000000000, 80 => 7ff0000000000000, 0
|
|
+ lfdx fff0000000000000, 88 => fff0000000000000, 0
|
|
+ lfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
|
|
+ lfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0
|
|
+ lfdx 7ff8000000000000, 112 => 7ff8000000000000, 0
|
|
+ lfdx fff8000000000000, 120 => fff8000000000000, 0
|
|
+
|
|
+ lfdux 0010000000000001, -120 => 0010000000000001, -120
|
|
+ lfdux 00100094e0000359, -112 => 00100094e0000359, -112
|
|
+ lfdux 3fe0000000000001, -104 => 3fe0000000000001, -104
|
|
+ lfdux 3fe00094e0000359, -96 => 3fe00094e0000359, -96
|
|
+ lfdux 8010000000000001, -88 => 8010000000000001, -88
|
|
+ lfdux 80100094e0000359, -80 => 80100094e0000359, -80
|
|
+ lfdux bfe0000000000001, -72 => bfe0000000000001, -72
|
|
+ lfdux bfe00094e0000359, -64 => bfe00094e0000359, -64
|
|
+ lfdux 0000000000000000, -56 => 0000000000000000, -56
|
|
+ lfdux 8000000000000000, -48 => 8000000000000000, -48
|
|
+ lfdux 7ff0000000000000, -40 => 7ff0000000000000, -40
|
|
+ lfdux fff0000000000000, -32 => fff0000000000000, -32
|
|
+ lfdux 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24
|
|
+ lfdux fff7ffffffffffff, -16 => fff7ffffffffffff, -16
|
|
+ lfdux 7ff8000000000000, -8 => 7ff8000000000000, -8
|
|
+ lfdux 0010000000000001, 0 => 0010000000000001, 0
|
|
+ lfdux 00100094e0000359, 8 => 00100094e0000359, 8
|
|
+ lfdux 3fe0000000000001, 16 => 3fe0000000000001, 16
|
|
+ lfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24
|
|
+ lfdux 8010000000000001, 32 => 8010000000000001, 32
|
|
+ lfdux 80100094e0000359, 40 => 80100094e0000359, 40
|
|
+ lfdux bfe0000000000001, 48 => bfe0000000000001, 48
|
|
+ lfdux bfe00094e0000359, 56 => bfe00094e0000359, 56
|
|
+ lfdux 0000000000000000, 64 => 0000000000000000, 64
|
|
+ lfdux 8000000000000000, 72 => 8000000000000000, 72
|
|
+ lfdux 7ff0000000000000, 80 => 7ff0000000000000, 80
|
|
+ lfdux fff0000000000000, 88 => fff0000000000000, 88
|
|
+ lfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
|
|
+ lfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104
|
|
+ lfdux 7ff8000000000000, 112 => 7ff8000000000000, 112
|
|
+ lfdux fff8000000000000, 120 => fff8000000000000, 120
|
|
+
|
|
+PPC float store insns
|
|
+ with one register + one 16 bits immediate args with flags update:
|
|
+ stfs 0010000000000001, -56 => 0000000000000000, 0
|
|
+ stfs 00100094e0000359, -48 => 0000000000000000, 0
|
|
+ stfs 3fe0000000000001, -40 => 000000003f000000, 0
|
|
+ stfs 3fe00094e0000359, -32 => 000000003f0004a7, 0
|
|
+ stfs 8010000000000001, -24 => 0000000080000000, 0
|
|
+ stfs 80100094e0000359, -16 => 0000000080000000, 0
|
|
+ stfs bfe0000000000001, -8 => 00000000bf000000, 0
|
|
+ stfs 0010000000000001, 0 => 0000000000000000, 0
|
|
+ stfs 00100094e0000359, 8 => 0000000000000000, 0
|
|
+ stfs 3fe0000000000001, 16 => 000000003f000000, 0
|
|
+ stfs 3fe00094e0000359, 24 => 000000003f0004a7, 0
|
|
+ stfs 8010000000000001, 32 => 0000000080000000, 0
|
|
+ stfs 80100094e0000359, 40 => 0000000080000000, 0
|
|
+ stfs bfe0000000000001, 48 => 00000000bf000000, 0
|
|
+ stfs bfe00094e0000359, 56 => 00000000bf0004a7, 0
|
|
+
|
|
+ stfsu 0010000000000001, -56 => 0000000000000000, -56
|
|
+ stfsu 00100094e0000359, -48 => 0000000000000000, -48
|
|
+ stfsu 3fe0000000000001, -40 => 000000003f000000, -40
|
|
+ stfsu 3fe00094e0000359, -32 => 000000003f0004a7, -32
|
|
+ stfsu 8010000000000001, -24 => 0000000080000000, -24
|
|
+ stfsu 80100094e0000359, -16 => 0000000080000000, -16
|
|
+ stfsu bfe0000000000001, -8 => 00000000bf000000, -8
|
|
+ stfsu 0010000000000001, 0 => 0000000000000000, 0
|
|
+ stfsu 00100094e0000359, 8 => 0000000000000000, 8
|
|
+ stfsu 3fe0000000000001, 16 => 000000003f000000, 16
|
|
+ stfsu 3fe00094e0000359, 24 => 000000003f0004a7, 24
|
|
+ stfsu 8010000000000001, 32 => 0000000080000000, 32
|
|
+ stfsu 80100094e0000359, 40 => 0000000080000000, 40
|
|
+ stfsu bfe0000000000001, 48 => 00000000bf000000, 48
|
|
+ stfsu bfe00094e0000359, 56 => 00000000bf0004a7, 56
|
|
+
|
|
+ stfd 0010000000000001, -120 => 0010000000000001, 0
|
|
+ stfd 00100094e0000359, -112 => 00100094e0000359, 0
|
|
+ stfd 3fe0000000000001, -104 => 3fe0000000000001, 0
|
|
+ stfd 3fe00094e0000359, -96 => 3fe00094e0000359, 0
|
|
+ stfd 8010000000000001, -88 => 8010000000000001, 0
|
|
+ stfd 80100094e0000359, -80 => 80100094e0000359, 0
|
|
+ stfd bfe0000000000001, -72 => bfe0000000000001, 0
|
|
+ stfd bfe00094e0000359, -64 => bfe00094e0000359, 0
|
|
+ stfd 0000000000000000, -56 => 0000000000000000, 0
|
|
+ stfd 8000000000000000, -48 => 8000000000000000, 0
|
|
+ stfd 7ff0000000000000, -40 => 7ff0000000000000, 0
|
|
+ stfd fff0000000000000, -32 => fff0000000000000, 0
|
|
+ stfd 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0
|
|
+ stfd fff7ffffffffffff, -16 => fff7ffffffffffff, 0
|
|
+ stfd 7ff8000000000000, -8 => 7ff8000000000000, 0
|
|
+ stfd 0010000000000001, 0 => 0010000000000001, 0
|
|
+ stfd 00100094e0000359, 8 => 00100094e0000359, 0
|
|
+ stfd 3fe0000000000001, 16 => 3fe0000000000001, 0
|
|
+ stfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0
|
|
+ stfd 8010000000000001, 32 => 8010000000000001, 0
|
|
+ stfd 80100094e0000359, 40 => 80100094e0000359, 0
|
|
+ stfd bfe0000000000001, 48 => bfe0000000000001, 0
|
|
+ stfd bfe00094e0000359, 56 => bfe00094e0000359, 0
|
|
+ stfd 0000000000000000, 64 => 0000000000000000, 0
|
|
+ stfd 8000000000000000, 72 => 8000000000000000, 0
|
|
+ stfd 7ff0000000000000, 80 => 7ff0000000000000, 0
|
|
+ stfd fff0000000000000, 88 => fff0000000000000, 0
|
|
+ stfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
|
|
+ stfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0
|
|
+ stfd 7ff8000000000000, 112 => 7ff8000000000000, 0
|
|
+ stfd fff8000000000000, 120 => fff8000000000000, 0
|
|
+
|
|
+ stfdu 0010000000000001, -120 => 0010000000000001, -120
|
|
+ stfdu 00100094e0000359, -112 => 00100094e0000359, -112
|
|
+ stfdu 3fe0000000000001, -104 => 3fe0000000000001, -104
|
|
+ stfdu 3fe00094e0000359, -96 => 3fe00094e0000359, -96
|
|
+ stfdu 8010000000000001, -88 => 8010000000000001, -88
|
|
+ stfdu 80100094e0000359, -80 => 80100094e0000359, -80
|
|
+ stfdu bfe0000000000001, -72 => bfe0000000000001, -72
|
|
+ stfdu bfe00094e0000359, -64 => bfe00094e0000359, -64
|
|
+ stfdu 0000000000000000, -56 => 0000000000000000, -56
|
|
+ stfdu 8000000000000000, -48 => 8000000000000000, -48
|
|
+ stfdu 7ff0000000000000, -40 => 7ff0000000000000, -40
|
|
+ stfdu fff0000000000000, -32 => fff0000000000000, -32
|
|
+ stfdu 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24
|
|
+ stfdu fff7ffffffffffff, -16 => fff7ffffffffffff, -16
|
|
+ stfdu 7ff8000000000000, -8 => 7ff8000000000000, -8
|
|
+ stfdu 0010000000000001, 0 => 0010000000000001, 0
|
|
+ stfdu 00100094e0000359, 8 => 00100094e0000359, 8
|
|
+ stfdu 3fe0000000000001, 16 => 3fe0000000000001, 16
|
|
+ stfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24
|
|
+ stfdu 8010000000000001, 32 => 8010000000000001, 32
|
|
+ stfdu 80100094e0000359, 40 => 80100094e0000359, 40
|
|
+ stfdu bfe0000000000001, 48 => bfe0000000000001, 48
|
|
+ stfdu bfe00094e0000359, 56 => bfe00094e0000359, 56
|
|
+ stfdu 0000000000000000, 64 => 0000000000000000, 64
|
|
+ stfdu 8000000000000000, 72 => 8000000000000000, 72
|
|
+ stfdu 7ff0000000000000, 80 => 7ff0000000000000, 80
|
|
+ stfdu fff0000000000000, 88 => fff0000000000000, 88
|
|
+ stfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
|
|
+ stfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104
|
|
+ stfdu 7ff8000000000000, 112 => 7ff8000000000000, 112
|
|
+ stfdu fff8000000000000, 120 => fff8000000000000, 120
|
|
+
|
|
+PPC float store insns with three register args:
|
|
+ stfsx 0010000000000001, 0 => 0000000000000000, 0
|
|
+ stfsx 00100094e0000359, 8 => 0000000000000000, 0
|
|
+ stfsx 3fe0000000000001, 16 => 000000003f000000, 0
|
|
+ stfsx 3fe00094e0000359, 24 => 000000003f0004a7, 0
|
|
+ stfsx 8010000000000001, 32 => 0000000080000000, 0
|
|
+ stfsx 80100094e0000359, 40 => 0000000080000000, 0
|
|
+ stfsx bfe0000000000001, 48 => 00000000bf000000, 0
|
|
+ stfsx bfe00094e0000359, 56 => 00000000bf0004a7, 0
|
|
+
|
|
+ stfsux 0010000000000001, 0 => 0000000000000000, 0
|
|
+ stfsux 00100094e0000359, 8 => 0000000000000000, 8
|
|
+ stfsux 3fe0000000000001, 16 => 000000003f000000, 16
|
|
+ stfsux 3fe00094e0000359, 24 => 000000003f0004a7, 24
|
|
+ stfsux 8010000000000001, 32 => 0000000080000000, 32
|
|
+ stfsux 80100094e0000359, 40 => 0000000080000000, 40
|
|
+ stfsux bfe0000000000001, 48 => 00000000bf000000, 48
|
|
+ stfsux bfe00094e0000359, 56 => 00000000bf0004a7, 56
|
|
+
|
|
+ stfdx 0010000000000001, 0 => 0010000000000001, 0
|
|
+ stfdx 00100094e0000359, 8 => 00100094e0000359, 0
|
|
+ stfdx 3fe0000000000001, 16 => 3fe0000000000001, 0
|
|
+ stfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0
|
|
+ stfdx 8010000000000001, 32 => 8010000000000001, 0
|
|
+ stfdx 80100094e0000359, 40 => 80100094e0000359, 0
|
|
+ stfdx bfe0000000000001, 48 => bfe0000000000001, 0
|
|
+ stfdx bfe00094e0000359, 56 => bfe00094e0000359, 0
|
|
+ stfdx 0000000000000000, 64 => 0000000000000000, 0
|
|
+ stfdx 8000000000000000, 72 => 8000000000000000, 0
|
|
+ stfdx 7ff0000000000000, 80 => 7ff0000000000000, 0
|
|
+ stfdx fff0000000000000, 88 => fff0000000000000, 0
|
|
+ stfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
|
|
+ stfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0
|
|
+ stfdx 7ff8000000000000, 112 => 7ff8000000000000, 0
|
|
+ stfdx fff8000000000000, 120 => fff8000000000000, 0
|
|
+
|
|
+ stfdux 0010000000000001, 0 => 0010000000000001, 0
|
|
+ stfdux 00100094e0000359, 8 => 00100094e0000359, 8
|
|
+ stfdux 3fe0000000000001, 16 => 3fe0000000000001, 16
|
|
+ stfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24
|
|
+ stfdux 8010000000000001, 32 => 8010000000000001, 32
|
|
+ stfdux 80100094e0000359, 40 => 80100094e0000359, 40
|
|
+ stfdux bfe0000000000001, 48 => bfe0000000000001, 48
|
|
+ stfdux bfe00094e0000359, 56 => bfe00094e0000359, 56
|
|
+ stfdux 0000000000000000, 64 => 0000000000000000, 64
|
|
+ stfdux 8000000000000000, 72 => 8000000000000000, 72
|
|
+ stfdux 7ff0000000000000, 80 => 7ff0000000000000, 80
|
|
+ stfdux fff0000000000000, 88 => fff0000000000000, 88
|
|
+ stfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
|
|
+ stfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104
|
|
+ stfdux 7ff8000000000000, 112 => 7ff8000000000000, 112
|
|
+ stfdux fff8000000000000, 120 => fff8000000000000, 120
|
|
+
|
|
+All done. Tested 77 different instructions
|
|
Index: none/tests/ppc64/std_reg_imm.stdout.exp-LE
|
|
===================================================================
|
|
--- /dev/null
|
|
+++ none/tests/ppc64/std_reg_imm.stdout.exp-LE
|
|
@@ -0,0 +1 @@
|
|
+....8877665544332211............
|
|
Index: none/tests/ppc64/jm-int.stdout.exp-LE
|
|
===================================================================
|
|
--- /dev/null
|
|
+++ none/tests/ppc64/jm-int.stdout.exp-LE
|
|
@@ -0,0 +1,4773 @@
|
|
+PPC integer arith insns with two args:
|
|
+ add 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ add 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
|
|
+ add 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+ add 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
|
|
+ add 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000)
|
|
+ add 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 00000000)
|
|
+ add ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ add ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 00000000)
|
|
+ add ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 00000000)
|
|
+
|
|
+ addo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ addo 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
|
|
+ addo 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+ addo 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
|
|
+ addo 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000)
|
|
+ addo 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 00000000)
|
|
+ addo ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ addo ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 00000000)
|
|
+ addo ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 00000000)
|
|
+
|
|
+ addc 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ addc 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
|
|
+ addc 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+ addc 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
|
|
+ addc 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000)
|
|
+ addc 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 20000000)
|
|
+ addc ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ addc ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
|
|
+ addc ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 20000000)
|
|
+
|
|
+ addco 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ addco 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
|
|
+ addco 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+ addco 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
|
|
+ addco 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000)
|
|
+ addco 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 20000000)
|
|
+ addco ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ addco ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
|
|
+ addco ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 20000000)
|
|
+
|
|
+ divw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ divw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ divw 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
|
|
+ divw 0000001cbe991def, ffffffffffffffff => 000000004166e211 (00000000 00000000)
|
|
+ divw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ divw ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
|
|
+
|
|
+ divwo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ divwo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ divwo 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
|
|
+ divwo 0000001cbe991def, ffffffffffffffff => 000000004166e211 (00000000 00000000)
|
|
+ divwo ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ divwo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
|
|
+
|
|
+ divwu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ divwu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ divwu 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
|
|
+ divwu 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ divwu ffffffffffffffff, 0000001cbe991def => 0000000000000001 (00000000 00000000)
|
|
+ divwu ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
|
|
+
|
|
+ divwuo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ divwuo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ divwuo 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
|
|
+ divwuo 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ divwuo ffffffffffffffff, 0000001cbe991def => 0000000000000001 (00000000 00000000)
|
|
+ divwuo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
|
|
+
|
|
+ mulhw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mulhw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ mulhw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ mulhw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mulhw 0000001cbe991def, 0000001cbe991def => 0000000010b56825 (00000000 00000000)
|
|
+ mulhw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ mulhw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mulhw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ mulhw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+
|
|
+ mulhwu 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mulhwu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ mulhwu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ mulhwu 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mulhwu 0000001cbe991def, 0000001cbe991def => 000000008de7a403 (00000000 00000000)
|
|
+ mulhwu 0000001cbe991def, ffffffffffffffff => 00000000be991dee (00000000 00000000)
|
|
+ mulhwu ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mulhwu ffffffffffffffff, 0000001cbe991def => 00000000be991dee (00000000 00000000)
|
|
+ mulhwu ffffffffffffffff, ffffffffffffffff => 00000000fffffffe (00000000 00000000)
|
|
+
|
|
+ mullw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mullw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ mullw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ mullw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mullw 0000001cbe991def, 0000001cbe991def => 10b568258f2e0521 (00000000 00000000)
|
|
+ mullw 0000001cbe991def, ffffffffffffffff => 000000004166e211 (00000000 00000000)
|
|
+ mullw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mullw ffffffffffffffff, 0000001cbe991def => 000000004166e211 (00000000 00000000)
|
|
+ mullw ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
|
|
+
|
|
+ mullwo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mullwo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ mullwo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ mullwo 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mullwo 0000001cbe991def, 0000001cbe991def => 10b568258f2e0521 (00000000 c0000000)
|
|
+ mullwo 0000001cbe991def, ffffffffffffffff => 000000004166e211 (00000000 00000000)
|
|
+ mullwo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mullwo ffffffffffffffff, 0000001cbe991def => 000000004166e211 (00000000 00000000)
|
|
+ mullwo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
|
|
+
|
|
+ subf 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ subf 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
|
|
+ subf 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+ subf 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000)
|
|
+ subf 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ subf 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000)
|
|
+ subf ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000)
|
|
+ subf ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
|
|
+ subf ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+
|
|
+ subfo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ subfo 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
|
|
+ subfo 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+ subfo 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000)
|
|
+ subfo 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ subfo 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000)
|
|
+ subfo ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000)
|
|
+ subfo ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
|
|
+ subfo ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+
|
|
+ subfc 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 20000000)
|
|
+ subfc 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 20000000)
|
|
+ subfc 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
|
|
+ subfc 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000)
|
|
+ subfc 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 20000000)
|
|
+ subfc 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 20000000)
|
|
+ subfc ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000)
|
|
+ subfc ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
|
|
+ subfc ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 20000000)
|
|
+
|
|
+ subfco 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 20000000)
|
|
+ subfco 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 20000000)
|
|
+ subfco 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
|
|
+ subfco 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000)
|
|
+ subfco 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 20000000)
|
|
+ subfco 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 20000000)
|
|
+ subfco ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000)
|
|
+ subfco ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
|
|
+ subfco ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 20000000)
|
|
+
|
|
+ mulhd 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mulhd 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ mulhd 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ mulhd 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mulhd 0000001cbe991def, 0000001cbe991def => 000000000000033a (00000000 00000000)
|
|
+ mulhd 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+ mulhd ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mulhd ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
|
|
+ mulhd ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+
|
|
+ mulhdu 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mulhdu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ mulhdu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ mulhdu 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mulhdu 0000001cbe991def, 0000001cbe991def => 000000000000033a (00000000 00000000)
|
|
+ mulhdu 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 00000000)
|
|
+ mulhdu ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mulhdu ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 00000000)
|
|
+ mulhdu ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 00000000)
|
|
+
|
|
+ mulld 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mulld 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ mulld 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ mulld 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mulld 0000001cbe991def, 0000001cbe991def => 3f66304b8f2e0521 (00000000 00000000)
|
|
+ mulld 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (00000000 00000000)
|
|
+ mulld ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mulld ffffffffffffffff, 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
|
|
+ mulld ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
|
|
+
|
|
+ mulldo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mulldo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ mulldo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ mulldo 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mulldo 0000001cbe991def, 0000001cbe991def => 3f66304b8f2e0521 (00000000 c0000000)
|
|
+ mulldo 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (00000000 00000000)
|
|
+ mulldo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ mulldo ffffffffffffffff, 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
|
|
+ mulldo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
|
|
+
|
|
+ divd 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ divd 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ divd 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ divd 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ divd 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
|
|
+ divd 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (00000000 00000000)
|
|
+ divd ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ divd ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ divd ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
|
|
+
|
|
+ divdu 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ divdu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ divdu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ divdu 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ divdu 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
|
|
+ divdu 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ divdu ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ divdu ffffffffffffffff, 0000001cbe991def => 0000000008e7f283 (00000000 00000000)
|
|
+ divdu ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
|
|
+
|
|
+ divdo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 c0000000)
|
|
+ divdo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ divdo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ divdo 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 c0000000)
|
|
+ divdo 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
|
|
+ divdo 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (00000000 00000000)
|
|
+ divdo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 c0000000)
|
|
+ divdo ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ divdo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
|
|
+
|
|
+ divduo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 c0000000)
|
|
+ divduo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ divduo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ divduo 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 c0000000)
|
|
+ divduo 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
|
|
+ divduo 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ divduo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 c0000000)
|
|
+ divduo ffffffffffffffff, 0000001cbe991def => 0000000008e7f283 (00000000 00000000)
|
|
+ divduo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
|
|
+
|
|
+PPC integer arith insns with two args with flags update:
|
|
+ add. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ add. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
|
|
+ add. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+ add. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
|
|
+ add. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000)
|
|
+ add. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 00000000)
|
|
+ add. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ add. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 00000000)
|
|
+ add. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 00000000)
|
|
+
|
|
+ addo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ addo. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
|
|
+ addo. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+ addo. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
|
|
+ addo. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000)
|
|
+ addo. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 00000000)
|
|
+ addo. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ addo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 00000000)
|
|
+ addo. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 00000000)
|
|
+
|
|
+ addc. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ addc. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
|
|
+ addc. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+ addc. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
|
|
+ addc. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000)
|
|
+ addc. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 20000000)
|
|
+ addc. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ addc. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
|
|
+ addc. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 20000000)
|
|
+
|
|
+ addco. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ addco. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
|
|
+ addco. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+ addco. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
|
|
+ addco. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000)
|
|
+ addco. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 20000000)
|
|
+ addco. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ addco. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
|
|
+ addco. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 20000000)
|
|
+
|
|
+ divw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ divw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ divw. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
|
|
+ divw. 0000001cbe991def, ffffffffffffffff => 000000004166e211 (40000000 00000000)
|
|
+ divw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ divw. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
|
|
+
|
|
+ divwo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ divwo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ divwo. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
|
|
+ divwo. 0000001cbe991def, ffffffffffffffff => 000000004166e211 (40000000 00000000)
|
|
+ divwo. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ divwo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
|
|
+
|
|
+ divwu. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ divwu. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ divwu. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
|
|
+ divwu. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ divwu. ffffffffffffffff, 0000001cbe991def => 0000000000000001 (40000000 00000000)
|
|
+ divwu. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
|
|
+
|
|
+ divwuo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ divwuo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ divwuo. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
|
|
+ divwuo. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ divwuo. ffffffffffffffff, 0000001cbe991def => 0000000000000001 (40000000 00000000)
|
|
+ divwuo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
|
|
+
|
|
+ mulhw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mulhw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ mulhw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ mulhw. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mulhw. 0000001cbe991def, 0000001cbe991def => 0000000010b56825 (40000000 00000000)
|
|
+ mulhw. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ mulhw. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mulhw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ mulhw. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+
|
|
+ mulhwu. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mulhwu. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ mulhwu. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ mulhwu. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mulhwu. 0000001cbe991def, 0000001cbe991def => 000000008de7a403 (80000000 00000000)
|
|
+ mulhwu. 0000001cbe991def, ffffffffffffffff => 00000000be991dee (80000000 00000000)
|
|
+ mulhwu. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mulhwu. ffffffffffffffff, 0000001cbe991def => 00000000be991dee (80000000 00000000)
|
|
+ mulhwu. ffffffffffffffff, ffffffffffffffff => 00000000fffffffe (80000000 00000000)
|
|
+
|
|
+ mullw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mullw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ mullw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ mullw. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mullw. 0000001cbe991def, 0000001cbe991def => 10b568258f2e0521 (40000000 00000000)
|
|
+ mullw. 0000001cbe991def, ffffffffffffffff => 000000004166e211 (40000000 00000000)
|
|
+ mullw. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mullw. ffffffffffffffff, 0000001cbe991def => 000000004166e211 (40000000 00000000)
|
|
+ mullw. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
|
|
+
|
|
+ mullwo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mullwo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ mullwo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ mullwo. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mullwo. 0000001cbe991def, 0000001cbe991def => 10b568258f2e0521 (50000000 c0000000)
|
|
+ mullwo. 0000001cbe991def, ffffffffffffffff => 000000004166e211 (40000000 00000000)
|
|
+ mullwo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mullwo. ffffffffffffffff, 0000001cbe991def => 000000004166e211 (40000000 00000000)
|
|
+ mullwo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
|
|
+
|
|
+ subf. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ subf. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
|
|
+ subf. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+ subf. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000)
|
|
+ subf. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ subf. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 00000000)
|
|
+ subf. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000)
|
|
+ subf. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
|
|
+ subf. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+
|
|
+ subfo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ subfo. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
|
|
+ subfo. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+ subfo. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000)
|
|
+ subfo. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ subfo. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 00000000)
|
|
+ subfo. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000)
|
|
+ subfo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
|
|
+ subfo. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+
|
|
+ subfc. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 20000000)
|
|
+ subfc. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 20000000)
|
|
+ subfc. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
|
|
+ subfc. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000)
|
|
+ subfc. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 20000000)
|
|
+ subfc. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 20000000)
|
|
+ subfc. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000)
|
|
+ subfc. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
|
|
+ subfc. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 20000000)
|
|
+
|
|
+ subfco. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 20000000)
|
|
+ subfco. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 20000000)
|
|
+ subfco. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
|
|
+ subfco. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000)
|
|
+ subfco. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 20000000)
|
|
+ subfco. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 20000000)
|
|
+ subfco. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000)
|
|
+ subfco. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
|
|
+ subfco. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 20000000)
|
|
+
|
|
+ mulhd. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mulhd. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ mulhd. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ mulhd. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mulhd. 0000001cbe991def, 0000001cbe991def => 000000000000033a (40000000 00000000)
|
|
+ mulhd. 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+ mulhd. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mulhd. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
|
|
+ mulhd. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+
|
|
+ mulhdu. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mulhdu. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ mulhdu. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ mulhdu. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mulhdu. 0000001cbe991def, 0000001cbe991def => 000000000000033a (40000000 00000000)
|
|
+ mulhdu. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 00000000)
|
|
+ mulhdu. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mulhdu. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 00000000)
|
|
+ mulhdu. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 00000000)
|
|
+
|
|
+ mulld. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mulld. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ mulld. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ mulld. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mulld. 0000001cbe991def, 0000001cbe991def => 3f66304b8f2e0521 (40000000 00000000)
|
|
+ mulld. 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (80000000 00000000)
|
|
+ mulld. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mulld. ffffffffffffffff, 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
|
|
+ mulld. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
|
|
+
|
|
+ mulldo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mulldo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ mulldo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ mulldo. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mulldo. 0000001cbe991def, 0000001cbe991def => 3f66304b8f2e0521 (50000000 c0000000)
|
|
+ mulldo. 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (80000000 00000000)
|
|
+ mulldo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ mulldo. ffffffffffffffff, 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
|
|
+ mulldo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
|
|
+
|
|
+ divd. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ divd. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ divd. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ divd. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ divd. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
|
|
+ divd. 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (80000000 00000000)
|
|
+ divd. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ divd. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ divd. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
|
|
+
|
|
+ divdu. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ divdu. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ divdu. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ divdu. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ divdu. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
|
|
+ divdu. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ divdu. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ divdu. ffffffffffffffff, 0000001cbe991def => 0000000008e7f283 (40000000 00000000)
|
|
+ divdu. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
|
|
+
|
|
+ divdo. 0000000000000000, 0000000000000000 => 0000000000000000 (30000000 c0000000)
|
|
+ divdo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ divdo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ divdo. 0000001cbe991def, 0000000000000000 => 0000000000000000 (30000000 c0000000)
|
|
+ divdo. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
|
|
+ divdo. 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (80000000 00000000)
|
|
+ divdo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (30000000 c0000000)
|
|
+ divdo. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ divdo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
|
|
+
|
|
+ divduo. 0000000000000000, 0000000000000000 => 0000000000000000 (30000000 c0000000)
|
|
+ divduo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ divduo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ divduo. 0000001cbe991def, 0000000000000000 => 0000000000000000 (30000000 c0000000)
|
|
+ divduo. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
|
|
+ divduo. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ divduo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (30000000 c0000000)
|
|
+ divduo. ffffffffffffffff, 0000001cbe991def => 0000000008e7f283 (40000000 00000000)
|
|
+ divduo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
|
|
+
|
|
+PPC integer arith insns with two args and carry:
|
|
+ adde 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ adde 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
|
|
+ adde 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+ adde 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
|
|
+ adde 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000)
|
|
+ adde 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 20000000)
|
|
+ adde ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ adde ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
|
|
+ adde ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 20000000)
|
|
+ adde 0000000000000000, 0000000000000000 => 0000000000000001 (00000000 00000000)
|
|
+ adde 0000000000000000, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
|
|
+ adde 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 20000000)
|
|
+ adde 0000001cbe991def, 0000000000000000 => 0000001cbe991df0 (00000000 00000000)
|
|
+ adde 0000001cbe991def, 0000001cbe991def => 000000397d323bdf (00000000 00000000)
|
|
+ adde 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 20000000)
|
|
+ adde ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 20000000)
|
|
+ adde ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 20000000)
|
|
+ adde ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
|
|
+
|
|
+ addeo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ addeo 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
|
|
+ addeo 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+ addeo 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
|
|
+ addeo 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000)
|
|
+ addeo 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 20000000)
|
|
+ addeo ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ addeo ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
|
|
+ addeo ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 20000000)
|
|
+ addeo 0000000000000000, 0000000000000000 => 0000000000000001 (00000000 00000000)
|
|
+ addeo 0000000000000000, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
|
|
+ addeo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 20000000)
|
|
+ addeo 0000001cbe991def, 0000000000000000 => 0000001cbe991df0 (00000000 00000000)
|
|
+ addeo 0000001cbe991def, 0000001cbe991def => 000000397d323bdf (00000000 00000000)
|
|
+ addeo 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 20000000)
|
|
+ addeo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 20000000)
|
|
+ addeo ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 20000000)
|
|
+ addeo ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
|
|
+
|
|
+ subfe 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ subfe 0000000000000000, 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
|
|
+ subfe 0000000000000000, ffffffffffffffff => fffffffffffffffe (00000000 20000000)
|
|
+ subfe 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (00000000 00000000)
|
|
+ subfe 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
|
|
+ subfe 0000001cbe991def, ffffffffffffffff => ffffffe34166e20f (00000000 20000000)
|
|
+ subfe ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ subfe ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
|
|
+ subfe ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+ subfe 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 20000000)
|
|
+ subfe 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 20000000)
|
|
+ subfe 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
|
|
+ subfe 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000)
|
|
+ subfe 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 20000000)
|
|
+ subfe 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 20000000)
|
|
+ subfe ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000)
|
|
+ subfe ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
|
|
+ subfe ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 20000000)
|
|
+
|
|
+ subfeo 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ subfeo 0000000000000000, 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
|
|
+ subfeo 0000000000000000, ffffffffffffffff => fffffffffffffffe (00000000 20000000)
|
|
+ subfeo 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (00000000 00000000)
|
|
+ subfeo 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
|
|
+ subfeo 0000001cbe991def, ffffffffffffffff => ffffffe34166e20f (00000000 20000000)
|
|
+ subfeo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ subfeo ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
|
|
+ subfeo ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+ subfeo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 20000000)
|
|
+ subfeo 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 20000000)
|
|
+ subfeo 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
|
|
+ subfeo 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000)
|
|
+ subfeo 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 20000000)
|
|
+ subfeo 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 20000000)
|
|
+ subfeo ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000)
|
|
+ subfeo ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
|
|
+ subfeo ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 20000000)
|
|
+
|
|
+PPC integer arith insns with two args and carry with flags update:
|
|
+ adde. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ adde. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
|
|
+ adde. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+ adde. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
|
|
+ adde. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000)
|
|
+ adde. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 20000000)
|
|
+ adde. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ adde. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
|
|
+ adde. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 20000000)
|
|
+ adde. 0000000000000000, 0000000000000000 => 0000000000000001 (40000000 00000000)
|
|
+ adde. 0000000000000000, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
|
|
+ adde. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 20000000)
|
|
+ adde. 0000001cbe991def, 0000000000000000 => 0000001cbe991df0 (40000000 00000000)
|
|
+ adde. 0000001cbe991def, 0000001cbe991def => 000000397d323bdf (40000000 00000000)
|
|
+ adde. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 20000000)
|
|
+ adde. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 20000000)
|
|
+ adde. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 20000000)
|
|
+ adde. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
|
|
+
|
|
+ addeo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ addeo. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
|
|
+ addeo. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+ addeo. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
|
|
+ addeo. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000)
|
|
+ addeo. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 20000000)
|
|
+ addeo. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ addeo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
|
|
+ addeo. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 20000000)
|
|
+ addeo. 0000000000000000, 0000000000000000 => 0000000000000001 (40000000 00000000)
|
|
+ addeo. 0000000000000000, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
|
|
+ addeo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 20000000)
|
|
+ addeo. 0000001cbe991def, 0000000000000000 => 0000001cbe991df0 (40000000 00000000)
|
|
+ addeo. 0000001cbe991def, 0000001cbe991def => 000000397d323bdf (40000000 00000000)
|
|
+ addeo. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 20000000)
|
|
+ addeo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 20000000)
|
|
+ addeo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 20000000)
|
|
+ addeo. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
|
|
+
|
|
+ subfe. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ subfe. 0000000000000000, 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
|
|
+ subfe. 0000000000000000, ffffffffffffffff => fffffffffffffffe (80000000 20000000)
|
|
+ subfe. 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (80000000 00000000)
|
|
+ subfe. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
|
|
+ subfe. 0000001cbe991def, ffffffffffffffff => ffffffe34166e20f (80000000 20000000)
|
|
+ subfe. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ subfe. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
|
|
+ subfe. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+ subfe. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 20000000)
|
|
+ subfe. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 20000000)
|
|
+ subfe. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
|
|
+ subfe. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000)
|
|
+ subfe. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 20000000)
|
|
+ subfe. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 20000000)
|
|
+ subfe. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000)
|
|
+ subfe. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
|
|
+ subfe. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 20000000)
|
|
+
|
|
+ subfeo. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ subfeo. 0000000000000000, 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
|
|
+ subfeo. 0000000000000000, ffffffffffffffff => fffffffffffffffe (80000000 20000000)
|
|
+ subfeo. 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (80000000 00000000)
|
|
+ subfeo. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
|
|
+ subfeo. 0000001cbe991def, ffffffffffffffff => ffffffe34166e20f (80000000 20000000)
|
|
+ subfeo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ subfeo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
|
|
+ subfeo. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+ subfeo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 20000000)
|
|
+ subfeo. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 20000000)
|
|
+ subfeo. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
|
|
+ subfeo. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000)
|
|
+ subfeo. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 20000000)
|
|
+ subfeo. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 20000000)
|
|
+ subfeo. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000)
|
|
+ subfeo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
|
|
+ subfeo. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 20000000)
|
|
+
|
|
+PPC integer logical insns with two args:
|
|
+ and 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ and 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ and 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ and 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ and 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
|
|
+ and 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000)
|
|
+ and ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ and ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
|
|
+ and ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+
|
|
+ andc 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ andc 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ andc 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ andc 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
|
|
+ andc 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ andc 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ andc ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ andc ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
|
|
+ andc ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+
|
|
+ eqv 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ eqv 0000000000000000, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
|
|
+ eqv 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ eqv 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (00000000 00000000)
|
|
+ eqv 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
|
|
+ eqv 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000)
|
|
+ eqv ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ eqv ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
|
|
+ eqv ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+
|
|
+ nand 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ nand 0000000000000000, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
|
|
+ nand 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+ nand 0000001cbe991def, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ nand 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
|
|
+ nand 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000)
|
|
+ nand ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ nand ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
|
|
+ nand ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+
|
|
+ nor 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ nor 0000000000000000, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
|
|
+ nor 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ nor 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (00000000 00000000)
|
|
+ nor 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
|
|
+ nor 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ nor ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ nor ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ nor ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+
|
|
+ or 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ or 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
|
|
+ or 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+ or 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
|
|
+ or 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
|
|
+ or 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+ or ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ or ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
|
|
+ or ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+
|
|
+ orc 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ orc 0000000000000000, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
|
|
+ orc 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ orc 0000001cbe991def, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ orc 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
|
|
+ orc 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000)
|
|
+ orc ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ orc ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
|
|
+ orc ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+
|
|
+ xor 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ xor 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
|
|
+ xor 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+ xor 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
|
|
+ xor 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ xor 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000)
|
|
+ xor ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ xor ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
|
|
+ xor ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+
|
|
+ slw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ slw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ slw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ slw 0000001cbe991def, 0000000000000000 => 00000000be991def (00000000 00000000)
|
|
+ slw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ slw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ slw ffffffffffffffff, 0000000000000000 => 00000000ffffffff (00000000 00000000)
|
|
+ slw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ slw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+
|
|
+ sraw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ sraw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ sraw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ sraw 0000001cbe991def, 0000000000000000 => ffffffffbe991def (00000000 00000000)
|
|
+ sraw 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 20000000)
|
|
+ sraw 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
|
|
+ sraw ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ sraw ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 20000000)
|
|
+ sraw ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
|
|
+
|
|
+ srw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ srw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ srw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ srw 0000001cbe991def, 0000000000000000 => 00000000be991def (00000000 00000000)
|
|
+ srw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ srw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ srw ffffffffffffffff, 0000000000000000 => 00000000ffffffff (00000000 00000000)
|
|
+ srw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ srw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+
|
|
+ sld 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ sld 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ sld 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ sld 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
|
|
+ sld 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ sld 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ sld ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ sld ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ sld ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+
|
|
+ srad 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ srad 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ srad 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ srad 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
|
|
+ srad 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ srad 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ srad ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ srad ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 20000000)
|
|
+ srad ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
|
|
+
|
|
+ srd 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ srd 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ srd 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ srd 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
|
|
+ srd 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ srd 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ srd ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ srd ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ srd ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+
|
|
+PPC integer logical insns with two args with flags update:
|
|
+ and. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ and. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ and. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ and. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ and. 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
|
|
+ and. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 00000000)
|
|
+ and. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ and. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
|
|
+ and. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+
|
|
+ andc. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ andc. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ andc. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ andc. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
|
|
+ andc. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ andc. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ andc. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ andc. ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
|
|
+ andc. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+
|
|
+ eqv. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ eqv. 0000000000000000, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
|
|
+ eqv. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ eqv. 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (80000000 00000000)
|
|
+ eqv. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
|
|
+ eqv. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 00000000)
|
|
+ eqv. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ eqv. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
|
|
+ eqv. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+
|
|
+ nand. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ nand. 0000000000000000, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
|
|
+ nand. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+ nand. 0000001cbe991def, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ nand. 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
|
|
+ nand. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 00000000)
|
|
+ nand. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ nand. ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
|
|
+ nand. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+
|
|
+ nor. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ nor. 0000000000000000, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
|
|
+ nor. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ nor. 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (80000000 00000000)
|
|
+ nor. 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
|
|
+ nor. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ nor. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ nor. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ nor. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+
|
|
+ or. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ or. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
|
|
+ or. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+ or. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
|
|
+ or. 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
|
|
+ or. 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+ or. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ or. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
|
|
+ or. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+
|
|
+ orc. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ orc. 0000000000000000, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
|
|
+ orc. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ orc. 0000001cbe991def, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ orc. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
|
|
+ orc. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 00000000)
|
|
+ orc. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ orc. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
|
|
+ orc. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+
|
|
+ xor. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ xor. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
|
|
+ xor. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+ xor. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
|
|
+ xor. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ xor. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 00000000)
|
|
+ xor. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ xor. ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
|
|
+ xor. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+
|
|
+ slw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ slw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ slw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ slw. 0000001cbe991def, 0000000000000000 => 00000000be991def (40000000 00000000)
|
|
+ slw. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ slw. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ slw. ffffffffffffffff, 0000000000000000 => 00000000ffffffff (40000000 00000000)
|
|
+ slw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ slw. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+
|
|
+ sraw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ sraw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ sraw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ sraw. 0000001cbe991def, 0000000000000000 => ffffffffbe991def (80000000 00000000)
|
|
+ sraw. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 20000000)
|
|
+ sraw. 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
|
|
+ sraw. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ sraw. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 20000000)
|
|
+ sraw. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
|
|
+
|
|
+ srw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ srw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ srw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ srw. 0000001cbe991def, 0000000000000000 => 00000000be991def (40000000 00000000)
|
|
+ srw. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ srw. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ srw. ffffffffffffffff, 0000000000000000 => 00000000ffffffff (40000000 00000000)
|
|
+ srw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ srw. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+
|
|
+ sld. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ sld. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ sld. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ sld. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
|
|
+ sld. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ sld. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ sld. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ sld. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ sld. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+
|
|
+ srad. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ srad. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ srad. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ srad. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
|
|
+ srad. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ srad. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ srad. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ srad. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 20000000)
|
|
+ srad. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
|
|
+
|
|
+ srd. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ srd. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ srd. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ srd. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
|
|
+ srd. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ srd. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ srd. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ srd. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ srd. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+
|
|
+PPC integer compare insns (two args):
|
|
+ cmpw 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000)
|
|
+ cmpw 0000000000000000, 0000001cbe991def => 0000000000000000 (00400000 00000000)
|
|
+ cmpw 0000000000000000, ffffffffffffffff => 0000000000000000 (00400000 00000000)
|
|
+ cmpw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00800000 00000000)
|
|
+ cmpw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000)
|
|
+ cmpw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00800000 00000000)
|
|
+ cmpw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00800000 00000000)
|
|
+ cmpw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00400000 00000000)
|
|
+ cmpw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000)
|
|
+
|
|
+ cmplw 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000)
|
|
+ cmplw 0000000000000000, 0000001cbe991def => 0000000000000000 (00800000 00000000)
|
|
+ cmplw 0000000000000000, ffffffffffffffff => 0000000000000000 (00800000 00000000)
|
|
+ cmplw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00400000 00000000)
|
|
+ cmplw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000)
|
|
+ cmplw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00800000 00000000)
|
|
+ cmplw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00400000 00000000)
|
|
+ cmplw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00400000 00000000)
|
|
+ cmplw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000)
|
|
+
|
|
+ cmpd 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000)
|
|
+ cmpd 0000000000000000, 0000001cbe991def => 0000000000000000 (00800000 00000000)
|
|
+ cmpd 0000000000000000, ffffffffffffffff => 0000000000000000 (00400000 00000000)
|
|
+ cmpd 0000001cbe991def, 0000000000000000 => 0000000000000000 (00400000 00000000)
|
|
+ cmpd 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000)
|
|
+ cmpd 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00400000 00000000)
|
|
+ cmpd ffffffffffffffff, 0000000000000000 => 0000000000000000 (00800000 00000000)
|
|
+ cmpd ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00800000 00000000)
|
|
+ cmpd ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000)
|
|
+
|
|
+ cmpld 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000)
|
|
+ cmpld 0000000000000000, 0000001cbe991def => 0000000000000000 (00800000 00000000)
|
|
+ cmpld 0000000000000000, ffffffffffffffff => 0000000000000000 (00800000 00000000)
|
|
+ cmpld 0000001cbe991def, 0000000000000000 => 0000000000000000 (00400000 00000000)
|
|
+ cmpld 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000)
|
|
+ cmpld 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00800000 00000000)
|
|
+ cmpld ffffffffffffffff, 0000000000000000 => 0000000000000000 (00400000 00000000)
|
|
+ cmpld ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00400000 00000000)
|
|
+ cmpld ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000)
|
|
+
|
|
+PPC integer compare with immediate insns (two args):
|
|
+ cmpwi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000)
|
|
+ cmpwi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000)
|
|
+ cmpwi 0000000000000000, 0000ffff => 0000000000000000 (00400000 00000000)
|
|
+ cmpwi 0000001cbe991def, 00000000 => 0000000000000000 (00800000 00000000)
|
|
+ cmpwi 0000001cbe991def, 000003e7 => 0000000000000000 (00800000 00000000)
|
|
+ cmpwi 0000001cbe991def, 0000ffff => 0000000000000000 (00800000 00000000)
|
|
+ cmpwi ffffffffffffffff, 00000000 => 0000000000000000 (00800000 00000000)
|
|
+ cmpwi ffffffffffffffff, 000003e7 => 0000000000000000 (00800000 00000000)
|
|
+ cmpwi ffffffffffffffff, 0000ffff => 0000000000000000 (00200000 00000000)
|
|
+
|
|
+ cmplwi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000)
|
|
+ cmplwi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000)
|
|
+ cmplwi 0000000000000000, 0000ffff => 0000000000000000 (00800000 00000000)
|
|
+ cmplwi 0000001cbe991def, 00000000 => 0000000000000000 (00400000 00000000)
|
|
+ cmplwi 0000001cbe991def, 000003e7 => 0000000000000000 (00400000 00000000)
|
|
+ cmplwi 0000001cbe991def, 0000ffff => 0000000000000000 (00400000 00000000)
|
|
+ cmplwi ffffffffffffffff, 00000000 => 0000000000000000 (00400000 00000000)
|
|
+ cmplwi ffffffffffffffff, 000003e7 => 0000000000000000 (00400000 00000000)
|
|
+ cmplwi ffffffffffffffff, 0000ffff => 0000000000000000 (00400000 00000000)
|
|
+
|
|
+ cmpdi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000)
|
|
+ cmpdi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000)
|
|
+ cmpdi 0000000000000000, 0000ffff => 0000000000000000 (00400000 00000000)
|
|
+ cmpdi 0000001cbe991def, 00000000 => 0000000000000000 (00400000 00000000)
|
|
+ cmpdi 0000001cbe991def, 000003e7 => 0000000000000000 (00400000 00000000)
|
|
+ cmpdi 0000001cbe991def, 0000ffff => 0000000000000000 (00400000 00000000)
|
|
+ cmpdi ffffffffffffffff, 00000000 => 0000000000000000 (00800000 00000000)
|
|
+ cmpdi ffffffffffffffff, 000003e7 => 0000000000000000 (00800000 00000000)
|
|
+ cmpdi ffffffffffffffff, 0000ffff => 0000000000000000 (00200000 00000000)
|
|
+
|
|
+ cmpldi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000)
|
|
+ cmpldi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000)
|
|
+ cmpldi 0000000000000000, 0000ffff => 0000000000000000 (00800000 00000000)
|
|
+ cmpldi 0000001cbe991def, 00000000 => 0000000000000000 (00400000 00000000)
|
|
+ cmpldi 0000001cbe991def, 000003e7 => 0000000000000000 (00400000 00000000)
|
|
+ cmpldi 0000001cbe991def, 0000ffff => 0000000000000000 (00400000 00000000)
|
|
+ cmpldi ffffffffffffffff, 00000000 => 0000000000000000 (00400000 00000000)
|
|
+ cmpldi ffffffffffffffff, 000003e7 => 0000000000000000 (00400000 00000000)
|
|
+ cmpldi ffffffffffffffff, 0000ffff => 0000000000000000 (00400000 00000000)
|
|
+
|
|
+PPC integer arith insns
|
|
+ with one register + one 16 bits immediate args:
|
|
+ addi 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
|
|
+ addi 0000000000000000, 000003e7 => 00000000000003e7 (00000000 00000000)
|
|
+ addi 0000000000000000, 0000ffff => ffffffffffffffff (00000000 00000000)
|
|
+ addi 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
|
|
+ addi 0000001cbe991def, 000003e7 => 0000001cbe9921d6 (00000000 00000000)
|
|
+ addi 0000001cbe991def, 0000ffff => 0000001cbe991dee (00000000 00000000)
|
|
+ addi ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
|
|
+ addi ffffffffffffffff, 000003e7 => 00000000000003e6 (00000000 00000000)
|
|
+ addi ffffffffffffffff, 0000ffff => fffffffffffffffe (00000000 00000000)
|
|
+
|
|
+ addic 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
|
|
+ addic 0000000000000000, 000003e7 => 00000000000003e7 (00000000 00000000)
|
|
+ addic 0000000000000000, 0000ffff => ffffffffffffffff (00000000 00000000)
|
|
+ addic 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
|
|
+ addic 0000001cbe991def, 000003e7 => 0000001cbe9921d6 (00000000 00000000)
|
|
+ addic 0000001cbe991def, 0000ffff => 0000001cbe991dee (00000000 20000000)
|
|
+ addic ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
|
|
+ addic ffffffffffffffff, 000003e7 => 00000000000003e6 (00000000 20000000)
|
|
+ addic ffffffffffffffff, 0000ffff => fffffffffffffffe (00000000 20000000)
|
|
+
|
|
+ addis 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
|
|
+ addis 0000000000000000, 000003e7 => 0000000003e70000 (00000000 00000000)
|
|
+ addis 0000000000000000, 0000ffff => ffffffffffff0000 (00000000 00000000)
|
|
+ addis 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
|
|
+ addis 0000001cbe991def, 000003e7 => 0000001cc2801def (00000000 00000000)
|
|
+ addis 0000001cbe991def, 0000ffff => 0000001cbe981def (00000000 00000000)
|
|
+ addis ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
|
|
+ addis ffffffffffffffff, 000003e7 => 0000000003e6ffff (00000000 00000000)
|
|
+ addis ffffffffffffffff, 0000ffff => fffffffffffeffff (00000000 00000000)
|
|
+
|
|
+ mulli 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
|
|
+ mulli 0000000000000000, 000003e7 => 0000000000000000 (00000000 00000000)
|
|
+ mulli 0000000000000000, 0000ffff => 0000000000000000 (00000000 00000000)
|
|
+ mulli 0000001cbe991def, 00000000 => 0000000000000000 (00000000 00000000)
|
|
+ mulli 0000001cbe991def, 000003e7 => 0000702bc783cfa9 (00000000 00000000)
|
|
+ mulli 0000001cbe991def, 0000ffff => ffffffe34166e211 (00000000 00000000)
|
|
+ mulli ffffffffffffffff, 00000000 => 0000000000000000 (00000000 00000000)
|
|
+ mulli ffffffffffffffff, 000003e7 => fffffffffffffc19 (00000000 00000000)
|
|
+ mulli ffffffffffffffff, 0000ffff => 0000000000000001 (00000000 00000000)
|
|
+
|
|
+ subfic 0000000000000000, 00000000 => 0000000000000000 (00000000 20000000)
|
|
+ subfic 0000000000000000, 000003e7 => 00000000000003e7 (00000000 20000000)
|
|
+ subfic 0000000000000000, 0000ffff => ffffffffffffffff (00000000 20000000)
|
|
+ subfic 0000001cbe991def, 00000000 => ffffffe34166e211 (00000000 00000000)
|
|
+ subfic 0000001cbe991def, 000003e7 => ffffffe34166e5f8 (00000000 00000000)
|
|
+ subfic 0000001cbe991def, 0000ffff => ffffffe34166e210 (00000000 20000000)
|
|
+ subfic ffffffffffffffff, 00000000 => 0000000000000001 (00000000 00000000)
|
|
+ subfic ffffffffffffffff, 000003e7 => 00000000000003e8 (00000000 00000000)
|
|
+ subfic ffffffffffffffff, 0000ffff => 0000000000000000 (00000000 20000000)
|
|
+
|
|
+PPC integer arith insns
|
|
+ with one register + one 16 bits immediate args with flags update:
|
|
+ addic. 0000000000000000, 00000000 => 0000000000000000 (20000000 00000000)
|
|
+ addic. 0000000000000000, 000003e7 => 00000000000003e7 (40000000 00000000)
|
|
+ addic. 0000000000000000, 0000ffff => ffffffffffffffff (80000000 00000000)
|
|
+ addic. 0000001cbe991def, 00000000 => 0000001cbe991def (40000000 00000000)
|
|
+ addic. 0000001cbe991def, 000003e7 => 0000001cbe9921d6 (40000000 00000000)
|
|
+ addic. 0000001cbe991def, 0000ffff => 0000001cbe991dee (40000000 20000000)
|
|
+ addic. ffffffffffffffff, 00000000 => ffffffffffffffff (80000000 00000000)
|
|
+ addic. ffffffffffffffff, 000003e7 => 00000000000003e6 (40000000 20000000)
|
|
+ addic. ffffffffffffffff, 0000ffff => fffffffffffffffe (80000000 20000000)
|
|
+
|
|
+PPC integer logical insns
|
|
+ with one register + one 16 bits immediate args:
|
|
+ ori 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
|
|
+ ori 0000000000000000, 000003e7 => 00000000000003e7 (00000000 00000000)
|
|
+ ori 0000000000000000, 0000ffff => 000000000000ffff (00000000 00000000)
|
|
+ ori 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
|
|
+ ori 0000001cbe991def, 000003e7 => 0000001cbe991fef (00000000 00000000)
|
|
+ ori 0000001cbe991def, 0000ffff => 0000001cbe99ffff (00000000 00000000)
|
|
+ ori ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
|
|
+ ori ffffffffffffffff, 000003e7 => ffffffffffffffff (00000000 00000000)
|
|
+ ori ffffffffffffffff, 0000ffff => ffffffffffffffff (00000000 00000000)
|
|
+
|
|
+ oris 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
|
|
+ oris 0000000000000000, 000003e7 => 0000000003e70000 (00000000 00000000)
|
|
+ oris 0000000000000000, 0000ffff => 00000000ffff0000 (00000000 00000000)
|
|
+ oris 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
|
|
+ oris 0000001cbe991def, 000003e7 => 0000001cbfff1def (00000000 00000000)
|
|
+ oris 0000001cbe991def, 0000ffff => 0000001cffff1def (00000000 00000000)
|
|
+ oris ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
|
|
+ oris ffffffffffffffff, 000003e7 => ffffffffffffffff (00000000 00000000)
|
|
+ oris ffffffffffffffff, 0000ffff => ffffffffffffffff (00000000 00000000)
|
|
+
|
|
+ xori 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
|
|
+ xori 0000000000000000, 000003e7 => 00000000000003e7 (00000000 00000000)
|
|
+ xori 0000000000000000, 0000ffff => 000000000000ffff (00000000 00000000)
|
|
+ xori 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
|
|
+ xori 0000001cbe991def, 000003e7 => 0000001cbe991e08 (00000000 00000000)
|
|
+ xori 0000001cbe991def, 0000ffff => 0000001cbe99e210 (00000000 00000000)
|
|
+ xori ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
|
|
+ xori ffffffffffffffff, 000003e7 => fffffffffffffc18 (00000000 00000000)
|
|
+ xori ffffffffffffffff, 0000ffff => ffffffffffff0000 (00000000 00000000)
|
|
+
|
|
+ xoris 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
|
|
+ xoris 0000000000000000, 000003e7 => 0000000003e70000 (00000000 00000000)
|
|
+ xoris 0000000000000000, 0000ffff => 00000000ffff0000 (00000000 00000000)
|
|
+ xoris 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
|
|
+ xoris 0000001cbe991def, 000003e7 => 0000001cbd7e1def (00000000 00000000)
|
|
+ xoris 0000001cbe991def, 0000ffff => 0000001c41661def (00000000 00000000)
|
|
+ xoris ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
|
|
+ xoris ffffffffffffffff, 000003e7 => fffffffffc18ffff (00000000 00000000)
|
|
+ xoris ffffffffffffffff, 0000ffff => ffffffff0000ffff (00000000 00000000)
|
|
+
|
|
+PPC integer logical insns
|
|
+ with one register + one 16 bits immediate args with flags update:
|
|
+ andi. 0000000000000000, 00000000 => 0000000000000000 (20000000 00000000)
|
|
+ andi. 0000000000000000, 000003e7 => 0000000000000000 (20000000 00000000)
|
|
+ andi. 0000000000000000, 0000ffff => 0000000000000000 (20000000 00000000)
|
|
+ andi. 0000001cbe991def, 00000000 => 0000000000000000 (20000000 00000000)
|
|
+ andi. 0000001cbe991def, 000003e7 => 00000000000001e7 (40000000 00000000)
|
|
+ andi. 0000001cbe991def, 0000ffff => 0000000000001def (40000000 00000000)
|
|
+ andi. ffffffffffffffff, 00000000 => 0000000000000000 (20000000 00000000)
|
|
+ andi. ffffffffffffffff, 000003e7 => 00000000000003e7 (40000000 00000000)
|
|
+ andi. ffffffffffffffff, 0000ffff => 000000000000ffff (40000000 00000000)
|
|
+
|
|
+ andis. 0000000000000000, 00000000 => 0000000000000000 (20000000 00000000)
|
|
+ andis. 0000000000000000, 000003e7 => 0000000000000000 (20000000 00000000)
|
|
+ andis. 0000000000000000, 0000ffff => 0000000000000000 (20000000 00000000)
|
|
+ andis. 0000001cbe991def, 00000000 => 0000000000000000 (20000000 00000000)
|
|
+ andis. 0000001cbe991def, 000003e7 => 0000000002810000 (40000000 00000000)
|
|
+ andis. 0000001cbe991def, 0000ffff => 00000000be990000 (40000000 00000000)
|
|
+ andis. ffffffffffffffff, 00000000 => 0000000000000000 (20000000 00000000)
|
|
+ andis. ffffffffffffffff, 000003e7 => 0000000003e70000 (40000000 00000000)
|
|
+ andis. ffffffffffffffff, 0000ffff => 00000000ffff0000 (40000000 00000000)
|
|
+
|
|
+PPC condition register logical insns - two operands:
|
|
+ crand 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
|
|
+ crand 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
|
|
+ crand 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
|
|
+ crand 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
|
|
+ crand 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
|
|
+ crand 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
|
|
+ crand ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
|
|
+ crand ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
|
|
+ crand ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
|
|
+
|
|
+ crandc 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
|
|
+ crandc 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
|
|
+ crandc 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
|
|
+ crandc 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
|
|
+ crandc 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
|
|
+ crandc 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
|
|
+ crandc ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
|
|
+ crandc ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
|
|
+ crandc ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
|
|
+
|
|
+ creqv 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
|
|
+ creqv 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
|
|
+ creqv 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
|
|
+ creqv 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
|
|
+ creqv 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
|
|
+ creqv 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
|
|
+ creqv ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
|
|
+ creqv ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
|
|
+ creqv ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
|
|
+
|
|
+ crnand 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
|
|
+ crnand 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
|
|
+ crnand 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
|
|
+ crnand 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
|
|
+ crnand 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
|
|
+ crnand 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
|
|
+ crnand ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
|
|
+ crnand ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
|
|
+ crnand ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
|
|
+
|
|
+ crnor 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
|
|
+ crnor 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
|
|
+ crnor 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
|
|
+ crnor 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
|
|
+ crnor 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
|
|
+ crnor 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
|
|
+ crnor ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
|
|
+ crnor ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
|
|
+ crnor ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
|
|
+
|
|
+ cror 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
|
|
+ cror 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
|
|
+ cror 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
|
|
+ cror 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
|
|
+ cror 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
|
|
+ cror 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
|
|
+ cror ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
|
|
+ cror ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
|
|
+ cror ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
|
|
+
|
|
+ crorc 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
|
|
+ crorc 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
|
|
+ crorc 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
|
|
+ crorc 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
|
|
+ crorc 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
|
|
+ crorc 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
|
|
+ crorc ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
|
|
+ crorc ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
|
|
+ crorc ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
|
|
+
|
|
+ crxor 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
|
|
+ crxor 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
|
|
+ crxor 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
|
|
+ crxor 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
|
|
+ crxor 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
|
|
+ crxor 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
|
|
+ crxor ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
|
|
+ crxor ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
|
|
+ crxor ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
|
|
+
|
|
+PPC integer arith insns with one arg and carry:
|
|
+ addme 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ addme 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
|
|
+ addme ffffffffffffffff => fffffffffffffffe (00000000 20000000)
|
|
+ addme 0000000000000000 => 0000000000000000 (00000000 20000000)
|
|
+ addme 0000001cbe991def => 0000001cbe991def (00000000 20000000)
|
|
+ addme ffffffffffffffff => ffffffffffffffff (00000000 20000000)
|
|
+
|
|
+ addmeo 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ addmeo 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
|
|
+ addmeo ffffffffffffffff => fffffffffffffffe (00000000 20000000)
|
|
+ addmeo 0000000000000000 => 0000000000000000 (00000000 20000000)
|
|
+ addmeo 0000001cbe991def => 0000001cbe991def (00000000 20000000)
|
|
+ addmeo ffffffffffffffff => ffffffffffffffff (00000000 20000000)
|
|
+
|
|
+ addze 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ addze 0000001cbe991def => 0000001cbe991def (00000000 00000000)
|
|
+ addze ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+ addze 0000000000000000 => 0000000000000001 (00000000 00000000)
|
|
+ addze 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
|
|
+ addze ffffffffffffffff => 0000000000000000 (00000000 20000000)
|
|
+
|
|
+ addzeo 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ addzeo 0000001cbe991def => 0000001cbe991def (00000000 00000000)
|
|
+ addzeo ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+ addzeo 0000000000000000 => 0000000000000001 (00000000 00000000)
|
|
+ addzeo 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
|
|
+ addzeo ffffffffffffffff => 0000000000000000 (00000000 20000000)
|
|
+
|
|
+ subfme 0000000000000000 => fffffffffffffffe (00000000 20000000)
|
|
+ subfme 0000001cbe991def => ffffffe34166e20f (00000000 20000000)
|
|
+ subfme ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+ subfme 0000000000000000 => ffffffffffffffff (00000000 20000000)
|
|
+ subfme 0000001cbe991def => ffffffe34166e210 (00000000 20000000)
|
|
+ subfme ffffffffffffffff => 0000000000000000 (00000000 20000000)
|
|
+
|
|
+ subfmeo 0000000000000000 => fffffffffffffffe (00000000 20000000)
|
|
+ subfmeo 0000001cbe991def => ffffffe34166e20f (00000000 20000000)
|
|
+ subfmeo ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+ subfmeo 0000000000000000 => ffffffffffffffff (00000000 20000000)
|
|
+ subfmeo 0000001cbe991def => ffffffe34166e210 (00000000 20000000)
|
|
+ subfmeo ffffffffffffffff => 0000000000000000 (00000000 20000000)
|
|
+
|
|
+ subfze 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ subfze 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
|
|
+ subfze ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ subfze 0000000000000000 => 0000000000000000 (00000000 20000000)
|
|
+ subfze 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
|
|
+ subfze ffffffffffffffff => 0000000000000001 (00000000 00000000)
|
|
+
|
|
+ subfzeo 0000000000000000 => ffffffffffffffff (00000000 00000000)
|
|
+ subfzeo 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
|
|
+ subfzeo ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+ subfzeo 0000000000000000 => 0000000000000000 (00000000 20000000)
|
|
+ subfzeo 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
|
|
+ subfzeo ffffffffffffffff => 0000000000000001 (00000000 00000000)
|
|
+
|
|
+PPC integer arith insns with one arg and carry with flags update:
|
|
+ addme. 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ addme. 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
|
|
+ addme. ffffffffffffffff => fffffffffffffffe (80000000 20000000)
|
|
+ addme. 0000000000000000 => 0000000000000000 (20000000 20000000)
|
|
+ addme. 0000001cbe991def => 0000001cbe991def (40000000 20000000)
|
|
+ addme. ffffffffffffffff => ffffffffffffffff (80000000 20000000)
|
|
+
|
|
+ addmeo. 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ addmeo. 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
|
|
+ addmeo. ffffffffffffffff => fffffffffffffffe (80000000 20000000)
|
|
+ addmeo. 0000000000000000 => 0000000000000000 (20000000 20000000)
|
|
+ addmeo. 0000001cbe991def => 0000001cbe991def (40000000 20000000)
|
|
+ addmeo. ffffffffffffffff => ffffffffffffffff (80000000 20000000)
|
|
+
|
|
+ addze. 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ addze. 0000001cbe991def => 0000001cbe991def (40000000 00000000)
|
|
+ addze. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+ addze. 0000000000000000 => 0000000000000001 (40000000 00000000)
|
|
+ addze. 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
|
|
+ addze. ffffffffffffffff => 0000000000000000 (20000000 20000000)
|
|
+
|
|
+ addzeo. 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ addzeo. 0000001cbe991def => 0000001cbe991def (40000000 00000000)
|
|
+ addzeo. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+ addzeo. 0000000000000000 => 0000000000000001 (40000000 00000000)
|
|
+ addzeo. 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
|
|
+ addzeo. ffffffffffffffff => 0000000000000000 (20000000 20000000)
|
|
+
|
|
+ subfme. 0000000000000000 => fffffffffffffffe (80000000 20000000)
|
|
+ subfme. 0000001cbe991def => ffffffe34166e20f (80000000 20000000)
|
|
+ subfme. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+ subfme. 0000000000000000 => ffffffffffffffff (80000000 20000000)
|
|
+ subfme. 0000001cbe991def => ffffffe34166e210 (80000000 20000000)
|
|
+ subfme. ffffffffffffffff => 0000000000000000 (20000000 20000000)
|
|
+
|
|
+ subfmeo. 0000000000000000 => fffffffffffffffe (80000000 20000000)
|
|
+ subfmeo. 0000001cbe991def => ffffffe34166e20f (80000000 20000000)
|
|
+ subfmeo. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+ subfmeo. 0000000000000000 => ffffffffffffffff (80000000 20000000)
|
|
+ subfmeo. 0000001cbe991def => ffffffe34166e210 (80000000 20000000)
|
|
+ subfmeo. ffffffffffffffff => 0000000000000000 (20000000 20000000)
|
|
+
|
|
+ subfze. 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ subfze. 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
|
|
+ subfze. ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ subfze. 0000000000000000 => 0000000000000000 (20000000 20000000)
|
|
+ subfze. 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
|
|
+ subfze. ffffffffffffffff => 0000000000000001 (40000000 00000000)
|
|
+
|
|
+ subfzeo. 0000000000000000 => ffffffffffffffff (80000000 00000000)
|
|
+ subfzeo. 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
|
|
+ subfzeo. ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+ subfzeo. 0000000000000000 => 0000000000000000 (20000000 20000000)
|
|
+ subfzeo. 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
|
|
+ subfzeo. ffffffffffffffff => 0000000000000001 (40000000 00000000)
|
|
+
|
|
+PPC integer logical insns with one arg:
|
|
+ cntlzw 0000000000000000 => 0000000000000020 (00000000 00000000)
|
|
+ cntlzw 0000001cbe991def => 0000000000000000 (00000000 00000000)
|
|
+ cntlzw ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+
|
|
+ extsb 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ extsb 0000001cbe991def => ffffffffffffffef (00000000 00000000)
|
|
+ extsb ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+
|
|
+ extsh 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ extsh 0000001cbe991def => 0000000000001def (00000000 00000000)
|
|
+ extsh ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+
|
|
+ neg 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ neg 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
|
|
+ neg ffffffffffffffff => 0000000000000001 (00000000 00000000)
|
|
+
|
|
+ nego 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ nego 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
|
|
+ nego ffffffffffffffff => 0000000000000001 (00000000 00000000)
|
|
+
|
|
+ cntlzd 0000000000000000 => 0000000000000040 (00000000 00000000)
|
|
+ cntlzd 0000001cbe991def => 000000000000001b (00000000 00000000)
|
|
+ cntlzd ffffffffffffffff => 0000000000000000 (00000000 00000000)
|
|
+
|
|
+ extsw 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ extsw 0000001cbe991def => ffffffffbe991def (00000000 00000000)
|
|
+ extsw ffffffffffffffff => ffffffffffffffff (00000000 00000000)
|
|
+
|
|
+PPC integer logical insns with one arg with flags update:
|
|
+ cntlzw. 0000000000000000 => 0000000000000020 (40000000 00000000)
|
|
+ cntlzw. 0000001cbe991def => 0000000000000000 (20000000 00000000)
|
|
+ cntlzw. ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+
|
|
+ extsb. 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ extsb. 0000001cbe991def => ffffffffffffffef (80000000 00000000)
|
|
+ extsb. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+
|
|
+ extsh. 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ extsh. 0000001cbe991def => 0000000000001def (40000000 00000000)
|
|
+ extsh. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+
|
|
+ neg. 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ neg. 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
|
|
+ neg. ffffffffffffffff => 0000000000000001 (40000000 00000000)
|
|
+
|
|
+ nego. 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ nego. 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
|
|
+ nego. ffffffffffffffff => 0000000000000001 (40000000 00000000)
|
|
+
|
|
+ cntlzd. 0000000000000000 => 0000000000000040 (40000000 00000000)
|
|
+ cntlzd. 0000001cbe991def => 000000000000001b (40000000 00000000)
|
|
+ cntlzd. ffffffffffffffff => 0000000000000000 (20000000 00000000)
|
|
+
|
|
+ extsw. 0000000000000000 => 0000000000000000 (20000000 00000000)
|
|
+ extsw. 0000001cbe991def => ffffffffbe991def (80000000 00000000)
|
|
+ extsw. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
|
|
+
|
|
+PPC logical insns with special forms:
|
|
+ rlwimi 0000000000000000, 0, 0, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rlwimi 0000000000000000, 0, 0, 31 => 0000000000000000 (00000000 00000000)
|
|
+ rlwimi 0000000000000000, 0, 31, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rlwimi 0000000000000000, 0, 31, 31 => 0000000000000000 (00000000 00000000)
|
|
+ rlwimi 0000000000000000, 31, 0, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rlwimi 0000000000000000, 31, 0, 31 => 0000000000000000 (00000000 00000000)
|
|
+ rlwimi 0000000000000000, 31, 31, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rlwimi 0000000000000000, 31, 31, 31 => 0000000000000000 (00000000 00000000)
|
|
+ rlwimi 0000001cbe991def, 0, 0, 0 => 0000000080000000 (00000000 00000000)
|
|
+ rlwimi 0000001cbe991def, 0, 0, 31 => 00000000be991def (00000000 00000000)
|
|
+ rlwimi 0000001cbe991def, 0, 31, 0 => be991defbe991def (00000000 00000000)
|
|
+ rlwimi 0000001cbe991def, 0, 31, 31 => be991defbe991def (00000000 00000000)
|
|
+ rlwimi 0000001cbe991def, 31, 0, 0 => be991defbe991def (00000000 00000000)
|
|
+ rlwimi 0000001cbe991def, 31, 0, 31 => be991defdf4c8ef7 (00000000 00000000)
|
|
+ rlwimi 0000001cbe991def, 31, 31, 0 => df4c8ef7df4c8ef7 (00000000 00000000)
|
|
+ rlwimi 0000001cbe991def, 31, 31, 31 => df4c8ef7df4c8ef7 (00000000 00000000)
|
|
+ rlwimi ffffffffffffffff, 0, 0, 0 => df4c8ef7df4c8ef7 (00000000 00000000)
|
|
+ rlwimi ffffffffffffffff, 0, 0, 31 => df4c8ef7ffffffff (00000000 00000000)
|
|
+ rlwimi ffffffffffffffff, 0, 31, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rlwimi ffffffffffffffff, 0, 31, 31 => ffffffffffffffff (00000000 00000000)
|
|
+ rlwimi ffffffffffffffff, 31, 0, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rlwimi ffffffffffffffff, 31, 0, 31 => ffffffffffffffff (00000000 00000000)
|
|
+ rlwimi ffffffffffffffff, 31, 31, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rlwimi ffffffffffffffff, 31, 31, 31 => ffffffffffffffff (00000000 00000000)
|
|
+
|
|
+ rlwinm 0000000000000000, 0, 0, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rlwinm 0000000000000000, 0, 0, 31 => 0000000000000000 (00000000 00000000)
|
|
+ rlwinm 0000000000000000, 0, 31, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rlwinm 0000000000000000, 0, 31, 31 => 0000000000000000 (00000000 00000000)
|
|
+ rlwinm 0000000000000000, 31, 0, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rlwinm 0000000000000000, 31, 0, 31 => 0000000000000000 (00000000 00000000)
|
|
+ rlwinm 0000000000000000, 31, 31, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rlwinm 0000000000000000, 31, 31, 31 => 0000000000000000 (00000000 00000000)
|
|
+ rlwinm 0000001cbe991def, 0, 0, 0 => 0000000080000000 (00000000 00000000)
|
|
+ rlwinm 0000001cbe991def, 0, 0, 31 => 00000000be991def (00000000 00000000)
|
|
+ rlwinm 0000001cbe991def, 0, 31, 0 => be991def80000001 (00000000 00000000)
|
|
+ rlwinm 0000001cbe991def, 0, 31, 31 => 0000000000000001 (00000000 00000000)
|
|
+ rlwinm 0000001cbe991def, 31, 0, 0 => 0000000080000000 (00000000 00000000)
|
|
+ rlwinm 0000001cbe991def, 31, 0, 31 => 00000000df4c8ef7 (00000000 00000000)
|
|
+ rlwinm 0000001cbe991def, 31, 31, 0 => df4c8ef780000001 (00000000 00000000)
|
|
+ rlwinm 0000001cbe991def, 31, 31, 31 => 0000000000000001 (00000000 00000000)
|
|
+ rlwinm ffffffffffffffff, 0, 0, 0 => 0000000080000000 (00000000 00000000)
|
|
+ rlwinm ffffffffffffffff, 0, 0, 31 => 00000000ffffffff (00000000 00000000)
|
|
+ rlwinm ffffffffffffffff, 0, 31, 0 => ffffffff80000001 (00000000 00000000)
|
|
+ rlwinm ffffffffffffffff, 0, 31, 31 => 0000000000000001 (00000000 00000000)
|
|
+ rlwinm ffffffffffffffff, 31, 0, 0 => 0000000080000000 (00000000 00000000)
|
|
+ rlwinm ffffffffffffffff, 31, 0, 31 => 00000000ffffffff (00000000 00000000)
|
|
+ rlwinm ffffffffffffffff, 31, 31, 0 => ffffffff80000001 (00000000 00000000)
|
|
+ rlwinm ffffffffffffffff, 31, 31, 31 => 0000000000000001 (00000000 00000000)
|
|
+
|
|
+ rlwnm 0000000000000000, 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rlwnm 0000000000000000, 0000000000000000, 0, 31 => 0000000000000000 (00000000 00000000)
|
|
+ rlwnm 0000000000000000, 0000000000000000, 31, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rlwnm 0000000000000000, 0000000000000000, 31, 31 => 0000000000000000 (00000000 00000000)
|
|
+ rlwnm 0000000000000000, 0000001cbe991def, 0, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rlwnm 0000000000000000, 0000001cbe991def, 0, 31 => 0000000000000000 (00000000 00000000)
|
|
+ rlwnm 0000000000000000, 0000001cbe991def, 31, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rlwnm 0000000000000000, 0000001cbe991def, 31, 31 => 0000000000000000 (00000000 00000000)
|
|
+ rlwnm 0000000000000000, ffffffffffffffff, 0, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rlwnm 0000000000000000, ffffffffffffffff, 0, 31 => 0000000000000000 (00000000 00000000)
|
|
+ rlwnm 0000000000000000, ffffffffffffffff, 31, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rlwnm 0000000000000000, ffffffffffffffff, 31, 31 => 0000000000000000 (00000000 00000000)
|
|
+ rlwnm 0000001cbe991def, 0000000000000000, 0, 0 => 0000000080000000 (00000000 00000000)
|
|
+ rlwnm 0000001cbe991def, 0000000000000000, 0, 31 => 00000000be991def (00000000 00000000)
|
|
+ rlwnm 0000001cbe991def, 0000000000000000, 31, 0 => be991def80000001 (00000000 00000000)
|
|
+ rlwnm 0000001cbe991def, 0000000000000000, 31, 31 => 0000000000000001 (00000000 00000000)
|
|
+ rlwnm 0000001cbe991def, 0000001cbe991def, 0, 0 => 0000000080000000 (00000000 00000000)
|
|
+ rlwnm 0000001cbe991def, 0000001cbe991def, 0, 31 => 000000008ef7df4c (00000000 00000000)
|
|
+ rlwnm 0000001cbe991def, 0000001cbe991def, 31, 0 => 8ef7df4c80000000 (00000000 00000000)
|
|
+ rlwnm 0000001cbe991def, 0000001cbe991def, 31, 31 => 0000000000000000 (00000000 00000000)
|
|
+ rlwnm 0000001cbe991def, ffffffffffffffff, 0, 0 => 0000000080000000 (00000000 00000000)
|
|
+ rlwnm 0000001cbe991def, ffffffffffffffff, 0, 31 => 00000000df4c8ef7 (00000000 00000000)
|
|
+ rlwnm 0000001cbe991def, ffffffffffffffff, 31, 0 => df4c8ef780000001 (00000000 00000000)
|
|
+ rlwnm 0000001cbe991def, ffffffffffffffff, 31, 31 => 0000000000000001 (00000000 00000000)
|
|
+ rlwnm ffffffffffffffff, 0000000000000000, 0, 0 => 0000000080000000 (00000000 00000000)
|
|
+ rlwnm ffffffffffffffff, 0000000000000000, 0, 31 => 00000000ffffffff (00000000 00000000)
|
|
+ rlwnm ffffffffffffffff, 0000000000000000, 31, 0 => ffffffff80000001 (00000000 00000000)
|
|
+ rlwnm ffffffffffffffff, 0000000000000000, 31, 31 => 0000000000000001 (00000000 00000000)
|
|
+ rlwnm ffffffffffffffff, 0000001cbe991def, 0, 0 => 0000000080000000 (00000000 00000000)
|
|
+ rlwnm ffffffffffffffff, 0000001cbe991def, 0, 31 => 00000000ffffffff (00000000 00000000)
|
|
+ rlwnm ffffffffffffffff, 0000001cbe991def, 31, 0 => ffffffff80000001 (00000000 00000000)
|
|
+ rlwnm ffffffffffffffff, 0000001cbe991def, 31, 31 => 0000000000000001 (00000000 00000000)
|
|
+ rlwnm ffffffffffffffff, ffffffffffffffff, 0, 0 => 0000000080000000 (00000000 00000000)
|
|
+ rlwnm ffffffffffffffff, ffffffffffffffff, 0, 31 => 00000000ffffffff (00000000 00000000)
|
|
+ rlwnm ffffffffffffffff, ffffffffffffffff, 31, 0 => ffffffff80000001 (00000000 00000000)
|
|
+ rlwnm ffffffffffffffff, ffffffffffffffff, 31, 31 => 0000000000000001 (00000000 00000000)
|
|
+
|
|
+ srawi 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
|
|
+ srawi 0000000000000000, 31 => 0000000000000000 (00000000 00000000)
|
|
+ srawi 0000001cbe991def, 0 => ffffffffbe991def (00000000 00000000)
|
|
+ srawi 0000001cbe991def, 31 => ffffffffffffffff (00000000 20000000)
|
|
+ srawi ffffffffffffffff, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ srawi ffffffffffffffff, 31 => ffffffffffffffff (00000000 20000000)
|
|
+
|
|
+ mfcr (0000000000000000) => 0000000000000000 (00000000 00000000)
|
|
+ mfcr (0000001cbe991def) => 00000000be991def (be991def 00000000)
|
|
+ mfcr (ffffffffffffffff) => 00000000ffffffff (ffffffff 00000000)
|
|
+
|
|
+ mfspr 1 (00000000) -> mtxer -> mfxer => 0000000000000000
|
|
+ mfspr 1 (be991def) -> mtxer -> mfxer => 00000000a000006f
|
|
+ mfspr 1 (ffffffff) -> mtxer -> mfxer => 00000000e000007f
|
|
+ mfspr 8 (00000000) -> mtlr -> mflr => 0000000000000000
|
|
+ mfspr 8 (be991def) -> mtlr -> mflr => ffffffffbe991def
|
|
+ mfspr 8 (ffffffff) -> mtlr -> mflr => ffffffffffffffff
|
|
+ mfspr 9 (00000000) -> mtctr -> mfctr => 0000000000000000
|
|
+ mfspr 9 (be991def) -> mtctr -> mfctr => ffffffffbe991def
|
|
+ mfspr 9 (ffffffff) -> mtctr -> mfctr => ffffffffffffffff
|
|
+
|
|
+
|
|
+ rldcl 0000000000000000, 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, 0000000000000000, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, 0000000000000000, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, 0000000000000000, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, 0000000000000000, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, 0000000000000000, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, 0000000000000000, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, 0000000000000000, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, 0000000000000000, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, 0000000000000000, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, 0000000000000000, 0 => 0000001cbe991def (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, 0000000000000000, 7 => 0000001cbe991def (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, 0000000000000000, 14 => 0000001cbe991def (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, 0000000000000000, 21 => 0000001cbe991def (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, 0000000000000000, 28 => 0000000cbe991def (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, 0000000000000000, 35 => 000000001e991def (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, 0000000000000000, 42 => 0000000000191def (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, 0000000000000000, 49 => 0000000000001def (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, 0000000000000000, 56 => 00000000000000ef (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, 0000000000000000, 63 => 0000000000000001 (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, 0000001cbe991def, 0 => 8ef78000000e5f4c (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, 0000001cbe991def, 7 => 00f78000000e5f4c (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, 0000001cbe991def, 14 => 00038000000e5f4c (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, 0000001cbe991def, 21 => 00000000000e5f4c (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, 0000001cbe991def, 28 => 00000000000e5f4c (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, 0000001cbe991def, 35 => 00000000000e5f4c (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, 0000001cbe991def, 42 => 00000000000e5f4c (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, 0000001cbe991def, 49 => 0000000000005f4c (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, 0000001cbe991def, 56 => 000000000000004c (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, ffffffffffffffff, 0 => 8000000e5f4c8ef7 (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, ffffffffffffffff, 7 => 0000000e5f4c8ef7 (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, ffffffffffffffff, 14 => 0000000e5f4c8ef7 (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, ffffffffffffffff, 21 => 0000000e5f4c8ef7 (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, ffffffffffffffff, 28 => 0000000e5f4c8ef7 (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, ffffffffffffffff, 35 => 000000001f4c8ef7 (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, ffffffffffffffff, 42 => 00000000000c8ef7 (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, ffffffffffffffff, 49 => 0000000000000ef7 (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, ffffffffffffffff, 56 => 00000000000000f7 (00000000 00000000)
|
|
+ rldcl 0000001cbe991def, ffffffffffffffff, 63 => 0000000000000001 (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, 0000000000000000, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, 0000000000000000, 7 => 01ffffffffffffff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, 0000000000000000, 14 => 0003ffffffffffff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, 0000000000000000, 21 => 000007ffffffffff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, 0000000000000000, 28 => 0000000fffffffff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, 0000000000000000, 35 => 000000001fffffff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, 0000000000000000, 42 => 00000000003fffff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, 0000000000000000, 49 => 0000000000007fff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, 0000000000000000, 56 => 00000000000000ff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, 0000000000000000, 63 => 0000000000000001 (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, 0000001cbe991def, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, 0000001cbe991def, 7 => 01ffffffffffffff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, 0000001cbe991def, 14 => 0003ffffffffffff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, 0000001cbe991def, 21 => 000007ffffffffff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, 0000001cbe991def, 28 => 0000000fffffffff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, 0000001cbe991def, 35 => 000000001fffffff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, 0000001cbe991def, 42 => 00000000003fffff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, 0000001cbe991def, 49 => 0000000000007fff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, 0000001cbe991def, 56 => 00000000000000ff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, 0000001cbe991def, 63 => 0000000000000001 (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, ffffffffffffffff, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, ffffffffffffffff, 7 => 01ffffffffffffff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, ffffffffffffffff, 14 => 0003ffffffffffff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, ffffffffffffffff, 21 => 000007ffffffffff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, ffffffffffffffff, 28 => 0000000fffffffff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, ffffffffffffffff, 35 => 000000001fffffff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, ffffffffffffffff, 42 => 00000000003fffff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, ffffffffffffffff, 49 => 0000000000007fff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, ffffffffffffffff, 56 => 00000000000000ff (00000000 00000000)
|
|
+ rldcl ffffffffffffffff, ffffffffffffffff, 63 => 0000000000000001 (00000000 00000000)
|
|
+
|
|
+ rldcr 0000000000000000, 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, 0000000000000000, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, 0000000000000000, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, 0000000000000000, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, 0000000000000000, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, 0000000000000000, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, 0000000000000000, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, 0000000000000000, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, 0000000000000000, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, 0000000000000000, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, 0000000000000000, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, 0000000000000000, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, 0000000000000000, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, 0000000000000000, 28 => 0000001800000000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, 0000000000000000, 35 => 0000001cb0000000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, 0000000000000000, 42 => 0000001cbe800000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, 0000000000000000, 49 => 0000001cbe990000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, 0000000000000000, 56 => 0000001cbe991d80 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, 0000000000000000, 63 => 0000001cbe991def (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, 0000001cbe991def, 0 => 8000000000000000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, 0000001cbe991def, 7 => 8e00000000000000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, 0000001cbe991def, 14 => 8ef6000000000000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, 0000001cbe991def, 21 => 8ef7800000000000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, 0000001cbe991def, 28 => 8ef7800000000000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, 0000001cbe991def, 35 => 8ef7800000000000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, 0000001cbe991def, 42 => 8ef7800000000000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, 0000001cbe991def, 49 => 8ef78000000e4000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, 0000001cbe991def, 56 => 8ef78000000e5f00 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, 0000001cbe991def, 63 => 8ef78000000e5f4c (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, ffffffffffffffff, 0 => 8000000000000000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, ffffffffffffffff, 7 => 8000000000000000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, ffffffffffffffff, 14 => 8000000000000000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, ffffffffffffffff, 21 => 8000000000000000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, ffffffffffffffff, 28 => 8000000800000000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, ffffffffffffffff, 35 => 8000000e50000000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, ffffffffffffffff, 42 => 8000000e5f400000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, ffffffffffffffff, 49 => 8000000e5f4c8000 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, ffffffffffffffff, 56 => 8000000e5f4c8e80 (00000000 00000000)
|
|
+ rldcr 0000001cbe991def, ffffffffffffffff, 63 => 8000000e5f4c8ef7 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, 0000000000000000, 0 => 8000000000000000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, 0000000000000000, 7 => ff00000000000000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, 0000000000000000, 14 => fffe000000000000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, 0000000000000000, 21 => fffffc0000000000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, 0000000000000000, 28 => fffffff800000000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, 0000000000000000, 35 => fffffffff0000000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, 0000000000000000, 42 => ffffffffffe00000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, 0000000000000000, 49 => ffffffffffffc000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, 0000000000000000, 56 => ffffffffffffff80 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, 0000000000000000, 63 => ffffffffffffffff (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, 0000001cbe991def, 0 => 8000000000000000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, 0000001cbe991def, 7 => ff00000000000000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, 0000001cbe991def, 14 => fffe000000000000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, 0000001cbe991def, 21 => fffffc0000000000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, 0000001cbe991def, 28 => fffffff800000000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, 0000001cbe991def, 35 => fffffffff0000000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, 0000001cbe991def, 42 => ffffffffffe00000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, 0000001cbe991def, 49 => ffffffffffffc000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, 0000001cbe991def, 56 => ffffffffffffff80 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, 0000001cbe991def, 63 => ffffffffffffffff (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, ffffffffffffffff, 0 => 8000000000000000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, ffffffffffffffff, 7 => ff00000000000000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, ffffffffffffffff, 14 => fffe000000000000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, ffffffffffffffff, 21 => fffffc0000000000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, ffffffffffffffff, 28 => fffffff800000000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, ffffffffffffffff, 35 => fffffffff0000000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, ffffffffffffffff, 42 => ffffffffffe00000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, ffffffffffffffff, 49 => ffffffffffffc000 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, ffffffffffffffff, 56 => ffffffffffffff80 (00000000 00000000)
|
|
+ rldcr ffffffffffffffff, ffffffffffffffff, 63 => ffffffffffffffff (00000000 00000000)
|
|
+
|
|
+ rldic 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 0, 0 => 0000001cbe991def (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 0, 7 => 0000001cbe991def (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 0, 14 => 0000001cbe991def (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 0, 21 => 0000001cbe991def (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 0, 28 => 0000000cbe991def (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 0, 35 => 000000001e991def (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 0, 42 => 0000000000191def (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 0, 49 => 0000000000001def (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 0, 56 => 00000000000000ef (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 0, 63 => 0000000000000001 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 7, 35 => 000000000c8ef780 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 7, 42 => 00000000000ef780 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 7, 49 => 0000000000007780 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 7, 56 => 0000000000000080 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 14, 0 => 00072fa6477bc000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 14, 7 => 00072fa6477bc000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 14, 14 => 00032fa6477bc000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 14, 21 => 000007a6477bc000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 14, 28 => 00000006477bc000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 14, 35 => 00000000077bc000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 14, 42 => 00000000003bc000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 14, 49 => 0000000000004000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 14, 56 => 00072fa6477bc000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 14, 63 => 00072fa6477bc000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 21, 0 => 0397d323bde00000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 21, 7 => 0197d323bde00000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 21, 14 => 0003d323bde00000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 21, 21 => 00000323bde00000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 21, 28 => 00000003bde00000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 21, 35 => 000000001de00000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 21, 42 => 0000000000200000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 21, 49 => 0397d323bde00000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 21, 56 => 0397d323bde00000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 21, 63 => 0397d323bde00000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 28, 0 => cbe991def0000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 28, 7 => 01e991def0000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 28, 14 => 000191def0000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 28, 21 => 000001def0000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 28, 28 => 0000000ef0000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 28, 35 => 0000000010000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 28, 42 => cbe991def0000001 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 28, 49 => cbe991def0000001 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 28, 56 => cbe991def0000001 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 28, 63 => cbe991def0000001 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 35, 0 => f4c8ef7800000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 35, 7 => 00c8ef7800000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 35, 14 => 0000ef7800000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 35, 21 => 0000077800000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 35, 28 => 0000000800000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 35, 35 => f4c8ef78000000e5 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 35, 42 => f4c8ef78000000e5 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 35, 49 => f4c8ef78000000e5 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 35, 56 => f4c8ef78000000e5 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 35, 63 => f4c8ef7800000001 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 42, 0 => 6477bc0000000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 42, 7 => 0077bc0000000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 42, 14 => 0003bc0000000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 42, 21 => 0000040000000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 42, 28 => 6477bc00000072fa (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 42, 35 => 6477bc00000072fa (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 42, 42 => 6477bc00000072fa (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 42, 49 => 6477bc00000072fa (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 42, 56 => 6477bc00000000fa (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 42, 63 => 6477bc0000000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 49, 0 => 3bde000000000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 49, 7 => 01de000000000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 49, 14 => 0002000000000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 49, 21 => 3bde000000397d32 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 49, 28 => 3bde000000397d32 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 49, 35 => 3bde000000397d32 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 49, 42 => 3bde000000397d32 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 49, 49 => 3bde000000007d32 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 49, 56 => 3bde000000000032 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 49, 63 => 3bde000000000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 56, 0 => ef00000000000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 56, 7 => 0100000000000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 56, 14 => ef0000001cbe991d (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 56, 21 => ef0000001cbe991d (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 56, 28 => ef0000001cbe991d (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 56, 35 => ef0000001cbe991d (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 56, 42 => ef000000003e991d (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 56, 49 => ef0000000000191d (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 56, 56 => ef0000000000001d (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 56, 63 => ef00000000000001 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 63, 0 => 8000000000000000 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 63, 7 => 8000000e5f4c8ef7 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 63, 14 => 8000000e5f4c8ef7 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 63, 21 => 8000000e5f4c8ef7 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 63, 28 => 8000000e5f4c8ef7 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 63, 35 => 800000001f4c8ef7 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 63, 42 => 80000000000c8ef7 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 63, 49 => 8000000000000ef7 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 63, 56 => 80000000000000f7 (00000000 00000000)
|
|
+ rldic 0000001cbe991def, 63, 63 => 8000000000000001 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 0, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 0, 7 => 01ffffffffffffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 0, 14 => 0003ffffffffffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 0, 21 => 000007ffffffffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 0, 28 => 0000000fffffffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 0, 35 => 000000001fffffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 0, 42 => 00000000003fffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 0, 49 => 0000000000007fff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 0, 56 => 00000000000000ff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 0, 63 => 0000000000000001 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 7, 0 => ffffffffffffff80 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 7, 7 => 01ffffffffffff80 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 7, 14 => 0003ffffffffff80 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 7, 21 => 000007ffffffff80 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 7, 28 => 0000000fffffff80 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 7, 35 => 000000001fffff80 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 7, 42 => 00000000003fff80 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 7, 49 => 0000000000007f80 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 7, 56 => 0000000000000080 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 7, 63 => ffffffffffffff81 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 14, 0 => ffffffffffffc000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 14, 7 => 01ffffffffffc000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 14, 14 => 0003ffffffffc000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 14, 21 => 000007ffffffc000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 14, 28 => 0000000fffffc000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 14, 35 => 000000001fffc000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 14, 42 => 00000000003fc000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 14, 49 => 0000000000004000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 14, 56 => ffffffffffffc0ff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 14, 63 => ffffffffffffc001 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 21, 0 => ffffffffffe00000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 21, 7 => 01ffffffffe00000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 21, 14 => 0003ffffffe00000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 21, 21 => 000007ffffe00000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 21, 28 => 0000000fffe00000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 21, 35 => 000000001fe00000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 21, 42 => 0000000000200000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 21, 49 => ffffffffffe07fff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 21, 56 => ffffffffffe000ff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 21, 63 => ffffffffffe00001 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 28, 0 => fffffffff0000000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 28, 7 => 01fffffff0000000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 28, 14 => 0003fffff0000000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 28, 21 => 000007fff0000000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 28, 28 => 0000000ff0000000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 28, 35 => 0000000010000000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 28, 42 => fffffffff03fffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 28, 49 => fffffffff0007fff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 28, 56 => fffffffff00000ff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 28, 63 => fffffffff0000001 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 35, 0 => fffffff800000000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 35, 7 => 01fffff800000000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 35, 14 => 0003fff800000000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 35, 21 => 000007f800000000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 35, 28 => 0000000800000000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 35, 35 => fffffff81fffffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 35, 42 => fffffff8003fffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 35, 49 => fffffff800007fff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 35, 56 => fffffff8000000ff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 35, 63 => fffffff800000001 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 42, 0 => fffffc0000000000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 42, 7 => 01fffc0000000000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 42, 14 => 0003fc0000000000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 42, 21 => 0000040000000000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 42, 28 => fffffc0fffffffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 42, 35 => fffffc001fffffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 42, 42 => fffffc00003fffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 42, 49 => fffffc0000007fff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 42, 56 => fffffc00000000ff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 42, 63 => fffffc0000000001 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 49, 0 => fffe000000000000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 49, 7 => 01fe000000000000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 49, 14 => 0002000000000000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 49, 21 => fffe07ffffffffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 49, 28 => fffe000fffffffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 49, 35 => fffe00001fffffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 49, 42 => fffe0000003fffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 49, 49 => fffe000000007fff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 49, 56 => fffe0000000000ff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 49, 63 => fffe000000000001 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 56, 0 => ff00000000000000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 56, 7 => 0100000000000000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 56, 14 => ff03ffffffffffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 56, 21 => ff0007ffffffffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 56, 28 => ff00000fffffffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 56, 35 => ff0000001fffffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 56, 42 => ff000000003fffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 56, 49 => ff00000000007fff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 56, 56 => ff000000000000ff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 56, 63 => ff00000000000001 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 63, 0 => 8000000000000000 (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 63, 7 => 81ffffffffffffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 63, 14 => 8003ffffffffffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 63, 21 => 800007ffffffffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 63, 28 => 8000000fffffffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 63, 35 => 800000001fffffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 63, 42 => 80000000003fffff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 63, 49 => 8000000000007fff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 63, 56 => 80000000000000ff (00000000 00000000)
|
|
+ rldic ffffffffffffffff, 63, 63 => 8000000000000001 (00000000 00000000)
|
|
+
|
|
+ rldicl 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 0, 0 => 0000001cbe991def (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 0, 7 => 0000001cbe991def (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 0, 14 => 0000001cbe991def (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 0, 21 => 0000001cbe991def (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 0, 28 => 0000000cbe991def (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 0, 35 => 000000001e991def (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 0, 42 => 0000000000191def (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 0, 49 => 0000000000001def (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 0, 56 => 00000000000000ef (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 0, 63 => 0000000000000001 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 7, 35 => 000000000c8ef780 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 7, 42 => 00000000000ef780 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 7, 49 => 0000000000007780 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 7, 56 => 0000000000000080 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 7, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 14, 0 => 00072fa6477bc000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 14, 7 => 00072fa6477bc000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 14, 14 => 00032fa6477bc000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 14, 21 => 000007a6477bc000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 14, 28 => 00000006477bc000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 14, 35 => 00000000077bc000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 14, 42 => 00000000003bc000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 14, 49 => 0000000000004000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 14, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 14, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 21, 0 => 0397d323bde00000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 21, 7 => 0197d323bde00000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 21, 14 => 0003d323bde00000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 21, 21 => 00000323bde00000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 21, 28 => 00000003bde00000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 21, 35 => 000000001de00000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 21, 42 => 0000000000200000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 21, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 21, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 21, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 28, 0 => cbe991def0000001 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 28, 7 => 01e991def0000001 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 28, 14 => 000191def0000001 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 28, 21 => 000001def0000001 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 28, 28 => 0000000ef0000001 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 28, 35 => 0000000010000001 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 28, 42 => 0000000000000001 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 28, 49 => 0000000000000001 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 28, 56 => 0000000000000001 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 28, 63 => 0000000000000001 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 35, 0 => f4c8ef78000000e5 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 35, 7 => 00c8ef78000000e5 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 35, 14 => 0000ef78000000e5 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 35, 21 => 00000778000000e5 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 35, 28 => 00000008000000e5 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 35, 35 => 00000000000000e5 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 35, 42 => 00000000000000e5 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 35, 49 => 00000000000000e5 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 35, 56 => 00000000000000e5 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 35, 63 => 0000000000000001 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 42, 0 => 6477bc00000072fa (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 42, 7 => 0077bc00000072fa (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 42, 14 => 0003bc00000072fa (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 42, 21 => 00000400000072fa (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 42, 28 => 00000000000072fa (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 42, 35 => 00000000000072fa (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 42, 42 => 00000000000072fa (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 42, 49 => 00000000000072fa (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 42, 56 => 00000000000000fa (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 42, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 49, 0 => 3bde000000397d32 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 49, 7 => 01de000000397d32 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 49, 14 => 0002000000397d32 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 49, 21 => 0000000000397d32 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 49, 28 => 0000000000397d32 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 49, 35 => 0000000000397d32 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 49, 42 => 0000000000397d32 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 49, 49 => 0000000000007d32 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 49, 56 => 0000000000000032 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 49, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 56, 0 => ef0000001cbe991d (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 56, 7 => 010000001cbe991d (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 56, 14 => 000000001cbe991d (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 56, 21 => 000000001cbe991d (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 56, 28 => 000000001cbe991d (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 56, 35 => 000000001cbe991d (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 56, 42 => 00000000003e991d (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 56, 49 => 000000000000191d (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 56, 56 => 000000000000001d (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 56, 63 => 0000000000000001 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 63, 0 => 8000000e5f4c8ef7 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 63, 7 => 0000000e5f4c8ef7 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 63, 14 => 0000000e5f4c8ef7 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 63, 21 => 0000000e5f4c8ef7 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 63, 28 => 0000000e5f4c8ef7 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 63, 35 => 000000001f4c8ef7 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 63, 42 => 00000000000c8ef7 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 63, 49 => 0000000000000ef7 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 63, 56 => 00000000000000f7 (00000000 00000000)
|
|
+ rldicl 0000001cbe991def, 63, 63 => 0000000000000001 (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 0, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 0, 7 => 01ffffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 0, 14 => 0003ffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 0, 21 => 000007ffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 0, 28 => 0000000fffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 0, 35 => 000000001fffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 0, 42 => 00000000003fffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 0, 49 => 0000000000007fff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 0, 56 => 00000000000000ff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 0, 63 => 0000000000000001 (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 7, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 7, 7 => 01ffffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 7, 14 => 0003ffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 7, 21 => 000007ffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 7, 28 => 0000000fffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 7, 35 => 000000001fffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 7, 42 => 00000000003fffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 7, 49 => 0000000000007fff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 7, 56 => 00000000000000ff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 7, 63 => 0000000000000001 (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 14, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 14, 7 => 01ffffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 14, 14 => 0003ffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 14, 21 => 000007ffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 14, 28 => 0000000fffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 14, 35 => 000000001fffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 14, 42 => 00000000003fffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 14, 49 => 0000000000007fff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 14, 56 => 00000000000000ff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 14, 63 => 0000000000000001 (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 21, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 21, 7 => 01ffffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 21, 14 => 0003ffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 21, 21 => 000007ffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 21, 28 => 0000000fffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 21, 35 => 000000001fffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 21, 42 => 00000000003fffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 21, 49 => 0000000000007fff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 21, 56 => 00000000000000ff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 21, 63 => 0000000000000001 (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 28, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 28, 7 => 01ffffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 28, 14 => 0003ffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 28, 21 => 000007ffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 28, 28 => 0000000fffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 28, 35 => 000000001fffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 28, 42 => 00000000003fffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 28, 49 => 0000000000007fff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 28, 56 => 00000000000000ff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 28, 63 => 0000000000000001 (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 35, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 35, 7 => 01ffffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 35, 14 => 0003ffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 35, 21 => 000007ffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 35, 28 => 0000000fffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 35, 35 => 000000001fffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 35, 42 => 00000000003fffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 35, 49 => 0000000000007fff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 35, 56 => 00000000000000ff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 35, 63 => 0000000000000001 (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 42, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 42, 7 => 01ffffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 42, 14 => 0003ffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 42, 21 => 000007ffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 42, 28 => 0000000fffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 42, 35 => 000000001fffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 42, 42 => 00000000003fffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 42, 49 => 0000000000007fff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 42, 56 => 00000000000000ff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 42, 63 => 0000000000000001 (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 49, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 49, 7 => 01ffffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 49, 14 => 0003ffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 49, 21 => 000007ffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 49, 28 => 0000000fffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 49, 35 => 000000001fffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 49, 42 => 00000000003fffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 49, 49 => 0000000000007fff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 49, 56 => 00000000000000ff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 49, 63 => 0000000000000001 (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 56, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 56, 7 => 01ffffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 56, 14 => 0003ffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 56, 21 => 000007ffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 56, 28 => 0000000fffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 56, 35 => 000000001fffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 56, 42 => 00000000003fffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 56, 49 => 0000000000007fff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 56, 56 => 00000000000000ff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 56, 63 => 0000000000000001 (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 63, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 63, 7 => 01ffffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 63, 14 => 0003ffffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 63, 21 => 000007ffffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 63, 28 => 0000000fffffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 63, 35 => 000000001fffffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 63, 42 => 00000000003fffff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 63, 49 => 0000000000007fff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 63, 56 => 00000000000000ff (00000000 00000000)
|
|
+ rldicl ffffffffffffffff, 63, 63 => 0000000000000001 (00000000 00000000)
|
|
+
|
|
+ rldicr 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 0, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 0, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 0, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 0, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 0, 28 => 0000001800000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 0, 35 => 0000001cb0000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 0, 42 => 0000001cbe800000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 0, 49 => 0000001cbe990000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 0, 56 => 0000001cbe991d80 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 0, 63 => 0000001cbe991def (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 7, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 7, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 7, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 7, 21 => 00000c0000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 7, 28 => 00000e5800000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 7, 35 => 00000e5f40000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 7, 42 => 00000e5f4c800000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 7, 49 => 00000e5f4c8ec000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 7, 56 => 00000e5f4c8ef780 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 14, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 14, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 14, 14 => 0006000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 14, 21 => 00072c0000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 14, 28 => 00072fa000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 14, 35 => 00072fa640000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 14, 42 => 00072fa647600000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 14, 49 => 00072fa6477bc000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 14, 56 => 00072fa6477bc000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 14, 63 => 00072fa6477bc000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 21, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 21, 7 => 0300000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 21, 14 => 0396000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 21, 21 => 0397d00000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 21, 28 => 0397d32000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 21, 35 => 0397d323b0000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 21, 42 => 0397d323bde00000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 21, 49 => 0397d323bde00000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 21, 56 => 0397d323bde00000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 21, 63 => 0397d323bde00000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 28, 0 => 8000000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 28, 7 => cb00000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 28, 14 => cbe8000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 28, 21 => cbe9900000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 28, 28 => cbe991d800000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 28, 35 => cbe991def0000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 28, 42 => cbe991def0000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 28, 49 => cbe991def0000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 28, 56 => cbe991def0000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 28, 63 => cbe991def0000001 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 35, 0 => 8000000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 35, 7 => f400000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 35, 14 => f4c8000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 35, 21 => f4c8ec0000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 35, 28 => f4c8ef7800000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 35, 35 => f4c8ef7800000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 35, 42 => f4c8ef7800000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 35, 49 => f4c8ef7800000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 35, 56 => f4c8ef7800000080 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 35, 63 => f4c8ef78000000e5 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 42, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 42, 7 => 6400000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 42, 14 => 6476000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 42, 21 => 6477bc0000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 42, 28 => 6477bc0000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 42, 35 => 6477bc0000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 42, 42 => 6477bc0000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 42, 49 => 6477bc0000004000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 42, 56 => 6477bc0000007280 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 42, 63 => 6477bc00000072fa (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 49, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 49, 7 => 3b00000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 49, 14 => 3bde000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 49, 21 => 3bde000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 49, 28 => 3bde000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 49, 35 => 3bde000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 49, 42 => 3bde000000200000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 49, 49 => 3bde000000394000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 49, 56 => 3bde000000397d00 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 49, 63 => 3bde000000397d32 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 56, 0 => 8000000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 56, 7 => ef00000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 56, 14 => ef00000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 56, 21 => ef00000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 56, 28 => ef00000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 56, 35 => ef00000010000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 56, 42 => ef0000001ca00000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 56, 49 => ef0000001cbe8000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 56, 56 => ef0000001cbe9900 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 56, 63 => ef0000001cbe991d (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 63, 0 => 8000000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 63, 7 => 8000000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 63, 14 => 8000000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 63, 21 => 8000000000000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 63, 28 => 8000000800000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 63, 35 => 8000000e50000000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 63, 42 => 8000000e5f400000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 63, 49 => 8000000e5f4c8000 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 63, 56 => 8000000e5f4c8e80 (00000000 00000000)
|
|
+ rldicr 0000001cbe991def, 63, 63 => 8000000e5f4c8ef7 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 0, 0 => 8000000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 0, 7 => ff00000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 0, 14 => fffe000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 0, 21 => fffffc0000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 0, 28 => fffffff800000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 0, 35 => fffffffff0000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 0, 42 => ffffffffffe00000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 0, 49 => ffffffffffffc000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 0, 56 => ffffffffffffff80 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 0, 63 => ffffffffffffffff (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 7, 0 => 8000000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 7, 7 => ff00000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 7, 14 => fffe000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 7, 21 => fffffc0000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 7, 28 => fffffff800000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 7, 35 => fffffffff0000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 7, 42 => ffffffffffe00000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 7, 49 => ffffffffffffc000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 7, 56 => ffffffffffffff80 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 7, 63 => ffffffffffffffff (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 14, 0 => 8000000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 14, 7 => ff00000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 14, 14 => fffe000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 14, 21 => fffffc0000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 14, 28 => fffffff800000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 14, 35 => fffffffff0000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 14, 42 => ffffffffffe00000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 14, 49 => ffffffffffffc000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 14, 56 => ffffffffffffff80 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 14, 63 => ffffffffffffffff (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 21, 0 => 8000000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 21, 7 => ff00000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 21, 14 => fffe000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 21, 21 => fffffc0000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 21, 28 => fffffff800000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 21, 35 => fffffffff0000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 21, 42 => ffffffffffe00000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 21, 49 => ffffffffffffc000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 21, 56 => ffffffffffffff80 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 21, 63 => ffffffffffffffff (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 28, 0 => 8000000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 28, 7 => ff00000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 28, 14 => fffe000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 28, 21 => fffffc0000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 28, 28 => fffffff800000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 28, 35 => fffffffff0000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 28, 42 => ffffffffffe00000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 28, 49 => ffffffffffffc000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 28, 56 => ffffffffffffff80 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 28, 63 => ffffffffffffffff (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 35, 0 => 8000000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 35, 7 => ff00000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 35, 14 => fffe000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 35, 21 => fffffc0000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 35, 28 => fffffff800000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 35, 35 => fffffffff0000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 35, 42 => ffffffffffe00000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 35, 49 => ffffffffffffc000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 35, 56 => ffffffffffffff80 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 35, 63 => ffffffffffffffff (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 42, 0 => 8000000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 42, 7 => ff00000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 42, 14 => fffe000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 42, 21 => fffffc0000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 42, 28 => fffffff800000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 42, 35 => fffffffff0000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 42, 42 => ffffffffffe00000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 42, 49 => ffffffffffffc000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 42, 56 => ffffffffffffff80 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 42, 63 => ffffffffffffffff (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 49, 0 => 8000000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 49, 7 => ff00000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 49, 14 => fffe000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 49, 21 => fffffc0000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 49, 28 => fffffff800000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 49, 35 => fffffffff0000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 49, 42 => ffffffffffe00000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 49, 49 => ffffffffffffc000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 49, 56 => ffffffffffffff80 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 49, 63 => ffffffffffffffff (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 56, 0 => 8000000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 56, 7 => ff00000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 56, 14 => fffe000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 56, 21 => fffffc0000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 56, 28 => fffffff800000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 56, 35 => fffffffff0000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 56, 42 => ffffffffffe00000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 56, 49 => ffffffffffffc000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 56, 56 => ffffffffffffff80 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 56, 63 => ffffffffffffffff (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 63, 0 => 8000000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 63, 7 => ff00000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 63, 14 => fffe000000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 63, 21 => fffffc0000000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 63, 28 => fffffff800000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 63, 35 => fffffffff0000000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 63, 42 => ffffffffffe00000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 63, 49 => ffffffffffffc000 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 63, 56 => ffffffffffffff80 (00000000 00000000)
|
|
+ rldicr ffffffffffffffff, 63, 63 => ffffffffffffffff (00000000 00000000)
|
|
+
|
|
+ rldimi 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 0, 0 => 0000001cbe991def (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 0, 7 => 0000001cbe991def (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 0, 14 => 0000001cbe991def (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 0, 21 => 0000001cbe991def (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 0, 28 => 0000001cbe991def (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 0, 35 => 0000001cbe991def (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 0, 42 => 0000001cbe991def (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 0, 49 => 0000001cbe991def (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 0, 56 => 0000001cbe991def (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 0, 63 => 0000001cbe991def (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 7, 0 => 00000e5f4c8ef7ef (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 7, 7 => 00000e5f4c8ef7ef (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 7, 14 => 00000e5f4c8ef7ef (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 7, 21 => 00000e5f4c8ef7ef (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 7, 28 => 00000e5f4c8ef7ef (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 7, 35 => 00000e5f4c8ef7ef (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 7, 42 => 00000e5f4c8ef7ef (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 7, 49 => 00000e5f4c8ef7ef (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 7, 56 => 00000e5f4c8ef7ef (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 7, 63 => 00000e5f4c8ef7ee (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 14, 0 => 00072fa6477bf7ee (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 14, 7 => 00072fa6477bf7ee (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 14, 14 => 00072fa6477bf7ee (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 14, 21 => 00072fa6477bf7ee (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 14, 28 => 00072fa6477bf7ee (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 14, 35 => 00072fa6477bf7ee (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 14, 42 => 00072fa6477bf7ee (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 14, 49 => 00072fa6477bf7ee (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 14, 56 => 00072fa6477bf700 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 14, 63 => 00072fa6477bf700 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 21, 0 => 0397d323bdfbf700 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 21, 7 => 0397d323bdfbf700 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 21, 14 => 0397d323bdfbf700 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 21, 21 => 0397d323bdfbf700 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 21, 28 => 0397d323bdfbf700 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 21, 35 => 0397d323bdfbf700 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 21, 42 => 0397d323bdfbf700 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 21, 49 => 0397d323bdfb8000 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 21, 56 => 0397d323bdfb8000 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 21, 63 => 0397d323bdfb8000 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 28, 0 => cbe991defdfb8000 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 28, 7 => cbe991defdfb8000 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 28, 14 => cbe991defdfb8000 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 28, 21 => cbe991defdfb8000 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 28, 28 => cbe991defdfb8000 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 28, 35 => cbe991defdfb8000 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 28, 42 => cbe991defdc00001 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 28, 49 => cbe991defdc00001 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 28, 56 => cbe991defdc00001 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 28, 63 => cbe991defdc00001 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 35, 0 => f4c8ef7efdc00001 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 35, 7 => f4c8ef7efdc00001 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 35, 14 => f4c8ef7efdc00001 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 35, 21 => f4c8ef7efdc00001 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 35, 28 => f4c8ef7efdc00001 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 35, 35 => f4c8ef7ee00000e5 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 35, 42 => f4c8ef7ee00000e5 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 35, 49 => f4c8ef7ee00000e5 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 35, 56 => f4c8ef7ee00000e5 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 35, 63 => f4c8ef7ee00000e5 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 42, 0 => 6477bf7ee00000e5 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 42, 7 => 6477bf7ee00000e5 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 42, 14 => 6477bf7ee00000e5 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 42, 21 => 6477bf7ee00000e5 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 42, 28 => 6477bf70000072fa (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 42, 35 => 6477bf70000072fa (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 42, 42 => 6477bf70000072fa (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 42, 49 => 6477bf70000072fa (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 42, 56 => 6477bf70000072fa (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 42, 63 => 6477bf70000072fa (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 49, 0 => 3bdfbf70000072fa (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 49, 7 => 3bdfbf70000072fa (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 49, 14 => 3bdfbf70000072fa (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 49, 21 => 3bdfb80000397d32 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 49, 28 => 3bdfb80000397d32 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 49, 35 => 3bdfb80000397d32 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 49, 42 => 3bdfb80000397d32 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 49, 49 => 3bdfb80000397d32 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 49, 56 => 3bdfb80000397d32 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 49, 63 => 3bdfb80000397d32 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 56, 0 => efdfb80000397d32 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 56, 7 => efdfb80000397d32 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 56, 14 => efdc00001cbe991d (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 56, 21 => efdc00001cbe991d (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 56, 28 => efdc00001cbe991d (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 56, 35 => efdc00001cbe991d (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 56, 42 => efdc00001cbe991d (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 56, 49 => efdc00001cbe991d (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 56, 56 => efdc00001cbe991d (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 56, 63 => efdc00001cbe991d (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 63, 0 => efdc00001cbe991d (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 63, 7 => ee00000e5f4c8ef7 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 63, 14 => ee00000e5f4c8ef7 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 63, 21 => ee00000e5f4c8ef7 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 63, 28 => ee00000e5f4c8ef7 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 63, 35 => ee00000e5f4c8ef7 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 63, 42 => ee00000e5f4c8ef7 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 63, 49 => ee00000e5f4c8ef7 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 63, 56 => ee00000e5f4c8ef7 (00000000 00000000)
|
|
+ rldimi 0000001cbe991def, 63, 63 => ee00000e5f4c8ef7 (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 0, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 0, 7 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 0, 14 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 0, 21 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 0, 28 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 0, 35 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 0, 42 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 0, 49 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 0, 56 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 0, 63 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 7, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 7, 7 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 7, 14 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 7, 21 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 7, 28 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 7, 35 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 7, 42 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 7, 49 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 7, 56 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 7, 63 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 14, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 14, 7 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 14, 14 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 14, 21 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 14, 28 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 14, 35 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 14, 42 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 14, 49 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 14, 56 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 14, 63 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 21, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 21, 7 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 21, 14 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 21, 21 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 21, 28 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 21, 35 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 21, 42 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 21, 49 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 21, 56 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 21, 63 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 28, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 28, 7 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 28, 14 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 28, 21 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 28, 28 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 28, 35 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 28, 42 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 28, 49 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 28, 56 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 28, 63 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 35, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 35, 7 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 35, 14 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 35, 21 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 35, 28 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 35, 35 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 35, 42 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 35, 49 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 35, 56 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 35, 63 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 42, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 42, 7 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 42, 14 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 42, 21 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 42, 28 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 42, 35 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 42, 42 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 42, 49 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 42, 56 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 42, 63 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 49, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 49, 7 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 49, 14 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 49, 21 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 49, 28 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 49, 35 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 49, 42 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 49, 49 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 49, 56 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 49, 63 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 56, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 56, 7 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 56, 14 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 56, 21 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 56, 28 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 56, 35 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 56, 42 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 56, 49 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 56, 56 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 56, 63 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 63, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 63, 7 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 63, 14 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 63, 21 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 63, 28 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 63, 35 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 63, 42 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 63, 49 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 63, 56 => ffffffffffffffff (00000000 00000000)
|
|
+ rldimi ffffffffffffffff, 63, 63 => ffffffffffffffff (00000000 00000000)
|
|
+
|
|
+ sradi 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
|
|
+ sradi 0000000000000000, 7 => 0000000000000000 (00000000 00000000)
|
|
+ sradi 0000000000000000, 14 => 0000000000000000 (00000000 00000000)
|
|
+ sradi 0000000000000000, 21 => 0000000000000000 (00000000 00000000)
|
|
+ sradi 0000000000000000, 28 => 0000000000000000 (00000000 00000000)
|
|
+ sradi 0000000000000000, 35 => 0000000000000000 (00000000 00000000)
|
|
+ sradi 0000000000000000, 42 => 0000000000000000 (00000000 00000000)
|
|
+ sradi 0000000000000000, 49 => 0000000000000000 (00000000 00000000)
|
|
+ sradi 0000000000000000, 56 => 0000000000000000 (00000000 00000000)
|
|
+ sradi 0000000000000000, 63 => 0000000000000000 (00000000 00000000)
|
|
+ sradi 0000001cbe991def, 0 => 0000001cbe991def (00000000 00000000)
|
|
+ sradi 0000001cbe991def, 7 => 00000000397d323b (00000000 00000000)
|
|
+ sradi 0000001cbe991def, 14 => 000000000072fa64 (00000000 00000000)
|
|
+ sradi 0000001cbe991def, 21 => 000000000000e5f4 (00000000 00000000)
|
|
+ sradi 0000001cbe991def, 28 => 00000000000001cb (00000000 00000000)
|
|
+ sradi 0000001cbe991def, 35 => 0000000000000003 (00000000 00000000)
|
|
+ sradi 0000001cbe991def, 42 => 0000000000000000 (00000000 00000000)
|
|
+ sradi 0000001cbe991def, 49 => 0000000000000000 (00000000 00000000)
|
|
+ sradi 0000001cbe991def, 56 => 0000000000000000 (00000000 00000000)
|
|
+ sradi 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000)
|
|
+ sradi ffffffffffffffff, 0 => ffffffffffffffff (00000000 00000000)
|
|
+ sradi ffffffffffffffff, 7 => ffffffffffffffff (00000000 20000000)
|
|
+ sradi ffffffffffffffff, 14 => ffffffffffffffff (00000000 20000000)
|
|
+ sradi ffffffffffffffff, 21 => ffffffffffffffff (00000000 20000000)
|
|
+ sradi ffffffffffffffff, 28 => ffffffffffffffff (00000000 20000000)
|
|
+ sradi ffffffffffffffff, 35 => ffffffffffffffff (00000000 20000000)
|
|
+ sradi ffffffffffffffff, 42 => ffffffffffffffff (00000000 20000000)
|
|
+ sradi ffffffffffffffff, 49 => ffffffffffffffff (00000000 20000000)
|
|
+ sradi ffffffffffffffff, 56 => ffffffffffffffff (00000000 20000000)
|
|
+ sradi ffffffffffffffff, 63 => ffffffffffffffff (00000000 20000000)
|
|
+
|
|
+PPC logical insns with special forms with flags update:
|
|
+ rlwimi. 0000000000000000, 0, 0, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rlwimi. 0000000000000000, 0, 0, 31 => 0000000000000000 (20000000 00000000)
|
|
+ rlwimi. 0000000000000000, 0, 31, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rlwimi. 0000000000000000, 0, 31, 31 => 0000000000000000 (20000000 00000000)
|
|
+ rlwimi. 0000000000000000, 31, 0, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rlwimi. 0000000000000000, 31, 0, 31 => 0000000000000000 (20000000 00000000)
|
|
+ rlwimi. 0000000000000000, 31, 31, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rlwimi. 0000000000000000, 31, 31, 31 => 0000000000000000 (20000000 00000000)
|
|
+ rlwimi. 0000001cbe991def, 0, 0, 0 => 0000000080000000 (40000000 00000000)
|
|
+ rlwimi. 0000001cbe991def, 0, 0, 31 => 00000000be991def (40000000 00000000)
|
|
+ rlwimi. 0000001cbe991def, 0, 31, 0 => be991defbe991def (80000000 00000000)
|
|
+ rlwimi. 0000001cbe991def, 0, 31, 31 => be991defbe991def (80000000 00000000)
|
|
+ rlwimi. 0000001cbe991def, 31, 0, 0 => be991defbe991def (80000000 00000000)
|
|
+ rlwimi. 0000001cbe991def, 31, 0, 31 => be991defdf4c8ef7 (80000000 00000000)
|
|
+ rlwimi. 0000001cbe991def, 31, 31, 0 => df4c8ef7df4c8ef7 (80000000 00000000)
|
|
+ rlwimi. 0000001cbe991def, 31, 31, 31 => df4c8ef7df4c8ef7 (80000000 00000000)
|
|
+ rlwimi. ffffffffffffffff, 0, 0, 0 => df4c8ef7df4c8ef7 (80000000 00000000)
|
|
+ rlwimi. ffffffffffffffff, 0, 0, 31 => df4c8ef7ffffffff (80000000 00000000)
|
|
+ rlwimi. ffffffffffffffff, 0, 31, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rlwimi. ffffffffffffffff, 0, 31, 31 => ffffffffffffffff (80000000 00000000)
|
|
+ rlwimi. ffffffffffffffff, 31, 0, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rlwimi. ffffffffffffffff, 31, 0, 31 => ffffffffffffffff (80000000 00000000)
|
|
+ rlwimi. ffffffffffffffff, 31, 31, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rlwimi. ffffffffffffffff, 31, 31, 31 => ffffffffffffffff (80000000 00000000)
|
|
+
|
|
+ rlwinm. 0000000000000000, 0, 0, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rlwinm. 0000000000000000, 0, 0, 31 => 0000000000000000 (20000000 00000000)
|
|
+ rlwinm. 0000000000000000, 0, 31, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rlwinm. 0000000000000000, 0, 31, 31 => 0000000000000000 (20000000 00000000)
|
|
+ rlwinm. 0000000000000000, 31, 0, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rlwinm. 0000000000000000, 31, 0, 31 => 0000000000000000 (20000000 00000000)
|
|
+ rlwinm. 0000000000000000, 31, 31, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rlwinm. 0000000000000000, 31, 31, 31 => 0000000000000000 (20000000 00000000)
|
|
+ rlwinm. 0000001cbe991def, 0, 0, 0 => 0000000080000000 (40000000 00000000)
|
|
+ rlwinm. 0000001cbe991def, 0, 0, 31 => 00000000be991def (40000000 00000000)
|
|
+ rlwinm. 0000001cbe991def, 0, 31, 0 => be991def80000001 (80000000 00000000)
|
|
+ rlwinm. 0000001cbe991def, 0, 31, 31 => 0000000000000001 (40000000 00000000)
|
|
+ rlwinm. 0000001cbe991def, 31, 0, 0 => 0000000080000000 (40000000 00000000)
|
|
+ rlwinm. 0000001cbe991def, 31, 0, 31 => 00000000df4c8ef7 (40000000 00000000)
|
|
+ rlwinm. 0000001cbe991def, 31, 31, 0 => df4c8ef780000001 (80000000 00000000)
|
|
+ rlwinm. 0000001cbe991def, 31, 31, 31 => 0000000000000001 (40000000 00000000)
|
|
+ rlwinm. ffffffffffffffff, 0, 0, 0 => 0000000080000000 (40000000 00000000)
|
|
+ rlwinm. ffffffffffffffff, 0, 0, 31 => 00000000ffffffff (40000000 00000000)
|
|
+ rlwinm. ffffffffffffffff, 0, 31, 0 => ffffffff80000001 (80000000 00000000)
|
|
+ rlwinm. ffffffffffffffff, 0, 31, 31 => 0000000000000001 (40000000 00000000)
|
|
+ rlwinm. ffffffffffffffff, 31, 0, 0 => 0000000080000000 (40000000 00000000)
|
|
+ rlwinm. ffffffffffffffff, 31, 0, 31 => 00000000ffffffff (40000000 00000000)
|
|
+ rlwinm. ffffffffffffffff, 31, 31, 0 => ffffffff80000001 (80000000 00000000)
|
|
+ rlwinm. ffffffffffffffff, 31, 31, 31 => 0000000000000001 (40000000 00000000)
|
|
+
|
|
+ rlwnm. 0000000000000000, 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rlwnm. 0000000000000000, 0000000000000000, 0, 31 => 0000000000000000 (20000000 00000000)
|
|
+ rlwnm. 0000000000000000, 0000000000000000, 31, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rlwnm. 0000000000000000, 0000000000000000, 31, 31 => 0000000000000000 (20000000 00000000)
|
|
+ rlwnm. 0000000000000000, 0000001cbe991def, 0, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rlwnm. 0000000000000000, 0000001cbe991def, 0, 31 => 0000000000000000 (20000000 00000000)
|
|
+ rlwnm. 0000000000000000, 0000001cbe991def, 31, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rlwnm. 0000000000000000, 0000001cbe991def, 31, 31 => 0000000000000000 (20000000 00000000)
|
|
+ rlwnm. 0000000000000000, ffffffffffffffff, 0, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rlwnm. 0000000000000000, ffffffffffffffff, 0, 31 => 0000000000000000 (20000000 00000000)
|
|
+ rlwnm. 0000000000000000, ffffffffffffffff, 31, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rlwnm. 0000000000000000, ffffffffffffffff, 31, 31 => 0000000000000000 (20000000 00000000)
|
|
+ rlwnm. 0000001cbe991def, 0000000000000000, 0, 0 => 0000000080000000 (40000000 00000000)
|
|
+ rlwnm. 0000001cbe991def, 0000000000000000, 0, 31 => 00000000be991def (40000000 00000000)
|
|
+ rlwnm. 0000001cbe991def, 0000000000000000, 31, 0 => be991def80000001 (80000000 00000000)
|
|
+ rlwnm. 0000001cbe991def, 0000000000000000, 31, 31 => 0000000000000001 (40000000 00000000)
|
|
+ rlwnm. 0000001cbe991def, 0000001cbe991def, 0, 0 => 0000000080000000 (40000000 00000000)
|
|
+ rlwnm. 0000001cbe991def, 0000001cbe991def, 0, 31 => 000000008ef7df4c (40000000 00000000)
|
|
+ rlwnm. 0000001cbe991def, 0000001cbe991def, 31, 0 => 8ef7df4c80000000 (80000000 00000000)
|
|
+ rlwnm. 0000001cbe991def, 0000001cbe991def, 31, 31 => 0000000000000000 (20000000 00000000)
|
|
+ rlwnm. 0000001cbe991def, ffffffffffffffff, 0, 0 => 0000000080000000 (40000000 00000000)
|
|
+ rlwnm. 0000001cbe991def, ffffffffffffffff, 0, 31 => 00000000df4c8ef7 (40000000 00000000)
|
|
+ rlwnm. 0000001cbe991def, ffffffffffffffff, 31, 0 => df4c8ef780000001 (80000000 00000000)
|
|
+ rlwnm. 0000001cbe991def, ffffffffffffffff, 31, 31 => 0000000000000001 (40000000 00000000)
|
|
+ rlwnm. ffffffffffffffff, 0000000000000000, 0, 0 => 0000000080000000 (40000000 00000000)
|
|
+ rlwnm. ffffffffffffffff, 0000000000000000, 0, 31 => 00000000ffffffff (40000000 00000000)
|
|
+ rlwnm. ffffffffffffffff, 0000000000000000, 31, 0 => ffffffff80000001 (80000000 00000000)
|
|
+ rlwnm. ffffffffffffffff, 0000000000000000, 31, 31 => 0000000000000001 (40000000 00000000)
|
|
+ rlwnm. ffffffffffffffff, 0000001cbe991def, 0, 0 => 0000000080000000 (40000000 00000000)
|
|
+ rlwnm. ffffffffffffffff, 0000001cbe991def, 0, 31 => 00000000ffffffff (40000000 00000000)
|
|
+ rlwnm. ffffffffffffffff, 0000001cbe991def, 31, 0 => ffffffff80000001 (80000000 00000000)
|
|
+ rlwnm. ffffffffffffffff, 0000001cbe991def, 31, 31 => 0000000000000001 (40000000 00000000)
|
|
+ rlwnm. ffffffffffffffff, ffffffffffffffff, 0, 0 => 0000000080000000 (40000000 00000000)
|
|
+ rlwnm. ffffffffffffffff, ffffffffffffffff, 0, 31 => 00000000ffffffff (40000000 00000000)
|
|
+ rlwnm. ffffffffffffffff, ffffffffffffffff, 31, 0 => ffffffff80000001 (80000000 00000000)
|
|
+ rlwnm. ffffffffffffffff, ffffffffffffffff, 31, 31 => 0000000000000001 (40000000 00000000)
|
|
+
|
|
+ srawi. 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
|
|
+ srawi. 0000000000000000, 31 => 0000000000000000 (20000000 00000000)
|
|
+ srawi. 0000001cbe991def, 0 => ffffffffbe991def (80000000 00000000)
|
|
+ srawi. 0000001cbe991def, 31 => ffffffffffffffff (80000000 20000000)
|
|
+ srawi. ffffffffffffffff, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ srawi. ffffffffffffffff, 31 => ffffffffffffffff (80000000 20000000)
|
|
+
|
|
+ mcrf 0, 0 (0000000000000000) => (00000000 00000000)
|
|
+ mcrf 0, 7 (0000000000000000) => (00000000 00000000)
|
|
+ mcrf 7, 0 (0000000000000000) => (00000000 00000000)
|
|
+ mcrf 7, 7 (0000000000000000) => (00000000 00000000)
|
|
+ mcrf 0, 0 (0000001cbe991def) => (be991def 00000000)
|
|
+ mcrf 0, 7 (0000001cbe991def) => (fe991def 00000000)
|
|
+ mcrf 7, 0 (0000001cbe991def) => (be991deb 00000000)
|
|
+ mcrf 7, 7 (0000001cbe991def) => (be991def 00000000)
|
|
+ mcrf 0, 0 (ffffffffffffffff) => (ffffffff 00000000)
|
|
+ mcrf 0, 7 (ffffffffffffffff) => (ffffffff 00000000)
|
|
+ mcrf 7, 0 (ffffffffffffffff) => (ffffffff 00000000)
|
|
+ mcrf 7, 7 (ffffffffffffffff) => (ffffffff 00000000)
|
|
+
|
|
+ mcrxr 0 (00000000) => (00000000 00000000)
|
|
+ mcrxr 1 (00000000) => (00000000 00000000)
|
|
+ mcrxr 2 (00000000) => (00000000 00000000)
|
|
+ mcrxr 3 (00000000) => (00000000 00000000)
|
|
+ mcrxr 4 (00000000) => (00000000 00000000)
|
|
+ mcrxr 5 (00000000) => (00000000 00000000)
|
|
+ mcrxr 6 (00000000) => (00000000 00000000)
|
|
+ mcrxr 7 (00000000) => (00000000 00000000)
|
|
+ mcrxr 0 (10000000) => (00000000 00000000)
|
|
+ mcrxr 1 (10000000) => (00000000 00000000)
|
|
+ mcrxr 2 (10000000) => (00000000 00000000)
|
|
+ mcrxr 3 (10000000) => (00000000 00000000)
|
|
+ mcrxr 4 (10000000) => (00000000 00000000)
|
|
+ mcrxr 5 (10000000) => (00000000 00000000)
|
|
+ mcrxr 6 (10000000) => (00000000 00000000)
|
|
+ mcrxr 7 (10000000) => (00000000 00000000)
|
|
+ mcrxr 0 (20000000) => (20000000 00000000)
|
|
+ mcrxr 1 (20000000) => (02000000 00000000)
|
|
+ mcrxr 2 (20000000) => (00200000 00000000)
|
|
+ mcrxr 3 (20000000) => (00020000 00000000)
|
|
+ mcrxr 4 (20000000) => (00002000 00000000)
|
|
+ mcrxr 5 (20000000) => (00000200 00000000)
|
|
+ mcrxr 6 (20000000) => (00000020 00000000)
|
|
+ mcrxr 7 (20000000) => (00000002 00000000)
|
|
+ mcrxr 0 (30000000) => (20000000 00000000)
|
|
+ mcrxr 1 (30000000) => (02000000 00000000)
|
|
+ mcrxr 2 (30000000) => (00200000 00000000)
|
|
+ mcrxr 3 (30000000) => (00020000 00000000)
|
|
+ mcrxr 4 (30000000) => (00002000 00000000)
|
|
+ mcrxr 5 (30000000) => (00000200 00000000)
|
|
+ mcrxr 6 (30000000) => (00000020 00000000)
|
|
+ mcrxr 7 (30000000) => (00000002 00000000)
|
|
+ mcrxr 0 (40000000) => (40000000 00000000)
|
|
+ mcrxr 1 (40000000) => (04000000 00000000)
|
|
+ mcrxr 2 (40000000) => (00400000 00000000)
|
|
+ mcrxr 3 (40000000) => (00040000 00000000)
|
|
+ mcrxr 4 (40000000) => (00004000 00000000)
|
|
+ mcrxr 5 (40000000) => (00000400 00000000)
|
|
+ mcrxr 6 (40000000) => (00000040 00000000)
|
|
+ mcrxr 7 (40000000) => (00000004 00000000)
|
|
+ mcrxr 0 (50000000) => (40000000 00000000)
|
|
+ mcrxr 1 (50000000) => (04000000 00000000)
|
|
+ mcrxr 2 (50000000) => (00400000 00000000)
|
|
+ mcrxr 3 (50000000) => (00040000 00000000)
|
|
+ mcrxr 4 (50000000) => (00004000 00000000)
|
|
+ mcrxr 5 (50000000) => (00000400 00000000)
|
|
+ mcrxr 6 (50000000) => (00000040 00000000)
|
|
+ mcrxr 7 (50000000) => (00000004 00000000)
|
|
+ mcrxr 0 (60000000) => (60000000 00000000)
|
|
+ mcrxr 1 (60000000) => (06000000 00000000)
|
|
+ mcrxr 2 (60000000) => (00600000 00000000)
|
|
+ mcrxr 3 (60000000) => (00060000 00000000)
|
|
+ mcrxr 4 (60000000) => (00006000 00000000)
|
|
+ mcrxr 5 (60000000) => (00000600 00000000)
|
|
+ mcrxr 6 (60000000) => (00000060 00000000)
|
|
+ mcrxr 7 (60000000) => (00000006 00000000)
|
|
+ mcrxr 0 (70000000) => (60000000 00000000)
|
|
+ mcrxr 1 (70000000) => (06000000 00000000)
|
|
+ mcrxr 2 (70000000) => (00600000 00000000)
|
|
+ mcrxr 3 (70000000) => (00060000 00000000)
|
|
+ mcrxr 4 (70000000) => (00006000 00000000)
|
|
+ mcrxr 5 (70000000) => (00000600 00000000)
|
|
+ mcrxr 6 (70000000) => (00000060 00000000)
|
|
+ mcrxr 7 (70000000) => (00000006 00000000)
|
|
+ mcrxr 0 (80000000) => (80000000 00000000)
|
|
+ mcrxr 1 (80000000) => (08000000 00000000)
|
|
+ mcrxr 2 (80000000) => (00800000 00000000)
|
|
+ mcrxr 3 (80000000) => (00080000 00000000)
|
|
+ mcrxr 4 (80000000) => (00008000 00000000)
|
|
+ mcrxr 5 (80000000) => (00000800 00000000)
|
|
+ mcrxr 6 (80000000) => (00000080 00000000)
|
|
+ mcrxr 7 (80000000) => (00000008 00000000)
|
|
+ mcrxr 0 (90000000) => (80000000 00000000)
|
|
+ mcrxr 1 (90000000) => (08000000 00000000)
|
|
+ mcrxr 2 (90000000) => (00800000 00000000)
|
|
+ mcrxr 3 (90000000) => (00080000 00000000)
|
|
+ mcrxr 4 (90000000) => (00008000 00000000)
|
|
+ mcrxr 5 (90000000) => (00000800 00000000)
|
|
+ mcrxr 6 (90000000) => (00000080 00000000)
|
|
+ mcrxr 7 (90000000) => (00000008 00000000)
|
|
+ mcrxr 0 (a0000000) => (a0000000 00000000)
|
|
+ mcrxr 1 (a0000000) => (0a000000 00000000)
|
|
+ mcrxr 2 (a0000000) => (00a00000 00000000)
|
|
+ mcrxr 3 (a0000000) => (000a0000 00000000)
|
|
+ mcrxr 4 (a0000000) => (0000a000 00000000)
|
|
+ mcrxr 5 (a0000000) => (00000a00 00000000)
|
|
+ mcrxr 6 (a0000000) => (000000a0 00000000)
|
|
+ mcrxr 7 (a0000000) => (0000000a 00000000)
|
|
+ mcrxr 0 (b0000000) => (a0000000 00000000)
|
|
+ mcrxr 1 (b0000000) => (0a000000 00000000)
|
|
+ mcrxr 2 (b0000000) => (00a00000 00000000)
|
|
+ mcrxr 3 (b0000000) => (000a0000 00000000)
|
|
+ mcrxr 4 (b0000000) => (0000a000 00000000)
|
|
+ mcrxr 5 (b0000000) => (00000a00 00000000)
|
|
+ mcrxr 6 (b0000000) => (000000a0 00000000)
|
|
+ mcrxr 7 (b0000000) => (0000000a 00000000)
|
|
+ mcrxr 0 (c0000000) => (c0000000 00000000)
|
|
+ mcrxr 1 (c0000000) => (0c000000 00000000)
|
|
+ mcrxr 2 (c0000000) => (00c00000 00000000)
|
|
+ mcrxr 3 (c0000000) => (000c0000 00000000)
|
|
+ mcrxr 4 (c0000000) => (0000c000 00000000)
|
|
+ mcrxr 5 (c0000000) => (00000c00 00000000)
|
|
+ mcrxr 6 (c0000000) => (000000c0 00000000)
|
|
+ mcrxr 7 (c0000000) => (0000000c 00000000)
|
|
+ mcrxr 0 (d0000000) => (c0000000 00000000)
|
|
+ mcrxr 1 (d0000000) => (0c000000 00000000)
|
|
+ mcrxr 2 (d0000000) => (00c00000 00000000)
|
|
+ mcrxr 3 (d0000000) => (000c0000 00000000)
|
|
+ mcrxr 4 (d0000000) => (0000c000 00000000)
|
|
+ mcrxr 5 (d0000000) => (00000c00 00000000)
|
|
+ mcrxr 6 (d0000000) => (000000c0 00000000)
|
|
+ mcrxr 7 (d0000000) => (0000000c 00000000)
|
|
+ mcrxr 0 (e0000000) => (e0000000 00000000)
|
|
+ mcrxr 1 (e0000000) => (0e000000 00000000)
|
|
+ mcrxr 2 (e0000000) => (00e00000 00000000)
|
|
+ mcrxr 3 (e0000000) => (000e0000 00000000)
|
|
+ mcrxr 4 (e0000000) => (0000e000 00000000)
|
|
+ mcrxr 5 (e0000000) => (00000e00 00000000)
|
|
+ mcrxr 6 (e0000000) => (000000e0 00000000)
|
|
+ mcrxr 7 (e0000000) => (0000000e 00000000)
|
|
+ mcrxr 0 (f0000000) => (e0000000 00000000)
|
|
+ mcrxr 1 (f0000000) => (0e000000 00000000)
|
|
+ mcrxr 2 (f0000000) => (00e00000 00000000)
|
|
+ mcrxr 3 (f0000000) => (000e0000 00000000)
|
|
+ mcrxr 4 (f0000000) => (0000e000 00000000)
|
|
+ mcrxr 5 (f0000000) => (00000e00 00000000)
|
|
+ mcrxr 6 (f0000000) => (000000e0 00000000)
|
|
+ mcrxr 7 (f0000000) => (0000000e 00000000)
|
|
+
|
|
+ mtcrf 0, 0000000000000000 => (00000000 00000000)
|
|
+ mtcrf 99, 0000000000000000 => (00000000 00000000)
|
|
+ mtcrf 198, 0000000000000000 => (00000000 00000000)
|
|
+ mtcrf 0, 0000001cbe991def => (00000000 00000000)
|
|
+ mtcrf 99, 0000001cbe991def => (0e9000ef 00000000)
|
|
+ mtcrf 198, 0000001cbe991def => (be000de0 00000000)
|
|
+ mtcrf 0, ffffffffffffffff => (00000000 00000000)
|
|
+ mtcrf 99, ffffffffffffffff => (0ff000ff 00000000)
|
|
+ mtcrf 198, ffffffffffffffff => (ff000ff0 00000000)
|
|
+
|
|
+ rldcl. 0000000000000000, 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, 0000000000000000, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, 0000000000000000, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, 0000000000000000, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, 0000000000000000, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, 0000000000000000, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, 0000000000000000, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, 0000000000000000, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, 0000000000000000, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, 0000000000000000, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000001cbe991def, 0000000000000000, 0 => 0000001cbe991def (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, 0000000000000000, 7 => 0000001cbe991def (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, 0000000000000000, 14 => 0000001cbe991def (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, 0000000000000000, 21 => 0000001cbe991def (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, 0000000000000000, 28 => 0000000cbe991def (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, 0000000000000000, 35 => 000000001e991def (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, 0000000000000000, 42 => 0000000000191def (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, 0000000000000000, 49 => 0000000000001def (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, 0000000000000000, 56 => 00000000000000ef (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, 0000000000000000, 63 => 0000000000000001 (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, 0000001cbe991def, 0 => 8ef78000000e5f4c (80000000 00000000)
|
|
+ rldcl. 0000001cbe991def, 0000001cbe991def, 7 => 00f78000000e5f4c (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, 0000001cbe991def, 14 => 00038000000e5f4c (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, 0000001cbe991def, 21 => 00000000000e5f4c (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, 0000001cbe991def, 28 => 00000000000e5f4c (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, 0000001cbe991def, 35 => 00000000000e5f4c (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, 0000001cbe991def, 42 => 00000000000e5f4c (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, 0000001cbe991def, 49 => 0000000000005f4c (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, 0000001cbe991def, 56 => 000000000000004c (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldcl. 0000001cbe991def, ffffffffffffffff, 0 => 8000000e5f4c8ef7 (80000000 00000000)
|
|
+ rldcl. 0000001cbe991def, ffffffffffffffff, 7 => 0000000e5f4c8ef7 (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, ffffffffffffffff, 14 => 0000000e5f4c8ef7 (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, ffffffffffffffff, 21 => 0000000e5f4c8ef7 (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, ffffffffffffffff, 28 => 0000000e5f4c8ef7 (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, ffffffffffffffff, 35 => 000000001f4c8ef7 (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, ffffffffffffffff, 42 => 00000000000c8ef7 (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, ffffffffffffffff, 49 => 0000000000000ef7 (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, ffffffffffffffff, 56 => 00000000000000f7 (40000000 00000000)
|
|
+ rldcl. 0000001cbe991def, ffffffffffffffff, 63 => 0000000000000001 (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, 0000000000000000, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldcl. ffffffffffffffff, 0000000000000000, 7 => 01ffffffffffffff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, 0000000000000000, 14 => 0003ffffffffffff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, 0000000000000000, 21 => 000007ffffffffff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, 0000000000000000, 28 => 0000000fffffffff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, 0000000000000000, 35 => 000000001fffffff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, 0000000000000000, 42 => 00000000003fffff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, 0000000000000000, 49 => 0000000000007fff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, 0000000000000000, 56 => 00000000000000ff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, 0000000000000000, 63 => 0000000000000001 (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, 0000001cbe991def, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldcl. ffffffffffffffff, 0000001cbe991def, 7 => 01ffffffffffffff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, 0000001cbe991def, 14 => 0003ffffffffffff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, 0000001cbe991def, 21 => 000007ffffffffff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, 0000001cbe991def, 28 => 0000000fffffffff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, 0000001cbe991def, 35 => 000000001fffffff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, 0000001cbe991def, 42 => 00000000003fffff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, 0000001cbe991def, 49 => 0000000000007fff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, 0000001cbe991def, 56 => 00000000000000ff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, 0000001cbe991def, 63 => 0000000000000001 (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, ffffffffffffffff, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldcl. ffffffffffffffff, ffffffffffffffff, 7 => 01ffffffffffffff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, ffffffffffffffff, 14 => 0003ffffffffffff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, ffffffffffffffff, 21 => 000007ffffffffff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, ffffffffffffffff, 28 => 0000000fffffffff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, ffffffffffffffff, 35 => 000000001fffffff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, ffffffffffffffff, 42 => 00000000003fffff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, ffffffffffffffff, 49 => 0000000000007fff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, ffffffffffffffff, 56 => 00000000000000ff (40000000 00000000)
|
|
+ rldcl. ffffffffffffffff, ffffffffffffffff, 63 => 0000000000000001 (40000000 00000000)
|
|
+
|
|
+ rldcr. 0000000000000000, 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, 0000000000000000, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, 0000000000000000, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, 0000000000000000, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, 0000000000000000, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, 0000000000000000, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, 0000000000000000, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, 0000000000000000, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, 0000000000000000, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, 0000000000000000, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000001cbe991def, 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000001cbe991def, 0000000000000000, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000001cbe991def, 0000000000000000, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000001cbe991def, 0000000000000000, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldcr. 0000001cbe991def, 0000000000000000, 28 => 0000001800000000 (40000000 00000000)
|
|
+ rldcr. 0000001cbe991def, 0000000000000000, 35 => 0000001cb0000000 (40000000 00000000)
|
|
+ rldcr. 0000001cbe991def, 0000000000000000, 42 => 0000001cbe800000 (40000000 00000000)
|
|
+ rldcr. 0000001cbe991def, 0000000000000000, 49 => 0000001cbe990000 (40000000 00000000)
|
|
+ rldcr. 0000001cbe991def, 0000000000000000, 56 => 0000001cbe991d80 (40000000 00000000)
|
|
+ rldcr. 0000001cbe991def, 0000000000000000, 63 => 0000001cbe991def (40000000 00000000)
|
|
+ rldcr. 0000001cbe991def, 0000001cbe991def, 0 => 8000000000000000 (80000000 00000000)
|
|
+ rldcr. 0000001cbe991def, 0000001cbe991def, 7 => 8e00000000000000 (80000000 00000000)
|
|
+ rldcr. 0000001cbe991def, 0000001cbe991def, 14 => 8ef6000000000000 (80000000 00000000)
|
|
+ rldcr. 0000001cbe991def, 0000001cbe991def, 21 => 8ef7800000000000 (80000000 00000000)
|
|
+ rldcr. 0000001cbe991def, 0000001cbe991def, 28 => 8ef7800000000000 (80000000 00000000)
|
|
+ rldcr. 0000001cbe991def, 0000001cbe991def, 35 => 8ef7800000000000 (80000000 00000000)
|
|
+ rldcr. 0000001cbe991def, 0000001cbe991def, 42 => 8ef7800000000000 (80000000 00000000)
|
|
+ rldcr. 0000001cbe991def, 0000001cbe991def, 49 => 8ef78000000e4000 (80000000 00000000)
|
|
+ rldcr. 0000001cbe991def, 0000001cbe991def, 56 => 8ef78000000e5f00 (80000000 00000000)
|
|
+ rldcr. 0000001cbe991def, 0000001cbe991def, 63 => 8ef78000000e5f4c (80000000 00000000)
|
|
+ rldcr. 0000001cbe991def, ffffffffffffffff, 0 => 8000000000000000 (80000000 00000000)
|
|
+ rldcr. 0000001cbe991def, ffffffffffffffff, 7 => 8000000000000000 (80000000 00000000)
|
|
+ rldcr. 0000001cbe991def, ffffffffffffffff, 14 => 8000000000000000 (80000000 00000000)
|
|
+ rldcr. 0000001cbe991def, ffffffffffffffff, 21 => 8000000000000000 (80000000 00000000)
|
|
+ rldcr. 0000001cbe991def, ffffffffffffffff, 28 => 8000000800000000 (80000000 00000000)
|
|
+ rldcr. 0000001cbe991def, ffffffffffffffff, 35 => 8000000e50000000 (80000000 00000000)
|
|
+ rldcr. 0000001cbe991def, ffffffffffffffff, 42 => 8000000e5f400000 (80000000 00000000)
|
|
+ rldcr. 0000001cbe991def, ffffffffffffffff, 49 => 8000000e5f4c8000 (80000000 00000000)
|
|
+ rldcr. 0000001cbe991def, ffffffffffffffff, 56 => 8000000e5f4c8e80 (80000000 00000000)
|
|
+ rldcr. 0000001cbe991def, ffffffffffffffff, 63 => 8000000e5f4c8ef7 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, 0000000000000000, 0 => 8000000000000000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, 0000000000000000, 7 => ff00000000000000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, 0000000000000000, 14 => fffe000000000000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, 0000000000000000, 21 => fffffc0000000000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, 0000000000000000, 28 => fffffff800000000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, 0000000000000000, 35 => fffffffff0000000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, 0000000000000000, 42 => ffffffffffe00000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, 0000000000000000, 49 => ffffffffffffc000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, 0000000000000000, 56 => ffffffffffffff80 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, 0000000000000000, 63 => ffffffffffffffff (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, 0000001cbe991def, 0 => 8000000000000000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, 0000001cbe991def, 7 => ff00000000000000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, 0000001cbe991def, 14 => fffe000000000000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, 0000001cbe991def, 21 => fffffc0000000000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, 0000001cbe991def, 28 => fffffff800000000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, 0000001cbe991def, 35 => fffffffff0000000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, 0000001cbe991def, 42 => ffffffffffe00000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, 0000001cbe991def, 49 => ffffffffffffc000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, 0000001cbe991def, 56 => ffffffffffffff80 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, 0000001cbe991def, 63 => ffffffffffffffff (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, ffffffffffffffff, 0 => 8000000000000000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, ffffffffffffffff, 7 => ff00000000000000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, ffffffffffffffff, 14 => fffe000000000000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, ffffffffffffffff, 21 => fffffc0000000000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, ffffffffffffffff, 28 => fffffff800000000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, ffffffffffffffff, 35 => fffffffff0000000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, ffffffffffffffff, 42 => ffffffffffe00000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, ffffffffffffffff, 49 => ffffffffffffc000 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, ffffffffffffffff, 56 => ffffffffffffff80 (80000000 00000000)
|
|
+ rldcr. ffffffffffffffff, ffffffffffffffff, 63 => ffffffffffffffff (80000000 00000000)
|
|
+
|
|
+ rldic. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldic. 0000001cbe991def, 0, 0 => 0000001cbe991def (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 0, 7 => 0000001cbe991def (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 0, 14 => 0000001cbe991def (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 0, 21 => 0000001cbe991def (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 0, 28 => 0000000cbe991def (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 0, 35 => 000000001e991def (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 0, 42 => 0000000000191def (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 0, 49 => 0000000000001def (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 0, 56 => 00000000000000ef (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 0, 63 => 0000000000000001 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 7, 35 => 000000000c8ef780 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 7, 42 => 00000000000ef780 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 7, 49 => 0000000000007780 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 7, 56 => 0000000000000080 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 14, 0 => 00072fa6477bc000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 14, 7 => 00072fa6477bc000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 14, 14 => 00032fa6477bc000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 14, 21 => 000007a6477bc000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 14, 28 => 00000006477bc000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 14, 35 => 00000000077bc000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 14, 42 => 00000000003bc000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 14, 49 => 0000000000004000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 14, 56 => 00072fa6477bc000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 14, 63 => 00072fa6477bc000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 21, 0 => 0397d323bde00000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 21, 7 => 0197d323bde00000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 21, 14 => 0003d323bde00000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 21, 21 => 00000323bde00000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 21, 28 => 00000003bde00000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 21, 35 => 000000001de00000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 21, 42 => 0000000000200000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 21, 49 => 0397d323bde00000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 21, 56 => 0397d323bde00000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 21, 63 => 0397d323bde00000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 28, 0 => cbe991def0000000 (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 28, 7 => 01e991def0000000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 28, 14 => 000191def0000000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 28, 21 => 000001def0000000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 28, 28 => 0000000ef0000000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 28, 35 => 0000000010000000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 28, 42 => cbe991def0000001 (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 28, 49 => cbe991def0000001 (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 28, 56 => cbe991def0000001 (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 28, 63 => cbe991def0000001 (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 35, 0 => f4c8ef7800000000 (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 35, 7 => 00c8ef7800000000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 35, 14 => 0000ef7800000000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 35, 21 => 0000077800000000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 35, 28 => 0000000800000000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 35, 35 => f4c8ef78000000e5 (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 35, 42 => f4c8ef78000000e5 (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 35, 49 => f4c8ef78000000e5 (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 35, 56 => f4c8ef78000000e5 (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 35, 63 => f4c8ef7800000001 (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 42, 0 => 6477bc0000000000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 42, 7 => 0077bc0000000000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 42, 14 => 0003bc0000000000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 42, 21 => 0000040000000000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 42, 28 => 6477bc00000072fa (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 42, 35 => 6477bc00000072fa (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 42, 42 => 6477bc00000072fa (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 42, 49 => 6477bc00000072fa (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 42, 56 => 6477bc00000000fa (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 42, 63 => 6477bc0000000000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 49, 0 => 3bde000000000000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 49, 7 => 01de000000000000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 49, 14 => 0002000000000000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 49, 21 => 3bde000000397d32 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 49, 28 => 3bde000000397d32 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 49, 35 => 3bde000000397d32 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 49, 42 => 3bde000000397d32 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 49, 49 => 3bde000000007d32 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 49, 56 => 3bde000000000032 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 49, 63 => 3bde000000000000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 56, 0 => ef00000000000000 (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 56, 7 => 0100000000000000 (40000000 00000000)
|
|
+ rldic. 0000001cbe991def, 56, 14 => ef0000001cbe991d (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 56, 21 => ef0000001cbe991d (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 56, 28 => ef0000001cbe991d (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 56, 35 => ef0000001cbe991d (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 56, 42 => ef000000003e991d (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 56, 49 => ef0000000000191d (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 56, 56 => ef0000000000001d (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 56, 63 => ef00000000000001 (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 63, 0 => 8000000000000000 (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 63, 7 => 8000000e5f4c8ef7 (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 63, 14 => 8000000e5f4c8ef7 (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 63, 21 => 8000000e5f4c8ef7 (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 63, 28 => 8000000e5f4c8ef7 (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 63, 35 => 800000001f4c8ef7 (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 63, 42 => 80000000000c8ef7 (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 63, 49 => 8000000000000ef7 (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 63, 56 => 80000000000000f7 (80000000 00000000)
|
|
+ rldic. 0000001cbe991def, 63, 63 => 8000000000000001 (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 0, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 0, 7 => 01ffffffffffffff (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 0, 14 => 0003ffffffffffff (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 0, 21 => 000007ffffffffff (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 0, 28 => 0000000fffffffff (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 0, 35 => 000000001fffffff (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 0, 42 => 00000000003fffff (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 0, 49 => 0000000000007fff (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 0, 56 => 00000000000000ff (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 0, 63 => 0000000000000001 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 7, 0 => ffffffffffffff80 (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 7, 7 => 01ffffffffffff80 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 7, 14 => 0003ffffffffff80 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 7, 21 => 000007ffffffff80 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 7, 28 => 0000000fffffff80 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 7, 35 => 000000001fffff80 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 7, 42 => 00000000003fff80 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 7, 49 => 0000000000007f80 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 7, 56 => 0000000000000080 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 7, 63 => ffffffffffffff81 (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 14, 0 => ffffffffffffc000 (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 14, 7 => 01ffffffffffc000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 14, 14 => 0003ffffffffc000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 14, 21 => 000007ffffffc000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 14, 28 => 0000000fffffc000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 14, 35 => 000000001fffc000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 14, 42 => 00000000003fc000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 14, 49 => 0000000000004000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 14, 56 => ffffffffffffc0ff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 14, 63 => ffffffffffffc001 (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 21, 0 => ffffffffffe00000 (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 21, 7 => 01ffffffffe00000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 21, 14 => 0003ffffffe00000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 21, 21 => 000007ffffe00000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 21, 28 => 0000000fffe00000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 21, 35 => 000000001fe00000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 21, 42 => 0000000000200000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 21, 49 => ffffffffffe07fff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 21, 56 => ffffffffffe000ff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 21, 63 => ffffffffffe00001 (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 28, 0 => fffffffff0000000 (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 28, 7 => 01fffffff0000000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 28, 14 => 0003fffff0000000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 28, 21 => 000007fff0000000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 28, 28 => 0000000ff0000000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 28, 35 => 0000000010000000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 28, 42 => fffffffff03fffff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 28, 49 => fffffffff0007fff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 28, 56 => fffffffff00000ff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 28, 63 => fffffffff0000001 (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 35, 0 => fffffff800000000 (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 35, 7 => 01fffff800000000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 35, 14 => 0003fff800000000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 35, 21 => 000007f800000000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 35, 28 => 0000000800000000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 35, 35 => fffffff81fffffff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 35, 42 => fffffff8003fffff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 35, 49 => fffffff800007fff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 35, 56 => fffffff8000000ff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 35, 63 => fffffff800000001 (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 42, 0 => fffffc0000000000 (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 42, 7 => 01fffc0000000000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 42, 14 => 0003fc0000000000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 42, 21 => 0000040000000000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 42, 28 => fffffc0fffffffff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 42, 35 => fffffc001fffffff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 42, 42 => fffffc00003fffff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 42, 49 => fffffc0000007fff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 42, 56 => fffffc00000000ff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 42, 63 => fffffc0000000001 (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 49, 0 => fffe000000000000 (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 49, 7 => 01fe000000000000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 49, 14 => 0002000000000000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 49, 21 => fffe07ffffffffff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 49, 28 => fffe000fffffffff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 49, 35 => fffe00001fffffff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 49, 42 => fffe0000003fffff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 49, 49 => fffe000000007fff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 49, 56 => fffe0000000000ff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 49, 63 => fffe000000000001 (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 56, 0 => ff00000000000000 (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 56, 7 => 0100000000000000 (40000000 00000000)
|
|
+ rldic. ffffffffffffffff, 56, 14 => ff03ffffffffffff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 56, 21 => ff0007ffffffffff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 56, 28 => ff00000fffffffff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 56, 35 => ff0000001fffffff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 56, 42 => ff000000003fffff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 56, 49 => ff00000000007fff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 56, 56 => ff000000000000ff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 56, 63 => ff00000000000001 (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 63, 0 => 8000000000000000 (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 63, 7 => 81ffffffffffffff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 63, 14 => 8003ffffffffffff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 63, 21 => 800007ffffffffff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 63, 28 => 8000000fffffffff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 63, 35 => 800000001fffffff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 63, 42 => 80000000003fffff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 63, 49 => 8000000000007fff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 63, 56 => 80000000000000ff (80000000 00000000)
|
|
+ rldic. ffffffffffffffff, 63, 63 => 8000000000000001 (80000000 00000000)
|
|
+
|
|
+ rldicl. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 0, 0 => 0000001cbe991def (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 0, 7 => 0000001cbe991def (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 0, 14 => 0000001cbe991def (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 0, 21 => 0000001cbe991def (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 0, 28 => 0000000cbe991def (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 0, 35 => 000000001e991def (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 0, 42 => 0000000000191def (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 0, 49 => 0000000000001def (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 0, 56 => 00000000000000ef (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 0, 63 => 0000000000000001 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 7, 35 => 000000000c8ef780 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 7, 42 => 00000000000ef780 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 7, 49 => 0000000000007780 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 7, 56 => 0000000000000080 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 7, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 14, 0 => 00072fa6477bc000 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 14, 7 => 00072fa6477bc000 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 14, 14 => 00032fa6477bc000 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 14, 21 => 000007a6477bc000 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 14, 28 => 00000006477bc000 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 14, 35 => 00000000077bc000 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 14, 42 => 00000000003bc000 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 14, 49 => 0000000000004000 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 14, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 14, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 21, 0 => 0397d323bde00000 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 21, 7 => 0197d323bde00000 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 21, 14 => 0003d323bde00000 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 21, 21 => 00000323bde00000 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 21, 28 => 00000003bde00000 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 21, 35 => 000000001de00000 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 21, 42 => 0000000000200000 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 21, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 21, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 21, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 28, 0 => cbe991def0000001 (80000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 28, 7 => 01e991def0000001 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 28, 14 => 000191def0000001 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 28, 21 => 000001def0000001 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 28, 28 => 0000000ef0000001 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 28, 35 => 0000000010000001 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 28, 42 => 0000000000000001 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 28, 49 => 0000000000000001 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 28, 56 => 0000000000000001 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 28, 63 => 0000000000000001 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 35, 0 => f4c8ef78000000e5 (80000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 35, 7 => 00c8ef78000000e5 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 35, 14 => 0000ef78000000e5 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 35, 21 => 00000778000000e5 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 35, 28 => 00000008000000e5 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 35, 35 => 00000000000000e5 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 35, 42 => 00000000000000e5 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 35, 49 => 00000000000000e5 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 35, 56 => 00000000000000e5 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 35, 63 => 0000000000000001 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 42, 0 => 6477bc00000072fa (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 42, 7 => 0077bc00000072fa (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 42, 14 => 0003bc00000072fa (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 42, 21 => 00000400000072fa (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 42, 28 => 00000000000072fa (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 42, 35 => 00000000000072fa (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 42, 42 => 00000000000072fa (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 42, 49 => 00000000000072fa (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 42, 56 => 00000000000000fa (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 42, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 49, 0 => 3bde000000397d32 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 49, 7 => 01de000000397d32 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 49, 14 => 0002000000397d32 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 49, 21 => 0000000000397d32 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 49, 28 => 0000000000397d32 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 49, 35 => 0000000000397d32 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 49, 42 => 0000000000397d32 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 49, 49 => 0000000000007d32 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 49, 56 => 0000000000000032 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 49, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 56, 0 => ef0000001cbe991d (80000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 56, 7 => 010000001cbe991d (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 56, 14 => 000000001cbe991d (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 56, 21 => 000000001cbe991d (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 56, 28 => 000000001cbe991d (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 56, 35 => 000000001cbe991d (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 56, 42 => 00000000003e991d (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 56, 49 => 000000000000191d (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 56, 56 => 000000000000001d (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 56, 63 => 0000000000000001 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 63, 0 => 8000000e5f4c8ef7 (80000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 63, 7 => 0000000e5f4c8ef7 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 63, 14 => 0000000e5f4c8ef7 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 63, 21 => 0000000e5f4c8ef7 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 63, 28 => 0000000e5f4c8ef7 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 63, 35 => 000000001f4c8ef7 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 63, 42 => 00000000000c8ef7 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 63, 49 => 0000000000000ef7 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 63, 56 => 00000000000000f7 (40000000 00000000)
|
|
+ rldicl. 0000001cbe991def, 63, 63 => 0000000000000001 (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 0, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 0, 7 => 01ffffffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 0, 14 => 0003ffffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 0, 21 => 000007ffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 0, 28 => 0000000fffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 0, 35 => 000000001fffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 0, 42 => 00000000003fffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 0, 49 => 0000000000007fff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 0, 56 => 00000000000000ff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 0, 63 => 0000000000000001 (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 7, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 7, 7 => 01ffffffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 7, 14 => 0003ffffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 7, 21 => 000007ffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 7, 28 => 0000000fffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 7, 35 => 000000001fffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 7, 42 => 00000000003fffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 7, 49 => 0000000000007fff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 7, 56 => 00000000000000ff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 7, 63 => 0000000000000001 (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 14, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 14, 7 => 01ffffffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 14, 14 => 0003ffffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 14, 21 => 000007ffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 14, 28 => 0000000fffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 14, 35 => 000000001fffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 14, 42 => 00000000003fffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 14, 49 => 0000000000007fff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 14, 56 => 00000000000000ff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 14, 63 => 0000000000000001 (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 21, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 21, 7 => 01ffffffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 21, 14 => 0003ffffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 21, 21 => 000007ffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 21, 28 => 0000000fffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 21, 35 => 000000001fffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 21, 42 => 00000000003fffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 21, 49 => 0000000000007fff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 21, 56 => 00000000000000ff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 21, 63 => 0000000000000001 (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 28, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 28, 7 => 01ffffffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 28, 14 => 0003ffffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 28, 21 => 000007ffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 28, 28 => 0000000fffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 28, 35 => 000000001fffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 28, 42 => 00000000003fffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 28, 49 => 0000000000007fff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 28, 56 => 00000000000000ff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 28, 63 => 0000000000000001 (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 35, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 35, 7 => 01ffffffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 35, 14 => 0003ffffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 35, 21 => 000007ffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 35, 28 => 0000000fffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 35, 35 => 000000001fffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 35, 42 => 00000000003fffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 35, 49 => 0000000000007fff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 35, 56 => 00000000000000ff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 35, 63 => 0000000000000001 (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 42, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 42, 7 => 01ffffffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 42, 14 => 0003ffffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 42, 21 => 000007ffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 42, 28 => 0000000fffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 42, 35 => 000000001fffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 42, 42 => 00000000003fffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 42, 49 => 0000000000007fff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 42, 56 => 00000000000000ff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 42, 63 => 0000000000000001 (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 49, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 49, 7 => 01ffffffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 49, 14 => 0003ffffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 49, 21 => 000007ffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 49, 28 => 0000000fffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 49, 35 => 000000001fffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 49, 42 => 00000000003fffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 49, 49 => 0000000000007fff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 49, 56 => 00000000000000ff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 49, 63 => 0000000000000001 (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 56, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 56, 7 => 01ffffffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 56, 14 => 0003ffffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 56, 21 => 000007ffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 56, 28 => 0000000fffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 56, 35 => 000000001fffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 56, 42 => 00000000003fffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 56, 49 => 0000000000007fff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 56, 56 => 00000000000000ff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 56, 63 => 0000000000000001 (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 63, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 63, 7 => 01ffffffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 63, 14 => 0003ffffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 63, 21 => 000007ffffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 63, 28 => 0000000fffffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 63, 35 => 000000001fffffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 63, 42 => 00000000003fffff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 63, 49 => 0000000000007fff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 63, 56 => 00000000000000ff (40000000 00000000)
|
|
+ rldicl. ffffffffffffffff, 63, 63 => 0000000000000001 (40000000 00000000)
|
|
+
|
|
+ rldicr. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 0, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 0, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 0, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 0, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 0, 28 => 0000001800000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 0, 35 => 0000001cb0000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 0, 42 => 0000001cbe800000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 0, 49 => 0000001cbe990000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 0, 56 => 0000001cbe991d80 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 0, 63 => 0000001cbe991def (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 7, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 7, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 7, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 7, 21 => 00000c0000000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 7, 28 => 00000e5800000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 7, 35 => 00000e5f40000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 7, 42 => 00000e5f4c800000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 7, 49 => 00000e5f4c8ec000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 7, 56 => 00000e5f4c8ef780 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 14, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 14, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 14, 14 => 0006000000000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 14, 21 => 00072c0000000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 14, 28 => 00072fa000000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 14, 35 => 00072fa640000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 14, 42 => 00072fa647600000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 14, 49 => 00072fa6477bc000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 14, 56 => 00072fa6477bc000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 14, 63 => 00072fa6477bc000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 21, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 21, 7 => 0300000000000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 21, 14 => 0396000000000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 21, 21 => 0397d00000000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 21, 28 => 0397d32000000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 21, 35 => 0397d323b0000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 21, 42 => 0397d323bde00000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 21, 49 => 0397d323bde00000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 21, 56 => 0397d323bde00000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 21, 63 => 0397d323bde00000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 28, 0 => 8000000000000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 28, 7 => cb00000000000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 28, 14 => cbe8000000000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 28, 21 => cbe9900000000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 28, 28 => cbe991d800000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 28, 35 => cbe991def0000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 28, 42 => cbe991def0000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 28, 49 => cbe991def0000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 28, 56 => cbe991def0000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 28, 63 => cbe991def0000001 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 35, 0 => 8000000000000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 35, 7 => f400000000000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 35, 14 => f4c8000000000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 35, 21 => f4c8ec0000000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 35, 28 => f4c8ef7800000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 35, 35 => f4c8ef7800000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 35, 42 => f4c8ef7800000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 35, 49 => f4c8ef7800000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 35, 56 => f4c8ef7800000080 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 35, 63 => f4c8ef78000000e5 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 42, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 42, 7 => 6400000000000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 42, 14 => 6476000000000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 42, 21 => 6477bc0000000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 42, 28 => 6477bc0000000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 42, 35 => 6477bc0000000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 42, 42 => 6477bc0000000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 42, 49 => 6477bc0000004000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 42, 56 => 6477bc0000007280 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 42, 63 => 6477bc00000072fa (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 49, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 49, 7 => 3b00000000000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 49, 14 => 3bde000000000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 49, 21 => 3bde000000000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 49, 28 => 3bde000000000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 49, 35 => 3bde000000000000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 49, 42 => 3bde000000200000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 49, 49 => 3bde000000394000 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 49, 56 => 3bde000000397d00 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 49, 63 => 3bde000000397d32 (40000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 56, 0 => 8000000000000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 56, 7 => ef00000000000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 56, 14 => ef00000000000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 56, 21 => ef00000000000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 56, 28 => ef00000000000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 56, 35 => ef00000010000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 56, 42 => ef0000001ca00000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 56, 49 => ef0000001cbe8000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 56, 56 => ef0000001cbe9900 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 56, 63 => ef0000001cbe991d (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 63, 0 => 8000000000000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 63, 7 => 8000000000000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 63, 14 => 8000000000000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 63, 21 => 8000000000000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 63, 28 => 8000000800000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 63, 35 => 8000000e50000000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 63, 42 => 8000000e5f400000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 63, 49 => 8000000e5f4c8000 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 63, 56 => 8000000e5f4c8e80 (80000000 00000000)
|
|
+ rldicr. 0000001cbe991def, 63, 63 => 8000000e5f4c8ef7 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 0, 0 => 8000000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 0, 7 => ff00000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 0, 14 => fffe000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 0, 21 => fffffc0000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 0, 28 => fffffff800000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 0, 35 => fffffffff0000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 0, 42 => ffffffffffe00000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 0, 49 => ffffffffffffc000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 0, 56 => ffffffffffffff80 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 0, 63 => ffffffffffffffff (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 7, 0 => 8000000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 7, 7 => ff00000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 7, 14 => fffe000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 7, 21 => fffffc0000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 7, 28 => fffffff800000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 7, 35 => fffffffff0000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 7, 42 => ffffffffffe00000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 7, 49 => ffffffffffffc000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 7, 56 => ffffffffffffff80 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 7, 63 => ffffffffffffffff (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 14, 0 => 8000000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 14, 7 => ff00000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 14, 14 => fffe000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 14, 21 => fffffc0000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 14, 28 => fffffff800000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 14, 35 => fffffffff0000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 14, 42 => ffffffffffe00000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 14, 49 => ffffffffffffc000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 14, 56 => ffffffffffffff80 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 14, 63 => ffffffffffffffff (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 21, 0 => 8000000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 21, 7 => ff00000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 21, 14 => fffe000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 21, 21 => fffffc0000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 21, 28 => fffffff800000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 21, 35 => fffffffff0000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 21, 42 => ffffffffffe00000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 21, 49 => ffffffffffffc000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 21, 56 => ffffffffffffff80 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 21, 63 => ffffffffffffffff (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 28, 0 => 8000000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 28, 7 => ff00000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 28, 14 => fffe000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 28, 21 => fffffc0000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 28, 28 => fffffff800000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 28, 35 => fffffffff0000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 28, 42 => ffffffffffe00000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 28, 49 => ffffffffffffc000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 28, 56 => ffffffffffffff80 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 28, 63 => ffffffffffffffff (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 35, 0 => 8000000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 35, 7 => ff00000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 35, 14 => fffe000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 35, 21 => fffffc0000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 35, 28 => fffffff800000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 35, 35 => fffffffff0000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 35, 42 => ffffffffffe00000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 35, 49 => ffffffffffffc000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 35, 56 => ffffffffffffff80 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 35, 63 => ffffffffffffffff (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 42, 0 => 8000000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 42, 7 => ff00000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 42, 14 => fffe000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 42, 21 => fffffc0000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 42, 28 => fffffff800000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 42, 35 => fffffffff0000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 42, 42 => ffffffffffe00000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 42, 49 => ffffffffffffc000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 42, 56 => ffffffffffffff80 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 42, 63 => ffffffffffffffff (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 49, 0 => 8000000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 49, 7 => ff00000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 49, 14 => fffe000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 49, 21 => fffffc0000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 49, 28 => fffffff800000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 49, 35 => fffffffff0000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 49, 42 => ffffffffffe00000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 49, 49 => ffffffffffffc000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 49, 56 => ffffffffffffff80 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 49, 63 => ffffffffffffffff (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 56, 0 => 8000000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 56, 7 => ff00000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 56, 14 => fffe000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 56, 21 => fffffc0000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 56, 28 => fffffff800000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 56, 35 => fffffffff0000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 56, 42 => ffffffffffe00000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 56, 49 => ffffffffffffc000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 56, 56 => ffffffffffffff80 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 56, 63 => ffffffffffffffff (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 63, 0 => 8000000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 63, 7 => ff00000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 63, 14 => fffe000000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 63, 21 => fffffc0000000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 63, 28 => fffffff800000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 63, 35 => fffffffff0000000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 63, 42 => ffffffffffe00000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 63, 49 => ffffffffffffc000 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 63, 56 => ffffffffffffff80 (80000000 00000000)
|
|
+ rldicr. ffffffffffffffff, 63, 63 => ffffffffffffffff (80000000 00000000)
|
|
+
|
|
+ rldimi. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 0, 0 => 0000001cbe991def (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 0, 7 => 0000001cbe991def (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 0, 14 => 0000001cbe991def (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 0, 21 => 0000001cbe991def (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 0, 28 => 0000001cbe991def (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 0, 35 => 0000001cbe991def (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 0, 42 => 0000001cbe991def (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 0, 49 => 0000001cbe991def (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 0, 56 => 0000001cbe991def (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 0, 63 => 0000001cbe991def (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 7, 0 => 00000e5f4c8ef7ef (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 7, 7 => 00000e5f4c8ef7ef (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 7, 14 => 00000e5f4c8ef7ef (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 7, 21 => 00000e5f4c8ef7ef (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 7, 28 => 00000e5f4c8ef7ef (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 7, 35 => 00000e5f4c8ef7ef (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 7, 42 => 00000e5f4c8ef7ef (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 7, 49 => 00000e5f4c8ef7ef (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 7, 56 => 00000e5f4c8ef7ef (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 7, 63 => 00000e5f4c8ef7ee (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 14, 0 => 00072fa6477bf7ee (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 14, 7 => 00072fa6477bf7ee (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 14, 14 => 00072fa6477bf7ee (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 14, 21 => 00072fa6477bf7ee (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 14, 28 => 00072fa6477bf7ee (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 14, 35 => 00072fa6477bf7ee (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 14, 42 => 00072fa6477bf7ee (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 14, 49 => 00072fa6477bf7ee (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 14, 56 => 00072fa6477bf700 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 14, 63 => 00072fa6477bf700 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 21, 0 => 0397d323bdfbf700 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 21, 7 => 0397d323bdfbf700 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 21, 14 => 0397d323bdfbf700 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 21, 21 => 0397d323bdfbf700 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 21, 28 => 0397d323bdfbf700 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 21, 35 => 0397d323bdfbf700 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 21, 42 => 0397d323bdfbf700 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 21, 49 => 0397d323bdfb8000 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 21, 56 => 0397d323bdfb8000 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 21, 63 => 0397d323bdfb8000 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 28, 0 => cbe991defdfb8000 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 28, 7 => cbe991defdfb8000 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 28, 14 => cbe991defdfb8000 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 28, 21 => cbe991defdfb8000 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 28, 28 => cbe991defdfb8000 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 28, 35 => cbe991defdfb8000 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 28, 42 => cbe991defdc00001 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 28, 49 => cbe991defdc00001 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 28, 56 => cbe991defdc00001 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 28, 63 => cbe991defdc00001 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 35, 0 => f4c8ef7efdc00001 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 35, 7 => f4c8ef7efdc00001 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 35, 14 => f4c8ef7efdc00001 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 35, 21 => f4c8ef7efdc00001 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 35, 28 => f4c8ef7efdc00001 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 35, 35 => f4c8ef7ee00000e5 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 35, 42 => f4c8ef7ee00000e5 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 35, 49 => f4c8ef7ee00000e5 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 35, 56 => f4c8ef7ee00000e5 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 35, 63 => f4c8ef7ee00000e5 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 42, 0 => 6477bf7ee00000e5 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 42, 7 => 6477bf7ee00000e5 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 42, 14 => 6477bf7ee00000e5 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 42, 21 => 6477bf7ee00000e5 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 42, 28 => 6477bf70000072fa (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 42, 35 => 6477bf70000072fa (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 42, 42 => 6477bf70000072fa (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 42, 49 => 6477bf70000072fa (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 42, 56 => 6477bf70000072fa (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 42, 63 => 6477bf70000072fa (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 49, 0 => 3bdfbf70000072fa (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 49, 7 => 3bdfbf70000072fa (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 49, 14 => 3bdfbf70000072fa (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 49, 21 => 3bdfb80000397d32 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 49, 28 => 3bdfb80000397d32 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 49, 35 => 3bdfb80000397d32 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 49, 42 => 3bdfb80000397d32 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 49, 49 => 3bdfb80000397d32 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 49, 56 => 3bdfb80000397d32 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 49, 63 => 3bdfb80000397d32 (40000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 56, 0 => efdfb80000397d32 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 56, 7 => efdfb80000397d32 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 56, 14 => efdc00001cbe991d (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 56, 21 => efdc00001cbe991d (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 56, 28 => efdc00001cbe991d (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 56, 35 => efdc00001cbe991d (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 56, 42 => efdc00001cbe991d (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 56, 49 => efdc00001cbe991d (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 56, 56 => efdc00001cbe991d (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 56, 63 => efdc00001cbe991d (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 63, 0 => efdc00001cbe991d (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 63, 7 => ee00000e5f4c8ef7 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 63, 14 => ee00000e5f4c8ef7 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 63, 21 => ee00000e5f4c8ef7 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 63, 28 => ee00000e5f4c8ef7 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 63, 35 => ee00000e5f4c8ef7 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 63, 42 => ee00000e5f4c8ef7 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 63, 49 => ee00000e5f4c8ef7 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 63, 56 => ee00000e5f4c8ef7 (80000000 00000000)
|
|
+ rldimi. 0000001cbe991def, 63, 63 => ee00000e5f4c8ef7 (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 0, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 0, 7 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 0, 14 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 0, 21 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 0, 28 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 0, 35 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 0, 42 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 0, 49 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 0, 56 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 0, 63 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 7, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 7, 7 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 7, 14 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 7, 21 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 7, 28 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 7, 35 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 7, 42 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 7, 49 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 7, 56 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 7, 63 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 14, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 14, 7 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 14, 14 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 14, 21 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 14, 28 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 14, 35 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 14, 42 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 14, 49 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 14, 56 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 14, 63 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 21, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 21, 7 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 21, 14 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 21, 21 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 21, 28 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 21, 35 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 21, 42 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 21, 49 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 21, 56 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 21, 63 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 28, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 28, 7 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 28, 14 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 28, 21 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 28, 28 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 28, 35 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 28, 42 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 28, 49 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 28, 56 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 28, 63 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 35, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 35, 7 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 35, 14 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 35, 21 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 35, 28 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 35, 35 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 35, 42 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 35, 49 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 35, 56 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 35, 63 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 42, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 42, 7 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 42, 14 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 42, 21 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 42, 28 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 42, 35 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 42, 42 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 42, 49 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 42, 56 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 42, 63 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 49, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 49, 7 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 49, 14 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 49, 21 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 49, 28 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 49, 35 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 49, 42 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 49, 49 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 49, 56 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 49, 63 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 56, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 56, 7 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 56, 14 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 56, 21 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 56, 28 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 56, 35 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 56, 42 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 56, 49 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 56, 56 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 56, 63 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 63, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 63, 7 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 63, 14 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 63, 21 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 63, 28 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 63, 35 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 63, 42 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 63, 49 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 63, 56 => ffffffffffffffff (80000000 00000000)
|
|
+ rldimi. ffffffffffffffff, 63, 63 => ffffffffffffffff (80000000 00000000)
|
|
+
|
|
+ sradi. 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
|
|
+ sradi. 0000000000000000, 7 => 0000000000000000 (20000000 00000000)
|
|
+ sradi. 0000000000000000, 14 => 0000000000000000 (20000000 00000000)
|
|
+ sradi. 0000000000000000, 21 => 0000000000000000 (20000000 00000000)
|
|
+ sradi. 0000000000000000, 28 => 0000000000000000 (20000000 00000000)
|
|
+ sradi. 0000000000000000, 35 => 0000000000000000 (20000000 00000000)
|
|
+ sradi. 0000000000000000, 42 => 0000000000000000 (20000000 00000000)
|
|
+ sradi. 0000000000000000, 49 => 0000000000000000 (20000000 00000000)
|
|
+ sradi. 0000000000000000, 56 => 0000000000000000 (20000000 00000000)
|
|
+ sradi. 0000000000000000, 63 => 0000000000000000 (20000000 00000000)
|
|
+ sradi. 0000001cbe991def, 0 => 0000001cbe991def (40000000 00000000)
|
|
+ sradi. 0000001cbe991def, 7 => 00000000397d323b (40000000 00000000)
|
|
+ sradi. 0000001cbe991def, 14 => 000000000072fa64 (40000000 00000000)
|
|
+ sradi. 0000001cbe991def, 21 => 000000000000e5f4 (40000000 00000000)
|
|
+ sradi. 0000001cbe991def, 28 => 00000000000001cb (40000000 00000000)
|
|
+ sradi. 0000001cbe991def, 35 => 0000000000000003 (40000000 00000000)
|
|
+ sradi. 0000001cbe991def, 42 => 0000000000000000 (20000000 00000000)
|
|
+ sradi. 0000001cbe991def, 49 => 0000000000000000 (20000000 00000000)
|
|
+ sradi. 0000001cbe991def, 56 => 0000000000000000 (20000000 00000000)
|
|
+ sradi. 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000)
|
|
+ sradi. ffffffffffffffff, 0 => ffffffffffffffff (80000000 00000000)
|
|
+ sradi. ffffffffffffffff, 7 => ffffffffffffffff (80000000 20000000)
|
|
+ sradi. ffffffffffffffff, 14 => ffffffffffffffff (80000000 20000000)
|
|
+ sradi. ffffffffffffffff, 21 => ffffffffffffffff (80000000 20000000)
|
|
+ sradi. ffffffffffffffff, 28 => ffffffffffffffff (80000000 20000000)
|
|
+ sradi. ffffffffffffffff, 35 => ffffffffffffffff (80000000 20000000)
|
|
+ sradi. ffffffffffffffff, 42 => ffffffffffffffff (80000000 20000000)
|
|
+ sradi. ffffffffffffffff, 49 => ffffffffffffffff (80000000 20000000)
|
|
+ sradi. ffffffffffffffff, 56 => ffffffffffffffff (80000000 20000000)
|
|
+ sradi. ffffffffffffffff, 63 => ffffffffffffffff (80000000 20000000)
|
|
+
|
|
+PPC integer load insns
|
|
+ with one register + one 16 bits immediate args with flags update:
|
|
+ lbz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lbz 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lbz 15, (ffffffffffffffff) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lbz 1, (00000000ffffffff) => 00000000000000ff, 0 (00000000 00000000)
|
|
+ lbz -7, (00000000be991def) => 000000000000001d, 0 (00000000 00000000)
|
|
+ lbz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+
|
|
+ lbzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lbzu 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
|
|
+ lbzu 15, (ffffffffffffffff) => 0000000000000000, 15 (00000000 00000000)
|
|
+ lbzu 1, (00000000ffffffff) => 00000000000000ff, 1 (00000000 00000000)
|
|
+ lbzu -7, (00000000be991def) => 000000000000001d, -7 (00000000 00000000)
|
|
+ lbzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
|
|
+
|
|
+ lha 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lha 7, (0000001cbe991def) => ffffffffffffef00, 0 (00000000 00000000)
|
|
+ lha 15, (ffffffffffffffff) => ffffffffffffff00, 0 (00000000 00000000)
|
|
+ lha 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
|
+ lha -7, (00000000be991def) => ffffffffffff991d, 0 (00000000 00000000)
|
|
+ lha -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+
|
|
+ lhau 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lhau 7, (0000001cbe991def) => ffffffffffffef00, 7 (00000000 00000000)
|
|
+ lhau 15, (ffffffffffffffff) => ffffffffffffff00, 15 (00000000 00000000)
|
|
+ lhau 1, (00000000ffffffff) => ffffffffffffffff, 1 (00000000 00000000)
|
|
+ lhau -7, (00000000be991def) => ffffffffffff991d, -7 (00000000 00000000)
|
|
+ lhau -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
|
|
+
|
|
+ lhz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lhz 7, (0000001cbe991def) => 000000000000ef00, 0 (00000000 00000000)
|
|
+ lhz 15, (ffffffffffffffff) => 000000000000ff00, 0 (00000000 00000000)
|
|
+ lhz 1, (00000000ffffffff) => 000000000000ffff, 0 (00000000 00000000)
|
|
+ lhz -7, (00000000be991def) => 000000000000991d, 0 (00000000 00000000)
|
|
+ lhz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+
|
|
+ lhzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lhzu 7, (0000001cbe991def) => 000000000000ef00, 7 (00000000 00000000)
|
|
+ lhzu 15, (ffffffffffffffff) => 000000000000ff00, 15 (00000000 00000000)
|
|
+ lhzu 1, (00000000ffffffff) => 000000000000ffff, 1 (00000000 00000000)
|
|
+ lhzu -7, (00000000be991def) => 000000000000991d, -7 (00000000 00000000)
|
|
+ lhzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
|
|
+
|
|
+ lwz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lwz 7, (0000001cbe991def) => 00000000991def00, 0 (00000000 00000000)
|
|
+ lwz 15, (ffffffffffffffff) => 00000000ffffff00, 0 (00000000 00000000)
|
|
+ lwz 1, (00000000ffffffff) => 00000000ffffffff, 0 (00000000 00000000)
|
|
+ lwz -7, (00000000be991def) => 000000001cbe991d, 0 (00000000 00000000)
|
|
+ lwz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+
|
|
+ lwzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lwzu 7, (0000001cbe991def) => 00000000991def00, 7 (00000000 00000000)
|
|
+ lwzu 15, (ffffffffffffffff) => 00000000ffffff00, 15 (00000000 00000000)
|
|
+ lwzu 1, (00000000ffffffff) => 00000000ffffffff, 1 (00000000 00000000)
|
|
+ lwzu -7, (00000000be991def) => 000000001cbe991d, -7 (00000000 00000000)
|
|
+ lwzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
|
|
+
|
|
+ ld 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ ld 7, (0000001cbe991def) => be991def00000000, 0 (00000000 00000000)
|
|
+ ld 15, (ffffffffffffffff) => ffffffff0000001c, 0 (00000000 00000000)
|
|
+ ld 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
|
+ ld -7, (00000000be991def) => 0000001cbe991def, -8 (00000000 00000000)
|
|
+ ld -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
|
|
+
|
|
+ ldu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ ldu 7, (0000001cbe991def) => be991def00000000, 4 (00000000 00000000)
|
|
+ ldu 15, (ffffffffffffffff) => ffffffff0000001c, 12 (00000000 00000000)
|
|
+ ldu 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
|
+ ldu -7, (00000000be991def) => 0000001cbe991def, -8 (00000000 00000000)
|
|
+ ldu -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
|
|
+
|
|
+ lwa 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lwa 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lwa 15, (ffffffffffffffff) => 000000000000001c, 0 (00000000 00000000)
|
|
+ lwa 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
|
+ lwa -7, (00000000be991def) => 0000001cbe991def, -8 (00000000 00000000)
|
|
+ lwa -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
|
|
+
|
|
+PPC integer load insns with two register args:
|
|
+ lbzx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lbzx 8, (0000001cbe991def) => 00000000000000ef, 0 (00000000 00000000)
|
|
+ lbzx 16, (ffffffffffffffff) => 00000000000000ff, 0 (00000000 00000000)
|
|
+
|
|
+ lbzux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lbzux 8, (0000001cbe991def) => 00000000000000ef, 8 (00000000 00000000)
|
|
+ lbzux 16, (ffffffffffffffff) => 00000000000000ff, 16 (00000000 00000000)
|
|
+
|
|
+ lhax 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lhax 8, (0000001cbe991def) => 0000000000001def, 0 (00000000 00000000)
|
|
+ lhax 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
|
+
|
|
+ lhaux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lhaux 8, (0000001cbe991def) => 0000000000001def, 8 (00000000 00000000)
|
|
+ lhaux 16, (ffffffffffffffff) => ffffffffffffffff, 16 (00000000 00000000)
|
|
+
|
|
+ lhzx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lhzx 8, (0000001cbe991def) => 0000000000001def, 0 (00000000 00000000)
|
|
+ lhzx 16, (ffffffffffffffff) => 000000000000ffff, 0 (00000000 00000000)
|
|
+
|
|
+ lhzux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lhzux 8, (0000001cbe991def) => 0000000000001def, 8 (00000000 00000000)
|
|
+ lhzux 16, (ffffffffffffffff) => 000000000000ffff, 16 (00000000 00000000)
|
|
+
|
|
+ lwzx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lwzx 8, (0000001cbe991def) => 00000000be991def, 0 (00000000 00000000)
|
|
+ lwzx 16, (ffffffffffffffff) => 00000000ffffffff, 0 (00000000 00000000)
|
|
+
|
|
+ lwzux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lwzux 8, (0000001cbe991def) => 00000000be991def, 8 (00000000 00000000)
|
|
+ lwzux 16, (ffffffffffffffff) => 00000000ffffffff, 16 (00000000 00000000)
|
|
+
|
|
+ ldx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ ldx 8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000)
|
|
+ ldx 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
|
+
|
|
+ ldux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ ldux 8, (0000001cbe991def) => 0000001cbe991def, 8 (00000000 00000000)
|
|
+ ldux 16, (ffffffffffffffff) => ffffffffffffffff, 16 (00000000 00000000)
|
|
+
|
|
+ lwax 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lwax 8, (0000001cbe991def) => ffffffffbe991def, 0 (00000000 00000000)
|
|
+ lwax 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
|
+
|
|
+ lwaux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lwaux 8, (0000001cbe991def) => ffffffffbe991def, 8 (00000000 00000000)
|
|
+ lwaux 16, (ffffffffffffffff) => ffffffffffffffff, 16 (00000000 00000000)
|
|
+
|
|
+PPC integer store insns
|
|
+ with one register + one 16 bits immediate args with flags update:
|
|
+ stb 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
|
|
+ stb 0000001cbe991def, 8 => 00000000000000ef, 0 (00000000 00000000)
|
|
+ stb ffffffffffffffff, 16 => 00000000000000ff, 0 (00000000 00000000)
|
|
+ stb 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
|
|
+ stb 0000001cbe991def, -8 => 00000000000000ef, 0 (00000000 00000000)
|
|
+ stb ffffffffffffffff, 0 => 00000000000000ff, 0 (00000000 00000000)
|
|
+
|
|
+ stbu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
|
|
+ stbu 0000001cbe991def, 8 => 00000000000000ef, 8 (00000000 00000000)
|
|
+ stbu ffffffffffffffff, 16 => 00000000000000ff, 16 (00000000 00000000)
|
|
+ stbu 0000000000000000, -16 => 0000000000000000, -16 (00000000 00000000)
|
|
+ stbu 0000001cbe991def, -8 => 00000000000000ef, -8 (00000000 00000000)
|
|
+ stbu ffffffffffffffff, 0 => 00000000000000ff, 0 (00000000 00000000)
|
|
+
|
|
+ sth 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
|
|
+ sth 0000001cbe991def, 8 => 0000000000001def, 0 (00000000 00000000)
|
|
+ sth ffffffffffffffff, 16 => 000000000000ffff, 0 (00000000 00000000)
|
|
+ sth 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
|
|
+ sth 0000001cbe991def, -8 => 0000000000001def, 0 (00000000 00000000)
|
|
+ sth ffffffffffffffff, 0 => 000000000000ffff, 0 (00000000 00000000)
|
|
+
|
|
+ sthu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
|
|
+ sthu 0000001cbe991def, 8 => 0000000000001def, 8 (00000000 00000000)
|
|
+ sthu ffffffffffffffff, 16 => 000000000000ffff, 16 (00000000 00000000)
|
|
+ sthu 0000000000000000, -16 => 0000000000000000, -16 (00000000 00000000)
|
|
+ sthu 0000001cbe991def, -8 => 0000000000001def, -8 (00000000 00000000)
|
|
+ sthu ffffffffffffffff, 0 => 000000000000ffff, 0 (00000000 00000000)
|
|
+
|
|
+ stw 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
|
|
+ stw 0000001cbe991def, 8 => 00000000be991def, 0 (00000000 00000000)
|
|
+ stw ffffffffffffffff, 16 => 00000000ffffffff, 0 (00000000 00000000)
|
|
+ stw 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
|
|
+ stw 0000001cbe991def, -8 => 00000000be991def, 0 (00000000 00000000)
|
|
+ stw ffffffffffffffff, 0 => 00000000ffffffff, 0 (00000000 00000000)
|
|
+
|
|
+ stwu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
|
|
+ stwu 0000001cbe991def, 8 => 00000000be991def, 8 (00000000 00000000)
|
|
+ stwu ffffffffffffffff, 16 => 00000000ffffffff, 16 (00000000 00000000)
|
|
+ stwu 0000000000000000, -16 => 0000000000000000, -16 (00000000 00000000)
|
|
+ stwu 0000001cbe991def, -8 => 00000000be991def, -8 (00000000 00000000)
|
|
+ stwu ffffffffffffffff, 0 => 00000000ffffffff, 0 (00000000 00000000)
|
|
+
|
|
+ std 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
|
|
+ std 0000001cbe991def, 8 => 0000001cbe991def, 0 (00000000 00000000)
|
|
+ std ffffffffffffffff, 16 => ffffffffffffffff, 0 (00000000 00000000)
|
|
+ std 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
|
|
+ std 0000001cbe991def, -8 => 0000001cbe991def, 0 (00000000 00000000)
|
|
+ std ffffffffffffffff, 0 => ffffffffffffffff, 0 (00000000 00000000)
|
|
+
|
|
+ stdu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
|
|
+ stdu 0000001cbe991def, 8 => 0000001cbe991def, 0 (00000000 00000000)
|
|
+ stdu ffffffffffffffff, 16 => ffffffffffffffff, 0 (00000000 00000000)
|
|
+ stdu 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
|
|
+ stdu 0000001cbe991def, -8 => 0000001cbe991def, 0 (00000000 00000000)
|
|
+ stdu ffffffffffffffff, 0 => ffffffffffffffff, 0 (00000000 00000000)
|
|
+
|
|
+PPC integer store insns with three register args:
|
|
+ stbx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
|
|
+ stbx 0000001cbe991def, 8 => 00000000000000ef, 0 (00000000 00000000)
|
|
+ stbx ffffffffffffffff, 16 => 00000000000000ff, 0 (00000000 00000000)
|
|
+
|
|
+ stbux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
|
|
+ stbux 0000001cbe991def, 8 => 00000000000000ef, 8 (00000000 00000000)
|
|
+ stbux ffffffffffffffff, 16 => 00000000000000ff, 16 (00000000 00000000)
|
|
+
|
|
+ sthx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
|
|
+ sthx 0000001cbe991def, 8 => 0000000000001def, 0 (00000000 00000000)
|
|
+ sthx ffffffffffffffff, 16 => 000000000000ffff, 0 (00000000 00000000)
|
|
+
|
|
+ sthux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
|
|
+ sthux 0000001cbe991def, 8 => 0000000000001def, 8 (00000000 00000000)
|
|
+ sthux ffffffffffffffff, 16 => 000000000000ffff, 16 (00000000 00000000)
|
|
+
|
|
+ stwx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
|
|
+ stwx 0000001cbe991def, 8 => 00000000be991def, 0 (00000000 00000000)
|
|
+ stwx ffffffffffffffff, 16 => 00000000ffffffff, 0 (00000000 00000000)
|
|
+
|
|
+ stwux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
|
|
+ stwux 0000001cbe991def, 8 => 00000000be991def, 8 (00000000 00000000)
|
|
+ stwux ffffffffffffffff, 16 => 00000000ffffffff, 16 (00000000 00000000)
|
|
+
|
|
+ stdx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
|
|
+ stdx 0000001cbe991def, 8 => 0000001cbe991def, 0 (00000000 00000000)
|
|
+ stdx ffffffffffffffff, 16 => ffffffffffffffff, 0 (00000000 00000000)
|
|
+
|
|
+ stdux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
|
|
+ stdux 0000001cbe991def, 8 => 0000001cbe991def, 8 (00000000 00000000)
|
|
+ stdux ffffffffffffffff, 16 => ffffffffffffffff, 16 (00000000 00000000)
|
|
+
|
|
+PPC integer population count with one register args, no flags:
|
|
+ popcntb 0000000000000000 => 0000000000000000 (00000000 00000000)
|
|
+ popcntb 0000001cbe991def => 0000000306040407 (00000000 00000000)
|
|
+ popcntb ffffffffffffffff => 0808080808080808 (00000000 00000000)
|
|
+
|
|
+All done. Tested 210 different instructions
|
|
Index: none/tests/ppc64/jm-int.stdout.exp
|
|
===================================================================
|
|
--- none/tests/ppc64/jm-int.stdout.exp.orig
|
|
+++ none/tests/ppc64/jm-int.stdout.exp
|
|
@@ -4549,81 +4549,81 @@ PPC logical insns with special forms wit
|
|
PPC integer load insns
|
|
with one register + one 16 bits immediate args with flags update:
|
|
lbz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
- lbz 8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
|
- lbz 16, (ffffffffffffffff) => 00000000000000ff, 0 (00000000 00000000)
|
|
- lbz -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
- lbz -8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
|
- lbz 0, (ffffffffffffffff) => 00000000000000ff, 0 (00000000 00000000)
|
|
+ lbz 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lbz 15, (ffffffffffffffff) => 00000000000000ef, 0 (00000000 00000000)
|
|
+ lbz 1, (00000000ffffffff) => 00000000000000ff, 0 (00000000 00000000)
|
|
+ lbz -7, (00000000be991def) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lbz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
|
|
lbzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
- lbzu 8, (0000001cbe991def) => 0000000000000000, 8 (00000000 00000000)
|
|
- lbzu 16, (ffffffffffffffff) => 00000000000000ff, 16 (00000000 00000000)
|
|
- lbzu -16, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
|
|
- lbzu -8, (0000001cbe991def) => 0000000000000000, -8 (00000000 00000000)
|
|
- lbzu 0, (ffffffffffffffff) => 00000000000000ff, 0 (00000000 00000000)
|
|
+ lbzu 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
|
|
+ lbzu 15, (ffffffffffffffff) => 00000000000000ef, 15 (00000000 00000000)
|
|
+ lbzu 1, (00000000ffffffff) => 00000000000000ff, 1 (00000000 00000000)
|
|
+ lbzu -7, (00000000be991def) => 0000000000000000, -7 (00000000 00000000)
|
|
+ lbzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
|
|
|
|
lha 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
- lha 8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
|
- lha 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
|
- lha -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
- lha -8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
|
- lha 0, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
|
+ lha 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lha 15, (ffffffffffffffff) => ffffffffffffefff, 0 (00000000 00000000)
|
|
+ lha 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
|
+ lha -7, (00000000be991def) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lha -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
|
|
lhau 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
- lhau 8, (0000001cbe991def) => 0000000000000000, 8 (00000000 00000000)
|
|
- lhau 16, (ffffffffffffffff) => ffffffffffffffff, 16 (00000000 00000000)
|
|
- lhau -16, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
|
|
- lhau -8, (0000001cbe991def) => 0000000000000000, -8 (00000000 00000000)
|
|
- lhau 0, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
|
+ lhau 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
|
|
+ lhau 15, (ffffffffffffffff) => ffffffffffffefff, 15 (00000000 00000000)
|
|
+ lhau 1, (00000000ffffffff) => ffffffffffffffff, 1 (00000000 00000000)
|
|
+ lhau -7, (00000000be991def) => 0000000000000000, -7 (00000000 00000000)
|
|
+ lhau -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
|
|
|
|
lhz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
- lhz 8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
|
- lhz 16, (ffffffffffffffff) => 000000000000ffff, 0 (00000000 00000000)
|
|
- lhz -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
- lhz -8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
|
- lhz 0, (ffffffffffffffff) => 000000000000ffff, 0 (00000000 00000000)
|
|
+ lhz 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lhz 15, (ffffffffffffffff) => 000000000000efff, 0 (00000000 00000000)
|
|
+ lhz 1, (00000000ffffffff) => 000000000000ffff, 0 (00000000 00000000)
|
|
+ lhz -7, (00000000be991def) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lhz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
|
|
lhzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
- lhzu 8, (0000001cbe991def) => 0000000000000000, 8 (00000000 00000000)
|
|
- lhzu 16, (ffffffffffffffff) => 000000000000ffff, 16 (00000000 00000000)
|
|
- lhzu -16, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
|
|
- lhzu -8, (0000001cbe991def) => 0000000000000000, -8 (00000000 00000000)
|
|
- lhzu 0, (ffffffffffffffff) => 000000000000ffff, 0 (00000000 00000000)
|
|
+ lhzu 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
|
|
+ lhzu 15, (ffffffffffffffff) => 000000000000efff, 15 (00000000 00000000)
|
|
+ lhzu 1, (00000000ffffffff) => 000000000000ffff, 1 (00000000 00000000)
|
|
+ lhzu -7, (00000000be991def) => 0000000000000000, -7 (00000000 00000000)
|
|
+ lhzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
|
|
|
|
lwz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
- lwz 8, (0000001cbe991def) => 000000000000001c, 0 (00000000 00000000)
|
|
- lwz 16, (ffffffffffffffff) => 00000000ffffffff, 0 (00000000 00000000)
|
|
- lwz -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
- lwz -8, (0000001cbe991def) => 000000000000001c, 0 (00000000 00000000)
|
|
- lwz 0, (ffffffffffffffff) => 00000000ffffffff, 0 (00000000 00000000)
|
|
+ lwz 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lwz 15, (ffffffffffffffff) => 00000000efffffff, 0 (00000000 00000000)
|
|
+ lwz 1, (00000000ffffffff) => 00000000ffffffff, 0 (00000000 00000000)
|
|
+ lwz -7, (00000000be991def) => 0000000000001cbe, 0 (00000000 00000000)
|
|
+ lwz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
|
|
lwzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
- lwzu 8, (0000001cbe991def) => 000000000000001c, 8 (00000000 00000000)
|
|
- lwzu 16, (ffffffffffffffff) => 00000000ffffffff, 16 (00000000 00000000)
|
|
- lwzu -16, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
|
|
- lwzu -8, (0000001cbe991def) => 000000000000001c, -8 (00000000 00000000)
|
|
- lwzu 0, (ffffffffffffffff) => 00000000ffffffff, 0 (00000000 00000000)
|
|
+ lwzu 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
|
|
+ lwzu 15, (ffffffffffffffff) => 00000000efffffff, 15 (00000000 00000000)
|
|
+ lwzu 1, (00000000ffffffff) => 00000000ffffffff, 1 (00000000 00000000)
|
|
+ lwzu -7, (00000000be991def) => 0000000000001cbe, -7 (00000000 00000000)
|
|
+ lwzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
|
|
|
|
ld 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
- ld 8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000)
|
|
- ld 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
|
- ld -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
- ld -8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000)
|
|
- ld 0, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
|
+ ld 7, (0000001cbe991def) => 000000000000001c, 0 (00000000 00000000)
|
|
+ ld 15, (ffffffffffffffff) => be991defffffffff, 0 (00000000 00000000)
|
|
+ ld 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
|
+ ld -7, (00000000be991def) => 0000001cbe991def, -8 (00000000 00000000)
|
|
+ ld -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
|
|
|
|
ldu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
- ldu 8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000)
|
|
- ldu 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
|
- ldu -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
- ldu -8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000)
|
|
- ldu 0, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
|
+ ldu 7, (0000001cbe991def) => 000000000000001c, 4 (00000000 00000000)
|
|
+ ldu 15, (ffffffffffffffff) => be991defffffffff, 12 (00000000 00000000)
|
|
+ ldu 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
|
+ ldu -7, (00000000be991def) => 0000001cbe991def, -8 (00000000 00000000)
|
|
+ ldu -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
|
|
|
|
lwa 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
- lwa 8, (0000001cbe991def) => 000000000000001c, 0 (00000000 00000000)
|
|
- lwa 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
|
- lwa -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
- lwa -8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000)
|
|
- lwa 0, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
|
+ lwa 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
|
+ lwa 15, (ffffffffffffffff) => ffffffffbe991def, 0 (00000000 00000000)
|
|
+ lwa 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
|
+ lwa -7, (00000000be991def) => 0000001cbe991def, -8 (00000000 00000000)
|
|
+ lwa -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
|
|
|
|
PPC integer load insns with two register args:
|
|
lbzx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
|
Index: none/tests/ppc64/test_isa_2_06_part1.stdout.exp
|
|
===================================================================
|
|
--- none/tests/ppc64/test_isa_2_06_part1.stdout.exp.orig
|
|
+++ none/tests/ppc64/test_isa_2_06_part1.stdout.exp
|
|
@@ -66,9 +66,9 @@ xxlandc: 00112233 44556677 8899aabb 9192
|
|
xxlandc: 44556677 8899aabb 91929394 a1a2a3a4 xxlandc b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => 44454443 0819283b 00000000 8180a280
|
|
|
|
Test ldbrx instruction
|
|
-ldbrx: 01 23 45 67 89 ab cd (reverse) => ef cd ab 89 67 45 23 01
|
|
-ldbrx: 89 ab cd ef 00 11 22 (reverse) => 33 22 11 00 ef cd ab 89
|
|
-ldbrx: 00 11 22 33 44 55 66 (reverse) => 77 66 55 44 33 22 11 00
|
|
+ldbrx: 01 23 45 67 89 ab cd ef (reverse) => ef cd ab 89 67 45 23 01
|
|
+ldbrx: 89 ab cd ef 00 11 22 33 (reverse) => 33 22 11 00 ef cd ab 89
|
|
+ldbrx: 00 11 22 33 44 55 66 77 (reverse) => 77 66 55 44 33 22 11 00
|
|
|
|
Test popcntd instruction
|
|
popcntd: 0x9182736405504536 => 24
|
|
@@ -138,13 +138,27 @@ ftdiv: 0000000000000000 <=> 000000000000
|
|
ftdiv: 0000000000000000 <=> 8000000000000000 ? e (CRx)
|
|
|
|
Test VSX move instructions
|
|
-xsabsdp: 01234567 89abcdef xsabsdp 8899aabb 91929394x => 0899aabb 91929394
|
|
-
|
|
-xscpsgndp: 8899aabb 91929394 xscpsgndp 01234567 89abcdefx => 81234567 89abcdef
|
|
-
|
|
-xsnabsdp: b1b2b3b4 c1c2c3c4 xsnabsdp 44556677 8899aabbx => c4556677 8899aabb
|
|
-
|
|
-xsnegdp: 01234567 89abcdef xsnegdp b1b2b3b4 c1c2c3c4x => 31b2b3b4 c1c2c3c4
|
|
+xsabsdp: X[B]: 0123456789abcdef => 0123456789abcdef
|
|
+xsabsdp: X[B]: 8899aabb19293942 => 0899aabb19293942
|
|
+xsabsdp: X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4
|
|
+
|
|
+xscpsgndp: X[A]: 0123456789abcdef X[B]: 0123456789abcdef => 0123456789abcdef
|
|
+xscpsgndp: X[A]: 8899aabb19293942 X[B]: 0123456789abcdef => 8123456789abcdef
|
|
+xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: 0123456789abcdef => 8123456789abcdef
|
|
+xscpsgndp: X[A]: 0123456789abcdef X[B]: 8899aabb19293942 => 0899aabb19293942
|
|
+xscpsgndp: X[A]: 8899aabb19293942 X[B]: 8899aabb19293942 => 8899aabb19293942
|
|
+xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: 8899aabb19293942 => 8899aabb19293942
|
|
+xscpsgndp: X[A]: 0123456789abcdef X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4
|
|
+xscpsgndp: X[A]: 8899aabb19293942 X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4
|
|
+xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4
|
|
+
|
|
+xsnabsdp: X[B]: 0123456789abcdef => 8123456789abcdef
|
|
+xsnabsdp: X[B]: 8899aabb19293942 => 8899aabb19293942
|
|
+xsnabsdp: X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4
|
|
+
|
|
+xsnegdp: X[B]: 0123456789abcdef => 8123456789abcdef
|
|
+xsnegdp: X[B]: 8899aabb19293942 => 0899aabb19293942
|
|
+xsnegdp: X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4
|
|
|
|
Test VSX permute instructions
|
|
xxmrghw:
|
|
@@ -1028,4 +1042,3 @@ Test VSX scalar integer conversion instr
|
|
#14: xscvuxddp c0d0650f5a07b353 => 43e81a0ca1eb40f6
|
|
|
|
|
|
-Testcase PASSED
|
|
Index: none/tests/ppc64/test_isa_2_07_part2.stdout.exp
|
|
===================================================================
|
|
--- none/tests/ppc64/test_isa_2_07_part2.stdout.exp.orig
|
|
+++ none/tests/ppc64/test_isa_2_07_part2.stdout.exp
|
|
@@ -651,26 +651,26 @@ Test VSX floating point instructions
|
|
|
|
|
|
Test VSX vector and scalar single argument instructions
|
|
-#0: xscvdpspn conv(3ec00000) = 3ec00000
|
|
-#1: xscvdpspn conv(42780000) = 42780000
|
|
-#2: xscvdpspn conv(00000000) = 00000000
|
|
-#3: xscvdpspn conv(7f800000) = 7f800000
|
|
-#4: xscvdpspn conv(00000000) = 00000000
|
|
-#5: xscvdpspn conv(00000000) = 00000000
|
|
-#6: xscvdpspn conv(80000000) = 80000000
|
|
-#7: xscvdpspn conv(7f800000) = 7f800000
|
|
-#8: xscvdpspn conv(ff800000) = ff800000
|
|
-#9: xscvdpspn conv(7fbfffff) = 7fbfffff
|
|
-#10: xscvdpspn conv(ffbfffff) = ffbfffff
|
|
-#11: xscvdpspn conv(7fc00000) = 7fc00000
|
|
-#12: xscvdpspn conv(ffc00000) = ffc00000
|
|
-#13: xscvdpspn conv(80000000) = 80000000
|
|
-#14: xscvdpspn conv(c683287b) = c683287b
|
|
-#15: xscvdpspn conv(49192c2d) = 49192c2d
|
|
-#16: xscvdpspn conv(49c1288d) = 49c1288d
|
|
-#17: xscvdpspn conv(418977ad) = 418977ad
|
|
-#18: xscvdpspn conv(428a5faf) = 428a5faf
|
|
-#19: xscvdpspn conv(44bb5fcc) = 44bb5fcc
|
|
+#0: xscvdpspn conv(3fd8000000000000) = 3ec00000
|
|
+#1: xscvdpspn conv(404f000000000000) = 42780000
|
|
+#2: xscvdpspn conv(0018000000b77501) = 00000000
|
|
+#3: xscvdpspn conv(7fe800000000051b) = 7f800000
|
|
+#4: xscvdpspn conv(0123214569900000) = 00000000
|
|
+#5: xscvdpspn conv(0000000000000000) = 00000000
|
|
+#6: xscvdpspn conv(8000000000000000) = 80000000
|
|
+#7: xscvdpspn conv(7ff0000000000000) = 7f800000
|
|
+#8: xscvdpspn conv(fff0000000000000) = ff800000
|
|
+#9: xscvdpspn conv(7ff7ffffffffffff) = 7fbfffff
|
|
+#10: xscvdpspn conv(fff7ffffffffffff) = ffbfffff
|
|
+#11: xscvdpspn conv(7ff8000000000000) = 7fc00000
|
|
+#12: xscvdpspn conv(fff8000000000000) = ffc00000
|
|
+#13: xscvdpspn conv(8008340000078000) = 80000000
|
|
+#14: xscvdpspn conv(c0d0650f5a07b353) = c683287b
|
|
+#15: xscvdpspn conv(41232585a9900000) = 49192c2d
|
|
+#16: xscvdpspn conv(41382511a2000000) = 49c1288d
|
|
+#17: xscvdpspn conv(40312ef5a9300000) = 418977ad
|
|
+#18: xscvdpspn conv(40514bf5d2300000) = 428a5faf
|
|
+#19: xscvdpspn conv(40976bf982440000) = 44bb5fcc
|
|
|
|
#0: xscvspdpn conv(3ec00000) = 3fd8000000000000
|
|
#1: xscvspdpn conv(42780000) = 404f000000000000
|
|
@@ -783,23 +783,15 @@ Test VSX logic instructions
|
|
#2: xxlnand (80000001 89abcdef 00112233 74556677, 80000001 89abcdef 00112233 74556677) ==> 7ffffffe 76543210 ffeeddcc 8baa9988
|
|
|
|
Test VSX scalar integer conversion instructions
|
|
-#0: xscvsxdsp 80000001 => c3e0000000000000
|
|
-#1: xscvsxdsp 89abcdef => c3dd950c80000000
|
|
-#2: xscvsxdsp 00112233 => 4331223380000000
|
|
-#3: xscvsxdsp 74556677 => 43dd1559a0000000
|
|
-#4: xscvsxdsp 00001abb => 42babb89a0000000
|
|
-#5: xscvsxdsp 00000001 => 41f89abce0000000
|
|
-#6: xscvsxdsp 31929394 => 43c8c949c0000000
|
|
-#7: xscvsxdsp a1a2a3a4 => c3d7975720000000
|
|
-
|
|
-#0: xscvuxdsp 80000001 => 43e0000000000000
|
|
-#1: xscvuxdsp 89abcdef => 43e13579c0000000
|
|
-#2: xscvuxdsp 00112233 => 4331223380000000
|
|
-#3: xscvuxdsp 74556677 => 43dd1559a0000000
|
|
-#4: xscvuxdsp 00001abb => 42babb89a0000000
|
|
-#5: xscvuxdsp 00000001 => 41f89abce0000000
|
|
-#6: xscvuxdsp 31929394 => 43c8c949c0000000
|
|
-#7: xscvuxdsp a1a2a3a4 => 43e4345480000000
|
|
+#0: xscvsxdsp 0102030405060708 => 4370203040000000
|
|
+#1: xscvsxdsp 090a0b0c0e0d0e0f => 43a2141620000000
|
|
+#2: xscvsxdsp f1f2f3f4f5f6f7f8 => c3ac1a1820000000
|
|
+#3: xscvsxdsp f9fafbfcfefdfeff => c398141000000000
|
|
+
|
|
+#0: xscvuxdsp 0102030405060708 => 4370203040000000
|
|
+#1: xscvuxdsp 090a0b0c0e0d0e0f => 43a2141620000000
|
|
+#2: xscvuxdsp f1f2f3f4f5f6f7f8 => 43ee3e5e80000000
|
|
+#3: xscvuxdsp f9fafbfcfefdfeff => 43ef3f5f80000000
|
|
|
|
|
|
Test VSX load/store dp to sp instructions
|
|
@@ -812,14 +804,13 @@ stxsspx: 41232585a0000000 ==> 49192c2d
|
|
stxsspx: 40514bf5e0000000 ==> 428a5faf
|
|
|
|
|
|
-stxsiwx: 80000001 ==> 80000001
|
|
-stxsiwx: 89abcdef ==> 89abcdef
|
|
-stxsiwx: 00112233 ==> 00112233
|
|
-stxsiwx: 74556677 ==> 74556677
|
|
-stxsiwx: 00001abb ==> 00001abb
|
|
-stxsiwx: 00000001 ==> 00000001
|
|
-stxsiwx: 31929394 ==> 31929394
|
|
-stxsiwx: a1a2a3a4 ==> a1a2a3a4
|
|
+stxsiwx: 3ec00000 ==> 3ec00000
|
|
+stxsiwx: 7f800000 ==> 7f800000
|
|
+stxsiwx: 80000000 ==> 80000000
|
|
+stxsiwx: 7fbfffff ==> 7fbfffff
|
|
+stxsiwx: ffc00000 ==> ffc00000
|
|
+stxsiwx: 49192c2d ==> 49192c2d
|
|
+stxsiwx: 428a5faf ==> 428a5faf
|
|
|
|
|
|
lxsiwax: 80000001 ==> ffffffff80000001
|
|
@@ -832,14 +823,13 @@ lxsiwax: 31929394 ==> 0000000031929394
|
|
lxsiwax: a1a2a3a4 ==> ffffffffa1a2a3a4
|
|
|
|
|
|
-lxsiwzx: 89abcdef ==> 00000000abcdef00
|
|
-lxsiwzx: 00112233 ==> 0000000011223374
|
|
-lxsiwzx: 74556677 ==> 0000000055667700
|
|
-lxsiwzx: 00001abb ==> 00000000001abb00
|
|
-lxsiwzx: 00000001 ==> 0000000000000131
|
|
-lxsiwzx: 31929394 ==> 00000000929394a1
|
|
-lxsiwzx: a1a2a3a4 ==> 00000000a2a3a400
|
|
-lxsiwzx: 00000000 ==> 0000000000000010
|
|
+lxsiwzx: 89abcdef ==> 0000000089abcdef
|
|
+lxsiwzx: 00112233 ==> 0000000000112233
|
|
+lxsiwzx: 74556677 ==> 0000000074556677
|
|
+lxsiwzx: 00001abb ==> 0000000000001abb
|
|
+lxsiwzx: 00000001 ==> 0000000000000001
|
|
+lxsiwzx: 31929394 ==> 0000000031929394
|
|
+lxsiwzx: a1a2a3a4 ==> 00000000a1a2a3a4
|
|
|
|
|
|
lxsspx: 3ec00000 ==> 3fd8000000000000
|
|
Index: none/tests/ppc64/test_isa_2_07_part1.c
|
|
===================================================================
|
|
--- none/tests/ppc64/test_isa_2_07_part1.c.orig
|
|
+++ none/tests/ppc64/test_isa_2_07_part1.c
|
|
@@ -135,6 +135,12 @@ typedef uint64_t HWord_t;
|
|
#define ZERO 0ULL
|
|
#endif /* __powerpc64__ */
|
|
|
|
+#ifdef VGP_ppc64le_linux
|
|
+#define isLE 1
|
|
+#else
|
|
+#define isLE 0
|
|
+#endif
|
|
+
|
|
typedef uint64_t Word_t;
|
|
|
|
enum {
|
|
@@ -1116,7 +1122,10 @@ static void mfvs(const char* name, test_
|
|
|
|
for (i=0; i < NB_VDARGS; i++) {
|
|
r14 = ZERO;
|
|
- vec_inA = (vector unsigned long long){ vdargs[i], 0ULL };
|
|
+ if (isLE)
|
|
+ vec_inA = (vector unsigned long long){ 0ULL, vdargs[i] };
|
|
+ else
|
|
+ vec_inA = (vector unsigned long long){ vdargs[i], 0ULL };
|
|
|
|
(*func)();
|
|
result = r14;
|
|
@@ -1139,6 +1148,8 @@ static void mtvs(const char* name, test_
|
|
|
|
(*func)();
|
|
dst = (unsigned long long *) &vec_out;
|
|
+ if (isLE)
|
|
+ dst++;
|
|
printf("%s: %016llx => %016llx\n", name, vdargs[i], *dst);
|
|
}
|
|
}
|
|
@@ -1154,13 +1165,16 @@ static void mtvs2s(const char* name, tes
|
|
for (i=0; i < NB_VDARGS; i++) {
|
|
// Only the lower half of the vdarg doubleword arg will be used as input by mtvsrwa
|
|
unsigned int * src = (unsigned int *)&vdargs[i];
|
|
- src++;
|
|
+ if (!isLE)
|
|
+ src++;
|
|
r14 = vdargs[i];
|
|
vec_out = (vector unsigned long long){ 0ULL, 0ULL };
|
|
|
|
(*func)();
|
|
// Only doubleword 0 is used in output
|
|
dst = (unsigned long long *) &vec_out;
|
|
+ if (isLE)
|
|
+ dst++;
|
|
printf("%s: %08x => %016llx\n", name, *src, *dst);
|
|
}
|
|
}
|
|
@@ -1222,16 +1236,27 @@ static void test_av_dint_two_args (const
|
|
unsigned int * dst_int;
|
|
int i,j;
|
|
int family = test_flags & PPC_FAMILY;
|
|
- int is_vpkudum;
|
|
+ int is_vpkudum, is_vpmsumd;
|
|
if (strcmp(name, "vpkudum") == 0)
|
|
is_vpkudum = 1;
|
|
else
|
|
is_vpkudum = 0;
|
|
|
|
+ if (strcmp(name, "vpmsumd") == 0)
|
|
+ is_vpmsumd = 1;
|
|
+ else
|
|
+ is_vpmsumd = 0;
|
|
+
|
|
for (i = 0; i < NB_VDARGS; i+=2) {
|
|
- vec_inA = (vector unsigned long long){ vdargs[i], vdargs[i+1] };
|
|
+ if (isLE && family == PPC_ALTIVECQ)
|
|
+ vec_inA = (vector unsigned long long){ vdargs[i+1], vdargs[i] };
|
|
+ else
|
|
+ vec_inA = (vector unsigned long long){ vdargs[i], vdargs[i+1] };
|
|
for (j = 0; j < NB_VDARGS; j+=2) {
|
|
- vec_inB = (vector unsigned long long){ vdargs[j], vdargs[j+1] };
|
|
+ if (isLE && family == PPC_ALTIVECQ)
|
|
+ vec_inB = (vector unsigned long long){ vdargs[j+1], vdargs[j] };
|
|
+ else
|
|
+ vec_inB = (vector unsigned long long){ vdargs[j], vdargs[j+1] };
|
|
vec_out = (vector unsigned long long){ 0,0 };
|
|
|
|
(*func)();
|
|
@@ -1244,12 +1269,32 @@ static void test_av_dint_two_args (const
|
|
printf("Inputs: %08llx %08llx %08llx %08llx\n", vdargs[i] & 0x00000000ffffffffULL,
|
|
vdargs[i+1] & 0x00000000ffffffffULL, vdargs[j] & 0x00000000ffffffffULL,
|
|
vdargs[j+1] & 0x00000000ffffffffULL);
|
|
- printf(" Output: %08x %08x %08x %08x\n", dst_int[0], dst_int[1],
|
|
- dst_int[2], dst_int[3]);
|
|
+ if (isLE)
|
|
+ printf(" Output: %08x %08x %08x %08x\n", dst_int[2], dst_int[3],
|
|
+ dst_int[0], dst_int[1]);
|
|
+ else
|
|
+ printf(" Output: %08x %08x %08x %08x\n", dst_int[0], dst_int[1],
|
|
+ dst_int[2], dst_int[3]);
|
|
+ } else if (is_vpmsumd) {
|
|
+ printf("%016llx @@ %016llx ", vdargs[i], vdargs[j]);
|
|
+ if (isLE)
|
|
+ printf(" ==> %016llx\n", dst[1]);
|
|
+ else
|
|
+ printf(" ==> %016llx\n", dst[0]);
|
|
+ printf("\t%016llx @@ %016llx ", vdargs[i+1], vdargs[j+1]);
|
|
+ if (isLE)
|
|
+ printf(" ==> %016llx\n", dst[0]);
|
|
+ else
|
|
+ printf(" ==> %016llx\n", dst[1]);
|
|
} else if (family == PPC_ALTIVECQ) {
|
|
- printf("%016llx%016llx @@ %016llx%016llx ==> %016llx%016llx\n",
|
|
- vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1],
|
|
- dst[0], dst[1]);
|
|
+ if (isLE)
|
|
+ printf("%016llx%016llx @@ %016llx%016llx ==> %016llx%016llx\n",
|
|
+ vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1],
|
|
+ dst[1], dst[0]);
|
|
+ else
|
|
+ printf("%016llx%016llx @@ %016llx%016llx ==> %016llx%016llx\n",
|
|
+ vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1],
|
|
+ dst[0], dst[1]);
|
|
} else {
|
|
printf("%016llx @@ %016llx ", vdargs[i], vdargs[j]);
|
|
printf(" ==> %016llx\n", dst[0]);
|
|
@@ -1311,9 +1356,15 @@ static void test_av_bcd (const char* nam
|
|
int i, j;
|
|
|
|
for (i = 0; i < NUM_VBCD_VALS; i+=2) {
|
|
- vec_inA = (vector unsigned long long){ vbcd_args[i], vbcd_args[i +1 ] };
|
|
+ if (isLE)
|
|
+ vec_inA = (vector unsigned long long){ vbcd_args[i+1], vbcd_args[i] };
|
|
+ else
|
|
+ vec_inA = (vector unsigned long long){ vbcd_args[i], vbcd_args[i+1] };
|
|
for (j = 0; j < NUM_VBCD_VALS; j+=2) {
|
|
- vec_inB = (vector unsigned long long){ vbcd_args[j], vbcd_args[j +1 ] };
|
|
+ if (isLE)
|
|
+ vec_inB = (vector unsigned long long){ vbcd_args[j+1], vbcd_args[j] };
|
|
+ else
|
|
+ vec_inB = (vector unsigned long long){ vbcd_args[j], vbcd_args[j+1] };
|
|
vec_out = (vector unsigned long long){ 0, 0 };
|
|
|
|
for (PS_bit = 0; PS_bit < 2; PS_bit++) {
|
|
@@ -1323,7 +1374,10 @@ static void test_av_bcd (const char* nam
|
|
printf("%016llx || %016llx @@ %016llx || %016llx",
|
|
vbcd_args[i], vbcd_args[i + 1],
|
|
vbcd_args[j], vbcd_args[j + 1]);
|
|
- printf(" ==> %016llx || %016llx\n", dst[0], dst[1]);
|
|
+ if (isLE)
|
|
+ printf(" ==> %016llx || %016llx\n", dst[1], dst[0]);
|
|
+ else
|
|
+ printf(" ==> %016llx || %016llx\n", dst[0], dst[1]);
|
|
}
|
|
}
|
|
}
|
|
@@ -1349,8 +1403,12 @@ static void test_av_dint_to_int_two_args
|
|
printf("%016llx, %016llx @@ %016llx, %016llx ",
|
|
vdargs_x[i], vdargs_x[i+1],
|
|
vdargs_x[j], vdargs_x[j+1]);
|
|
- printf(" ==> %08x %08x %08x %08x\n", dst_int[0], dst_int[1],
|
|
- dst_int[2], dst_int[3]);
|
|
+ if (isLE)
|
|
+ printf(" ==> %08x %08x %08x %08x\n", dst_int[2], dst_int[3],
|
|
+ dst_int[0], dst_int[1]);
|
|
+ else
|
|
+ printf(" ==> %08x %08x %08x %08x\n", dst_int[0], dst_int[1],
|
|
+ dst_int[2], dst_int[3]);
|
|
}
|
|
}
|
|
}
|
|
@@ -1365,16 +1423,26 @@ static void test_av_wint_two_args_dres (
|
|
int i,j;
|
|
|
|
for (i = 0; i < NB_VWARGS; i+=4) {
|
|
- vec_inA_wd = (vector unsigned int){ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3] };
|
|
+ if (isLE)
|
|
+ vec_inA_wd = (vector unsigned int){ vwargs[i+3], vwargs[i+2], vwargs[i+1], vwargs[i] };
|
|
+ else
|
|
+ vec_inA_wd = (vector unsigned int){ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3] };
|
|
for (j = 0; j < NB_VWARGS; j+=4) {
|
|
- vec_inB_wd = (vector unsigned int){ vwargs[j], vwargs[j+1], vwargs[j+2], vwargs[j+3] };
|
|
+ if (isLE)
|
|
+ vec_inB_wd = (vector unsigned int){ vwargs[j+3], vwargs[j+2], vwargs[j+1], vwargs[j] };
|
|
+ else
|
|
+ vec_inB_wd = (vector unsigned int){ vwargs[j], vwargs[j+1], vwargs[j+2], vwargs[j+3] };
|
|
vec_out = (vector unsigned long long){ 0, 0 };
|
|
|
|
(*func)();
|
|
dst = (unsigned long long *)&vec_out;
|
|
printf("%s: ", name);
|
|
- printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
|
|
- vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[0], dst[1]);
|
|
+ if (isLE)
|
|
+ printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
|
|
+ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[1], dst[0]);
|
|
+ else
|
|
+ printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
|
|
+ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[0], dst[1]);
|
|
}
|
|
}
|
|
}
|
|
@@ -1387,14 +1455,21 @@ static void test_av_wint_one_arg_dres (c
|
|
unsigned long long * dst;
|
|
int i;
|
|
for (i = 0; i < NB_VWARGS; i+=4) {
|
|
- vec_inB_wd = (vector unsigned int){ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3] };
|
|
+ if (isLE)
|
|
+ vec_inB_wd = (vector unsigned int){ vwargs[i+3], vwargs[i+2], vwargs[i+1], vwargs[i] };
|
|
+ else
|
|
+ vec_inB_wd = (vector unsigned int){ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3] };
|
|
vec_out = (vector unsigned long long){ 0, 0 };
|
|
|
|
(*func)();
|
|
dst = (unsigned long long *)&vec_out;
|
|
printf("%s: ", name);
|
|
- printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
|
|
- vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[0], dst[1]);
|
|
+ if (isLE)
|
|
+ printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
|
|
+ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[1], dst[0]);
|
|
+ else
|
|
+ printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
|
|
+ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[0], dst[1]);
|
|
}
|
|
}
|
|
|
|
@@ -1556,28 +1631,52 @@ static void test_av_dint_three_args (con
|
|
0xf000000000000000ULL, 0xf000000000000001ULL
|
|
};
|
|
for (i = 0; i < NB_VDARGS; i+=2) {
|
|
- vec_inA = (vector unsigned long long){ vdargs[i], vdargs[i+1] };
|
|
+ if (isLE)
|
|
+ vec_inA = (vector unsigned long long){ vdargs[i+1], vdargs[i] };
|
|
+ else
|
|
+ vec_inA = (vector unsigned long long){ vdargs[i], vdargs[i+1] };
|
|
for (j = 0; j < NB_VDARGS; j+=2) {
|
|
- vec_inB = (vector unsigned long long){ vdargs[j], vdargs[j+1] };
|
|
+ if (isLE)
|
|
+ vec_inB = (vector unsigned long long){ vdargs[j+1], vdargs[j] };
|
|
+ else
|
|
+ vec_inB = (vector unsigned long long){ vdargs[j], vdargs[j+1] };
|
|
for (k = 0; k < 4; k+=2) {
|
|
- if (family == PPC_ALTIVECQ)
|
|
- vec_inC = (vector unsigned long long){ cin_vals[k], cin_vals[k+1] };
|
|
- else
|
|
- vec_inC = (vector unsigned long long){ vdargs[k], vdargs[k+1] };
|
|
+ if (family == PPC_ALTIVECQ) {
|
|
+ if (isLE)
|
|
+ vec_inC = (vector unsigned long long){ cin_vals[k+1], cin_vals[k] };
|
|
+ else
|
|
+ vec_inC = (vector unsigned long long){ cin_vals[k], cin_vals[k+1] };
|
|
+ } else {
|
|
+ if (isLE)
|
|
+ vec_inC = (vector unsigned long long){ vdargs[k+1], vdargs[k] };
|
|
+ else
|
|
+ vec_inC = (vector unsigned long long){ vdargs[k], vdargs[k+1] };
|
|
+ }
|
|
vec_out = (vector unsigned long long){ 0,0 };
|
|
|
|
(*func)();
|
|
dst = (unsigned long long*)&vec_out;
|
|
printf("%s: ", name);
|
|
if (family == PPC_ALTIVECQ) {
|
|
- printf("%016llx%016llx @@ %016llx%016llx @@ %llx ==> %016llx%016llx\n",
|
|
- vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1], cin_vals[k+1],
|
|
- dst[0], dst[1]);
|
|
+ if (isLE)
|
|
+ printf("%016llx%016llx @@ %016llx%016llx @@ %llx ==> %016llx%016llx\n",
|
|
+ vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1], cin_vals[k+1],
|
|
+ dst[1], dst[0]);
|
|
+ else
|
|
+ printf("%016llx%016llx @@ %016llx%016llx @@ %llx ==> %016llx%016llx\n",
|
|
+ vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1], cin_vals[k+1],
|
|
+ dst[0], dst[1]);
|
|
} else {
|
|
printf("%016llx @@ %016llx @@ %016llx ", vdargs[i], vdargs[j], vdargs[k]);
|
|
- printf(" ==> %016llx\n", dst[0]);
|
|
+ if (isLE)
|
|
+ printf(" ==> %016llx\n", dst[1]);
|
|
+ else
|
|
+ printf(" ==> %016llx\n", dst[0]);
|
|
printf("\t%016llx @@ %016llx @@ %016llx ", vdargs[i+1], vdargs[j+1], vdargs[k+1]);
|
|
- printf(" ==> %016llx\n", dst[1]);
|
|
+ if (isLE)
|
|
+ printf(" ==> %016llx\n", dst[0]);
|
|
+ else
|
|
+ printf(" ==> %016llx\n", dst[1]);
|
|
}
|
|
}
|
|
}
|
|
Index: none/tests/ppc64/Makefile.am
|
|
===================================================================
|
|
--- none/tests/ppc64/Makefile.am.orig
|
|
+++ none/tests/ppc64/Makefile.am
|
|
@@ -4,20 +4,20 @@ include $(top_srcdir)/Makefile.tool-test
|
|
dist_noinst_SCRIPTS = filter_stderr
|
|
|
|
EXTRA_DIST = \
|
|
- jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest \
|
|
- jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest \
|
|
- jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan \
|
|
+ jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest jm-int.stdout.exp-LE \
|
|
+ jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-LE jm-fp.stdout.exp-LE2 jm-fp.stdout.exp-BE2 \
|
|
+ jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan jm-vmx.stdout.exp-LE \
|
|
jm-vmx.vgtest \
|
|
jm-misc.stderr.exp jm-misc.stdout.exp jm-misc.vgtest \
|
|
lsw.stderr.exp lsw.stdout.exp lsw.vgtest \
|
|
- std_reg_imm.vgtest std_reg_imm.stderr.exp std_reg_imm.stdout.exp \
|
|
- round.stderr.exp round.stdout.exp round.vgtest \
|
|
+ std_reg_imm.vgtest std_reg_imm.stderr.exp std_reg_imm.stdout.exp std_reg_imm.stdout.exp-LE \
|
|
+ round.stderr.exp round.stdout.exp round.vgtest round.stdout.exp-RM-fix \
|
|
twi_tdi.stderr.exp twi_tdi.stdout.exp twi_tdi.vgtest \
|
|
tw_td.stderr.exp tw_td.stdout.exp tw_td.vgtest \
|
|
opcodes.h \
|
|
power6_bcmp.stderr.exp power6_bcmp.stdout.exp power6_bcmp.vgtest \
|
|
power6_mf_gpr.stderr.exp power6_mf_gpr.stdout.exp power6_mf_gpr.vgtest \
|
|
- test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest \
|
|
+ test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest test_isa_2_06_part1.stdout.exp-LE \
|
|
test_isa_2_06_part2.stderr.exp test_isa_2_06_part2.stdout.exp test_isa_2_06_part2.vgtest \
|
|
test_isa_2_06_part3.stderr.exp test_isa_2_06_part3.stdout.exp test_isa_2_06_part3.vgtest \
|
|
test_dfp1.stderr.exp test_dfp1.stdout.exp test_dfp1.vgtest \
|
|
@@ -83,33 +83,45 @@ test_isa_2_06_part1_CFLAGS = $(AM_CFLAGS
|
|
test_isa_2_06_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
|
|
@FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
|
|
|
|
-test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(VSX_FLAG) \
|
|
+test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
|
|
@FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
|
|
|
|
jm_insns_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames -maltivec \
|
|
@FLAG_M64@ $(ALTIVEC_FLAG)
|
|
|
|
-test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
|
|
+test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
|
|
@FLAG_M64@ $(BUILD_FLAGS_DFP)
|
|
|
|
-test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
|
|
+test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
|
|
@FLAG_M64@ $(BUILD_FLAGS_DFP)
|
|
-test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
|
|
+test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
|
|
@FLAG_M64@ $(BUILD_FLAGS_DFP)
|
|
|
|
-test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
|
|
+test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
|
|
@FLAG_M64@ $(BUILD_FLAGS_DFP)
|
|
|
|
-test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
|
|
+test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
|
|
@FLAG_M64@ $(BUILD_FLAGS_DFP)
|
|
|
|
-test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
|
|
+test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
|
|
@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
|
|
|
|
-test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
|
|
+test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
|
|
@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
|
|
|
|
-test_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
|
|
+test_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
|
|
@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
|
|
-test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
|
|
+test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
|
|
@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
|
|
+
|
|
+test_isa_2_06_part3_LDADD = -lm
|
|
+test_dfp1_LDADD = -lm
|
|
+test_dfp2_LDADD = -lm
|
|
+test_dfp3_LDADD = -lm
|
|
+test_dfp4_LDADD = -lm
|
|
+test_dfp5_LDADD = -lm
|
|
+test_isa_2_07_part1_LDADD = -lm
|
|
+test_isa_2_07_part2_LDADD = -lm
|
|
+test_tm_LDADD = -lm
|
|
+test_touch_tm_LDADD = -lm
|
|
+
|
|
Index: none/tests/amd64/xadd.c
|
|
===================================================================
|
|
--- none/tests/amd64/xadd.c.orig
|
|
+++ none/tests/amd64/xadd.c
|
|
@@ -9,7 +9,7 @@
|
|
#undef PLAT_x86_linux
|
|
#undef PLAT_amd64_linux
|
|
#undef PLAT_ppc32_linux
|
|
-#undef PLAT_ppc64_linux
|
|
+#undef PLAT_ppc64be_linux
|
|
|
|
#if defined(__i386__)
|
|
# define PLAT_x86_linux 1
|
|
Index: none/tests/ppc32/Makefile.am
|
|
===================================================================
|
|
--- none/tests/ppc32/Makefile.am.orig
|
|
+++ none/tests/ppc32/Makefile.am
|
|
@@ -11,13 +11,13 @@ EXTRA_DIST = \
|
|
ldstrev.stderr.exp ldstrev.stdout.exp ldstrev.vgtest \
|
|
lsw.stderr.exp lsw.stdout.exp lsw.vgtest \
|
|
jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest \
|
|
- jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest \
|
|
+ jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-BE2 \
|
|
jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan \
|
|
jm-vmx.vgtest \
|
|
jm-misc.stderr.exp jm-misc.stdout.exp jm-misc.vgtest \
|
|
mftocrf.stderr.exp mftocrf.stdout.exp mftocrf.vgtest \
|
|
mcrfs.stderr.exp mcrfs.stdout.exp mcrfs.vgtest \
|
|
- round.stderr.exp round.stdout.exp round.vgtest \
|
|
+ round.stderr.exp round.stdout.exp round.vgtest round.stdout.exp-RM-fix\
|
|
test_fx.stderr.exp test_fx.stdout.exp test_fx.stdout.exp_Minus_nan \
|
|
test_fx.vgtest \
|
|
test_gx.stderr.exp test_gx.stdout.exp test_gx.stdout.exp_Minus_nan \
|
|
@@ -109,29 +109,41 @@ test_isa_2_06_part1_CFLAGS = $(AM_CFLAGS
|
|
test_isa_2_06_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
|
|
@FLAG_M32@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
|
|
|
|
-test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(VSX_FLAG) \
|
|
+test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
|
|
@FLAG_M32@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
|
|
|
|
-test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
|
|
+test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
|
|
@FLAG_M32@ $(BUILD_FLAGS_DFP)
|
|
-test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
|
|
+test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
|
|
@FLAG_M32@ $(BUILD_FLAGS_DFP)
|
|
-test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
|
|
+test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
|
|
@FLAG_M32@ $(BUILD_FLAGS_DFP)
|
|
|
|
-test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
|
|
+test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
|
|
@FLAG_M32@ $(BUILD_FLAGS_DFP)
|
|
|
|
-test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
|
|
+test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
|
|
@FLAG_M32@ $(BUILD_FLAGS_DFP)
|
|
|
|
-test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
|
|
+test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
|
|
@FLAG_M32@ $(BUILD_FLAGS_ISA_2_07)
|
|
|
|
-test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
|
|
+test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
|
|
@FLAG_M32@ $(BUILD_FLAGS_ISA_2_07)
|
|
|
|
-test_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
|
|
+test_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
|
|
@FLAG_M32@ $(BUILD_FLAGS_ISA_2_07)
|
|
-test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
|
|
+test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
|
|
@FLAG_M32@ $(BUILD_FLAGS_ISA_2_07)
|
|
+
|
|
+test_isa_2_06_part3_LDADD = -lm
|
|
+test_dfp1_LDADD = -lm
|
|
+test_dfp2_LDADD = -lm
|
|
+test_dfp3_LDADD = -lm
|
|
+test_dfp4_LDADD = -lm
|
|
+test_dfp5_LDADD = -lm
|
|
+test_isa_2_07_part1_LDADD = -lm
|
|
+test_isa_2_07_part2_LDADD = -lm
|
|
+test_tm_LDADD = -lm
|
|
+test_touch_tm_LDADD = -lm
|
|
+
|
|
Index: none/tests/ppc32/jm-vmx.stdout.exp
|
|
===================================================================
|
|
--- none/tests/ppc32/jm-vmx.stdout.exp.orig
|
|
+++ none/tests/ppc32/jm-vmx.stdout.exp
|
|
@@ -1407,43 +1407,43 @@ Altivec integer special insns:
|
|
vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 14
|
|
vsldoi: => fefff1f2 f3f4f5f6 f7f8f9fa fbfcfefd] (00000000)
|
|
|
|
- lvsl -1, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
|
|
- lvsl 0, 0 => 00010203 04050607 08090a0b 0c0d0e0f (00000000)
|
|
- lvsl 1, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
|
|
- lvsl 2, 0 => 02030405 06070809 0a0b0c0d 0e0f1011 (00000000)
|
|
- lvsl 3, 0 => 03040506 0708090a 0b0c0d0e 0f101112 (00000000)
|
|
- lvsl 4, 0 => 04050607 08090a0b 0c0d0e0f 10111213 (00000000)
|
|
- lvsl 5, 0 => 05060708 090a0b0c 0d0e0f10 11121314 (00000000)
|
|
- lvsl 6, 0 => 06070809 0a0b0c0d 0e0f1011 12131415 (00000000)
|
|
- lvsl 7, 0 => 0708090a 0b0c0d0e 0f101112 13141516 (00000000)
|
|
- lvsl 8, 0 => 08090a0b 0c0d0e0f 10111213 14151617 (00000000)
|
|
- lvsl 9, 0 => 090a0b0c 0d0e0f10 11121314 15161718 (00000000)
|
|
- lvsl 10, 0 => 0a0b0c0d 0e0f1011 12131415 16171819 (00000000)
|
|
- lvsl 11, 0 => 0b0c0d0e 0f101112 13141516 1718191a (00000000)
|
|
- lvsl 12, 0 => 0c0d0e0f 10111213 14151617 18191a1b (00000000)
|
|
- lvsl 13, 0 => 0d0e0f10 11121314 15161718 191a1b1c (00000000)
|
|
- lvsl 14, 0 => 0e0f1011 12131415 16171819 1a1b1c1d (00000000)
|
|
- lvsl 15, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
|
|
- lvsl 16, 0 => 00010203 04050607 08090a0b 0c0d0e0f (00000000)
|
|
-
|
|
- lvsr -1, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
|
|
- lvsr 0, 0 => 10111213 14151617 18191a1b 1c1d1e1f (00000000)
|
|
- lvsr 1, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
|
|
- lvsr 2, 0 => 0e0f1011 12131415 16171819 1a1b1c1d (00000000)
|
|
- lvsr 3, 0 => 0d0e0f10 11121314 15161718 191a1b1c (00000000)
|
|
- lvsr 4, 0 => 0c0d0e0f 10111213 14151617 18191a1b (00000000)
|
|
- lvsr 5, 0 => 0b0c0d0e 0f101112 13141516 1718191a (00000000)
|
|
- lvsr 6, 0 => 0a0b0c0d 0e0f1011 12131415 16171819 (00000000)
|
|
- lvsr 7, 0 => 090a0b0c 0d0e0f10 11121314 15161718 (00000000)
|
|
- lvsr 8, 0 => 08090a0b 0c0d0e0f 10111213 14151617 (00000000)
|
|
- lvsr 9, 0 => 0708090a 0b0c0d0e 0f101112 13141516 (00000000)
|
|
- lvsr 10, 0 => 06070809 0a0b0c0d 0e0f1011 12131415 (00000000)
|
|
- lvsr 11, 0 => 05060708 090a0b0c 0d0e0f10 11121314 (00000000)
|
|
- lvsr 12, 0 => 04050607 08090a0b 0c0d0e0f 10111213 (00000000)
|
|
- lvsr 13, 0 => 03040506 0708090a 0b0c0d0e 0f101112 (00000000)
|
|
- lvsr 14, 0 => 02030405 06070809 0a0b0c0d 0e0f1011 (00000000)
|
|
- lvsr 15, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
|
|
- lvsr 16, 0 => 10111213 14151617 18191a1b 1c1d1e1f (00000000)
|
|
+ lvsl 3, 0 => 0x030405060708090a 0x0b0c0d0e0f101112 (00000000)
|
|
+ lvsl 4, 0 => 0x0405060708090a0b 0x0c0d0e0f10111213 (00000000)
|
|
+ lvsl 5, 0 => 0x05060708090a0b0c 0x0d0e0f1011121314 (00000000)
|
|
+ lvsl 6, 0 => 0x060708090a0b0c0d 0x0e0f101112131415 (00000000)
|
|
+ lvsl 7, 0 => 0x0708090a0b0c0d0e 0x0f10111213141516 (00000000)
|
|
+ lvsl 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000)
|
|
+ lvsl 9, 0 => 0x090a0b0c0d0e0f10 0x1112131415161718 (00000000)
|
|
+ lvsl a, 0 => 0x0a0b0c0d0e0f1011 0x1213141516171819 (00000000)
|
|
+ lvsl b, 0 => 0x0b0c0d0e0f101112 0x131415161718191a (00000000)
|
|
+ lvsl c, 0 => 0x0c0d0e0f10111213 0x1415161718191a1b (00000000)
|
|
+ lvsl d, 0 => 0x0d0e0f1011121314 0x15161718191a1b1c (00000000)
|
|
+ lvsl e, 0 => 0x0e0f101112131415 0x161718191a1b1c1d (00000000)
|
|
+ lvsl f, 0 => 0x0f10111213141516 0x1718191a1b1c1d1e (00000000)
|
|
+ lvsl 0, 0 => 0x0001020304050607 0x08090a0b0c0d0e0f (00000000)
|
|
+ lvsl 1, 0 => 0x0102030405060708 0x090a0b0c0d0e0f10 (00000000)
|
|
+ lvsl 2, 0 => 0x0203040506070809 0x0a0b0c0d0e0f1011 (00000000)
|
|
+ lvsl 3, 0 => 0x030405060708090a 0x0b0c0d0e0f101112 (00000000)
|
|
+ lvsl 4, 0 => 0x0405060708090a0b 0x0c0d0e0f10111213 (00000000)
|
|
+
|
|
+ lvsr 3, 0 => 0x0d0e0f1011121314 0x15161718191a1b1c (00000000)
|
|
+ lvsr 4, 0 => 0x0c0d0e0f10111213 0x1415161718191a1b (00000000)
|
|
+ lvsr 5, 0 => 0x0b0c0d0e0f101112 0x131415161718191a (00000000)
|
|
+ lvsr 6, 0 => 0x0a0b0c0d0e0f1011 0x1213141516171819 (00000000)
|
|
+ lvsr 7, 0 => 0x090a0b0c0d0e0f10 0x1112131415161718 (00000000)
|
|
+ lvsr 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000)
|
|
+ lvsr 9, 0 => 0x0708090a0b0c0d0e 0x0f10111213141516 (00000000)
|
|
+ lvsr a, 0 => 0x060708090a0b0c0d 0x0e0f101112131415 (00000000)
|
|
+ lvsr b, 0 => 0x05060708090a0b0c 0x0d0e0f1011121314 (00000000)
|
|
+ lvsr c, 0 => 0x0405060708090a0b 0x0c0d0e0f10111213 (00000000)
|
|
+ lvsr d, 0 => 0x030405060708090a 0x0b0c0d0e0f101112 (00000000)
|
|
+ lvsr e, 0 => 0x0203040506070809 0x0a0b0c0d0e0f1011 (00000000)
|
|
+ lvsr f, 0 => 0x0102030405060708 0x090a0b0c0d0e0f10 (00000000)
|
|
+ lvsr 0, 0 => 0x1011121314151617 0x18191a1b1c1d1e1f (00000000)
|
|
+ lvsr 1, 0 => 0x0f10111213141516 0x1718191a1b1c1d1e (00000000)
|
|
+ lvsr 2, 0 => 0x0e0f101112131415 0x161718191a1b1c1d (00000000)
|
|
+ lvsr 3, 0 => 0x0d0e0f1011121314 0x15161718191a1b1c (00000000)
|
|
+ lvsr 4, 0 => 0x0c0d0e0f10111213 0x1415161718191a1b (00000000)
|
|
|
|
Altivec load insns with two register args:
|
|
lvebx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01000000 00000000 00000000 00000000 (00000000)
|
|
@@ -3451,18 +3451,18 @@ Altivec float special insns:
|
|
vcfux: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000)
|
|
vcfux: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000)
|
|
vcfux: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000)
|
|
- vcfux: ffffffff ( nan), 0 => 4f800000 ( 4.294967e+09) (00000000)
|
|
- vcfux: ffffffff ( nan), 9 => 4b000000 ( 8.388608e+06) (00000000)
|
|
- vcfux: ffffffff ( nan), 18 => 46800000 ( 1.638400e+04) (00000000)
|
|
- vcfux: ffffffff ( nan), 27 => 42000000 ( 3.200000e+01) (00000000)
|
|
+ vcfux: ffffffff ( -nan), 0 => 4f800000 ( 4.294967e+09) (00000000)
|
|
+ vcfux: ffffffff ( -nan), 9 => 4b000000 ( 8.388608e+06) (00000000)
|
|
+ vcfux: ffffffff ( -nan), 18 => 46800000 ( 1.638400e+04) (00000000)
|
|
+ vcfux: ffffffff ( -nan), 27 => 42000000 ( 3.200000e+01) (00000000)
|
|
vcfux: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000)
|
|
vcfux: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000)
|
|
vcfux: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000)
|
|
vcfux: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000)
|
|
- vcfux: ffbfffff ( nan), 0 => 4f7fc000 ( 4.290773e+09) (00000000)
|
|
- vcfux: ffbfffff ( nan), 9 => 4affc000 ( 8.380416e+06) (00000000)
|
|
- vcfux: ffbfffff ( nan), 18 => 467fc000 ( 1.636800e+04) (00000000)
|
|
- vcfux: ffbfffff ( nan), 27 => 41ffc000 ( 3.196875e+01) (00000000)
|
|
+ vcfux: ffbfffff ( -nan), 0 => 4f7fc000 ( 4.290773e+09) (00000000)
|
|
+ vcfux: ffbfffff ( -nan), 9 => 4affc000 ( 8.380416e+06) (00000000)
|
|
+ vcfux: ffbfffff ( -nan), 18 => 467fc000 ( 1.636800e+04) (00000000)
|
|
+ vcfux: ffbfffff ( -nan), 27 => 41ffc000 ( 3.196875e+01) (00000000)
|
|
|
|
vcfsx: 02bfffff ( 2.821186e-37), 0 => 4c300000 ( 4.613734e+07) (00000000)
|
|
vcfsx: 02bfffff ( 2.821186e-37), 9 => 47b00000 ( 9.011200e+04) (00000000)
|
|
@@ -3500,27 +3500,27 @@ Altivec float special insns:
|
|
vcfsx: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000)
|
|
vcfsx: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000)
|
|
vcfsx: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000)
|
|
- vcfsx: ffffffff ( nan), 0 => bf800000 (-1.000000e+00) (00000000)
|
|
- vcfsx: ffffffff ( nan), 9 => bb000000 (-1.953125e-03) (00000000)
|
|
- vcfsx: ffffffff ( nan), 18 => b6800000 (-3.814697e-06) (00000000)
|
|
- vcfsx: ffffffff ( nan), 27 => b2000000 (-7.450581e-09) (00000000)
|
|
+ vcfsx: ffffffff ( -nan), 0 => bf800000 (-1.000000e+00) (00000000)
|
|
+ vcfsx: ffffffff ( -nan), 9 => bb000000 (-1.953125e-03) (00000000)
|
|
+ vcfsx: ffffffff ( -nan), 18 => b6800000 (-3.814697e-06) (00000000)
|
|
+ vcfsx: ffffffff ( -nan), 27 => b2000000 (-7.450581e-09) (00000000)
|
|
vcfsx: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000)
|
|
vcfsx: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000)
|
|
vcfsx: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000)
|
|
vcfsx: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000)
|
|
- vcfsx: ffbfffff ( nan), 0 => ca800002 (-4.194305e+06) (00000000)
|
|
- vcfsx: ffbfffff ( nan), 9 => c6000002 (-8.192002e+03) (00000000)
|
|
- vcfsx: ffbfffff ( nan), 18 => c1800002 (-1.600000e+01) (00000000)
|
|
- vcfsx: ffbfffff ( nan), 27 => bd000002 (-3.125001e-02) (00000000)
|
|
+ vcfsx: ffbfffff ( -nan), 0 => ca800002 (-4.194305e+06) (00000000)
|
|
+ vcfsx: ffbfffff ( -nan), 9 => c6000002 (-8.192002e+03) (00000000)
|
|
+ vcfsx: ffbfffff ( -nan), 18 => c1800002 (-1.600000e+01) (00000000)
|
|
+ vcfsx: ffbfffff ( -nan), 27 => bd000002 (-3.125001e-02) (00000000)
|
|
|
|
vctuxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 02bfffff ( 2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 02bfffff ( 2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctuxs: 513fffff ( 5.153960e+10), 0 => ffffffff ( nan) (00000000)
|
|
- vctuxs: 513fffff ( 5.153960e+10), 9 => ffffffff ( nan) (00000000)
|
|
- vctuxs: 513fffff ( 5.153960e+10), 18 => ffffffff ( nan) (00000000)
|
|
- vctuxs: 513fffff ( 5.153960e+10), 27 => ffffffff ( nan) (00000000)
|
|
+ vctuxs: 513fffff ( 5.153960e+10), 0 => ffffffff ( -nan) (00000000)
|
|
+ vctuxs: 513fffff ( 5.153960e+10), 9 => ffffffff ( -nan) (00000000)
|
|
+ vctuxs: 513fffff ( 5.153960e+10), 18 => ffffffff ( -nan) (00000000)
|
|
+ vctuxs: 513fffff ( 5.153960e+10), 27 => ffffffff ( -nan) (00000000)
|
|
vctuxs: 82bfffff (-2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 82bfffff (-2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 82bfffff (-2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
@@ -3537,10 +3537,10 @@ Altivec float special insns:
|
|
vctuxs: 80000000 (-0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 80000000 (-0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 80000000 (-0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctuxs: 7f800000 ( inf), 0 => ffffffff ( nan) (00000000)
|
|
- vctuxs: 7f800000 ( inf), 9 => ffffffff ( nan) (00000000)
|
|
- vctuxs: 7f800000 ( inf), 18 => ffffffff ( nan) (00000000)
|
|
- vctuxs: 7f800000 ( inf), 27 => ffffffff ( nan) (00000000)
|
|
+ vctuxs: 7f800000 ( inf), 0 => ffffffff ( -nan) (00000000)
|
|
+ vctuxs: 7f800000 ( inf), 9 => ffffffff ( -nan) (00000000)
|
|
+ vctuxs: 7f800000 ( inf), 18 => ffffffff ( -nan) (00000000)
|
|
+ vctuxs: 7f800000 ( inf), 27 => ffffffff ( -nan) (00000000)
|
|
vctuxs: ff800000 ( -inf), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: ff800000 ( -inf), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: ff800000 ( -inf), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
@@ -3549,18 +3549,18 @@ Altivec float special insns:
|
|
vctuxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctuxs: ffffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctuxs: ffffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctuxs: ffffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctuxs: ffffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctuxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctuxs: ffbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctuxs: ffbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctuxs: ffbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctuxs: ffbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctuxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
|
|
vctsxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctsxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
@@ -3598,17 +3598,17 @@ Altivec float special insns:
|
|
vctsxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctsxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctsxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctsxs: ffffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctsxs: ffffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctsxs: ffffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctsxs: ffffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctsxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctsxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctsxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
vctsxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctsxs: ffbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctsxs: ffbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctsxs: ffbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
- vctsxs: ffbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
|
+ vctsxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
|
|
|
All done. Tested 165 different instructions
|
|
Index: none/tests/ppc32/round.stdout.exp-RM-fix
|
|
===================================================================
|
|
--- /dev/null
|
|
+++ none/tests/ppc32/round.stdout.exp-RM-fix
|
|
@@ -0,0 +1,2335 @@
|
|
+-------------------------- test denormalized convert --------------------------
|
|
+near:PASSED:(double)(0x1p-148 ) = 0x1.cp-149
|
|
+near:PASSED:(double)(0x1p-149 ) = 0x1.4p-149
|
|
+zero:PASSED:(double)(0x1p-149 ) = 0x1.cp-149
|
|
+zero:PASSED:(double)(0x1p-149 ) = 0x1.4p-149
|
|
++inf:PASSED:(double)(0x1p-148 ) = 0x1.cp-149
|
|
++inf:PASSED:(double)(0x1p-148 ) = 0x1.4p-149
|
|
+-inf:PASSED:(double)(0x1p-149 ) = 0x1.cp-149
|
|
+-inf:PASSED:(double)(0x1p-149 ) = 0x1.4p-149
|
|
+-------------------------- test normalized convert --------------------------
|
|
+near:PASSED:(double)(0x1.000004p-126 ) = 0x1.0000038p-126
|
|
+near:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000028p-126
|
|
+zero:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000038p-126
|
|
+zero:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000028p-126
|
|
++inf:PASSED:(double)(0x1.000004p-126 ) = 0x1.0000038p-126
|
|
++inf:PASSED:(double)(0x1.000004p-126 ) = 0x1.0000028p-126
|
|
+-inf:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000038p-126
|
|
+-inf:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000028p-126
|
|
+-------------------------- test (float)int convert --------------------------
|
|
+near:PASSED:(float)( int) 67047421 = 67047420.0
|
|
+near:PASSED:(float)( int) 67047423 = 67047424.0
|
|
+zero:PASSED:(float)( int) 67047421 = 67047420.0
|
|
+zero:PASSED:(float)( int) 67047423 = 67047420.0
|
|
++inf:PASSED:(float)( int) 67047421 = 67047424.0
|
|
++inf:PASSED:(float)( int) 67047423 = 67047424.0
|
|
+-inf:PASSED:(float)( int) 67047421 = 67047420.0
|
|
+-inf:PASSED:(float)( int) 67047423 = 67047420.0
|
|
+near:PASSED:(float)( int)-67047421 = -67047420.0
|
|
+near:PASSED:(float)( int)-67047423 = -67047424.0
|
|
+zero:PASSED:(float)( int)-67047421 = -67047420.0
|
|
+zero:PASSED:(float)( int)-67047423 = -67047420.0
|
|
++inf:PASSED:(float)( int)-67047421 = -67047420.0
|
|
++inf:PASSED:(float)( int)-67047423 = -67047420.0
|
|
+-inf:PASSED:(float)( int)-67047421 = -67047424.0
|
|
+-inf:PASSED:(float)( int)-67047423 = -67047424.0
|
|
+-------------------------- test (float)int convert --------------------------
|
|
+near:PASSED:(float)( int) 67047421 = 67047420.0
|
|
+near:PASSED:(float)( int) 67047423 = 67047424.0
|
|
+zero:PASSED:(float)( int) 67047421 = 67047420.0
|
|
+zero:PASSED:(float)( int) 67047423 = 67047420.0
|
|
++inf:PASSED:(float)( int) 67047421 = 67047424.0
|
|
++inf:PASSED:(float)( int) 67047423 = 67047424.0
|
|
+-inf:PASSED:(float)( int) 67047421 = 67047420.0
|
|
+-inf:PASSED:(float)( int) 67047423 = 67047420.0
|
|
+near:PASSED:(float)( int)-67047421 = -67047420.0
|
|
+near:PASSED:(float)( int)-67047423 = -67047424.0
|
|
+zero:PASSED:(float)( int)-67047421 = -67047420.0
|
|
+zero:PASSED:(float)( int)-67047423 = -67047420.0
|
|
++inf:PASSED:(float)( int)-67047421 = -67047420.0
|
|
++inf:PASSED:(float)( int)-67047423 = -67047420.0
|
|
+-inf:PASSED:(float)( int)-67047421 = -67047424.0
|
|
+-inf:PASSED:(float)( int)-67047423 = -67047424.0
|
|
+-------------------------- test rounding of float operators without guard bits --------------------------
|
|
+near:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-149
|
|
+near:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-148
|
|
+near:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-149
|
|
+near:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-148
|
|
+zero:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-149
|
|
+zero:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-149
|
|
+zero:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-149
|
|
+zero:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-149
|
|
++inf:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-149
|
|
++inf:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-149
|
|
++inf:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-148
|
|
++inf:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-148
|
|
+-inf:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-148
|
|
+-inf:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-148
|
|
+-inf:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-149
|
|
+-inf:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-149
|
|
+near:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-149
|
|
+near:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-148
|
|
+near:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-149
|
|
+near:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-148
|
|
+zero:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-149
|
|
+zero:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-149
|
|
+zero:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-149
|
|
+zero:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-149
|
|
++inf:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-149
|
|
++inf:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-149
|
|
++inf:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-148
|
|
++inf:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-148
|
|
+-inf:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-148
|
|
+-inf:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-148
|
|
+-inf:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-149
|
|
+-inf:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-149
|
|
+near:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-149
|
|
+near:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-148
|
|
+near:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-149
|
|
+near:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-148
|
|
+zero:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-149
|
|
+zero:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-149
|
|
+zero:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-149
|
|
+zero:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-149
|
|
++inf:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-149
|
|
++inf:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-149
|
|
++inf:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-148
|
|
++inf:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-148
|
|
+-inf:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-148
|
|
+-inf:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-148
|
|
+-inf:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-149
|
|
+-inf:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-149
|
|
+near:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-149
|
|
+near:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-148
|
|
+near:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-149
|
|
+near:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-148
|
|
+zero:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-149
|
|
+zero:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-149
|
|
+zero:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-149
|
|
+zero:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-149
|
|
++inf:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-149
|
|
++inf:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-149
|
|
++inf:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-148
|
|
++inf:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-148
|
|
+-inf:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-148
|
|
+-inf:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-148
|
|
+-inf:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-149
|
|
+-inf:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-149
|
|
+-------------------------- test rounding of float operators with guard bits --------------------------
|
|
+near:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.2p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.2p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.2p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.2p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.200002p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.200002p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.200002p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200002p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200002p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200002p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200004p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200004p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200004p+0
|
|
+near:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200004p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.2p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.2p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.2p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.2p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.200002p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.200002p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.200002p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200002p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200002p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200002p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200004p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200004p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200004p+0
|
|
+near:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200004p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.2p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.2p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.2p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.2p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.2p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.2p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.2p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200002p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200002p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200002p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200002p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200002p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200002p+0
|
|
+zero:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200002p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.2p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.2p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.2p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.2p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.2p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.2p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.2p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200002p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200002p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200002p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200002p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200002p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200002p+0
|
|
+zero:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200002p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.2p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.2p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.2p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.2p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.2p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.2p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.2p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200002p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200002p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200002p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200002p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200002p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200002p+0
|
|
++inf:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200002p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.200002p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.200002p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.200002p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.200002p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.200002p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.200002p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.200002p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200004p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200004p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200004p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200004p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200004p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200004p+0
|
|
++inf:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200004p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.200002p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.200002p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.200002p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.200002p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.200002p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.200002p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.200002p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200004p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200004p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200004p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200004p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200004p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200004p+0
|
|
+-inf:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200004p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200002p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200002p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200002p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200002p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200002p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200002p+0
|
|
+-inf:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200002p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1p-3 ) = -0x1.000004p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.000002p-3) = -0x1.000004p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.000004p-3) = -0x1.000004p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.000006p-3) = -0x1.000004p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.000008p-3) = -0x1.000004p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.00000ap-3) = -0x1.000002p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.00000cp-3) = -0x1.000002p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.00000ep-3) = -0x1.000002p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.00001p-3) = -0x1.000002p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.000012p-3) = -0x1.000002p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.000014p-3) = -0x1.000002p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.000016p-3) = -0x1.000002p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.000018p-3) = -0x1p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1p+0
|
|
+near:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000004p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000004p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.000006p-3) = 0x1.000004p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.000008p-3) = 0x1.000004p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.00000ap-3) = 0x1.000002p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.00000cp-3) = 0x1.000002p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.00000ep-3) = 0x1.000002p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.00001p-3 ) = 0x1.000002p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.000012p-3) = 0x1.000002p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.000014p-3) = 0x1.000002p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.000016p-3) = 0x1.000002p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.000018p-3) = 0x1p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.00001ap-3) = 0x1p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.00001cp-3) = 0x1p+0
|
|
+near:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1p-3 ) = -0x1.000004p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.000002p-3) = -0x1.000002p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.000004p-3) = -0x1.000002p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.000006p-3) = -0x1.000002p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.000008p-3) = -0x1.000002p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.00000ap-3) = -0x1.000002p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.00000cp-3) = -0x1.000002p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.00000ep-3) = -0x1.000002p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.00001p-3) = -0x1.000002p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.000012p-3) = -0x1p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.000014p-3) = -0x1p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.000016p-3) = -0x1p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.000018p-3) = -0x1p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1p+0
|
|
+zero:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000002p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000002p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.000006p-3) = 0x1.000002p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.000008p-3) = 0x1.000002p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.00000ap-3) = 0x1.000002p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.00000cp-3) = 0x1.000002p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.00000ep-3) = 0x1.000002p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.00001p-3 ) = 0x1.000002p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.000012p-3) = 0x1p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.000014p-3) = 0x1p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.000016p-3) = 0x1p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.000018p-3) = 0x1p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.00001ap-3) = 0x1p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.00001cp-3) = 0x1p+0
|
|
+zero:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1p-3 ) = -0x1.000004p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.000002p-3) = -0x1.000002p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.000004p-3) = -0x1.000002p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.000006p-3) = -0x1.000002p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.000008p-3) = -0x1.000002p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.00000ap-3) = -0x1.000002p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.00000cp-3) = -0x1.000002p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.00000ep-3) = -0x1.000002p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.00001p-3) = -0x1.000002p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.000012p-3) = -0x1p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.000014p-3) = -0x1p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.000016p-3) = -0x1p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.000018p-3) = -0x1p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1p+0
|
|
++inf:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1p-3 ) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000002p-3) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000004p-3) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000006p-3) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000008p-3) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.00000ap-3) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.00000cp-3) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.00000ep-3) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.00001p-3 ) = 0x1.000002p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000012p-3) = 0x1.000002p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000014p-3) = 0x1.000002p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000016p-3) = 0x1.000002p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000018p-3) = 0x1.000002p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.00001ap-3) = 0x1.000002p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.00001cp-3) = 0x1.000002p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.00001ep-3) = 0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1p-3 ) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000002p-3) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000004p-3) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000006p-3) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000008p-3) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.00000ap-3) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.00000cp-3) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.00000ep-3) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.00001p-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000012p-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000014p-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000016p-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000018p-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.00001ap-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.00001cp-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.00001ep-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000002p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000002p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.000006p-3) = 0x1.000002p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.000008p-3) = 0x1.000002p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.00000ap-3) = 0x1.000002p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.00000cp-3) = 0x1.000002p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.00000ep-3) = 0x1.000002p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.00001p-3 ) = 0x1.000002p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.000012p-3) = 0x1p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.000014p-3) = 0x1p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.000016p-3) = 0x1p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.000018p-3) = 0x1p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.00001ap-3) = 0x1p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.00001cp-3) = 0x1p+0
|
|
+-inf:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1p+0
|
|
+near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0
|
|
+near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0
|
|
+near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0
|
|
+near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0
|
|
+near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0
|
|
+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0
|
|
+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0
|
|
+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001p+0
|
|
+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0
|
|
+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0
|
|
+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0
|
|
+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0
|
|
+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0
|
|
+near:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0
|
|
+near:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0
|
|
+near:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200022p+0
|
|
+near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0
|
|
+near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200002p+0
|
|
+near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0
|
|
+near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0
|
|
+near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0
|
|
+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0
|
|
+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0
|
|
+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001p+0
|
|
+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0
|
|
+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0
|
|
+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0
|
|
+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0
|
|
+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0
|
|
+near:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0
|
|
+near:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0
|
|
+near:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200022p+0
|
|
+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0
|
|
+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0
|
|
+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0
|
|
+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0
|
|
+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0
|
|
+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0
|
|
+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000cp+0
|
|
+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ep+0
|
|
+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200012p+0
|
|
+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0
|
|
+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0
|
|
+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0
|
|
+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0
|
|
+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0
|
|
+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ep+0
|
|
+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20002p+0
|
|
+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0
|
|
+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200002p+0
|
|
+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0
|
|
+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0
|
|
+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0
|
|
+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0
|
|
+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000cp+0
|
|
+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ep+0
|
|
+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200012p+0
|
|
+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0
|
|
+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0
|
|
+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0
|
|
+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0
|
|
+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0
|
|
+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ep+0
|
|
+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20002p+0
|
|
++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0
|
|
++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0
|
|
++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0
|
|
++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0
|
|
++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0
|
|
++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0
|
|
++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000cp+0
|
|
++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ep+0
|
|
++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200012p+0
|
|
++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0
|
|
++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0
|
|
++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0
|
|
++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0
|
|
++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0
|
|
++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ep+0
|
|
++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20002p+0
|
|
++inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0
|
|
++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200004p+0
|
|
++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200006p+0
|
|
++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200008p+0
|
|
++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ap+0
|
|
++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0
|
|
++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0
|
|
++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001p+0
|
|
++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0
|
|
++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200016p+0
|
|
++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200018p+0
|
|
++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ap+0
|
|
++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001cp+0
|
|
++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0
|
|
++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0
|
|
++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200022p+0
|
|
+-inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0
|
|
+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200004p+0
|
|
+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200006p+0
|
|
+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200008p+0
|
|
+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ap+0
|
|
+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0
|
|
+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0
|
|
+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001p+0
|
|
+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0
|
|
+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200016p+0
|
|
+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200018p+0
|
|
+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ap+0
|
|
+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001cp+0
|
|
+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0
|
|
+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0
|
|
+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200022p+0
|
|
+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0
|
|
+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200002p+0
|
|
+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0
|
|
+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0
|
|
+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0
|
|
+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0
|
|
+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000cp+0
|
|
+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ep+0
|
|
+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200012p+0
|
|
+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0
|
|
+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0
|
|
+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0
|
|
+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0
|
|
+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0
|
|
+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ep+0
|
|
+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20002p+0
|
|
+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
+near:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0
|
|
+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
+near:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec4p+0
|
|
+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
+near:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745ep+0
|
|
+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
+near:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f6p+0
|
|
+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
+near:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92492p+0
|
|
+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
+near:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f6p+0
|
|
+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148
|
|
+near:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f8p+0
|
|
+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148
|
|
+near:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b14p+0
|
|
+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+near:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f7p+0
|
|
+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+near:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec4p+0
|
|
+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+near:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745ep+0
|
|
+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
+near:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f6p+0
|
|
+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
+near:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92492p+0
|
|
+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
+near:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f6p+0
|
|
+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148
|
|
+near:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f8p+0
|
|
+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148
|
|
+near:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b14p+0
|
|
+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
+zero:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0
|
|
+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
+zero:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec4p+0
|
|
+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
+zero:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745cp+0
|
|
+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
+zero:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f4p+0
|
|
+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
+zero:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92492p+0
|
|
+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
+zero:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f6p+0
|
|
+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
+zero:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f6p+0
|
|
+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
+zero:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b12p+0
|
|
+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+zero:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f7p+0
|
|
+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+zero:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec4p+0
|
|
+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+zero:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745cp+0
|
|
+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+zero:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f4p+0
|
|
+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
+zero:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92492p+0
|
|
+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
+zero:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f6p+0
|
|
+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
+zero:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f6p+0
|
|
+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
+zero:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b12p+0
|
|
++inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
++inf:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0
|
|
++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0
|
|
++inf:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec4p+0
|
|
++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0
|
|
++inf:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745cp+0
|
|
++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0
|
|
++inf:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f4p+0
|
|
++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
|
|
++inf:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92492p+0
|
|
++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
|
|
++inf:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f6p+0
|
|
++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
|
|
++inf:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f6p+0
|
|
++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
|
|
++inf:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b12p+0
|
|
++inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
++inf:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f72p+0
|
|
++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
|
|
++inf:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec6p+0
|
|
++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
|
|
++inf:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745ep+0
|
|
++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
|
|
++inf:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f6p+0
|
|
++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
|
|
++inf:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92494p+0
|
|
++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148
|
|
++inf:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f8p+0
|
|
++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148
|
|
++inf:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f8p+0
|
|
++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148
|
|
++inf:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b14p+0
|
|
+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
+-inf:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f72p+0
|
|
+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
+-inf:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec6p+0
|
|
+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
+-inf:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745ep+0
|
|
+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
+-inf:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f6p+0
|
|
+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
+-inf:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92494p+0
|
|
+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148
|
|
+-inf:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f8p+0
|
|
+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148
|
|
+-inf:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f8p+0
|
|
+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148
|
|
+-inf:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b14p+0
|
|
+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+-inf:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f7p+0
|
|
+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+-inf:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec4p+0
|
|
+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+-inf:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745cp+0
|
|
+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+-inf:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f4p+0
|
|
+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
+-inf:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92492p+0
|
|
+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
+-inf:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f6p+0
|
|
+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
+-inf:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f6p+0
|
|
+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
+-inf:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b12p+0
|
|
+near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
|
|
+near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
+near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
+near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
|
|
+near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
|
+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
|
+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
|
|
+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
+near:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
|
+near:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
+near:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
+near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
|
|
+near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
+near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
+near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
|
|
+near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
|
+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
|
+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
|
|
+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
+near:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
|
+near:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
+near:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
|
|
+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
|
|
+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
|
+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
|
+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
|
+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
|
+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
|
|
+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
|
|
+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
|
+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
|
+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
|
+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
|
+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
|
|
++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
|
|
++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
|
++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
|
++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
|
++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
|
++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
++inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
|
|
++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
|
|
++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
|
++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
|
++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
|
|
++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00024p+0
|
|
+-inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
|
|
+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
|
|
+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
|
+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
|
+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
|
|
+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00024p+0
|
|
+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
|
|
+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
|
|
+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
|
+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
|
+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
|
+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
|
+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
+near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
|
|
+near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
+near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
+near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
|
|
+near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
|
+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
|
+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
|
|
+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
+near:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
|
+near:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
+near:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
+near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
|
|
+near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
+near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
+near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
|
|
+near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
|
+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
|
+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
|
|
+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
+near:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
|
+near:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
+near:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
|
|
+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
|
|
+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
|
+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
|
+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
|
+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
|
+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
|
|
+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
|
|
+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
|
+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
|
+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
|
+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
|
+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
|
|
++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
|
|
++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
|
++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
|
++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
|
++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
|
++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
++inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
|
|
++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
|
|
++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
|
++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
|
++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
|
|
++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00024p+0
|
|
+-inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
|
|
+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
|
|
+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
|
+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
|
+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
|
|
+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00024p+0
|
|
+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
|
|
+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
|
|
+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
|
+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
|
+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
|
+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
|
+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
+near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
|
|
+near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
+near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
+near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
|
|
+near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
|
+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
|
+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
|
|
+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
+near:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
|
+near:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
+near:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
+near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
|
|
+near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
+near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
+near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
|
|
+near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
|
+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
|
+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
|
|
+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
+near:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
|
+near:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
+near:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
|
|
+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
|
|
+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
|
+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
|
+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
|
+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
|
+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
|
|
+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
|
|
+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
|
+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
|
+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
|
+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
|
+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
|
|
++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
|
|
++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
|
++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
|
++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
|
++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
|
++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
++inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
|
|
++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
|
|
++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
|
++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
|
++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
|
|
++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00024p+0
|
|
+-inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
|
|
+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
|
|
+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
|
+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
|
+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
|
|
+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00024p+0
|
|
+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
|
|
+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
|
|
+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
|
+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
|
+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
|
+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
|
+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
+near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
|
|
+near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
+near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
+near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
|
|
+near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
|
+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
|
+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
|
|
+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
+near:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
|
+near:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
+near:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
+near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
|
|
+near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
+near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
+near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
|
|
+near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
|
+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
|
+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
|
|
+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
+near:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
|
+near:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
+near:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
|
|
+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
|
|
+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
|
+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
|
+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
|
+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
|
+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
|
|
+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
|
|
+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
|
+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
|
+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
|
+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
|
+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
|
|
++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
|
|
++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
|
++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
|
++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
|
++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
|
++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
++inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
|
|
++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
|
|
++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
|
++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
|
++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
|
|
++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00024p+0
|
|
+-inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
|
|
+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
|
|
+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
|
+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
|
+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
|
|
+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00024p+0
|
|
+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
|
|
+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
|
|
+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
|
+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
|
+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
|
+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
|
+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
+-------------------------- test rounding of double operators with guard bits --------------------------
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2000000000001p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2000000000001p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2000000000001p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000001p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000001p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000001p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000002p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000002p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000002p+0
|
|
+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000002p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2000000000001p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2000000000001p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2000000000001p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000001p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000001p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000001p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000002p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000002p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000002p+0
|
|
+near:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000002p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000001p+0
|
|
+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000002p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000002p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000002p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000002p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000002p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000002p+0
|
|
++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000002p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000002p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000002p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000002p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000002p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000002p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000002p+0
|
|
+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000002p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000001p+0
|
|
+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000001p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000002p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000002p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000002p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000002p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000001p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000001p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000001p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1.0000000000001p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1.0000000000001p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1.0000000000001p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1p+0
|
|
+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000002p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000002p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000002p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000002p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000001p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000001p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000001p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1.0000000000001p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1.0000000000001p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1.0000000000001p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1p+0
|
|
+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1p+0
|
|
+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1p+0
|
|
+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1p+0
|
|
++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000002p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000002p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000002p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000002p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000002p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000002p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000002p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1.0000000000001p+0
|
|
++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000002p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000002p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000002p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000002p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000002p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000002p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000002p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1p+0
|
|
+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1p+0
|
|
+near:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0
|
|
+near:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000001p+0
|
|
+near:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0
|
|
+near:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0
|
|
+near:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0
|
|
+near:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0
|
|
+near:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0
|
|
+near:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000008p+0
|
|
+near:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0
|
|
+near:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000ap+0
|
|
+near:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000bp+0
|
|
+near:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000cp+0
|
|
+near:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0
|
|
+near:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000fp+0
|
|
+near:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000001p+0
|
|
+near:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.2000000000011p+0
|
|
+near:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0
|
|
+near:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000001p+0
|
|
+near:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0
|
|
+near:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0
|
|
+near:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0
|
|
+near:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0
|
|
+near:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0
|
|
+near:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000008p+0
|
|
+near:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0
|
|
+near:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000ap+0
|
|
+near:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000bp+0
|
|
+near:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000cp+0
|
|
+near:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0
|
|
+near:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000fp+0
|
|
+near:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000001p+0
|
|
+near:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.2000000000011p+0
|
|
+zero:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0
|
|
+zero:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000001p+0
|
|
+zero:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0
|
|
+zero:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0
|
|
+zero:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0
|
|
+zero:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000005p+0
|
|
+zero:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0
|
|
+zero:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0
|
|
+zero:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0
|
|
+zero:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000ap+0
|
|
+zero:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000bp+0
|
|
+zero:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000cp+0
|
|
+zero:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000dp+0
|
|
+zero:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0
|
|
+zero:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000000fp+0
|
|
+zero:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.200000000001p+0
|
|
+zero:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0
|
|
+zero:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000001p+0
|
|
+zero:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0
|
|
+zero:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0
|
|
+zero:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0
|
|
+zero:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000005p+0
|
|
+zero:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0
|
|
+zero:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0
|
|
+zero:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0
|
|
+zero:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000ap+0
|
|
+zero:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000bp+0
|
|
+zero:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000cp+0
|
|
+zero:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000dp+0
|
|
+zero:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0
|
|
+zero:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000000fp+0
|
|
+zero:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.200000000001p+0
|
|
++inf:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0
|
|
++inf:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000001p+0
|
|
++inf:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0
|
|
++inf:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0
|
|
++inf:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0
|
|
++inf:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000005p+0
|
|
++inf:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0
|
|
++inf:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0
|
|
++inf:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0
|
|
++inf:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000ap+0
|
|
++inf:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000bp+0
|
|
++inf:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000cp+0
|
|
++inf:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000dp+0
|
|
++inf:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0
|
|
++inf:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000000fp+0
|
|
++inf:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.200000000001p+0
|
|
++inf:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0
|
|
++inf:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0
|
|
++inf:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0
|
|
++inf:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0
|
|
++inf:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000005p+0
|
|
++inf:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0
|
|
++inf:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0
|
|
++inf:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000008p+0
|
|
++inf:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0
|
|
++inf:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000bp+0
|
|
++inf:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000cp+0
|
|
++inf:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000dp+0
|
|
++inf:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0
|
|
++inf:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000fp+0
|
|
++inf:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000001p+0
|
|
++inf:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.2000000000011p+0
|
|
+-inf:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0
|
|
+-inf:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0
|
|
+-inf:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0
|
|
+-inf:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0
|
|
+-inf:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000005p+0
|
|
+-inf:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0
|
|
+-inf:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0
|
|
+-inf:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000008p+0
|
|
+-inf:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0
|
|
+-inf:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000bp+0
|
|
+-inf:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000cp+0
|
|
+-inf:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000dp+0
|
|
+-inf:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0
|
|
+-inf:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000fp+0
|
|
+-inf:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000001p+0
|
|
+-inf:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.2000000000011p+0
|
|
+-inf:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0
|
|
+-inf:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000001p+0
|
|
+-inf:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0
|
|
+-inf:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0
|
|
+-inf:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0
|
|
+-inf:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000005p+0
|
|
+-inf:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0
|
|
+-inf:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0
|
|
+-inf:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0
|
|
+-inf:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000ap+0
|
|
+-inf:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000bp+0
|
|
+-inf:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000cp+0
|
|
+-inf:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000dp+0
|
|
+-inf:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0
|
|
+-inf:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000000fp+0
|
|
+-inf:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.200000000001p+0
|
|
+-62/62
|
|
+near:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0
|
|
+-64/62
|
|
+near:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421084p+0
|
|
+-66/62
|
|
+near:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842108p+0
|
|
+-100/62
|
|
+near:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cep+0
|
|
+near:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0p+0
|
|
+-102/62
|
|
+near:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a53p+0
|
|
+-106/62
|
|
+near:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5bp+0
|
|
+-108/62
|
|
+near:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdfp+0
|
|
+-108/108
|
|
+near:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0
|
|
+-112/62
|
|
+near:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce7p+0
|
|
+-114/62
|
|
+near:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6bp+0
|
|
+-116/62
|
|
+near:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdefp+0
|
|
+near:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000002p-1022
|
|
+-118/62
|
|
+near:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce74p+0
|
|
+-90/62
|
|
+near:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce73ap+0
|
|
+-92/62
|
|
+near:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bep+0
|
|
+62/62
|
|
+near:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0
|
|
+64/62
|
|
+near:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421084p+0
|
|
+66/62
|
|
+near:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842108p+0
|
|
+100/62
|
|
+near:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cep+0
|
|
+near:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0p+0
|
|
+102/62
|
|
+near:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a53p+0
|
|
+106/62
|
|
+near:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5bp+0
|
|
+108/62
|
|
+near:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdfp+0
|
|
+108/108
|
|
+near:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0
|
|
+112/62
|
|
+near:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce7p+0
|
|
+114/62
|
|
+near:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6bp+0
|
|
+116/62
|
|
+near:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdefp+0
|
|
+near:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000002p-1022
|
|
+118/62
|
|
+near:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce74p+0
|
|
+90/62
|
|
+near:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce73ap+0
|
|
+92/62
|
|
+near:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bep+0
|
|
+-62/62
|
|
+zero:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0
|
|
+-64/62
|
|
+zero:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421084p+0
|
|
+-66/62
|
|
+zero:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842108p+0
|
|
+-100/62
|
|
+zero:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cep+0
|
|
+zero:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0p+0
|
|
+-102/62
|
|
+zero:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a52p+0
|
|
+-106/62
|
|
+zero:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5ap+0
|
|
+-108/62
|
|
+zero:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdep+0
|
|
+-108/108
|
|
+zero:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0
|
|
+-112/62
|
|
+zero:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce7p+0
|
|
+-114/62
|
|
+zero:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6bp+0
|
|
+-116/62
|
|
+zero:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdefp+0
|
|
+zero:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000001p-1022
|
|
+-118/62
|
|
+zero:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce73p+0
|
|
+-90/62
|
|
+zero:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce739p+0
|
|
+-92/62
|
|
+zero:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bdp+0
|
|
+62/62
|
|
+zero:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0
|
|
+64/62
|
|
+zero:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421084p+0
|
|
+66/62
|
|
+zero:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842108p+0
|
|
+100/62
|
|
+zero:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cep+0
|
|
+zero:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0p+0
|
|
+102/62
|
|
+zero:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a52p+0
|
|
+106/62
|
|
+zero:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5ap+0
|
|
+108/62
|
|
+zero:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdep+0
|
|
+108/108
|
|
+zero:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0
|
|
+112/62
|
|
+zero:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce7p+0
|
|
+114/62
|
|
+zero:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6bp+0
|
|
+116/62
|
|
+zero:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdefp+0
|
|
+zero:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000001p-1022
|
|
+118/62
|
|
+zero:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce73p+0
|
|
+90/62
|
|
+zero:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce739p+0
|
|
+92/62
|
|
+zero:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bdp+0
|
|
+-62/62
|
|
++inf:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0
|
|
+-64/62
|
|
++inf:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421084p+0
|
|
+-66/62
|
|
++inf:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842108p+0
|
|
+-100/62
|
|
++inf:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cep+0
|
|
++inf:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0p+0
|
|
+-102/62
|
|
++inf:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a52p+0
|
|
+-106/62
|
|
++inf:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5ap+0
|
|
+-108/62
|
|
++inf:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdep+0
|
|
+-108/108
|
|
++inf:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0
|
|
+-112/62
|
|
++inf:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce7p+0
|
|
+-114/62
|
|
++inf:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6bp+0
|
|
+-116/62
|
|
++inf:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdefp+0
|
|
++inf:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000001p-1022
|
|
+-118/62
|
|
++inf:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce73p+0
|
|
+-90/62
|
|
++inf:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce739p+0
|
|
+-92/62
|
|
++inf:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bdp+0
|
|
+62/62
|
|
++inf:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0
|
|
+64/62
|
|
++inf:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421085p+0
|
|
+66/62
|
|
++inf:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842109p+0
|
|
+100/62
|
|
++inf:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cfp+0
|
|
++inf:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0.0000000000001p-1022
|
|
+102/62
|
|
++inf:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a53p+0
|
|
+106/62
|
|
++inf:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5bp+0
|
|
+108/62
|
|
++inf:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdfp+0
|
|
+108/108
|
|
++inf:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0
|
|
+112/62
|
|
++inf:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce8p+0
|
|
+114/62
|
|
++inf:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6cp+0
|
|
+116/62
|
|
++inf:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdfp+0
|
|
++inf:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000002p-1022
|
|
+118/62
|
|
++inf:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce74p+0
|
|
+90/62
|
|
++inf:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce73ap+0
|
|
+92/62
|
|
++inf:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bep+0
|
|
+-62/62
|
|
+-inf:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0
|
|
+-64/62
|
|
+-inf:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421085p+0
|
|
+-66/62
|
|
+-inf:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842109p+0
|
|
+-100/62
|
|
+-inf:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cfp+0
|
|
+-inf:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0.0000000000001p-1022
|
|
+-102/62
|
|
+-inf:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a53p+0
|
|
+-106/62
|
|
+-inf:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5bp+0
|
|
+-108/62
|
|
+-inf:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdfp+0
|
|
+-108/108
|
|
+-inf:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0
|
|
+-112/62
|
|
+-inf:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce8p+0
|
|
+-114/62
|
|
+-inf:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6cp+0
|
|
+-116/62
|
|
+-inf:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdfp+0
|
|
+-inf:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000002p-1022
|
|
+-118/62
|
|
+-inf:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce74p+0
|
|
+-90/62
|
|
+-inf:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce73ap+0
|
|
+-92/62
|
|
+-inf:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bep+0
|
|
+62/62
|
|
+-inf:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0
|
|
+64/62
|
|
+-inf:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421084p+0
|
|
+66/62
|
|
+-inf:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842108p+0
|
|
+100/62
|
|
+-inf:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cep+0
|
|
+-inf:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0p+0
|
|
+102/62
|
|
+-inf:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a52p+0
|
|
+106/62
|
|
+-inf:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5ap+0
|
|
+108/62
|
|
+-inf:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdep+0
|
|
+108/108
|
|
+-inf:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0
|
|
+112/62
|
|
+-inf:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce7p+0
|
|
+114/62
|
|
+-inf:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6bp+0
|
|
+116/62
|
|
+-inf:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdefp+0
|
|
+-inf:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000001p-1022
|
|
+118/62
|
|
+-inf:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce73p+0
|
|
+90/62
|
|
+-inf:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce739p+0
|
|
+92/62
|
|
+-inf:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bdp+0
|
|
+near:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
|
|
+near:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+near:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+near:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0
|
|
+near:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+near:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
+near:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+near:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+near:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+near:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+near:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+near:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0
|
|
+near:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+near:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
+near:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+near:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
+near:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
|
|
+near:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+near:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+near:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0
|
|
+near:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+near:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
+near:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+near:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+near:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+near:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+near:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+near:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0
|
|
+near:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+near:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
+near:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+near:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
+zero:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
|
|
+zero:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
+zero:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+zero:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+zero:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+zero:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
+zero:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+zero:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+zero:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
+zero:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+zero:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+zero:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+zero:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+zero:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
+zero:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+zero:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
+zero:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
|
|
+zero:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
+zero:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+zero:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+zero:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+zero:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
+zero:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+zero:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+zero:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
+zero:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+zero:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+zero:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+zero:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+zero:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
+zero:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+zero:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
++inf:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
|
|
++inf:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
++inf:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
++inf:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
++inf:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
++inf:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
++inf:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
++inf:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
++inf:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
++inf:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
++inf:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
++inf:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
++inf:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
++inf:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
++inf:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
++inf:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
++inf:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
++inf:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
++inf:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
++inf:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0
|
|
++inf:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
++inf:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
++inf:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
++inf:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
++inf:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
++inf:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
++inf:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
++inf:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0
|
|
++inf:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
++inf:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
++inf:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
++inf:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000012p+0
|
|
+-inf:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
+-inf:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+-inf:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+-inf:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0
|
|
+-inf:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+-inf:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+-inf:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+-inf:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
+-inf:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+-inf:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+-inf:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+-inf:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0
|
|
+-inf:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+-inf:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+-inf:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
+-inf:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000012p+0
|
|
+-inf:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
|
|
+-inf:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
+-inf:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+-inf:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+-inf:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+-inf:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
+-inf:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+-inf:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+-inf:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
+-inf:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+-inf:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+-inf:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+-inf:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+-inf:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
+-inf:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+-inf:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
+near:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
|
|
+near:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+near:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+near:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0
|
|
+near:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+near:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
+near:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+near:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+near:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+near:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+near:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+near:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0
|
|
+near:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+near:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
+near:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+near:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
+near:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
|
|
+near:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+near:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+near:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0
|
|
+near:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+near:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
+near:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+near:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+near:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+near:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+near:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+near:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0
|
|
+near:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+near:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
+near:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+near:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
+zero:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
|
|
+zero:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
+zero:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+zero:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+zero:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+zero:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
+zero:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+zero:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+zero:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
+zero:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+zero:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+zero:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+zero:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+zero:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
+zero:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+zero:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
+zero:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
|
|
+zero:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
+zero:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+zero:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+zero:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+zero:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
+zero:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+zero:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+zero:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
+zero:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+zero:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+zero:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+zero:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+zero:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
+zero:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+zero:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
++inf:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
|
|
++inf:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
++inf:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
++inf:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
++inf:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
++inf:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
++inf:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
++inf:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
++inf:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
++inf:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
++inf:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
++inf:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
++inf:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
++inf:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
++inf:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
++inf:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
++inf:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
++inf:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
++inf:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
++inf:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0
|
|
++inf:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
++inf:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
++inf:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
++inf:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
++inf:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
++inf:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
++inf:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
++inf:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0
|
|
++inf:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
++inf:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
++inf:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
++inf:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000012p+0
|
|
+-inf:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
+-inf:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+-inf:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+-inf:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0
|
|
+-inf:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+-inf:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+-inf:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+-inf:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
+-inf:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+-inf:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+-inf:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+-inf:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0
|
|
+-inf:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+-inf:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+-inf:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
+-inf:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000012p+0
|
|
+-inf:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
|
|
+-inf:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
+-inf:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+-inf:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+-inf:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+-inf:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
+-inf:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+-inf:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+-inf:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
+-inf:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+-inf:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+-inf:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+-inf:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+-inf:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
+-inf:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+-inf:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
+near:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
|
|
+near:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+near:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+near:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0
|
|
+near:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+near:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
+near:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+near:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+near:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+near:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+near:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+near:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0
|
|
+near:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+near:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
+near:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+near:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
+near:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
|
|
+near:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+near:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+near:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0
|
|
+near:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+near:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
+near:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+near:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+near:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+near:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+near:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+near:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0
|
|
+near:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+near:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
+near:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+near:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
+zero:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
|
|
+zero:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
+zero:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+zero:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+zero:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+zero:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
+zero:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+zero:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+zero:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
+zero:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+zero:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+zero:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+zero:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+zero:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
+zero:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+zero:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
+zero:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
|
|
+zero:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
+zero:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+zero:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+zero:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+zero:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
+zero:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+zero:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+zero:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
+zero:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+zero:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+zero:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+zero:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+zero:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
+zero:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+zero:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
++inf:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
|
|
++inf:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
++inf:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
++inf:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
++inf:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
++inf:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
++inf:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
++inf:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
++inf:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
++inf:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
++inf:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
++inf:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
++inf:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
++inf:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
++inf:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
++inf:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
++inf:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
++inf:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
++inf:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
++inf:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0
|
|
++inf:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
++inf:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
++inf:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
++inf:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
++inf:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
++inf:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
++inf:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
++inf:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0
|
|
++inf:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
++inf:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
++inf:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
++inf:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000012p+0
|
|
+-inf:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
+-inf:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+-inf:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+-inf:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0
|
|
+-inf:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+-inf:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+-inf:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+-inf:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
+-inf:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+-inf:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+-inf:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+-inf:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0
|
|
+-inf:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+-inf:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+-inf:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
+-inf:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000012p+0
|
|
+-inf:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
|
|
+-inf:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
+-inf:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+-inf:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+-inf:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+-inf:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
+-inf:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+-inf:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+-inf:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
+-inf:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+-inf:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+-inf:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+-inf:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+-inf:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
+-inf:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+-inf:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
+near:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
|
|
+near:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+near:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+near:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0
|
|
+near:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+near:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
+near:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+near:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+near:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+near:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+near:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+near:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0
|
|
+near:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+near:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
+near:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+near:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
+near:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
|
|
+near:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+near:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+near:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0
|
|
+near:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+near:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
+near:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+near:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+near:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+near:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+near:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+near:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0
|
|
+near:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+near:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
+near:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+near:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
+zero:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
|
|
+zero:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
+zero:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+zero:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+zero:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+zero:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
+zero:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+zero:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+zero:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
+zero:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+zero:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+zero:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+zero:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+zero:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
+zero:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+zero:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
+zero:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
|
|
+zero:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
+zero:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+zero:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+zero:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+zero:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
+zero:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+zero:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+zero:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
+zero:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+zero:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+zero:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+zero:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+zero:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
+zero:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+zero:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
++inf:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
|
|
++inf:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
++inf:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
++inf:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
++inf:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
++inf:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
|
|
++inf:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
++inf:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
++inf:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
++inf:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
++inf:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
++inf:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
++inf:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
++inf:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
|
|
++inf:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
++inf:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
++inf:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
++inf:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
++inf:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
++inf:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0
|
|
++inf:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
++inf:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
++inf:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
++inf:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
++inf:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
++inf:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
++inf:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
++inf:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0
|
|
++inf:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
++inf:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
++inf:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
++inf:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000012p+0
|
|
+-inf:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
|
|
+-inf:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
|
|
+-inf:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
|
|
+-inf:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0
|
|
+-inf:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
|
|
+-inf:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
|
|
+-inf:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
|
|
+-inf:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
|
|
+-inf:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
|
|
+-inf:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
|
|
+-inf:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
|
|
+-inf:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0
|
|
+-inf:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
|
|
+-inf:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
|
|
+-inf:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
|
|
+-inf:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000012p+0
|
|
+-inf:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
|
|
+-inf:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
|
|
+-inf:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
|
|
+-inf:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
|
|
+-inf:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
|
|
+-inf:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
|
|
+-inf:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
|
|
+-inf:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
|
|
+-inf:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
|
|
+-inf:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
|
|
+-inf:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
|
|
+-inf:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
|
|
+-inf:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
|
|
+-inf:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
|
|
+-inf:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
|
|
+-inf:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
|
|
+near:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049ep-1
|
|
+near:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6dp+0
|
|
+near:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3bfp+0
|
|
+near:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0937p-1
|
|
+near:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b2p+0
|
|
+near:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7483p+0
|
|
+near:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7cp-1
|
|
+near:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9ep+0
|
|
+near:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6cp-1
|
|
+near:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0acp-1
|
|
+near:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e3p+0
|
|
+near:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0b1p-1
|
|
+near:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907afp-1
|
|
+near:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed828p+0
|
|
+zero:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049ep-1
|
|
+zero:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6dp+0
|
|
+zero:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3bfp+0
|
|
+zero:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0937p-1
|
|
+zero:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b2p+0
|
|
+zero:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7483p+0
|
|
+zero:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7cp-1
|
|
+zero:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9dp+0
|
|
+zero:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6bp-1
|
|
+zero:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0abfp-1
|
|
+zero:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e2p+0
|
|
+zero:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0bp-1
|
|
+zero:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907aep-1
|
|
+zero:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed827p+0
|
|
++inf:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049fp-1
|
|
++inf:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6ep+0
|
|
++inf:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3cp+0
|
|
++inf:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0938p-1
|
|
++inf:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b3p+0
|
|
++inf:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7484p+0
|
|
++inf:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7dp-1
|
|
++inf:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9ep+0
|
|
++inf:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6cp-1
|
|
++inf:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0acp-1
|
|
++inf:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e3p+0
|
|
++inf:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0b1p-1
|
|
++inf:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907afp-1
|
|
++inf:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed828p+0
|
|
+-inf:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049ep-1
|
|
+-inf:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6dp+0
|
|
+-inf:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3bfp+0
|
|
+-inf:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0937p-1
|
|
+-inf:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b2p+0
|
|
+-inf:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7483p+0
|
|
+-inf:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7cp-1
|
|
+-inf:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9dp+0
|
|
+-inf:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6bp-1
|
|
+-inf:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0abfp-1
|
|
+-inf:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e2p+0
|
|
+-inf:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0bp-1
|
|
+-inf:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907aep-1
|
|
+-inf:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed827p+0
|
|
Index: none/tests/ppc32/test_isa_2_07_part2.stdout.exp
|
|
===================================================================
|
|
--- none/tests/ppc32/test_isa_2_07_part2.stdout.exp.orig
|
|
+++ none/tests/ppc32/test_isa_2_07_part2.stdout.exp
|
|
@@ -651,26 +651,26 @@ Test VSX floating point instructions
|
|
|
|
|
|
Test VSX vector and scalar single argument instructions
|
|
-#0: xscvdpspn conv(3ec00000) = 3ec00000
|
|
-#1: xscvdpspn conv(42780000) = 42780000
|
|
-#2: xscvdpspn conv(00000000) = 00000000
|
|
-#3: xscvdpspn conv(7f800000) = 7f800000
|
|
-#4: xscvdpspn conv(00000000) = 00000000
|
|
-#5: xscvdpspn conv(00000000) = 00000000
|
|
-#6: xscvdpspn conv(80000000) = 80000000
|
|
-#7: xscvdpspn conv(7f800000) = 7f800000
|
|
-#8: xscvdpspn conv(ff800000) = ff800000
|
|
-#9: xscvdpspn conv(7fbfffff) = 7fbfffff
|
|
-#10: xscvdpspn conv(ffbfffff) = ffbfffff
|
|
-#11: xscvdpspn conv(7fc00000) = 7fc00000
|
|
-#12: xscvdpspn conv(ffc00000) = ffc00000
|
|
-#13: xscvdpspn conv(80000000) = 80000000
|
|
-#14: xscvdpspn conv(c683287b) = c683287b
|
|
-#15: xscvdpspn conv(49192c2d) = 49192c2d
|
|
-#16: xscvdpspn conv(49c1288d) = 49c1288d
|
|
-#17: xscvdpspn conv(418977ad) = 418977ad
|
|
-#18: xscvdpspn conv(428a5faf) = 428a5faf
|
|
-#19: xscvdpspn conv(44bb5fcc) = 44bb5fcc
|
|
+#0: xscvdpspn conv(3fd8000000000000) = 3ec00000
|
|
+#1: xscvdpspn conv(404f000000000000) = 42780000
|
|
+#2: xscvdpspn conv(0018000000b77501) = 00000000
|
|
+#3: xscvdpspn conv(7fe800000000051b) = 7f800000
|
|
+#4: xscvdpspn conv(0123214569900000) = 00000000
|
|
+#5: xscvdpspn conv(0000000000000000) = 00000000
|
|
+#6: xscvdpspn conv(8000000000000000) = 80000000
|
|
+#7: xscvdpspn conv(7ff0000000000000) = 7f800000
|
|
+#8: xscvdpspn conv(fff0000000000000) = ff800000
|
|
+#9: xscvdpspn conv(7ff7ffffffffffff) = 7fbfffff
|
|
+#10: xscvdpspn conv(fff7ffffffffffff) = ffbfffff
|
|
+#11: xscvdpspn conv(7ff8000000000000) = 7fc00000
|
|
+#12: xscvdpspn conv(fff8000000000000) = ffc00000
|
|
+#13: xscvdpspn conv(8008340000078000) = 80000000
|
|
+#14: xscvdpspn conv(c0d0650f5a07b353) = c683287b
|
|
+#15: xscvdpspn conv(41232585a9900000) = 49192c2d
|
|
+#16: xscvdpspn conv(41382511a2000000) = 49c1288d
|
|
+#17: xscvdpspn conv(40312ef5a9300000) = 418977ad
|
|
+#18: xscvdpspn conv(40514bf5d2300000) = 428a5faf
|
|
+#19: xscvdpspn conv(40976bf982440000) = 44bb5fcc
|
|
|
|
#0: xscvspdpn conv(3ec00000) = 3fd8000000000000
|
|
#1: xscvspdpn conv(42780000) = 404f000000000000
|
|
@@ -783,23 +783,15 @@ Test VSX logic instructions
|
|
#2: xxlnand (80000001 89abcdef 00112233 74556677, 80000001 89abcdef 00112233 74556677) ==> 7ffffffe 76543210 ffeeddcc 8baa9988
|
|
|
|
Test VSX scalar integer conversion instructions
|
|
-#0: xscvsxdsp 80000001 => c3e0000000000000
|
|
-#1: xscvsxdsp 89abcdef => c3dd950c80000000
|
|
-#2: xscvsxdsp 00112233 => 4331223380000000
|
|
-#3: xscvsxdsp 74556677 => 43dd1559a0000000
|
|
-#4: xscvsxdsp 00001abb => 42babb89a0000000
|
|
-#5: xscvsxdsp 00000001 => 41f89abce0000000
|
|
-#6: xscvsxdsp 31929394 => 43c8c949c0000000
|
|
-#7: xscvsxdsp a1a2a3a4 => c3d7975720000000
|
|
-
|
|
-#0: xscvuxdsp 80000001 => 43e0000000000000
|
|
-#1: xscvuxdsp 89abcdef => 43e13579c0000000
|
|
-#2: xscvuxdsp 00112233 => 4331223380000000
|
|
-#3: xscvuxdsp 74556677 => 43dd1559a0000000
|
|
-#4: xscvuxdsp 00001abb => 42babb89a0000000
|
|
-#5: xscvuxdsp 00000001 => 41f89abce0000000
|
|
-#6: xscvuxdsp 31929394 => 43c8c949c0000000
|
|
-#7: xscvuxdsp a1a2a3a4 => 43e4345480000000
|
|
+#0: xscvsxdsp 0102030405060708 => 4370203040000000
|
|
+#1: xscvsxdsp 090a0b0c0e0d0e0f => 43a2141620000000
|
|
+#2: xscvsxdsp f1f2f3f4f5f6f7f8 => c3ac1a1820000000
|
|
+#3: xscvsxdsp f9fafbfcfefdfeff => c398141000000000
|
|
+
|
|
+#0: xscvuxdsp 0102030405060708 => 4370203040000000
|
|
+#1: xscvuxdsp 090a0b0c0e0d0e0f => 43a2141620000000
|
|
+#2: xscvuxdsp f1f2f3f4f5f6f7f8 => 43ee3e5e80000000
|
|
+#3: xscvuxdsp f9fafbfcfefdfeff => 43ef3f5f80000000
|
|
|
|
|
|
Test VSX load/store dp to sp instructions
|
|
@@ -812,14 +804,13 @@ stxsspx: 41232585a0000000 ==> 49192c2d
|
|
stxsspx: 40514bf5e0000000 ==> 428a5faf
|
|
|
|
|
|
-stxsiwx: 80000001 ==> 80000001
|
|
-stxsiwx: 89abcdef ==> 89abcdef
|
|
-stxsiwx: 00112233 ==> 00112233
|
|
-stxsiwx: 74556677 ==> 74556677
|
|
-stxsiwx: 00001abb ==> 00001abb
|
|
-stxsiwx: 00000001 ==> 00000001
|
|
-stxsiwx: 31929394 ==> 31929394
|
|
-stxsiwx: a1a2a3a4 ==> a1a2a3a4
|
|
+stxsiwx: 3ec00000 ==> 3ec00000
|
|
+stxsiwx: 7f800000 ==> 7f800000
|
|
+stxsiwx: 80000000 ==> 80000000
|
|
+stxsiwx: 7fbfffff ==> 7fbfffff
|
|
+stxsiwx: ffc00000 ==> ffc00000
|
|
+stxsiwx: 49192c2d ==> 49192c2d
|
|
+stxsiwx: 428a5faf ==> 428a5faf
|
|
|
|
|
|
lxsiwax: 80000001 ==> ffffffff80000001
|
|
@@ -832,14 +823,13 @@ lxsiwax: 31929394 ==> 0000000031929394
|
|
lxsiwax: a1a2a3a4 ==> ffffffffa1a2a3a4
|
|
|
|
|
|
-lxsiwzx: 89abcdef ==> 00000000abcdef00
|
|
-lxsiwzx: 00112233 ==> 0000000011223374
|
|
-lxsiwzx: 74556677 ==> 0000000055667700
|
|
-lxsiwzx: 00001abb ==> 00000000001abb00
|
|
-lxsiwzx: 00000001 ==> 0000000000000131
|
|
-lxsiwzx: 31929394 ==> 00000000929394a1
|
|
-lxsiwzx: a1a2a3a4 ==> 00000000a2a3a410
|
|
-lxsiwzx: 10000b08 ==> 00000000000b0810
|
|
+lxsiwzx: 89abcdef ==> 0000000089abcdef
|
|
+lxsiwzx: 00112233 ==> 0000000000112233
|
|
+lxsiwzx: 74556677 ==> 0000000074556677
|
|
+lxsiwzx: 00001abb ==> 0000000000001abb
|
|
+lxsiwzx: 00000001 ==> 0000000000000001
|
|
+lxsiwzx: 31929394 ==> 0000000031929394
|
|
+lxsiwzx: a1a2a3a4 ==> 00000000a1a2a3a4
|
|
|
|
|
|
lxsspx: 3ec00000 ==> 3fd8000000000000
|
|
Index: none/tests/ppc32/test_isa_2_06_part2.c
|
|
===================================================================
|
|
--- none/tests/ppc32/test_isa_2_06_part2.c.orig
|
|
+++ none/tests/ppc32/test_isa_2_06_part2.c
|
|
@@ -39,6 +39,13 @@ typedef uint64_t HWord_t;
|
|
typedef unsigned char Bool;
|
|
#define True 1
|
|
#define False 0
|
|
+
|
|
+#ifdef VGP_ppc64le_linux
|
|
+#define isLE 1
|
|
+#else
|
|
+#define isLE 0
|
|
+#endif
|
|
+
|
|
register HWord_t r14 __asm__ ("r14");
|
|
register HWord_t r15 __asm__ ("r15");
|
|
register HWord_t r16 __asm__ ("r16");
|
|
@@ -798,8 +805,20 @@ static void test_xxspltw(void)
|
|
{
|
|
int uim;
|
|
unsigned long long * dst = NULL;
|
|
- unsigned long long xb[] = { 0xfedc432124681235ULL, 0xf1e2d3c4e0057708ULL};
|
|
- memcpy(&vec_inB, xb, 16);
|
|
+ unsigned int xb[] = { 0xfedc4321, 0x24681235, 0xf1e2d3c4, 0xe0057708};
|
|
+ int i;
|
|
+ void * vecB_ptr = &vec_inB;
|
|
+ if (isLE) {
|
|
+ for (i = 3; i >=0; i--) {
|
|
+ memcpy(vecB_ptr, &xb[i], 4);
|
|
+ vecB_ptr+=4;
|
|
+ }
|
|
+ } else {
|
|
+ for (i = 0; i < 4; i++) {
|
|
+ memcpy(vecB_ptr, &xb[i], 4);
|
|
+ vecB_ptr+=4;
|
|
+ }
|
|
+ }
|
|
|
|
for (uim = 0; uim < 4; uim++) {
|
|
switch (uim) {
|
|
@@ -817,7 +836,8 @@ static void test_xxspltw(void)
|
|
break;
|
|
}
|
|
dst = (unsigned long long *) &vec_out;
|
|
- printf("xxspltw 0x%016llx%016llx %d=> 0x%016llx", xb[0], xb[1], uim, *dst);
|
|
+ printf("xxspltw 0x%08x%08x%08x%08x %d=> 0x%016llx", xb[0], xb[1],
|
|
+ xb[2], xb[3], uim, *dst);
|
|
dst++;
|
|
printf("%016llx\n", *dst);
|
|
}
|
|
@@ -1226,22 +1246,33 @@ static void test_vx_simple_scalar_fp_ops
|
|
* (e.g. xssqrtdp).
|
|
*/
|
|
if (test_group.num_tests == nb_special_fargs && !test_group.targs) {
|
|
- void * inB;
|
|
+ void * inB, * vec_void_ptr = (void *)&vec_inB;
|
|
int i;
|
|
+ if (isLE)
|
|
+ vec_void_ptr += 8;
|
|
for (i = 0; i < nb_special_fargs; i++) {
|
|
inB = (void *)&spec_fargs[i];
|
|
frbp = (unsigned long long *)&spec_fargs[i];
|
|
- memcpy(&vec_inB, inB, 8);
|
|
+ memcpy(vec_void_ptr, inB, 8);
|
|
(*func)();
|
|
dst = (unsigned long long *) &vec_out;
|
|
+ if (isLE)
|
|
+ dst++;
|
|
printf("#%d: %s %016llx => %016llx\n", i, test_group.name, *frbp,
|
|
convToWord ? (*dst & 0x00000000ffffffffULL) : *dst);
|
|
}
|
|
} else {
|
|
- void * inA, * inB;
|
|
+ void * inA, * inB, * vecA_void_ptr, * vecB_void_ptr;
|
|
unsigned int condreg, flags;
|
|
int isTdiv = (strstr(test_group.name, "xstdivdp") != NULL) ? 1 : 0;
|
|
int i;
|
|
+ if (isLE) {
|
|
+ vecA_void_ptr = (void *)&vec_inA + 8;
|
|
+ vecB_void_ptr = (void *)&vec_inB + 8;
|
|
+ } else {
|
|
+ vecA_void_ptr = (void *)&vec_inA;
|
|
+ vecB_void_ptr = (void *)&vec_inB;
|
|
+ }
|
|
for (i = 0; i < test_group.num_tests; i++) {
|
|
fp_test_args_t aTest = test_group.targs[i];
|
|
inA = (void *)&spec_fargs[aTest.fra_idx];
|
|
@@ -1249,8 +1280,8 @@ static void test_vx_simple_scalar_fp_ops
|
|
frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
|
|
frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
|
|
// Only need to copy one doubleword into each vector's element 0
|
|
- memcpy(&vec_inA, inA, 8);
|
|
- memcpy(&vec_inB, inB, 8);
|
|
+ memcpy(vecA_void_ptr, inA, 8);
|
|
+ memcpy(vecB_void_ptr, inB, 8);
|
|
SET_FPSCR_ZERO;
|
|
SET_CR_XER_ZERO;
|
|
(*func)();
|
|
@@ -1260,6 +1291,8 @@ static void test_vx_simple_scalar_fp_ops
|
|
printf("#%d: %s %016llx,%016llx => cr %x\n", i, test_group.name, *frap, *frbp, condreg);
|
|
} else {
|
|
dst = (unsigned long long *) &vec_out;
|
|
+ if (isLE)
|
|
+ dst++;
|
|
printf("#%d: %s %016llx,%016llx => %016llx\n", i, test_group.name,
|
|
*frap, *frbp, *dst);
|
|
}
|
|
@@ -1346,21 +1379,26 @@ again:
|
|
* src3 <= VSX[XB]
|
|
*/
|
|
if (scalar) {
|
|
+#ifdef VGP_ppc64le_linux
|
|
+#define VECTOR_ADDR(_v) ((void *)&_v) + 8
|
|
+#else
|
|
+#define VECTOR_ADDR(_v) ((void *)&_v)
|
|
+#endif
|
|
// For scalar op, only need to copy one doubleword into each vector's element 0
|
|
inA = (void *)&spec_fargs[aTest.fra_idx];
|
|
inB = (void *)&spec_fargs[aTest.frb_idx];
|
|
frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
|
|
- memcpy(&vec_inA, inA, 8);
|
|
+ memcpy(VECTOR_ADDR(vec_inA), inA, 8);
|
|
if (repeat) {
|
|
- memcpy(&vec_out, inB, 8); // src2
|
|
- memcpy(&vec_inB, &spec_fargs[fp_idx[0]], 8); //src3
|
|
+ memcpy(VECTOR_ADDR(vec_out), inB, 8); // src2
|
|
+ memcpy(VECTOR_ADDR(vec_inB), &spec_fargs[fp_idx[0]], 8); //src3
|
|
frbp = (unsigned long long *)&spec_fargs[fp_idx[0]];
|
|
} else {
|
|
frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
|
|
- memcpy(&vec_inB, inB, 8); // src2
|
|
- memcpy(&vec_out, &spec_fargs[fp_idx[0]], 8); //src3
|
|
+ memcpy(VECTOR_ADDR(vec_inB), inB, 8); // src2
|
|
+ memcpy(VECTOR_ADDR(vec_out), &spec_fargs[fp_idx[0]], 8); //src3
|
|
}
|
|
- memcpy(vsr_XT, &vec_out, 8);
|
|
+ memcpy(vsr_XT, VECTOR_ADDR(vec_out), 8);
|
|
} else {
|
|
int j, loops = do_dp ? 2 : 4;
|
|
size_t len = do_dp ? 8 : 4;
|
|
@@ -1382,6 +1420,8 @@ again:
|
|
|
|
(*func)();
|
|
dst = (unsigned long long *) &vec_out;
|
|
+ if (isLE)
|
|
+ dst++;
|
|
if (test_type < VX_VECTOR_FP_MULT_AND_OP2)
|
|
printf( "#%d: %s %s(%016llx,%016llx,%016llx) = %016llx\n", i,
|
|
test_name, test_group.op, vsr_XT[0], *frap, *frbp, *dst );
|
|
Index: none/tests/ppc32/test_dfp4.c
|
|
===================================================================
|
|
--- none/tests/ppc32/test_dfp4.c.orig
|
|
+++ none/tests/ppc32/test_dfp4.c
|
|
@@ -31,8 +31,13 @@ typedef union stuff {
|
|
_Decimal128 dec_val128;
|
|
unsigned long long u64_val;
|
|
struct {
|
|
+#if defined(VGP_ppc64le_linux)
|
|
+ unsigned long long vall;
|
|
+ unsigned long long valu;
|
|
+#else
|
|
unsigned long long valu;
|
|
unsigned long long vall;
|
|
+#endif
|
|
} u128;
|
|
} dfp_val_t;
|
|
|
|
@@ -495,7 +500,6 @@ static void test_dfp_ClassAndGroupTest_o
|
|
test_val.u64_val = dfp64_vals[i];
|
|
} else {
|
|
test_val.u128.valu = dfp128_vals[i * 2];
|
|
- test_val.u64_val = test_val.u128.valu;
|
|
test_val.u128.vall = dfp128_vals[(i * 2) + 1];
|
|
}
|
|
|
|
@@ -509,11 +513,15 @@ again:
|
|
GET_CR(flags);
|
|
|
|
condreg = ((flags >> (4 * (7-BF)))) & 0xf;
|
|
- printf("%s (DC/DG=%d) %s%016llx", test_def.name, data_class_OR_group,
|
|
- test_def.op, test_val.u64_val);
|
|
+ printf("%s (DC/DG=%d) %s", test_def.name, data_class_OR_group,
|
|
+ test_def.op);
|
|
if (test_def.precision == QUAD_TEST) {
|
|
- printf(" %016llx", test_val.u128.vall);
|
|
+ printf("%016llx %016llx", test_val.u128.valu, test_val.u128.vall);
|
|
+ } else {
|
|
+ printf("%016llx", test_val.u64_val);
|
|
}
|
|
+
|
|
+ //%016llx
|
|
printf(" => %x (BF=%d)\n", condreg, BF);
|
|
}
|
|
if (repeat) {
|
|
@@ -562,10 +570,8 @@ again:
|
|
test_val2.u64_val = dfp64_vals[test_def.targs[i].frb_idx];
|
|
} else {
|
|
test_val1.u128.valu = dfp128_vals[test_def.targs[i].fra_idx * 2];
|
|
- test_val1.u64_val = test_val1.u128.valu;
|
|
test_val1.u128.vall = dfp128_vals[(test_def.targs[i].fra_idx * 2) + 1];
|
|
test_val2.u128.valu = dfp128_vals[test_def.targs[i].frb_idx * 2];
|
|
- test_val2.u64_val = test_val2.u128.valu;
|
|
test_val2.u128.vall = dfp128_vals[(test_def.targs[i].frb_idx * 2) + 1];
|
|
}
|
|
|
|
@@ -575,13 +581,13 @@ again:
|
|
GET_CR(flags);
|
|
|
|
condreg = ((flags >> (4 * (7-BF)))) & 0xf;
|
|
- printf("%s %016llx", test_def.name, test_val1.u64_val);
|
|
+ printf("%s ", test_def.name);
|
|
if (test_def.precision == LONG_TEST) {
|
|
- printf(" %s %016llx ",
|
|
- test_def.op, test_val2.u64_val);
|
|
+ printf("%016llx %s %016llx ",
|
|
+ test_val1.u64_val, test_def.op, test_val2.u64_val);
|
|
} else {
|
|
- printf(" %016llx %s %016llx %016llx ",
|
|
- test_val1.u128.vall, test_def.op, test_val2.u128.valu, test_val2.u128.vall);
|
|
+ printf("%016llx %016llx %s %016llx %016llx ",
|
|
+ test_val1.u128.valu, test_val1.u128.vall, test_def.op, test_val2.u128.valu, test_val2.u128.vall);
|
|
}
|
|
printf(" => %x (BF=%d)\n", condreg, BF);
|
|
}
|
|
Index: none/tests/ppc32/jm-insns.c
|
|
===================================================================
|
|
--- none/tests/ppc32/jm-insns.c.orig
|
|
+++ none/tests/ppc32/jm-insns.c
|
|
@@ -260,6 +260,7 @@ asm(".section \".text\"\n"
|
|
"\t.previous\n" \
|
|
)
|
|
#else
|
|
+#if defined(VGP_ppc64be_linux)
|
|
#define ASSEMBLY_FUNC(__fname, __insn) \
|
|
asm(".section \".text\"\n" \
|
|
"\t.align 2\n" \
|
|
@@ -275,6 +276,16 @@ asm(".section \".text\"\n"
|
|
"\t"__insn"\n" \
|
|
"\tblr\n" \
|
|
)
|
|
+#elif defined(VGP_ppc64le_linux)
|
|
+#define ASSEMBLY_FUNC(__fname, __insn) \
|
|
+asm(".section \".text\"\n" \
|
|
+ "\t.align 2\n" \
|
|
+ "\t.global "__fname"\n" \
|
|
+ ""__fname":\n" \
|
|
+ "\t"__insn"\n" \
|
|
+ "\tblr\n" \
|
|
+ )
|
|
+#endif // VGP_ppc64 or VGP_ppc64le
|
|
#endif // #ifndef __powerpc64__
|
|
|
|
|
|
@@ -4849,7 +4860,7 @@ static inline
|
|
test_func_t init_function( test_func_t p_func_F, uint32_t func_buf[] )
|
|
{
|
|
uint32_t* p_func = (uint32_t*)p_func_F;
|
|
-#ifndef __powerpc64__
|
|
+#if !defined(__powerpc64__) || _CALL_ELF == 2
|
|
func_buf[0] = p_func[0];
|
|
func_buf[1] = p_func[1];
|
|
return (test_func_t)&func_buf[0];
|
|
@@ -5521,20 +5532,21 @@ static void test_int_ld_one_reg_imm16 (c
|
|
uint32_t* func_buf = get_rwx_area();
|
|
volatile HWord_t res, base;
|
|
volatile uint32_t flags, xer;
|
|
- int i, offs, is_lwa=0;
|
|
+ int i, offs, shift_offset = 0;
|
|
|
|
#ifdef __powerpc64__
|
|
- is_lwa = strstr(name, "lwa") != NULL;
|
|
+ if (strstr(name, "lwa") || strstr(name, "ld") || strstr(name, "ldu"))
|
|
+ shift_offset = 1;
|
|
#endif
|
|
|
|
// +ve d
|
|
base = (HWord_t)&iargs[0];
|
|
for (i=0; i<nb_iargs; i++) {
|
|
- offs = i * sizeof(HWord_t);
|
|
+ offs = (i == 0) ? i : (i * sizeof(HWord_t)) - 1;
|
|
|
|
/* Patch up the instruction */
|
|
func = init_function( func_IN, func_buf );
|
|
- if (is_lwa)
|
|
+ if (shift_offset)
|
|
patch_op_imm(&func_buf[0], offs>>2, 2, 14);
|
|
else
|
|
patch_op_imm16(&func_buf[0], offs);
|
|
@@ -5557,8 +5569,8 @@ static void test_int_ld_one_reg_imm16 (c
|
|
|
|
// -ve d
|
|
base = (HWord_t)&iargs[nb_iargs-1];
|
|
- for (i = -nb_iargs+1; i<=0; i++) {
|
|
- offs = i * sizeof(HWord_t);
|
|
+ for (i = 0; i > -nb_iargs; i--) {
|
|
+ offs = (i * sizeof(HWord_t)) + 1;
|
|
|
|
/* Patch up the instruction */
|
|
func = init_function( func, func_buf );
|
|
@@ -5574,9 +5586,9 @@ static void test_int_ld_one_reg_imm16 (c
|
|
#ifndef __powerpc64__
|
|
printf("%s %2d, (%08x) => %08x, %2d (%08x %08x)\n",
|
|
#else
|
|
- printf("%s %3d, (%016llx) => %016llx, %3lld (%08x %08x)\n",
|
|
+ printf("%s %3d, (%016x) => %016llx, %3lld (%08x %08x)\n",
|
|
#endif
|
|
- name, offs, iargs[nb_iargs-1+i], res, r14-base, flags, xer);
|
|
+ name, offs, iargs[nb_iargs-1 + i], res, r14-base, flags, xer);
|
|
}
|
|
}
|
|
|
|
@@ -5767,7 +5779,6 @@ static void test_float_three_args (const
|
|
/* Note: using nb_normal_fargs:
|
|
- not testing special values for these insns
|
|
*/
|
|
-
|
|
for (i=0; i<nb_normal_fargs; i+=3) {
|
|
for (j=0; j<nb_normal_fargs; j+=5) {
|
|
for (k=0; k<nb_normal_fargs; k+=7) {
|
|
@@ -5965,10 +5976,11 @@ static void test_float_ld_one_reg_imm16
|
|
{
|
|
volatile test_func_t func;
|
|
uint32_t* func_buf = get_rwx_area();
|
|
- uint32_t base;
|
|
+ HWord_t base;
|
|
volatile uint32_t flags, xer;
|
|
volatile double src, res;
|
|
- int i, offs;
|
|
+ int i;
|
|
+ uint16_t offs;
|
|
|
|
/* offset within [1-nb_fargs:nb_fargs] */
|
|
for (i=1-nb_fargs; i<nb_fargs; i++) {
|
|
@@ -6016,7 +6028,7 @@ static void test_float_ld_two_regs (cons
|
|
volatile uint32_t flags, xer;
|
|
volatile double src, res;
|
|
int i, offs;
|
|
-
|
|
+
|
|
/* offset within [1-nb_fargs:nb_fargs] */
|
|
for (i=1-nb_fargs; i<nb_fargs; i++) {
|
|
offs = i * 8; // offset = i * sizeof(double)
|
|
@@ -6721,8 +6733,9 @@ static void lvs_cb (const char *name, te
|
|
volatile uint32_t flags, tmpcr;
|
|
volatile vector unsigned int tmpvscr;
|
|
volatile vector unsigned int vec_out, vscr;
|
|
- unsigned int *dst;
|
|
- int i;
|
|
+ unsigned shift;
|
|
+ unsigned char * dst;
|
|
+ int i, j;
|
|
#if defined TEST_VSCR_SAT
|
|
unsigned int* p_vscr;
|
|
#endif
|
|
@@ -6731,7 +6744,8 @@ static void lvs_cb (const char *name, te
|
|
vec_out = (vector unsigned int){ 0,0,0,0 };
|
|
|
|
// make sure start address is 16 aligned - use viargs[0]
|
|
- r15 = (HWord_t)&viargs[0];
|
|
+ HWord_t * r15_in_ptr = (HWord_t *)&viargs[0];
|
|
+ r15 = *r15_in_ptr;
|
|
r14 = i;
|
|
|
|
/* Save flags */
|
|
@@ -6758,11 +6772,18 @@ static void lvs_cb (const char *name, te
|
|
__asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
|
|
__asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
|
|
|
|
- dst = (unsigned int*)&vec_out;
|
|
+ dst = (unsigned char*)&vec_out;
|
|
|
|
- printf("%s %3d, %3d", name, i, 0);
|
|
- printf(" => %08x %08x %08x %08x ", dst[0], dst[1], dst[2], dst[3]);
|
|
- printf("(%08x)\n", flags);
|
|
+ shift = ((unsigned int)i + *r15_in_ptr) & 0xf;
|
|
+ printf("%s %x, %3d", name, shift, 0);
|
|
+ printf(" => 0x");
|
|
+ for (j = 0; j < 16; j++) {
|
|
+ printf("%02x", dst[j]);
|
|
+ if (j == 7)
|
|
+ printf(" 0x");
|
|
+ }
|
|
+
|
|
+ printf(" (%08x)\n", flags);
|
|
}
|
|
if (verbose) printf("\n");
|
|
}
|
|
Index: none/tests/ppc32/test_isa_2_06_part3.c
|
|
===================================================================
|
|
--- none/tests/ppc32/test_isa_2_06_part3.c.orig
|
|
+++ none/tests/ppc32/test_isa_2_06_part3.c
|
|
@@ -36,6 +36,12 @@ typedef uint32_t HWord_t;
|
|
typedef uint64_t HWord_t;
|
|
#endif /* __powerpc64__ */
|
|
|
|
+#ifdef VGP_ppc64le_linux
|
|
+#define isLE 1
|
|
+#else
|
|
+#define isLE 0
|
|
+#endif
|
|
+
|
|
typedef unsigned char Bool;
|
|
#define True 1
|
|
#define False 0
|
|
@@ -1116,7 +1122,7 @@ static void test_vsx_one_fp_arg(void)
|
|
|
|
for (i = 0; i < test_group.num_tests; i+=stride) {
|
|
unsigned int * pv;
|
|
- void * inB;
|
|
+ void * inB, * vecB_void_ptr = (void *)&vec_inB;
|
|
|
|
pv = (unsigned int *)&vec_out;
|
|
// clear vec_out
|
|
@@ -1129,11 +1135,15 @@ static void test_vsx_one_fp_arg(void)
|
|
for (j = 0; j < loops; j++) {
|
|
inB = (void *)&spec_fargs[i + j];
|
|
// copy double precision FP into vector element i
|
|
- memcpy(((void *)&vec_inB) + (j * 8), inB, 8);
|
|
+ if (isLE && is_scalar)
|
|
+ vecB_void_ptr += 8;
|
|
+ memcpy(vecB_void_ptr + (j * 8), inB, 8);
|
|
}
|
|
// execute test insn
|
|
(*func)();
|
|
dst_dp = (unsigned long long *) &vec_out;
|
|
+ if (isLE && is_scalar)
|
|
+ dst_dp++;
|
|
printf("#%d: %s ", i/stride, test_group.name);
|
|
for (j = 0; j < loops; j++) {
|
|
if (j)
|
|
@@ -1141,7 +1151,7 @@ static void test_vsx_one_fp_arg(void)
|
|
frB_dp = (unsigned long long *)&spec_fargs[i + j];
|
|
printf("%s(%016llx)", test_group.op, *frB_dp);
|
|
if (estimate) {
|
|
- Bool res = check_estimate(DOUBLE_TEST, is_sqrt, i + j, j);
|
|
+ Bool res = check_estimate(DOUBLE_TEST, is_sqrt, i + j, (isLE && is_scalar) ? 1: j);
|
|
printf(" ==> %s)", res ? "PASS" : "FAIL");
|
|
/* For debugging . . .
|
|
printf(" ==> %s (res=%016llx)", res ? "PASS" : "FAIL", dst_dp[j]);
|
|
@@ -1162,29 +1172,36 @@ static void test_vsx_one_fp_arg(void)
|
|
}
|
|
printf("\n");
|
|
} else {
|
|
- int j, skip_slot;
|
|
+ int j;
|
|
unsigned int * frB_sp, * dst_sp = NULL;
|
|
unsigned long long * dst_dp = NULL;
|
|
- if (sparse_sp) {
|
|
- skip_slot = 1;
|
|
+ if (sparse_sp)
|
|
loops = 2;
|
|
- } else {
|
|
- skip_slot = 0;
|
|
- }
|
|
for (j = 0; j < loops; j++) {
|
|
inB = (void *)&spec_sp_fargs[i + j];
|
|
// copy single precision FP into vector element i
|
|
- if (skip_slot && j > 0)
|
|
- memcpy(((void *)&vec_inB) + ((j + j) * 4), inB, 4);
|
|
- else
|
|
- memcpy(((void *)&vec_inB) + (j * 4), inB, 4);
|
|
+ if (sparse_sp) {
|
|
+ if (isLE)
|
|
+ memcpy(vecB_void_ptr + ((2 * j * 4) + 4), inB, 4);
|
|
+ else
|
|
+ memcpy(vecB_void_ptr + ((2 * j * 4) ), inB, 4);
|
|
+ } else {
|
|
+ if (isLE && is_scalar)
|
|
+ vecB_void_ptr += 12;
|
|
+ memcpy(vecB_void_ptr + (j * 4), inB, 4);
|
|
+ }
|
|
}
|
|
// execute test insn
|
|
(*func)();
|
|
- if (test_group.type == VX_CONV_TO_DOUBLE)
|
|
+ if (test_group.type == VX_CONV_TO_DOUBLE) {
|
|
dst_dp = (unsigned long long *) &vec_out;
|
|
- else
|
|
+ if (isLE && is_scalar)
|
|
+ dst_dp++;
|
|
+ } else {
|
|
dst_sp = (unsigned int *) &vec_out;
|
|
+ if (isLE && is_scalar)
|
|
+ dst_sp += 3;
|
|
+ }
|
|
// print result
|
|
printf("#%d: %s ", i/stride, test_group.name);
|
|
for (j = 0; j < loops; j++) {
|
|
@@ -1193,7 +1210,7 @@ static void test_vsx_one_fp_arg(void)
|
|
frB_sp = (unsigned int *)&spec_sp_fargs[i + j];
|
|
printf("%s(%08x)", test_group.op, *frB_sp);
|
|
if (estimate) {
|
|
- Bool res = check_estimate(SINGLE_TEST, is_sqrt, i + j, j);
|
|
+ Bool res = check_estimate(SINGLE_TEST, is_sqrt, i + j, (isLE && is_scalar) ? 3 : j);
|
|
printf(" ==> %s)", res ? "PASS" : "FAIL");
|
|
} else {
|
|
if (test_group.type == VX_CONV_TO_DOUBLE)
|
|
@@ -1275,23 +1292,24 @@ static void test_int_to_fp_convert(void)
|
|
}
|
|
printf("\n");
|
|
} else {
|
|
- int j, skip_slot;
|
|
+ int j;
|
|
unsigned int * dst_sp = NULL;
|
|
unsigned int * targs = test_group.targs;
|
|
unsigned long long * dst_dp = NULL;
|
|
- if (sparse_sp) {
|
|
- skip_slot = 1;
|
|
+ void * vecB_void_ptr = (void *)&vec_inB;
|
|
+ if (sparse_sp)
|
|
loops = 2;
|
|
- } else {
|
|
- skip_slot = 0;
|
|
- }
|
|
for (j = 0; j < loops; j++) {
|
|
inB = (void *)&targs[i + j];
|
|
// copy single word into vector element i
|
|
- if (skip_slot && j > 0)
|
|
- memcpy(((void *)&vec_inB) + ((j + j) * 4), inB, 4);
|
|
- else
|
|
- memcpy(((void *)&vec_inB) + (j * 4), inB, 4);
|
|
+ if (sparse_sp) {
|
|
+ if (isLE)
|
|
+ memcpy(vecB_void_ptr + ((2 * j * 4) + 4), inB, 4);
|
|
+ else
|
|
+ memcpy(vecB_void_ptr + ((2 * j * 4) ), inB, 4);
|
|
+ } else {
|
|
+ memcpy(vecB_void_ptr + (j * 4), inB, 4);
|
|
+ }
|
|
}
|
|
// execute test insn
|
|
(*func)();
|
|
@@ -1441,7 +1459,7 @@ static void test_vx_tdivORtsqrt(void)
|
|
|
|
for (i = 0; i < test_group.num_tests; i+=stride) {
|
|
unsigned int * pv;
|
|
- void * inB;
|
|
+ void * inB, * vecB_void_ptr = (void *)&vec_inB;
|
|
|
|
pv = (unsigned int *)&vec_out;
|
|
// clear vec_out
|
|
@@ -1457,7 +1475,9 @@ static void test_vx_tdivORtsqrt(void)
|
|
for (j = 0; j < loops; j++) {
|
|
inB = (void *)&spec_fargs[i + j];
|
|
// copy double precision FP into vector element i
|
|
- memcpy(((void *)&vec_inB) + (j * 8), inB, 8);
|
|
+ if (isLE && is_scalar)
|
|
+ vecB_void_ptr += 8;
|
|
+ memcpy(vecB_void_ptr + (j * 8), inB, 8);
|
|
}
|
|
}
|
|
// execute test insn
|
|
Index: none/tests/ppc32/jm_vec_isa_2_07.stdout.exp
|
|
===================================================================
|
|
--- none/tests/ppc32/jm_vec_isa_2_07.stdout.exp.orig
|
|
+++ none/tests/ppc32/jm_vec_isa_2_07.stdout.exp
|
|
@@ -443,9 +443,9 @@ vsubuqm: 0102030405060708090a0b0c0e0d0e0
|
|
vsubuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0
|
|
vsubuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
|
|
|
|
-vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 0000000000000000000000000000020a
|
|
+vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 000000000000020a0000000000000000
|
|
vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
|
|
-vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> 0000000000000000000000000000e3ea
|
|
+vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> 000000000000e3ea0000000000000000
|
|
vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
|
|
|
|
vaddecuq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> 00000000000000000000000000000000
|
|
Index: none/tests/ppc32/test_dfp5.c
|
|
===================================================================
|
|
--- none/tests/ppc32/test_dfp5.c.orig
|
|
+++ none/tests/ppc32/test_dfp5.c
|
|
@@ -31,8 +31,13 @@ typedef union stuff {
|
|
_Decimal128 dec_val128;
|
|
unsigned long long u64_val;
|
|
struct {
|
|
+#if defined(VGP_ppc64le_linux)
|
|
+ unsigned long long vall;
|
|
+ unsigned long long valu;
|
|
+#else
|
|
unsigned long long valu;
|
|
unsigned long long vall;
|
|
+#endif
|
|
} u128;
|
|
} dfp_val_t;
|
|
|
|
@@ -418,22 +423,20 @@ static void test_dfp_ddedpd_ops(void)
|
|
test_val.u64_val = dfp64_vals[i];
|
|
} else {
|
|
test_val.u128.valu = dfp128_vals[i * 2];
|
|
- test_val.u64_val = test_val.u128.valu;
|
|
test_val.u128.vall = dfp128_vals[(i * 2) + 1];
|
|
}
|
|
|
|
for (SP = 0; SP < 4; SP++) {
|
|
dfp_val_t result;
|
|
result = (*func)(SP, test_val);
|
|
- printf("%s (SP=%d) %s%016llx", test_def.name, SP,
|
|
- test_def.op, test_val.u64_val);
|
|
- if (test_def.precision == QUAD_TEST) {
|
|
- printf(" %016llx", test_val.u128.vall);
|
|
+ printf("%s (SP=%d) %s", test_def.name, SP, test_def.op);
|
|
+ if (test_def.precision == LONG_TEST) {
|
|
+ printf("%016llx ==> %016llx\n", test_val.u64_val, result.u64_val);
|
|
+ } else {
|
|
+ printf("%016llx %016llx ==> %016llx %016llx\n",
|
|
+ test_val.u128.valu, test_val.u128.vall,
|
|
+ result.u128.valu, result.u128.vall);
|
|
}
|
|
- if (test_def.precision == LONG_TEST)
|
|
- printf(" ==> %016llx\n", result.u64_val);
|
|
- else
|
|
- printf(" ==> %016llx %016llx\n", result.u128.valu, result.u128.vall);
|
|
}
|
|
}
|
|
k++;
|
|
@@ -484,20 +487,18 @@ static void test_dfp_denbcd_ops(void)
|
|
test_val.u64_val = bcd64_vals[i];
|
|
} else {
|
|
test_val.u128.valu = bcd128_vals[i * 2];
|
|
- test_val.u64_val = test_val.u128.valu;
|
|
test_val.u128.vall = bcd128_vals[(i * 2) + 1];
|
|
}
|
|
|
|
result = (*func)(S, test_val);
|
|
- printf("%s (S=%d) %s%016llx", test_def.name, S,
|
|
- test_def.op, test_val.u64_val);
|
|
- if (test_def.precision == QUAD_TEST) {
|
|
- printf(" %016llx", test_val.u128.vall);
|
|
+ printf("%s (S=%d) %s", test_def.name, S, test_def.op);
|
|
+ if (test_def.precision == LONG_TEST) {
|
|
+ printf("%016llx ==> %016llx\n", test_val.u64_val, result.u64_val);
|
|
+ } else {
|
|
+ printf("%016llx %016llx ==> %016llx %016llx\n",
|
|
+ test_val.u128.valu, test_val.u128.vall,
|
|
+ result.u128.valu, result.u128.vall);
|
|
}
|
|
- if (test_def.precision == LONG_TEST)
|
|
- printf(" ==> %016llx\n", result.u64_val);
|
|
- else
|
|
- printf(" ==> %016llx %016llx\n", result.u128.valu, result.u128.vall);
|
|
}
|
|
}
|
|
k++;
|
|
@@ -532,7 +533,6 @@ static void test_dfp_test_significance_o
|
|
test_valB.u64_val = dfp64_vals[i];
|
|
} else {
|
|
test_valB.u128.valu = dfp128_vals[i * 2];
|
|
- test_valB.u64_val = test_valB.u128.valu;
|
|
test_valB.u128.vall = dfp128_vals[(i * 2) + 1];
|
|
}
|
|
|
|
@@ -549,10 +549,11 @@ static void test_dfp_test_significance_o
|
|
GET_CR(flags);
|
|
|
|
condreg = ((flags >> (4 * (7-BF)))) & 0xf;
|
|
- printf("%s (ref_sig=%d) %s%016llx", test_def.name, reference_sig,
|
|
- test_def.op, test_valB.u64_val);
|
|
- if (test_def.precision == QUAD_TEST) {
|
|
- printf(" %016llx", test_valB.u128.vall);
|
|
+ printf("%s (ref_sig=%d) %s", test_def.name, reference_sig, test_def.op);
|
|
+ if (test_def.precision == LONG_TEST) {
|
|
+ printf("%016llx", test_valB.u64_val);
|
|
+ } else {
|
|
+ printf("%016llx %016llx", test_valB.u128.valu, test_valB.u128.vall);
|
|
}
|
|
printf(" => %x (BF=%d)\n", condreg, BF);
|
|
}
|
|
Index: none/tests/ppc32/test_isa_2_06_part1.stdout.exp
|
|
===================================================================
|
|
--- none/tests/ppc32/test_isa_2_06_part1.stdout.exp.orig
|
|
+++ none/tests/ppc32/test_isa_2_06_part1.stdout.exp
|
|
@@ -130,13 +130,27 @@ ftdiv: 0000000000000000 <=> 000000000000
|
|
ftdiv: 0000000000000000 <=> 8000000000000000 ? e (CRx)
|
|
|
|
Test VSX move instructions
|
|
-xsabsdp: 01234567 89abcdef xsabsdp 8899aabb 91929394x => 0899aabb 91929394
|
|
-
|
|
-xscpsgndp: 8899aabb 91929394 xscpsgndp 01234567 89abcdefx => 81234567 89abcdef
|
|
-
|
|
-xsnabsdp: b1b2b3b4 c1c2c3c4 xsnabsdp 44556677 8899aabbx => c4556677 8899aabb
|
|
-
|
|
-xsnegdp: 01234567 89abcdef xsnegdp b1b2b3b4 c1c2c3c4x => 31b2b3b4 c1c2c3c4
|
|
+xsabsdp: X[B]: 0123456789abcdef => 0123456789abcdef
|
|
+xsabsdp: X[B]: 8899aabb19293942 => 0899aabb19293942
|
|
+xsabsdp: X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4
|
|
+
|
|
+xscpsgndp: X[A]: 0123456789abcdef X[B]: 0123456789abcdef => 0123456789abcdef
|
|
+xscpsgndp: X[A]: 8899aabb19293942 X[B]: 0123456789abcdef => 8123456789abcdef
|
|
+xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: 0123456789abcdef => 8123456789abcdef
|
|
+xscpsgndp: X[A]: 0123456789abcdef X[B]: 8899aabb19293942 => 0899aabb19293942
|
|
+xscpsgndp: X[A]: 8899aabb19293942 X[B]: 8899aabb19293942 => 8899aabb19293942
|
|
+xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: 8899aabb19293942 => 8899aabb19293942
|
|
+xscpsgndp: X[A]: 0123456789abcdef X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4
|
|
+xscpsgndp: X[A]: 8899aabb19293942 X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4
|
|
+xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4
|
|
+
|
|
+xsnabsdp: X[B]: 0123456789abcdef => 8123456789abcdef
|
|
+xsnabsdp: X[B]: 8899aabb19293942 => 8899aabb19293942
|
|
+xsnabsdp: X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4
|
|
+
|
|
+xsnegdp: X[B]: 0123456789abcdef => 8123456789abcdef
|
|
+xsnegdp: X[B]: 8899aabb19293942 => 0899aabb19293942
|
|
+xsnegdp: X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4
|
|
|
|
Test VSX permute instructions
|
|
xxmrghw:
|
|
@@ -1020,4 +1034,3 @@ Test VSX scalar integer conversion instr
|
|
#14: xscvuxddp c0d0650f5a07b353 => 43e81a0ca1eb40f6
|
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|
|
|
|
-Testcase PASSED
|
|
Index: none/tests/ppc32/round.stdout.exp
|
|
===================================================================
|
|
--- none/tests/ppc32/round.stdout.exp.orig
|
|
+++ none/tests/ppc32/round.stdout.exp
|
|
@@ -324,38 +324,38 @@ zero:PASSED:fsubs(1.125000 , 0x1.000
|
|
+inf:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1p+0
|
|
+inf:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1p+0
|
|
+inf:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1p+0
|
|
-+inf:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0
|
|
-+inf:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000004p+0
|
|
-+inf:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000004p+0
|
|
-+inf:PASSED:fsubs(1.125000 , 0x1.000006p-3) = 0x1.000004p+0
|
|
-+inf:PASSED:fsubs(1.125000 , 0x1.000008p-3) = 0x1.000004p+0
|
|
-+inf:PASSED:fsubs(1.125000 , 0x1.00000ap-3) = 0x1.000004p+0
|
|
-+inf:PASSED:fsubs(1.125000 , 0x1.00000cp-3) = 0x1.000004p+0
|
|
-+inf:PASSED:fsubs(1.125000 , 0x1.00000ep-3) = 0x1.000004p+0
|
|
-+inf:PASSED:fsubs(1.125000 , 0x1.00001p-3 ) = 0x1.000002p+0
|
|
-+inf:PASSED:fsubs(1.125000 , 0x1.000012p-3) = 0x1.000002p+0
|
|
-+inf:PASSED:fsubs(1.125000 , 0x1.000014p-3) = 0x1.000002p+0
|
|
-+inf:PASSED:fsubs(1.125000 , 0x1.000016p-3) = 0x1.000002p+0
|
|
-+inf:PASSED:fsubs(1.125000 , 0x1.000018p-3) = 0x1.000002p+0
|
|
-+inf:PASSED:fsubs(1.125000 , 0x1.00001ap-3) = 0x1.000002p+0
|
|
-+inf:PASSED:fsubs(1.125000 , 0x1.00001cp-3) = 0x1.000002p+0
|
|
-+inf:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1.000002p+0
|
|
--inf:PASSED:fsubs(-1.125000 , -0x1p-3 ) = -0x1.000004p+0
|
|
--inf:PASSED:fsubs(-1.125000 , -0x1.000002p-3) = -0x1.000004p+0
|
|
--inf:PASSED:fsubs(-1.125000 , -0x1.000004p-3) = -0x1.000004p+0
|
|
--inf:PASSED:fsubs(-1.125000 , -0x1.000006p-3) = -0x1.000004p+0
|
|
--inf:PASSED:fsubs(-1.125000 , -0x1.000008p-3) = -0x1.000004p+0
|
|
--inf:PASSED:fsubs(-1.125000 , -0x1.00000ap-3) = -0x1.000004p+0
|
|
--inf:PASSED:fsubs(-1.125000 , -0x1.00000cp-3) = -0x1.000004p+0
|
|
--inf:PASSED:fsubs(-1.125000 , -0x1.00000ep-3) = -0x1.000004p+0
|
|
--inf:PASSED:fsubs(-1.125000 , -0x1.00001p-3) = -0x1.000002p+0
|
|
--inf:PASSED:fsubs(-1.125000 , -0x1.000012p-3) = -0x1.000002p+0
|
|
--inf:PASSED:fsubs(-1.125000 , -0x1.000014p-3) = -0x1.000002p+0
|
|
--inf:PASSED:fsubs(-1.125000 , -0x1.000016p-3) = -0x1.000002p+0
|
|
--inf:PASSED:fsubs(-1.125000 , -0x1.000018p-3) = -0x1.000002p+0
|
|
--inf:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1.000002p+0
|
|
--inf:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1.000002p+0
|
|
--inf:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1.000002p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1p-3 ) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000002p-3) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000004p-3) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000006p-3) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000008p-3) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.00000ap-3) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.00000cp-3) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.00000ep-3) = 0x1.000004p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.00001p-3 ) = 0x1.000002p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000012p-3) = 0x1.000002p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000014p-3) = 0x1.000002p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000016p-3) = 0x1.000002p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.000018p-3) = 0x1.000002p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.00001ap-3) = 0x1.000002p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.00001cp-3) = 0x1.000002p+0
|
|
++inf:PASSED:fsubs(1.125001 , 0x1.00001ep-3) = 0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1p-3 ) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000002p-3) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000004p-3) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000006p-3) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000008p-3) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.00000ap-3) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.00000cp-3) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.00000ep-3) = -0x1.000004p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.00001p-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000012p-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000014p-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000016p-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.000018p-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.00001ap-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.00001cp-3) = -0x1.000002p+0
|
|
+-inf:PASSED:fsubs(-1.125001 , -0x1.00001ep-3) = -0x1.000002p+0
|
|
-inf:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0
|
|
-inf:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000002p+0
|
|
-inf:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000002p+0
|
|
@@ -409,78 +409,78 @@ zero:PASSED:fmuls(-1.000000 , 0x1.2p+
|
|
zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0
|
|
zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0
|
|
zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0
|
|
-zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ap+0
|
|
-zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0
|
|
-zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0
|
|
-zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0
|
|
+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0
|
|
+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000cp+0
|
|
+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ep+0
|
|
+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200012p+0
|
|
zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0
|
|
zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0
|
|
zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0
|
|
zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0
|
|
-zero:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001cp+0
|
|
-zero:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0
|
|
-zero:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0
|
|
+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0
|
|
+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ep+0
|
|
+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20002p+0
|
|
zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0
|
|
zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200002p+0
|
|
zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0
|
|
zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0
|
|
zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0
|
|
-zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ap+0
|
|
-zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0
|
|
-zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0
|
|
-zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0
|
|
+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0
|
|
+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000cp+0
|
|
+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ep+0
|
|
+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200012p+0
|
|
zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0
|
|
zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0
|
|
zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0
|
|
zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0
|
|
-zero:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001cp+0
|
|
-zero:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0
|
|
-zero:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0
|
|
+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0
|
|
+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ep+0
|
|
+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20002p+0
|
|
+inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0
|
|
+inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0
|
|
+inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0
|
|
+inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0
|
|
+inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0
|
|
-+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ap+0
|
|
-+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0
|
|
-+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0
|
|
-+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0
|
|
++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0
|
|
++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000cp+0
|
|
++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ep+0
|
|
++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200012p+0
|
|
+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0
|
|
+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0
|
|
+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0
|
|
+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0
|
|
-+inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001cp+0
|
|
-+inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0
|
|
-+inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0
|
|
++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0
|
|
++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ep+0
|
|
++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20002p+0
|
|
+inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0
|
|
-+inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0
|
|
-+inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0
|
|
-+inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0
|
|
-+inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0
|
|
++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200004p+0
|
|
++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200006p+0
|
|
++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200008p+0
|
|
++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ap+0
|
|
+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0
|
|
+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0
|
|
+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001p+0
|
|
+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0
|
|
-+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0
|
|
-+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0
|
|
-+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0
|
|
-+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0
|
|
++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200016p+0
|
|
++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200018p+0
|
|
++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ap+0
|
|
++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001cp+0
|
|
+inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0
|
|
+inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0
|
|
+inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200022p+0
|
|
-inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0
|
|
--inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0
|
|
--inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0
|
|
--inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0
|
|
--inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0
|
|
+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200004p+0
|
|
+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200006p+0
|
|
+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200008p+0
|
|
+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ap+0
|
|
-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0
|
|
-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0
|
|
-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001p+0
|
|
-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0
|
|
--inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0
|
|
--inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0
|
|
--inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0
|
|
--inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0
|
|
+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200016p+0
|
|
+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200018p+0
|
|
+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ap+0
|
|
+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001cp+0
|
|
-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0
|
|
-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0
|
|
-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200022p+0
|
|
@@ -489,17 +489,17 @@ zero:PASSED:fmuls(1.000002 , 0x1.2p+
|
|
-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0
|
|
-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0
|
|
-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0
|
|
--inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ap+0
|
|
--inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0
|
|
--inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0
|
|
--inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0
|
|
+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0
|
|
+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000cp+0
|
|
+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ep+0
|
|
+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200012p+0
|
|
-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0
|
|
-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0
|
|
-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0
|
|
-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0
|
|
--inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001cp+0
|
|
--inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0
|
|
--inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0
|
|
+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0
|
|
+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ep+0
|
|
+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20002p+0
|
|
near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
near:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0
|
|
near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
@@ -566,35 +566,35 @@ zero:PASSED:fdivs(0.000000 , 0x1p+3
|
|
zero:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b12p+0
|
|
+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
+inf:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0
|
|
-+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0
|
|
+inf:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec4p+0
|
|
-+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0
|
|
+inf:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745cp+0
|
|
-+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0
|
|
+inf:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f4p+0
|
|
-+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
|
|
+inf:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92492p+0
|
|
-+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
|
|
+inf:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f6p+0
|
|
-+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
|
|
+inf:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f6p+0
|
|
-+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
|
++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
|
|
+inf:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b12p+0
|
|
+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
|
+inf:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f72p+0
|
|
-+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
|
|
+inf:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec6p+0
|
|
-+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
|
|
+inf:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745ep+0
|
|
-+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
|
|
+inf:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f6p+0
|
|
-+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
|
++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
|
|
+inf:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92494p+0
|
|
-+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148
|
|
++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148
|
|
+inf:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f8p+0
|
|
-+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148
|
|
++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148
|
|
+inf:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f8p+0
|
|
-+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148
|
|
++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148
|
|
+inf:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b14p+0
|
|
-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
|
-inf:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f72p+0
|
|
@@ -665,78 +665,78 @@ zero:PASSED:fmadds(-1.000000 , 0x1.2p
|
|
zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
-zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
|
-zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
-zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
-zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
|
+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
|
+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
|
zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
|
zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
-zero:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
|
-zero:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
-zero:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
|
+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
|
|
zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
|
|
zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
-zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
|
-zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
-zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
-zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
|
+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
|
+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
|
zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
|
zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
-zero:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
|
-zero:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
-zero:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
|
+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
+inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
|
|
+inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
|
|
+inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
+inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
+inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
-+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
|
-+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
-+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
-+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
|
++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
|
++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
|
+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
|
+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
-+inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
|
-+inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
-+inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
|
++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
+inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
|
|
-+inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
-+inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
-+inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
|
|
-+inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
|
|
++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
|
+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
|
-+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
-+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
-+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
|
|
-+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
|
|
++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
+inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
+inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
+inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00024p+0
|
|
-inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
|
|
--inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
--inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
--inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
|
|
--inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
|
|
+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
|
-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
|
--inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
--inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
--inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
|
|
--inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
|
|
+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00024p+0
|
|
@@ -745,17 +745,17 @@ zero:PASSED:fmadds(1.000002 , 0x1.2p
|
|
-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
--inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
|
--inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
--inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
--inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
|
+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
|
+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
|
-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
|
-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
--inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
|
--inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
--inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
|
+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
|
|
near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
@@ -793,78 +793,78 @@ zero:PASSED:fmsubs(-1.000000 , 0x1.2p
|
|
zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
-zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
|
-zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
-zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
-zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
|
+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
|
+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
|
zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
|
zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
-zero:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
|
-zero:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
-zero:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
|
+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
|
|
zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
|
|
zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
-zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
|
-zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
-zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
-zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
|
+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
|
+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
|
zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
|
zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
-zero:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
|
-zero:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
-zero:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
|
+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
+inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
|
|
+inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
|
|
+inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
+inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
+inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
-+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
|
-+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
-+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
-+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
|
++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
|
++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
|
+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
|
+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
-+inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
|
-+inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
-+inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
|
++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
+inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
|
|
-+inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
-+inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
-+inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
|
|
-+inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
|
|
++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
|
+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
|
-+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
-+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
-+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
|
|
-+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
|
|
++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
+inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
+inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
+inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00024p+0
|
|
-inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
|
|
--inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
--inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
--inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
|
|
--inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
|
|
+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
|
-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
|
--inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
--inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
--inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
|
|
--inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
|
|
+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00024p+0
|
|
@@ -873,17 +873,17 @@ zero:PASSED:fmsubs(1.000002 , 0x1.2p
|
|
-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
--inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
|
--inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
--inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
--inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
|
+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
|
+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
|
-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
|
-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
--inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
|
--inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
--inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
|
+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
|
|
near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
@@ -921,78 +921,78 @@ zero:PASSED:fnmadds(-1.000000 , 0x1.2
|
|
zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
-zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
|
-zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
-zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
-zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
|
+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
|
+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
|
zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
|
zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
-zero:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
|
-zero:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
-zero:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
|
+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
|
|
zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
|
|
zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
-zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
|
-zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
-zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
-zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
|
+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
|
+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
|
zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
|
zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
-zero:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
|
-zero:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
-zero:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
|
+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
+inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
|
|
+inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
|
|
+inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
+inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
+inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
-+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
|
-+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
-+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
-+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
|
++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
|
++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
|
+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
|
+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
-+inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
|
-+inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
-+inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
|
++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
+inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
|
|
-+inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
-+inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
-+inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
|
|
-+inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
|
|
++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
|
+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
|
-+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
-+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
-+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
|
|
-+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
|
|
++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
+inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
+inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
+inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00024p+0
|
|
-inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
|
|
--inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
--inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
--inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
|
|
--inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
|
+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
|
+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
|
|
+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
|
-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
|
-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
|
-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
|
-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
|
--inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
--inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
--inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
|
|
--inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
|
+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
|
+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
|
|
+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
|
-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
|
-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
|
-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00024p+0
|
|
@@ -1001,17 +1001,17 @@ zero:PASSED:fnmadds(1.000002 , 0x1.2
|
|
-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
|
-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
|
-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
|
--inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
|
--inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
--inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
--inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
|
+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
|
+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
|
+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
|
+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
|
-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
|
-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
|
-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
|
-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
|
--inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
|
--inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
--inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
|
+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
|
+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
|
near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
|
|
near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
@@ -1049,78 +1049,78 @@ zero:PASSED:fnmsubs(-1.000000 , 0x1.2
|
|
zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
-zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
|
-zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
-zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
-zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
|
+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
|
+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
|
zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
|
zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
-zero:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
|
-zero:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
-zero:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
|
+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
|
|
zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
|
|
zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
-zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
|
-zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
-zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
-zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
|
+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
|
+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
|
zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
|
zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
-zero:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
|
-zero:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
-zero:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
|
+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
+inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
|
|
+inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
|
|
+inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
+inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
+inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
-+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
|
-+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
-+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
-+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
|
++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
|
++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
|
+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
|
+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
-+inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
|
-+inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
-+inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
|
++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
+inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
|
|
-+inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
-+inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
-+inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
|
|
-+inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
|
|
++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
|
+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
|
-+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
-+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
-+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
|
|
-+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
|
|
++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
+inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
+inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
+inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00024p+0
|
|
-inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
|
|
--inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
--inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
--inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
|
|
--inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
|
+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
|
+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
|
|
+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
|
-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
|
-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
|
-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
|
-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
|
--inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
--inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
--inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
|
|
--inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
|
+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
|
+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
|
|
+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
|
-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
|
-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
|
-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00024p+0
|
|
@@ -1129,17 +1129,17 @@ zero:PASSED:fnmsubs(1.000002 , 0x1.2
|
|
-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
|
-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
|
-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
|
--inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
|
--inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
--inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
--inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
|
+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
|
+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
|
+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
|
+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
|
-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
|
-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
|
-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
|
-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
|
--inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
|
--inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
--inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
|
+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
|
+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
|
-------------------------- test rounding of double operators with guard bits --------------------------
|
|
near:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0
|
|
near:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2p+0
|
|
Index: none/tests/ppc32/jm-fp.stdout.exp-BE2
|
|
===================================================================
|
|
--- /dev/null
|
|
+++ none/tests/ppc32/jm-fp.stdout.exp-BE2
|
|
@@ -0,0 +1,1431 @@
|
|
+PPC floating point arith insns with three args:
|
|
+ fsel 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000
|
|
+ fsel 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300
|
|
+ fsel 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
|
|
+ fsel 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000
|
|
+ fsel 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300
|
|
+ fsel 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
|
|
+ fsel bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fsel bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fsel bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fmadd 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100
|
|
+ fmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00
|
|
+ fmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000
|
|
+ fmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100
|
|
+ fmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fmadds 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+
|
|
+ fmsub 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
|
|
+ fmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
|
|
+ fmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00
|
|
+ fmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100
|
|
+ fmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000
|
|
+ fmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00
|
|
+ fmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+
|
|
+ fmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+
|
|
+ fnmadd 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
|
|
+ fnmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
|
|
+ fnmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100
|
|
+ fnmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00
|
|
+ fnmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000
|
|
+ fnmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100
|
|
+ fnmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+
|
|
+ fnmadds 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+
|
|
+ fnmsub 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fnmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fnmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00
|
|
+ fnmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100
|
|
+ fnmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000
|
|
+ fnmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00
|
|
+ fnmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fnmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+
|
|
+PPC floating point arith insns
|
|
+ with three args with flags update:
|
|
+ fsel. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel. 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000
|
|
+ fsel. 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300
|
|
+ fsel. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
|
|
+ fsel. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000
|
|
+ fsel. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300
|
|
+ fsel. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
|
|
+ fsel. bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fsel. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fsel. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fsel. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100
|
|
+ fmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00
|
|
+ fmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000
|
|
+ fmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100
|
|
+ fmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+
|
|
+ fmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
|
|
+ fmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
|
|
+ fmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00
|
|
+ fmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100
|
|
+ fmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000
|
|
+ fmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00
|
|
+ fmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+
|
|
+ fmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+
|
|
+ fnmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
|
|
+ fnmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
|
|
+ fnmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100
|
|
+ fnmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00
|
|
+ fnmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000
|
|
+ fnmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
|
|
+ fnmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100
|
|
+ fnmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
|
|
+
|
|
+ fnmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
|
|
+ fnmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
|
|
+ fnmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
|
|
+
|
|
+ fnmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
|
|
+ fnmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
|
|
+ fnmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00
|
|
+ fnmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100
|
|
+ fnmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000
|
|
+ fnmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
|
|
+ fnmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00
|
|
+ fnmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
|
|
+
|
|
+ fnmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
|
|
+ fnmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fnmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
|
|
+
|
|
+PPC floating point arith insns with two args:
|
|
+ fadd 0010000000000001, 0010000000000001 => 0020000000000001
|
|
+ fadd 0010000000000001, 80100094e0000359 => 80000094e0000358
|
|
+ fadd 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadd 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
|
|
+ fadd 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
|
|
+ fadd 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fadd bfe0000000000001, 0010000000000001 => bfe0000000000001
|
|
+ fadd bfe0000000000001, 80100094e0000359 => bfe0000000000001
|
|
+ fadd bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadd 8000000000000000, 0010000000000001 => 0010000000000001
|
|
+ fadd 8000000000000000, 80100094e0000359 => 80100094e0000359
|
|
+ fadd 8000000000000000, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fadd 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fadd 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fadd 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fadd 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fadd fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fadd fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fadd fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fadd fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fadds 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fadds 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fadds 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadds 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
|
|
+ fadds 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
|
|
+ fadds 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fadds bfe0000000000001, 0010000000000001 => bfe0000000000000
|
|
+ fadds bfe0000000000001, 80100094e0000359 => bfe0000000000000
|
|
+ fadds bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadds 8000000000000000, 0010000000000001 => 0000000000000000
|
|
+ fadds 8000000000000000, 80100094e0000359 => 8000000000000000
|
|
+ fadds 8000000000000000, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fadds 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fadds 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fadds 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fadds 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fadds fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fadds fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fadds fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fadds fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fsub 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fsub 0010000000000001, 80100094e0000359 => 0020004a700001ad
|
|
+ fsub 0010000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsub 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsub 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
|
|
+ fsub 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
|
|
+ fsub 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
|
|
+ fsub 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fsub bfe0000000000001, 0010000000000001 => bfe0000000000001
|
|
+ fsub bfe0000000000001, 80100094e0000359 => bfe0000000000001
|
|
+ fsub bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsub bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsub 8000000000000000, 0010000000000001 => 8010000000000001
|
|
+ fsub 8000000000000000, 80100094e0000359 => 00100094e0000359
|
|
+ fsub 8000000000000000, 7ff0000000000000 => fff0000000000000
|
|
+ fsub 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fsub 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fsub 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fsub 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fsub 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fsub fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fsub fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fsub fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fsub fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fsubs 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fsubs 0010000000000001, 80100094e0000359 => 0000000000000000
|
|
+ fsubs 0010000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsubs 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
|
|
+ fsubs 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
|
|
+ fsubs 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fsubs bfe0000000000001, 0010000000000001 => bfe0000000000000
|
|
+ fsubs bfe0000000000001, 80100094e0000359 => bfe0000000000000
|
|
+ fsubs bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsubs 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fsubs 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fsubs 8000000000000000, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fsubs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fsubs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fsubs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fsubs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fsubs fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fsubs fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fsubs fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fsubs fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fmul 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmul 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fmul 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmul 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmul 3fe00094e0000359, 0010000000000001 => 0008004a700001ad
|
|
+ fmul 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179
|
|
+ fmul 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmul 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fmul bfe0000000000001, 0010000000000001 => 8008000000000001
|
|
+ fmul bfe0000000000001, 80100094e0000359 => 0008004a700001ad
|
|
+ fmul bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fmul bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmul 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fmul 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fmul 8000000000000000, 7ff0000000000000 => 7ff8000000000000
|
|
+ fmul 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fmul 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fmul 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fmul 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fmul 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fmul fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fmul fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fmul fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fmul fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fmuls 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmuls 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fmuls 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmuls 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmuls 3fe00094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmuls 3fe00094e0000359, 80100094e0000359 => 8000000000000000
|
|
+ fmuls 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmuls 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fmuls bfe0000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmuls bfe0000000000001, 80100094e0000359 => 0000000000000000
|
|
+ fmuls bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fmuls bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmuls 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fmuls 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fmuls 8000000000000000, 7ff0000000000000 => 7ff8000000000000
|
|
+ fmuls 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fmuls 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fmuls 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fmuls 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fmuls 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fmuls fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fmuls fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fmuls fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fmuls fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fdiv 0010000000000001, 0010000000000001 => 3ff0000000000000
|
|
+ fdiv 0010000000000001, 80100094e0000359 => bfeffed64ad20d22
|
|
+ fdiv 0010000000000001, 7ff0000000000000 => 0000000000000000
|
|
+ fdiv 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdiv 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358
|
|
+ fdiv 3fe00094e0000359, 80100094e0000359 => ffc0000000000000
|
|
+ fdiv 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
|
|
+ fdiv 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fdiv bfe0000000000001, 0010000000000001 => ffc0000000000000
|
|
+ fdiv bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22
|
|
+ fdiv bfe0000000000001, 7ff0000000000000 => 8000000000000000
|
|
+ fdiv bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdiv 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fdiv 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fdiv 8000000000000000, 7ff0000000000000 => 8000000000000000
|
|
+ fdiv 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fdiv 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fdiv 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fdiv 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fdiv 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fdiv fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fdiv fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fdiv fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fdiv fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fdivs 0010000000000001, 0010000000000001 => 3ff0000000000000
|
|
+ fdivs 0010000000000001, 80100094e0000359 => bfeffed640000000
|
|
+ fdivs 0010000000000001, 7ff0000000000000 => 0000000000000000
|
|
+ fdivs 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdivs 3fe00094e0000359, 0010000000000001 => 7ff0000000000000
|
|
+ fdivs 3fe00094e0000359, 80100094e0000359 => fff0000000000000
|
|
+ fdivs 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
|
|
+ fdivs 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fdivs bfe0000000000001, 0010000000000001 => fff0000000000000
|
|
+ fdivs bfe0000000000001, 80100094e0000359 => 7ff0000000000000
|
|
+ fdivs bfe0000000000001, 7ff0000000000000 => 8000000000000000
|
|
+ fdivs bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdivs 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fdivs 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fdivs 8000000000000000, 7ff0000000000000 => 8000000000000000
|
|
+ fdivs 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fdivs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fdivs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fdivs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fdivs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fdivs fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fdivs fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fdivs fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fdivs fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+PPC floating point arith insns
|
|
+ with two args with flags update:
|
|
+ fadd. 0010000000000001, 0010000000000001 => 0020000000000001
|
|
+ fadd. 0010000000000001, 80100094e0000359 => 80000094e0000358
|
|
+ fadd. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadd. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
|
|
+ fadd. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
|
|
+ fadd. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fadd. bfe0000000000001, 0010000000000001 => bfe0000000000001
|
|
+ fadd. bfe0000000000001, 80100094e0000359 => bfe0000000000001
|
|
+ fadd. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadd. 8000000000000000, 0010000000000001 => 0010000000000001
|
|
+ fadd. 8000000000000000, 80100094e0000359 => 80100094e0000359
|
|
+ fadd. 8000000000000000, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadd. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fadd. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fadd. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fadd. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fadd. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fadd. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fadd. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fadd. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fadd. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fadds. 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fadds. 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fadds. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadds. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
|
|
+ fadds. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
|
|
+ fadds. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fadds. bfe0000000000001, 0010000000000001 => bfe0000000000000
|
|
+ fadds. bfe0000000000001, 80100094e0000359 => bfe0000000000000
|
|
+ fadds. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fadds. 8000000000000000, 0010000000000001 => 0000000000000000
|
|
+ fadds. 8000000000000000, 80100094e0000359 => 8000000000000000
|
|
+ fadds. 8000000000000000, 7ff0000000000000 => 7ff0000000000000
|
|
+ fadds. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fadds. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fadds. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fadds. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fadds. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fadds. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fadds. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fadds. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fadds. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fsub. 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fsub. 0010000000000001, 80100094e0000359 => 0020004a700001ad
|
|
+ fsub. 0010000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsub. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsub. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
|
|
+ fsub. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
|
|
+ fsub. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
|
|
+ fsub. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fsub. bfe0000000000001, 0010000000000001 => bfe0000000000001
|
|
+ fsub. bfe0000000000001, 80100094e0000359 => bfe0000000000001
|
|
+ fsub. bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsub. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsub. 8000000000000000, 0010000000000001 => 8010000000000001
|
|
+ fsub. 8000000000000000, 80100094e0000359 => 00100094e0000359
|
|
+ fsub. 8000000000000000, 7ff0000000000000 => fff0000000000000
|
|
+ fsub. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fsub. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fsub. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fsub. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fsub. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fsub. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fsub. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fsub. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fsub. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fsubs. 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fsubs. 0010000000000001, 80100094e0000359 => 0000000000000000
|
|
+ fsubs. 0010000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsubs. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
|
|
+ fsubs. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
|
|
+ fsubs. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fsubs. bfe0000000000001, 0010000000000001 => bfe0000000000000
|
|
+ fsubs. bfe0000000000001, 80100094e0000359 => bfe0000000000000
|
|
+ fsubs. bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fsubs. 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fsubs. 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fsubs. 8000000000000000, 7ff0000000000000 => fff0000000000000
|
|
+ fsubs. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fsubs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fsubs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fsubs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fsubs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fsubs. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fsubs. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fsubs. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fsubs. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fmul. 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmul. 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fmul. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmul. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmul. 3fe00094e0000359, 0010000000000001 => 0008004a700001ad
|
|
+ fmul. 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179
|
|
+ fmul. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmul. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fmul. bfe0000000000001, 0010000000000001 => 8008000000000001
|
|
+ fmul. bfe0000000000001, 80100094e0000359 => 0008004a700001ad
|
|
+ fmul. bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fmul. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmul. 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fmul. 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fmul. 8000000000000000, 7ff0000000000000 => 7ff8000000000000
|
|
+ fmul. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fmul. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fmul. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fmul. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fmul. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fmul. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fmul. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fmul. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fmul. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fmuls. 0010000000000001, 0010000000000001 => 0000000000000000
|
|
+ fmuls. 0010000000000001, 80100094e0000359 => 8000000000000000
|
|
+ fmuls. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmuls. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmuls. 3fe00094e0000359, 0010000000000001 => 0000000000000000
|
|
+ fmuls. 3fe00094e0000359, 80100094e0000359 => 8000000000000000
|
|
+ fmuls. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
|
|
+ fmuls. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fmuls. bfe0000000000001, 0010000000000001 => 8000000000000000
|
|
+ fmuls. bfe0000000000001, 80100094e0000359 => 0000000000000000
|
|
+ fmuls. bfe0000000000001, 7ff0000000000000 => fff0000000000000
|
|
+ fmuls. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fmuls. 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fmuls. 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fmuls. 8000000000000000, 7ff0000000000000 => 7ff8000000000000
|
|
+ fmuls. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fmuls. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fmuls. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fmuls. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fmuls. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fmuls. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fmuls. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fmuls. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fmuls. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fdiv. 0010000000000001, 0010000000000001 => 3ff0000000000000
|
|
+ fdiv. 0010000000000001, 80100094e0000359 => bfeffed64ad20d22
|
|
+ fdiv. 0010000000000001, 7ff0000000000000 => 0000000000000000
|
|
+ fdiv. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdiv. 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358
|
|
+ fdiv. 3fe00094e0000359, 80100094e0000359 => ffc0000000000000
|
|
+ fdiv. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
|
|
+ fdiv. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fdiv. bfe0000000000001, 0010000000000001 => ffc0000000000000
|
|
+ fdiv. bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22
|
|
+ fdiv. bfe0000000000001, 7ff0000000000000 => 8000000000000000
|
|
+ fdiv. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdiv. 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fdiv. 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fdiv. 8000000000000000, 7ff0000000000000 => 8000000000000000
|
|
+ fdiv. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fdiv. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
|
|
+ fdiv. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
|
|
+ fdiv. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
|
|
+ fdiv. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
|
|
+ fdiv. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fdiv. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fdiv. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fdiv. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fdivs. 0010000000000001, 0010000000000001 => 3ff0000000000000
|
|
+ fdivs. 0010000000000001, 80100094e0000359 => bfeffed640000000
|
|
+ fdivs. 0010000000000001, 7ff0000000000000 => 0000000000000000
|
|
+ fdivs. 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdivs. 3fe00094e0000359, 0010000000000001 => 7ff0000000000000
|
|
+ fdivs. 3fe00094e0000359, 80100094e0000359 => fff0000000000000
|
|
+ fdivs. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
|
|
+ fdivs. 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fdivs. bfe0000000000001, 0010000000000001 => fff0000000000000
|
|
+ fdivs. bfe0000000000001, 80100094e0000359 => 7ff0000000000000
|
|
+ fdivs. bfe0000000000001, 7ff0000000000000 => 8000000000000000
|
|
+ fdivs. bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fdivs. 8000000000000000, 0010000000000001 => 8000000000000000
|
|
+ fdivs. 8000000000000000, 80100094e0000359 => 0000000000000000
|
|
+ fdivs. 8000000000000000, 7ff0000000000000 => 8000000000000000
|
|
+ fdivs. 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fdivs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
|
|
+ fdivs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
|
|
+ fdivs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
|
|
+ fdivs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
|
|
+ fdivs. fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fdivs. fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fdivs. fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fdivs. fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+PPC floating point compare insns (two args):
|
|
+ fcmpo 0010000000000001, 0010000000000001 => fff8000000000000
|
|
+ fcmpo 0010000000000001, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo 0010000000000001, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fcmpo 3fe00094e0000359, 0010000000000001 => fff8000000000000
|
|
+ fcmpo 3fe00094e0000359, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo 3fe00094e0000359, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fcmpo bfe0000000000001, 0010000000000001 => fff8000000000000
|
|
+ fcmpo bfe0000000000001, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo bfe0000000000001, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fcmpo 8000000000000000, 0010000000000001 => fff8000000000000
|
|
+ fcmpo 8000000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo 8000000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fcmpo 7ff7ffffffffffff, 0010000000000001 => fff8000000000000
|
|
+ fcmpo 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo 7ff7ffffffffffff, fff8000000000000 => fff8000000000000
|
|
+ fcmpo fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fcmpo fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fcmpo fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpo fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fcmpu 0010000000000001, 0010000000000001 => fff8000000000000
|
|
+ fcmpu 0010000000000001, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu 0010000000000001, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu 0010000000000001, fff8000000000000 => fff8000000000000
|
|
+ fcmpu 3fe00094e0000359, 0010000000000001 => fff8000000000000
|
|
+ fcmpu 3fe00094e0000359, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu 3fe00094e0000359, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu 3fe00094e0000359, fff8000000000000 => fff8000000000000
|
|
+ fcmpu bfe0000000000001, 0010000000000001 => fff8000000000000
|
|
+ fcmpu bfe0000000000001, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu bfe0000000000001, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu bfe0000000000001, fff8000000000000 => fff8000000000000
|
|
+ fcmpu 8000000000000000, 0010000000000001 => fff8000000000000
|
|
+ fcmpu 8000000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu 8000000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu 8000000000000000, fff8000000000000 => fff8000000000000
|
|
+ fcmpu 7ff7ffffffffffff, 0010000000000001 => fff8000000000000
|
|
+ fcmpu 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu 7ff7ffffffffffff, fff8000000000000 => fff8000000000000
|
|
+ fcmpu fff8000000000000, 0010000000000001 => fff8000000000000
|
|
+ fcmpu fff8000000000000, 80100094e0000359 => fff8000000000000
|
|
+ fcmpu fff8000000000000, 7ff0000000000000 => fff8000000000000
|
|
+ fcmpu fff8000000000000, fff8000000000000 => fff8000000000000
|
|
+
|
|
+PPC floating point arith insns with one arg:
|
|
+ fres 0010000000000001 => 7ff0000000000000
|
|
+ fres 00100094e0000359 => 7ff0000000000000
|
|
+ fres 3fe0000000000001 => 4000000000000000
|
|
+ fres 3fe00094e0000359 => 3ffff00000000000
|
|
+ fres 8010000000000001 => fff0000000000000
|
|
+ fres 80100094e0000359 => fff0000000000000
|
|
+ fres bfe0000000000001 => c000000000000000
|
|
+ fres bfe00094e0000359 => bffff00000000000
|
|
+ fres 0000000000000000 => 7ff0000000000000
|
|
+ fres 8000000000000000 => fff0000000000000
|
|
+ fres 7ff0000000000000 => 0000000000000000
|
|
+ fres fff0000000000000 => 8000000000000000
|
|
+ fres 7ff7ffffffffffff => 7ffff00000000000
|
|
+ fres fff7ffffffffffff => fffff00000000000
|
|
+ fres 7ff8000000000000 => 7ff8000000000000
|
|
+ fres fff8000000000000 => fff8000000000000
|
|
+
|
|
+ frsqrte 0010000000000001 => 5fdf000000000000
|
|
+ frsqrte 00100094e0000359 => 5fdf000000000000
|
|
+ frsqrte 3fe0000000000001 => 3ff6000000000000
|
|
+ frsqrte 3fe00094e0000359 => 3ff6000000000000
|
|
+ frsqrte 8010000000000001 => 7ff8000000000000
|
|
+ frsqrte 80100094e0000359 => 7ff8000000000000
|
|
+ frsqrte bfe0000000000001 => 7ff8000000000000
|
|
+ frsqrte bfe00094e0000359 => 7ff8000000000000
|
|
+ frsqrte 0000000000000000 => 7ff0000000000000
|
|
+ frsqrte 8000000000000000 => fff0000000000000
|
|
+ frsqrte 7ff0000000000000 => 0000000000000000
|
|
+ frsqrte fff0000000000000 => 7ff8000000000000
|
|
+ frsqrte 7ff7ffffffffffff => 7fff000000000000
|
|
+ frsqrte fff7ffffffffffff => ffff000000000000
|
|
+ frsqrte 7ff8000000000000 => 7ff8000000000000
|
|
+ frsqrte fff8000000000000 => fff8000000000000
|
|
+
|
|
+ frsp 0010000000000001 => 0000000000000000
|
|
+ frsp 00100094e0000359 => 0000000000000000
|
|
+ frsp 3fe0000000000001 => 3fe0000000000000
|
|
+ frsp 3fe00094e0000359 => 3fe00094e0000000
|
|
+ frsp 8010000000000001 => 8000000000000000
|
|
+ frsp 80100094e0000359 => 8000000000000000
|
|
+ frsp bfe0000000000001 => bfe0000000000000
|
|
+ frsp bfe00094e0000359 => bfe00094e0000000
|
|
+ frsp 0000000000000000 => 0000000000000000
|
|
+ frsp 8000000000000000 => 8000000000000000
|
|
+ frsp 7ff0000000000000 => 7ff0000000000000
|
|
+ frsp fff0000000000000 => fff0000000000000
|
|
+ frsp 7ff7ffffffffffff => 7fffffffe0000000
|
|
+ frsp fff7ffffffffffff => ffffffffe0000000
|
|
+ frsp 7ff8000000000000 => 7ff8000000000000
|
|
+ frsp fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fctiw 0010000000000001 => 0000000000000000
|
|
+ fctiw 00100094e0000359 => 0000000000000000
|
|
+ fctiw 3fe0000000000001 => 0000000000000001
|
|
+ fctiw 3fe00094e0000359 => 0000000000000001
|
|
+ fctiw 8010000000000001 => 0000000000000000
|
|
+ fctiw 80100094e0000359 => 0000000000000000
|
|
+ fctiw bfe0000000000001 => 00000000ffffffff
|
|
+ fctiw bfe00094e0000359 => 00000000ffffffff
|
|
+ fctiw 0000000000000000 => 0000000000000000
|
|
+ fctiw 8000000000000000 => 0000000000000000
|
|
+ fctiw 7ff0000000000000 => 000000007fffffff
|
|
+ fctiw fff0000000000000 => 0000000080000000
|
|
+ fctiw 7ff7ffffffffffff => 0000000080000000
|
|
+ fctiw fff7ffffffffffff => 0000000080000000
|
|
+ fctiw 7ff8000000000000 => 0000000080000000
|
|
+ fctiw fff8000000000000 => 0000000080000000
|
|
+
|
|
+ fctiwz 0010000000000001 => 0000000000000000
|
|
+ fctiwz 00100094e0000359 => 0000000000000000
|
|
+ fctiwz 3fe0000000000001 => 0000000000000000
|
|
+ fctiwz 3fe00094e0000359 => 0000000000000000
|
|
+ fctiwz 8010000000000001 => 0000000000000000
|
|
+ fctiwz 80100094e0000359 => 0000000000000000
|
|
+ fctiwz bfe0000000000001 => 0000000000000000
|
|
+ fctiwz bfe00094e0000359 => 0000000000000000
|
|
+ fctiwz 0000000000000000 => 0000000000000000
|
|
+ fctiwz 8000000000000000 => 0000000000000000
|
|
+ fctiwz 7ff0000000000000 => 000000007fffffff
|
|
+ fctiwz fff0000000000000 => 0000000080000000
|
|
+ fctiwz 7ff7ffffffffffff => 0000000080000000
|
|
+ fctiwz fff7ffffffffffff => 0000000080000000
|
|
+ fctiwz 7ff8000000000000 => 0000000080000000
|
|
+ fctiwz fff8000000000000 => 0000000080000000
|
|
+
|
|
+ fmr 0010000000000001 => 0010000000000001
|
|
+ fmr 00100094e0000359 => 00100094e0000359
|
|
+ fmr 3fe0000000000001 => 3fe0000000000001
|
|
+ fmr 3fe00094e0000359 => 3fe00094e0000359
|
|
+ fmr 8010000000000001 => 8010000000000001
|
|
+ fmr 80100094e0000359 => 80100094e0000359
|
|
+ fmr bfe0000000000001 => bfe0000000000001
|
|
+ fmr bfe00094e0000359 => bfe00094e0000359
|
|
+ fmr 0000000000000000 => 0000000000000000
|
|
+ fmr 8000000000000000 => 8000000000000000
|
|
+ fmr 7ff0000000000000 => 7ff0000000000000
|
|
+ fmr fff0000000000000 => fff0000000000000
|
|
+ fmr 7ff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fmr fff7ffffffffffff => fff7ffffffffffff
|
|
+ fmr 7ff8000000000000 => 7ff8000000000000
|
|
+ fmr fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fneg 0010000000000001 => 8010000000000001
|
|
+ fneg 00100094e0000359 => 80100094e0000359
|
|
+ fneg 3fe0000000000001 => bfe0000000000001
|
|
+ fneg 3fe00094e0000359 => bfe00094e0000359
|
|
+ fneg 8010000000000001 => 0010000000000001
|
|
+ fneg 80100094e0000359 => 00100094e0000359
|
|
+ fneg bfe0000000000001 => 3fe0000000000001
|
|
+ fneg bfe00094e0000359 => 3fe00094e0000359
|
|
+ fneg 0000000000000000 => 8000000000000000
|
|
+ fneg 8000000000000000 => 0000000000000000
|
|
+ fneg 7ff0000000000000 => fff0000000000000
|
|
+ fneg fff0000000000000 => 7ff0000000000000
|
|
+ fneg 7ff7ffffffffffff => fff7ffffffffffff
|
|
+ fneg fff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fneg 7ff8000000000000 => fff8000000000000
|
|
+ fneg fff8000000000000 => 7ff8000000000000
|
|
+
|
|
+ fabs 0010000000000001 => 0010000000000001
|
|
+ fabs 00100094e0000359 => 00100094e0000359
|
|
+ fabs 3fe0000000000001 => 3fe0000000000001
|
|
+ fabs 3fe00094e0000359 => 3fe00094e0000359
|
|
+ fabs 8010000000000001 => 0010000000000001
|
|
+ fabs 80100094e0000359 => 00100094e0000359
|
|
+ fabs bfe0000000000001 => 3fe0000000000001
|
|
+ fabs bfe00094e0000359 => 3fe00094e0000359
|
|
+ fabs 0000000000000000 => 0000000000000000
|
|
+ fabs 8000000000000000 => 0000000000000000
|
|
+ fabs 7ff0000000000000 => 7ff0000000000000
|
|
+ fabs fff0000000000000 => 7ff0000000000000
|
|
+ fabs 7ff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fabs fff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fabs 7ff8000000000000 => 7ff8000000000000
|
|
+ fabs fff8000000000000 => 7ff8000000000000
|
|
+
|
|
+ fnabs 0010000000000001 => 8010000000000001
|
|
+ fnabs 00100094e0000359 => 80100094e0000359
|
|
+ fnabs 3fe0000000000001 => bfe0000000000001
|
|
+ fnabs 3fe00094e0000359 => bfe00094e0000359
|
|
+ fnabs 8010000000000001 => 8010000000000001
|
|
+ fnabs 80100094e0000359 => 80100094e0000359
|
|
+ fnabs bfe0000000000001 => bfe0000000000001
|
|
+ fnabs bfe00094e0000359 => bfe00094e0000359
|
|
+ fnabs 0000000000000000 => 8000000000000000
|
|
+ fnabs 8000000000000000 => 8000000000000000
|
|
+ fnabs 7ff0000000000000 => fff0000000000000
|
|
+ fnabs fff0000000000000 => fff0000000000000
|
|
+ fnabs 7ff7ffffffffffff => fff7ffffffffffff
|
|
+ fnabs fff7ffffffffffff => fff7ffffffffffff
|
|
+ fnabs 7ff8000000000000 => fff8000000000000
|
|
+ fnabs fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fsqrt 0010000000000001 => 2000000000000000
|
|
+ fsqrt 00100094e0000359 => 2000004a6f52dd4a
|
|
+ fsqrt 3fe0000000000001 => 3fe6a09e667f3bcd
|
|
+ fsqrt 3fe00094e0000359 => 3fe6a107aacb50df
|
|
+ fsqrt 8010000000000001 => 7ff8000000000000
|
|
+ fsqrt 80100094e0000359 => 7ff8000000000000
|
|
+ fsqrt bfe0000000000001 => 7ff8000000000000
|
|
+ fsqrt bfe00094e0000359 => 7ff8000000000000
|
|
+ fsqrt 0000000000000000 => 0000000000000000
|
|
+ fsqrt 8000000000000000 => 8000000000000000
|
|
+ fsqrt 7ff0000000000000 => 7ff0000000000000
|
|
+ fsqrt fff0000000000000 => 7ff8000000000000
|
|
+ fsqrt 7ff7ffffffffffff => 7fffffffffffffff
|
|
+ fsqrt fff7ffffffffffff => ffffffffffffffff
|
|
+ fsqrt 7ff8000000000000 => 7ff8000000000000
|
|
+ fsqrt fff8000000000000 => fff8000000000000
|
|
+
|
|
+PPC floating point arith insns
|
|
+ with one arg with flags update:
|
|
+ fres. 0010000000000001 => 7ff0000000000000
|
|
+ fres. 00100094e0000359 => 7ff0000000000000
|
|
+ fres. 3fe0000000000001 => 4000000000000000
|
|
+ fres. 3fe00094e0000359 => 3ffff00000000000
|
|
+ fres. 8010000000000001 => fff0000000000000
|
|
+ fres. 80100094e0000359 => fff0000000000000
|
|
+ fres. bfe0000000000001 => c000000000000000
|
|
+ fres. bfe00094e0000359 => bffff00000000000
|
|
+ fres. 0000000000000000 => 7ff0000000000000
|
|
+ fres. 8000000000000000 => fff0000000000000
|
|
+ fres. 7ff0000000000000 => 0000000000000000
|
|
+ fres. fff0000000000000 => 8000000000000000
|
|
+ fres. 7ff7ffffffffffff => 7ffff00000000000
|
|
+ fres. fff7ffffffffffff => fffff00000000000
|
|
+ fres. 7ff8000000000000 => 7ff8000000000000
|
|
+ fres. fff8000000000000 => fff8000000000000
|
|
+
|
|
+ frsqrte. 0010000000000001 => 5fdf000000000000
|
|
+ frsqrte. 00100094e0000359 => 5fdf000000000000
|
|
+ frsqrte. 3fe0000000000001 => 3ff6000000000000
|
|
+ frsqrte. 3fe00094e0000359 => 3ff6000000000000
|
|
+ frsqrte. 8010000000000001 => 7ff8000000000000
|
|
+ frsqrte. 80100094e0000359 => 7ff8000000000000
|
|
+ frsqrte. bfe0000000000001 => 7ff8000000000000
|
|
+ frsqrte. bfe00094e0000359 => 7ff8000000000000
|
|
+ frsqrte. 0000000000000000 => 7ff0000000000000
|
|
+ frsqrte. 8000000000000000 => fff0000000000000
|
|
+ frsqrte. 7ff0000000000000 => 0000000000000000
|
|
+ frsqrte. fff0000000000000 => 7ff8000000000000
|
|
+ frsqrte. 7ff7ffffffffffff => 7fff000000000000
|
|
+ frsqrte. fff7ffffffffffff => ffff000000000000
|
|
+ frsqrte. 7ff8000000000000 => 7ff8000000000000
|
|
+ frsqrte. fff8000000000000 => fff8000000000000
|
|
+
|
|
+ frsp. 0010000000000001 => 0000000000000000
|
|
+ frsp. 00100094e0000359 => 0000000000000000
|
|
+ frsp. 3fe0000000000001 => 3fe0000000000000
|
|
+ frsp. 3fe00094e0000359 => 3fe00094e0000000
|
|
+ frsp. 8010000000000001 => 8000000000000000
|
|
+ frsp. 80100094e0000359 => 8000000000000000
|
|
+ frsp. bfe0000000000001 => bfe0000000000000
|
|
+ frsp. bfe00094e0000359 => bfe00094e0000000
|
|
+ frsp. 0000000000000000 => 0000000000000000
|
|
+ frsp. 8000000000000000 => 8000000000000000
|
|
+ frsp. 7ff0000000000000 => 7ff0000000000000
|
|
+ frsp. fff0000000000000 => fff0000000000000
|
|
+ frsp. 7ff7ffffffffffff => 7fffffffe0000000
|
|
+ frsp. fff7ffffffffffff => ffffffffe0000000
|
|
+ frsp. 7ff8000000000000 => 7ff8000000000000
|
|
+ frsp. fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fctiw. 0010000000000001 => 0000000000000000
|
|
+ fctiw. 00100094e0000359 => 0000000000000000
|
|
+ fctiw. 3fe0000000000001 => 0000000000000001
|
|
+ fctiw. 3fe00094e0000359 => 0000000000000001
|
|
+ fctiw. 8010000000000001 => 0000000000000000
|
|
+ fctiw. 80100094e0000359 => 0000000000000000
|
|
+ fctiw. bfe0000000000001 => 00000000ffffffff
|
|
+ fctiw. bfe00094e0000359 => 00000000ffffffff
|
|
+ fctiw. 0000000000000000 => 0000000000000000
|
|
+ fctiw. 8000000000000000 => 0000000000000000
|
|
+ fctiw. 7ff0000000000000 => 000000007fffffff
|
|
+ fctiw. fff0000000000000 => 0000000080000000
|
|
+ fctiw. 7ff7ffffffffffff => 0000000080000000
|
|
+ fctiw. fff7ffffffffffff => 0000000080000000
|
|
+ fctiw. 7ff8000000000000 => 0000000080000000
|
|
+ fctiw. fff8000000000000 => 0000000080000000
|
|
+
|
|
+ fctiwz. 0010000000000001 => 0000000000000000
|
|
+ fctiwz. 00100094e0000359 => 0000000000000000
|
|
+ fctiwz. 3fe0000000000001 => 0000000000000000
|
|
+ fctiwz. 3fe00094e0000359 => 0000000000000000
|
|
+ fctiwz. 8010000000000001 => 0000000000000000
|
|
+ fctiwz. 80100094e0000359 => 0000000000000000
|
|
+ fctiwz. bfe0000000000001 => 0000000000000000
|
|
+ fctiwz. bfe00094e0000359 => 0000000000000000
|
|
+ fctiwz. 0000000000000000 => 0000000000000000
|
|
+ fctiwz. 8000000000000000 => 0000000000000000
|
|
+ fctiwz. 7ff0000000000000 => 000000007fffffff
|
|
+ fctiwz. fff0000000000000 => 0000000080000000
|
|
+ fctiwz. 7ff7ffffffffffff => 0000000080000000
|
|
+ fctiwz. fff7ffffffffffff => 0000000080000000
|
|
+ fctiwz. 7ff8000000000000 => 0000000080000000
|
|
+ fctiwz. fff8000000000000 => 0000000080000000
|
|
+
|
|
+ fmr. 0010000000000001 => 0010000000000001
|
|
+ fmr. 00100094e0000359 => 00100094e0000359
|
|
+ fmr. 3fe0000000000001 => 3fe0000000000001
|
|
+ fmr. 3fe00094e0000359 => 3fe00094e0000359
|
|
+ fmr. 8010000000000001 => 8010000000000001
|
|
+ fmr. 80100094e0000359 => 80100094e0000359
|
|
+ fmr. bfe0000000000001 => bfe0000000000001
|
|
+ fmr. bfe00094e0000359 => bfe00094e0000359
|
|
+ fmr. 0000000000000000 => 0000000000000000
|
|
+ fmr. 8000000000000000 => 8000000000000000
|
|
+ fmr. 7ff0000000000000 => 7ff0000000000000
|
|
+ fmr. fff0000000000000 => fff0000000000000
|
|
+ fmr. 7ff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fmr. fff7ffffffffffff => fff7ffffffffffff
|
|
+ fmr. 7ff8000000000000 => 7ff8000000000000
|
|
+ fmr. fff8000000000000 => fff8000000000000
|
|
+
|
|
+ fneg. 0010000000000001 => 8010000000000001
|
|
+ fneg. 00100094e0000359 => 80100094e0000359
|
|
+ fneg. 3fe0000000000001 => bfe0000000000001
|
|
+ fneg. 3fe00094e0000359 => bfe00094e0000359
|
|
+ fneg. 8010000000000001 => 0010000000000001
|
|
+ fneg. 80100094e0000359 => 00100094e0000359
|
|
+ fneg. bfe0000000000001 => 3fe0000000000001
|
|
+ fneg. bfe00094e0000359 => 3fe00094e0000359
|
|
+ fneg. 0000000000000000 => 8000000000000000
|
|
+ fneg. 8000000000000000 => 0000000000000000
|
|
+ fneg. 7ff0000000000000 => fff0000000000000
|
|
+ fneg. fff0000000000000 => 7ff0000000000000
|
|
+ fneg. 7ff7ffffffffffff => fff7ffffffffffff
|
|
+ fneg. fff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fneg. 7ff8000000000000 => fff8000000000000
|
|
+ fneg. fff8000000000000 => 7ff8000000000000
|
|
+
|
|
+ fabs. 0010000000000001 => 0010000000000001
|
|
+ fabs. 00100094e0000359 => 00100094e0000359
|
|
+ fabs. 3fe0000000000001 => 3fe0000000000001
|
|
+ fabs. 3fe00094e0000359 => 3fe00094e0000359
|
|
+ fabs. 8010000000000001 => 0010000000000001
|
|
+ fabs. 80100094e0000359 => 00100094e0000359
|
|
+ fabs. bfe0000000000001 => 3fe0000000000001
|
|
+ fabs. bfe00094e0000359 => 3fe00094e0000359
|
|
+ fabs. 0000000000000000 => 0000000000000000
|
|
+ fabs. 8000000000000000 => 0000000000000000
|
|
+ fabs. 7ff0000000000000 => 7ff0000000000000
|
|
+ fabs. fff0000000000000 => 7ff0000000000000
|
|
+ fabs. 7ff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fabs. fff7ffffffffffff => 7ff7ffffffffffff
|
|
+ fabs. 7ff8000000000000 => 7ff8000000000000
|
|
+ fabs. fff8000000000000 => 7ff8000000000000
|
|
+
|
|
+ fnabs. 0010000000000001 => 8010000000000001
|
|
+ fnabs. 00100094e0000359 => 80100094e0000359
|
|
+ fnabs. 3fe0000000000001 => bfe0000000000001
|
|
+ fnabs. 3fe00094e0000359 => bfe00094e0000359
|
|
+ fnabs. 8010000000000001 => 8010000000000001
|
|
+ fnabs. 80100094e0000359 => 80100094e0000359
|
|
+ fnabs. bfe0000000000001 => bfe0000000000001
|
|
+ fnabs. bfe00094e0000359 => bfe00094e0000359
|
|
+ fnabs. 0000000000000000 => 8000000000000000
|
|
+ fnabs. 8000000000000000 => 8000000000000000
|
|
+ fnabs. 7ff0000000000000 => fff0000000000000
|
|
+ fnabs. fff0000000000000 => fff0000000000000
|
|
+ fnabs. 7ff7ffffffffffff => fff7ffffffffffff
|
|
+ fnabs. fff7ffffffffffff => fff7ffffffffffff
|
|
+ fnabs. 7ff8000000000000 => fff8000000000000
|
|
+ fnabs. fff8000000000000 => fff8000000000000
|
|
+
|
|
+PPC floating point status register manipulation insns:
|
|
+PPC floating point status register manipulation insns
|
|
+ with flags update:
|
|
+PPC float load insns
|
|
+ with one register + one 16 bits immediate args with flags update:
|
|
+ lfs 0010000000000001, 65416 => 37e0000000000000, 0
|
|
+ lfs 00100094e0000359, 65424 => 37e0009400000000, 0
|
|
+ lfs 3fe0000000000001, 65432 => 3ffc000000000000, 0
|
|
+ lfs 3fe00094e0000359, 65440 => 3ffc001280000000, 0
|
|
+ lfs 8010000000000001, 65448 => b7e0000000000000, 0
|
|
+ lfs 80100094e0000359, 65456 => b7e0009400000000, 0
|
|
+ lfs bfe0000000000001, 65464 => bffc000000000000, 0
|
|
+ lfs bfe00094e0000359, 65472 => bffc001280000000, 0
|
|
+ lfs 0000000000000000, 65480 => 0000000000000000, 0
|
|
+ lfs 8000000000000000, 65488 => 8000000000000000, 0
|
|
+ lfs 7ff0000000000000, 65496 => 7ffe000000000000, 0
|
|
+ lfs fff0000000000000, 65504 => fffe000000000000, 0
|
|
+ lfs 7ff7ffffffffffff, 65512 => 7ffeffffe0000000, 0
|
|
+ lfs fff7ffffffffffff, 65520 => fffeffffe0000000, 0
|
|
+ lfs 7ff8000000000000, 65528 => 7fff000000000000, 0
|
|
+ lfs 0010000000000001, 0 => 37e0000000000000, 0
|
|
+ lfs 00100094e0000359, 8 => 37e0009400000000, 0
|
|
+ lfs 3fe0000000000001, 16 => 3ffc000000000000, 0
|
|
+ lfs 3fe00094e0000359, 24 => 3ffc001280000000, 0
|
|
+ lfs 8010000000000001, 32 => b7e0000000000000, 0
|
|
+ lfs 80100094e0000359, 40 => b7e0009400000000, 0
|
|
+ lfs bfe0000000000001, 48 => bffc000000000000, 0
|
|
+ lfs bfe00094e0000359, 56 => bffc001280000000, 0
|
|
+ lfs 0000000000000000, 64 => 0000000000000000, 0
|
|
+ lfs 8000000000000000, 72 => 8000000000000000, 0
|
|
+ lfs 7ff0000000000000, 80 => 7ffe000000000000, 0
|
|
+ lfs fff0000000000000, 88 => fffe000000000000, 0
|
|
+ lfs 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 0
|
|
+ lfs fff7ffffffffffff, 104 => fffeffffe0000000, 0
|
|
+ lfs 7ff8000000000000, 112 => 7fff000000000000, 0
|
|
+ lfs fff8000000000000, 120 => ffff000000000000, 0
|
|
+
|
|
+ lfsu 0010000000000001, 65416 => 37e0000000000000, -120
|
|
+ lfsu 00100094e0000359, 65424 => 37e0009400000000, -112
|
|
+ lfsu 3fe0000000000001, 65432 => 3ffc000000000000, -104
|
|
+ lfsu 3fe00094e0000359, 65440 => 3ffc001280000000, -96
|
|
+ lfsu 8010000000000001, 65448 => b7e0000000000000, -88
|
|
+ lfsu 80100094e0000359, 65456 => b7e0009400000000, -80
|
|
+ lfsu bfe0000000000001, 65464 => bffc000000000000, -72
|
|
+ lfsu bfe00094e0000359, 65472 => bffc001280000000, -64
|
|
+ lfsu 0000000000000000, 65480 => 0000000000000000, -56
|
|
+ lfsu 8000000000000000, 65488 => 8000000000000000, -48
|
|
+ lfsu 7ff0000000000000, 65496 => 7ffe000000000000, -40
|
|
+ lfsu fff0000000000000, 65504 => fffe000000000000, -32
|
|
+ lfsu 7ff7ffffffffffff, 65512 => 7ffeffffe0000000, -24
|
|
+ lfsu fff7ffffffffffff, 65520 => fffeffffe0000000, -16
|
|
+ lfsu 7ff8000000000000, 65528 => 7fff000000000000, -8
|
|
+ lfsu 0010000000000001, 0 => 37e0000000000000, 0
|
|
+ lfsu 00100094e0000359, 8 => 37e0009400000000, 8
|
|
+ lfsu 3fe0000000000001, 16 => 3ffc000000000000, 16
|
|
+ lfsu 3fe00094e0000359, 24 => 3ffc001280000000, 24
|
|
+ lfsu 8010000000000001, 32 => b7e0000000000000, 32
|
|
+ lfsu 80100094e0000359, 40 => b7e0009400000000, 40
|
|
+ lfsu bfe0000000000001, 48 => bffc000000000000, 48
|
|
+ lfsu bfe00094e0000359, 56 => bffc001280000000, 56
|
|
+ lfsu 0000000000000000, 64 => 0000000000000000, 64
|
|
+ lfsu 8000000000000000, 72 => 8000000000000000, 72
|
|
+ lfsu 7ff0000000000000, 80 => 7ffe000000000000, 80
|
|
+ lfsu fff0000000000000, 88 => fffe000000000000, 88
|
|
+ lfsu 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 96
|
|
+ lfsu fff7ffffffffffff, 104 => fffeffffe0000000, 104
|
|
+ lfsu 7ff8000000000000, 112 => 7fff000000000000, 112
|
|
+ lfsu fff8000000000000, 120 => ffff000000000000, 120
|
|
+
|
|
+ lfd 0010000000000001, 65416 => 0010000000000001, 0
|
|
+ lfd 00100094e0000359, 65424 => 00100094e0000359, 0
|
|
+ lfd 3fe0000000000001, 65432 => 3fe0000000000001, 0
|
|
+ lfd 3fe00094e0000359, 65440 => 3fe00094e0000359, 0
|
|
+ lfd 8010000000000001, 65448 => 8010000000000001, 0
|
|
+ lfd 80100094e0000359, 65456 => 80100094e0000359, 0
|
|
+ lfd bfe0000000000001, 65464 => bfe0000000000001, 0
|
|
+ lfd bfe00094e0000359, 65472 => bfe00094e0000359, 0
|
|
+ lfd 0000000000000000, 65480 => 0000000000000000, 0
|
|
+ lfd 8000000000000000, 65488 => 8000000000000000, 0
|
|
+ lfd 7ff0000000000000, 65496 => 7ff0000000000000, 0
|
|
+ lfd fff0000000000000, 65504 => fff0000000000000, 0
|
|
+ lfd 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, 0
|
|
+ lfd fff7ffffffffffff, 65520 => fff7ffffffffffff, 0
|
|
+ lfd 7ff8000000000000, 65528 => 7ff8000000000000, 0
|
|
+ lfd 0010000000000001, 0 => 0010000000000001, 0
|
|
+ lfd 00100094e0000359, 8 => 00100094e0000359, 0
|
|
+ lfd 3fe0000000000001, 16 => 3fe0000000000001, 0
|
|
+ lfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0
|
|
+ lfd 8010000000000001, 32 => 8010000000000001, 0
|
|
+ lfd 80100094e0000359, 40 => 80100094e0000359, 0
|
|
+ lfd bfe0000000000001, 48 => bfe0000000000001, 0
|
|
+ lfd bfe00094e0000359, 56 => bfe00094e0000359, 0
|
|
+ lfd 0000000000000000, 64 => 0000000000000000, 0
|
|
+ lfd 8000000000000000, 72 => 8000000000000000, 0
|
|
+ lfd 7ff0000000000000, 80 => 7ff0000000000000, 0
|
|
+ lfd fff0000000000000, 88 => fff0000000000000, 0
|
|
+ lfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
|
|
+ lfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0
|
|
+ lfd 7ff8000000000000, 112 => 7ff8000000000000, 0
|
|
+ lfd fff8000000000000, 120 => fff8000000000000, 0
|
|
+
|
|
+ lfdu 0010000000000001, 65416 => 0010000000000001, -120
|
|
+ lfdu 00100094e0000359, 65424 => 00100094e0000359, -112
|
|
+ lfdu 3fe0000000000001, 65432 => 3fe0000000000001, -104
|
|
+ lfdu 3fe00094e0000359, 65440 => 3fe00094e0000359, -96
|
|
+ lfdu 8010000000000001, 65448 => 8010000000000001, -88
|
|
+ lfdu 80100094e0000359, 65456 => 80100094e0000359, -80
|
|
+ lfdu bfe0000000000001, 65464 => bfe0000000000001, -72
|
|
+ lfdu bfe00094e0000359, 65472 => bfe00094e0000359, -64
|
|
+ lfdu 0000000000000000, 65480 => 0000000000000000, -56
|
|
+ lfdu 8000000000000000, 65488 => 8000000000000000, -48
|
|
+ lfdu 7ff0000000000000, 65496 => 7ff0000000000000, -40
|
|
+ lfdu fff0000000000000, 65504 => fff0000000000000, -32
|
|
+ lfdu 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, -24
|
|
+ lfdu fff7ffffffffffff, 65520 => fff7ffffffffffff, -16
|
|
+ lfdu 7ff8000000000000, 65528 => 7ff8000000000000, -8
|
|
+ lfdu 0010000000000001, 0 => 0010000000000001, 0
|
|
+ lfdu 00100094e0000359, 8 => 00100094e0000359, 8
|
|
+ lfdu 3fe0000000000001, 16 => 3fe0000000000001, 16
|
|
+ lfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24
|
|
+ lfdu 8010000000000001, 32 => 8010000000000001, 32
|
|
+ lfdu 80100094e0000359, 40 => 80100094e0000359, 40
|
|
+ lfdu bfe0000000000001, 48 => bfe0000000000001, 48
|
|
+ lfdu bfe00094e0000359, 56 => bfe00094e0000359, 56
|
|
+ lfdu 0000000000000000, 64 => 0000000000000000, 64
|
|
+ lfdu 8000000000000000, 72 => 8000000000000000, 72
|
|
+ lfdu 7ff0000000000000, 80 => 7ff0000000000000, 80
|
|
+ lfdu fff0000000000000, 88 => fff0000000000000, 88
|
|
+ lfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
|
|
+ lfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104
|
|
+ lfdu 7ff8000000000000, 112 => 7ff8000000000000, 112
|
|
+ lfdu fff8000000000000, 120 => fff8000000000000, 120
|
|
+
|
|
+PPC float load insns with two register args:
|
|
+ lfsx 0010000000000001, -120 => 37e0000000000000, 0
|
|
+ lfsx 00100094e0000359, -112 => 37e0009400000000, 0
|
|
+ lfsx 3fe0000000000001, -104 => 3ffc000000000000, 0
|
|
+ lfsx 3fe00094e0000359, -96 => 3ffc001280000000, 0
|
|
+ lfsx 8010000000000001, -88 => b7e0000000000000, 0
|
|
+ lfsx 80100094e0000359, -80 => b7e0009400000000, 0
|
|
+ lfsx bfe0000000000001, -72 => bffc000000000000, 0
|
|
+ lfsx bfe00094e0000359, -64 => bffc001280000000, 0
|
|
+ lfsx 0000000000000000, -56 => 0000000000000000, 0
|
|
+ lfsx 8000000000000000, -48 => 8000000000000000, 0
|
|
+ lfsx 7ff0000000000000, -40 => 7ffe000000000000, 0
|
|
+ lfsx fff0000000000000, -32 => fffe000000000000, 0
|
|
+ lfsx 7ff7ffffffffffff, -24 => 7ffeffffe0000000, 0
|
|
+ lfsx fff7ffffffffffff, -16 => fffeffffe0000000, 0
|
|
+ lfsx 7ff8000000000000, -8 => 7fff000000000000, 0
|
|
+ lfsx 0010000000000001, 0 => 37e0000000000000, 0
|
|
+ lfsx 00100094e0000359, 8 => 37e0009400000000, 0
|
|
+ lfsx 3fe0000000000001, 16 => 3ffc000000000000, 0
|
|
+ lfsx 3fe00094e0000359, 24 => 3ffc001280000000, 0
|
|
+ lfsx 8010000000000001, 32 => b7e0000000000000, 0
|
|
+ lfsx 80100094e0000359, 40 => b7e0009400000000, 0
|
|
+ lfsx bfe0000000000001, 48 => bffc000000000000, 0
|
|
+ lfsx bfe00094e0000359, 56 => bffc001280000000, 0
|
|
+ lfsx 0000000000000000, 64 => 0000000000000000, 0
|
|
+ lfsx 8000000000000000, 72 => 8000000000000000, 0
|
|
+ lfsx 7ff0000000000000, 80 => 7ffe000000000000, 0
|
|
+ lfsx fff0000000000000, 88 => fffe000000000000, 0
|
|
+ lfsx 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 0
|
|
+ lfsx fff7ffffffffffff, 104 => fffeffffe0000000, 0
|
|
+ lfsx 7ff8000000000000, 112 => 7fff000000000000, 0
|
|
+ lfsx fff8000000000000, 120 => ffff000000000000, 0
|
|
+
|
|
+ lfsux 0010000000000001, -120 => 37e0000000000000, -120
|
|
+ lfsux 00100094e0000359, -112 => 37e0009400000000, -112
|
|
+ lfsux 3fe0000000000001, -104 => 3ffc000000000000, -104
|
|
+ lfsux 3fe00094e0000359, -96 => 3ffc001280000000, -96
|
|
+ lfsux 8010000000000001, -88 => b7e0000000000000, -88
|
|
+ lfsux 80100094e0000359, -80 => b7e0009400000000, -80
|
|
+ lfsux bfe0000000000001, -72 => bffc000000000000, -72
|
|
+ lfsux bfe00094e0000359, -64 => bffc001280000000, -64
|
|
+ lfsux 0000000000000000, -56 => 0000000000000000, -56
|
|
+ lfsux 8000000000000000, -48 => 8000000000000000, -48
|
|
+ lfsux 7ff0000000000000, -40 => 7ffe000000000000, -40
|
|
+ lfsux fff0000000000000, -32 => fffe000000000000, -32
|
|
+ lfsux 7ff7ffffffffffff, -24 => 7ffeffffe0000000, -24
|
|
+ lfsux fff7ffffffffffff, -16 => fffeffffe0000000, -16
|
|
+ lfsux 7ff8000000000000, -8 => 7fff000000000000, -8
|
|
+ lfsux 0010000000000001, 0 => 37e0000000000000, 0
|
|
+ lfsux 00100094e0000359, 8 => 37e0009400000000, 8
|
|
+ lfsux 3fe0000000000001, 16 => 3ffc000000000000, 16
|
|
+ lfsux 3fe00094e0000359, 24 => 3ffc001280000000, 24
|
|
+ lfsux 8010000000000001, 32 => b7e0000000000000, 32
|
|
+ lfsux 80100094e0000359, 40 => b7e0009400000000, 40
|
|
+ lfsux bfe0000000000001, 48 => bffc000000000000, 48
|
|
+ lfsux bfe00094e0000359, 56 => bffc001280000000, 56
|
|
+ lfsux 0000000000000000, 64 => 0000000000000000, 64
|
|
+ lfsux 8000000000000000, 72 => 8000000000000000, 72
|
|
+ lfsux 7ff0000000000000, 80 => 7ffe000000000000, 80
|
|
+ lfsux fff0000000000000, 88 => fffe000000000000, 88
|
|
+ lfsux 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 96
|
|
+ lfsux fff7ffffffffffff, 104 => fffeffffe0000000, 104
|
|
+ lfsux 7ff8000000000000, 112 => 7fff000000000000, 112
|
|
+ lfsux fff8000000000000, 120 => ffff000000000000, 120
|
|
+
|
|
+ lfdx 0010000000000001, -120 => 0010000000000001, 0
|
|
+ lfdx 00100094e0000359, -112 => 00100094e0000359, 0
|
|
+ lfdx 3fe0000000000001, -104 => 3fe0000000000001, 0
|
|
+ lfdx 3fe00094e0000359, -96 => 3fe00094e0000359, 0
|
|
+ lfdx 8010000000000001, -88 => 8010000000000001, 0
|
|
+ lfdx 80100094e0000359, -80 => 80100094e0000359, 0
|
|
+ lfdx bfe0000000000001, -72 => bfe0000000000001, 0
|
|
+ lfdx bfe00094e0000359, -64 => bfe00094e0000359, 0
|
|
+ lfdx 0000000000000000, -56 => 0000000000000000, 0
|
|
+ lfdx 8000000000000000, -48 => 8000000000000000, 0
|
|
+ lfdx 7ff0000000000000, -40 => 7ff0000000000000, 0
|
|
+ lfdx fff0000000000000, -32 => fff0000000000000, 0
|
|
+ lfdx 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0
|
|
+ lfdx fff7ffffffffffff, -16 => fff7ffffffffffff, 0
|
|
+ lfdx 7ff8000000000000, -8 => 7ff8000000000000, 0
|
|
+ lfdx 0010000000000001, 0 => 0010000000000001, 0
|
|
+ lfdx 00100094e0000359, 8 => 00100094e0000359, 0
|
|
+ lfdx 3fe0000000000001, 16 => 3fe0000000000001, 0
|
|
+ lfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0
|
|
+ lfdx 8010000000000001, 32 => 8010000000000001, 0
|
|
+ lfdx 80100094e0000359, 40 => 80100094e0000359, 0
|
|
+ lfdx bfe0000000000001, 48 => bfe0000000000001, 0
|
|
+ lfdx bfe00094e0000359, 56 => bfe00094e0000359, 0
|
|
+ lfdx 0000000000000000, 64 => 0000000000000000, 0
|
|
+ lfdx 8000000000000000, 72 => 8000000000000000, 0
|
|
+ lfdx 7ff0000000000000, 80 => 7ff0000000000000, 0
|
|
+ lfdx fff0000000000000, 88 => fff0000000000000, 0
|
|
+ lfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
|
|
+ lfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0
|
|
+ lfdx 7ff8000000000000, 112 => 7ff8000000000000, 0
|
|
+ lfdx fff8000000000000, 120 => fff8000000000000, 0
|
|
+
|
|
+ lfdux 0010000000000001, -120 => 0010000000000001, -120
|
|
+ lfdux 00100094e0000359, -112 => 00100094e0000359, -112
|
|
+ lfdux 3fe0000000000001, -104 => 3fe0000000000001, -104
|
|
+ lfdux 3fe00094e0000359, -96 => 3fe00094e0000359, -96
|
|
+ lfdux 8010000000000001, -88 => 8010000000000001, -88
|
|
+ lfdux 80100094e0000359, -80 => 80100094e0000359, -80
|
|
+ lfdux bfe0000000000001, -72 => bfe0000000000001, -72
|
|
+ lfdux bfe00094e0000359, -64 => bfe00094e0000359, -64
|
|
+ lfdux 0000000000000000, -56 => 0000000000000000, -56
|
|
+ lfdux 8000000000000000, -48 => 8000000000000000, -48
|
|
+ lfdux 7ff0000000000000, -40 => 7ff0000000000000, -40
|
|
+ lfdux fff0000000000000, -32 => fff0000000000000, -32
|
|
+ lfdux 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24
|
|
+ lfdux fff7ffffffffffff, -16 => fff7ffffffffffff, -16
|
|
+ lfdux 7ff8000000000000, -8 => 7ff8000000000000, -8
|
|
+ lfdux 0010000000000001, 0 => 0010000000000001, 0
|
|
+ lfdux 00100094e0000359, 8 => 00100094e0000359, 8
|
|
+ lfdux 3fe0000000000001, 16 => 3fe0000000000001, 16
|
|
+ lfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24
|
|
+ lfdux 8010000000000001, 32 => 8010000000000001, 32
|
|
+ lfdux 80100094e0000359, 40 => 80100094e0000359, 40
|
|
+ lfdux bfe0000000000001, 48 => bfe0000000000001, 48
|
|
+ lfdux bfe00094e0000359, 56 => bfe00094e0000359, 56
|
|
+ lfdux 0000000000000000, 64 => 0000000000000000, 64
|
|
+ lfdux 8000000000000000, 72 => 8000000000000000, 72
|
|
+ lfdux 7ff0000000000000, 80 => 7ff0000000000000, 80
|
|
+ lfdux fff0000000000000, 88 => fff0000000000000, 88
|
|
+ lfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
|
|
+ lfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104
|
|
+ lfdux 7ff8000000000000, 112 => 7ff8000000000000, 112
|
|
+ lfdux fff8000000000000, 120 => fff8000000000000, 120
|
|
+
|
|
+PPC float store insns
|
|
+ with one register + one 16 bits immediate args with flags update:
|
|
+ stfs 0010000000000001, -56 => 0000000000000000, 0
|
|
+ stfs 00100094e0000359, -48 => 0000000000000000, 0
|
|
+ stfs 3fe0000000000001, -40 => 3f00000000000000, 0
|
|
+ stfs 3fe00094e0000359, -32 => 3f0004a700000000, 0
|
|
+ stfs 8010000000000001, -24 => 8000000000000000, 0
|
|
+ stfs 80100094e0000359, -16 => 8000000000000000, 0
|
|
+ stfs bfe0000000000001, -8 => bf00000000000000, 0
|
|
+ stfs 0010000000000001, 0 => 0000000000000000, 0
|
|
+ stfs 00100094e0000359, 8 => 0000000000000000, 0
|
|
+ stfs 3fe0000000000001, 16 => 3f00000000000000, 0
|
|
+ stfs 3fe00094e0000359, 24 => 3f0004a700000000, 0
|
|
+ stfs 8010000000000001, 32 => 8000000000000000, 0
|
|
+ stfs 80100094e0000359, 40 => 8000000000000000, 0
|
|
+ stfs bfe0000000000001, 48 => bf00000000000000, 0
|
|
+ stfs bfe00094e0000359, 56 => bf0004a700000000, 0
|
|
+
|
|
+ stfsu 0010000000000001, -56 => 0000000000000000, -56
|
|
+ stfsu 00100094e0000359, -48 => 0000000000000000, -48
|
|
+ stfsu 3fe0000000000001, -40 => 3f00000000000000, -40
|
|
+ stfsu 3fe00094e0000359, -32 => 3f0004a700000000, -32
|
|
+ stfsu 8010000000000001, -24 => 8000000000000000, -24
|
|
+ stfsu 80100094e0000359, -16 => 8000000000000000, -16
|
|
+ stfsu bfe0000000000001, -8 => bf00000000000000, -8
|
|
+ stfsu 0010000000000001, 0 => 0000000000000000, 0
|
|
+ stfsu 00100094e0000359, 8 => 0000000000000000, 8
|
|
+ stfsu 3fe0000000000001, 16 => 3f00000000000000, 16
|
|
+ stfsu 3fe00094e0000359, 24 => 3f0004a700000000, 24
|
|
+ stfsu 8010000000000001, 32 => 8000000000000000, 32
|
|
+ stfsu 80100094e0000359, 40 => 8000000000000000, 40
|
|
+ stfsu bfe0000000000001, 48 => bf00000000000000, 48
|
|
+ stfsu bfe00094e0000359, 56 => bf0004a700000000, 56
|
|
+
|
|
+ stfd 0010000000000001, -120 => 0010000000000001, 0
|
|
+ stfd 00100094e0000359, -112 => 00100094e0000359, 0
|
|
+ stfd 3fe0000000000001, -104 => 3fe0000000000001, 0
|
|
+ stfd 3fe00094e0000359, -96 => 3fe00094e0000359, 0
|
|
+ stfd 8010000000000001, -88 => 8010000000000001, 0
|
|
+ stfd 80100094e0000359, -80 => 80100094e0000359, 0
|
|
+ stfd bfe0000000000001, -72 => bfe0000000000001, 0
|
|
+ stfd bfe00094e0000359, -64 => bfe00094e0000359, 0
|
|
+ stfd 0000000000000000, -56 => 0000000000000000, 0
|
|
+ stfd 8000000000000000, -48 => 8000000000000000, 0
|
|
+ stfd 7ff0000000000000, -40 => 7ff0000000000000, 0
|
|
+ stfd fff0000000000000, -32 => fff0000000000000, 0
|
|
+ stfd 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0
|
|
+ stfd fff7ffffffffffff, -16 => fff7ffffffffffff, 0
|
|
+ stfd 7ff8000000000000, -8 => 7ff8000000000000, 0
|
|
+ stfd 0010000000000001, 0 => 0010000000000001, 0
|
|
+ stfd 00100094e0000359, 8 => 00100094e0000359, 0
|
|
+ stfd 3fe0000000000001, 16 => 3fe0000000000001, 0
|
|
+ stfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0
|
|
+ stfd 8010000000000001, 32 => 8010000000000001, 0
|
|
+ stfd 80100094e0000359, 40 => 80100094e0000359, 0
|
|
+ stfd bfe0000000000001, 48 => bfe0000000000001, 0
|
|
+ stfd bfe00094e0000359, 56 => bfe00094e0000359, 0
|
|
+ stfd 0000000000000000, 64 => 0000000000000000, 0
|
|
+ stfd 8000000000000000, 72 => 8000000000000000, 0
|
|
+ stfd 7ff0000000000000, 80 => 7ff0000000000000, 0
|
|
+ stfd fff0000000000000, 88 => fff0000000000000, 0
|
|
+ stfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
|
|
+ stfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0
|
|
+ stfd 7ff8000000000000, 112 => 7ff8000000000000, 0
|
|
+ stfd fff8000000000000, 120 => fff8000000000000, 0
|
|
+
|
|
+ stfdu 0010000000000001, -120 => 0010000000000001, -120
|
|
+ stfdu 00100094e0000359, -112 => 00100094e0000359, -112
|
|
+ stfdu 3fe0000000000001, -104 => 3fe0000000000001, -104
|
|
+ stfdu 3fe00094e0000359, -96 => 3fe00094e0000359, -96
|
|
+ stfdu 8010000000000001, -88 => 8010000000000001, -88
|
|
+ stfdu 80100094e0000359, -80 => 80100094e0000359, -80
|
|
+ stfdu bfe0000000000001, -72 => bfe0000000000001, -72
|
|
+ stfdu bfe00094e0000359, -64 => bfe00094e0000359, -64
|
|
+ stfdu 0000000000000000, -56 => 0000000000000000, -56
|
|
+ stfdu 8000000000000000, -48 => 8000000000000000, -48
|
|
+ stfdu 7ff0000000000000, -40 => 7ff0000000000000, -40
|
|
+ stfdu fff0000000000000, -32 => fff0000000000000, -32
|
|
+ stfdu 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24
|
|
+ stfdu fff7ffffffffffff, -16 => fff7ffffffffffff, -16
|
|
+ stfdu 7ff8000000000000, -8 => 7ff8000000000000, -8
|
|
+ stfdu 0010000000000001, 0 => 0010000000000001, 0
|
|
+ stfdu 00100094e0000359, 8 => 00100094e0000359, 8
|
|
+ stfdu 3fe0000000000001, 16 => 3fe0000000000001, 16
|
|
+ stfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24
|
|
+ stfdu 8010000000000001, 32 => 8010000000000001, 32
|
|
+ stfdu 80100094e0000359, 40 => 80100094e0000359, 40
|
|
+ stfdu bfe0000000000001, 48 => bfe0000000000001, 48
|
|
+ stfdu bfe00094e0000359, 56 => bfe00094e0000359, 56
|
|
+ stfdu 0000000000000000, 64 => 0000000000000000, 64
|
|
+ stfdu 8000000000000000, 72 => 8000000000000000, 72
|
|
+ stfdu 7ff0000000000000, 80 => 7ff0000000000000, 80
|
|
+ stfdu fff0000000000000, 88 => fff0000000000000, 88
|
|
+ stfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
|
|
+ stfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104
|
|
+ stfdu 7ff8000000000000, 112 => 7ff8000000000000, 112
|
|
+ stfdu fff8000000000000, 120 => fff8000000000000, 120
|
|
+
|
|
+PPC float store insns with three register args:
|
|
+ stfsx 0010000000000001, 0 => 0000000000000000, 0
|
|
+ stfsx 00100094e0000359, 8 => 0000000000000000, 0
|
|
+ stfsx 3fe0000000000001, 16 => 3f00000000000000, 0
|
|
+ stfsx 3fe00094e0000359, 24 => 3f0004a700000000, 0
|
|
+ stfsx 8010000000000001, 32 => 8000000000000000, 0
|
|
+ stfsx 80100094e0000359, 40 => 8000000000000000, 0
|
|
+ stfsx bfe0000000000001, 48 => bf00000000000000, 0
|
|
+ stfsx bfe00094e0000359, 56 => bf0004a700000000, 0
|
|
+
|
|
+ stfsux 0010000000000001, 0 => 0000000000000000, 0
|
|
+ stfsux 00100094e0000359, 8 => 0000000000000000, 8
|
|
+ stfsux 3fe0000000000001, 16 => 3f00000000000000, 16
|
|
+ stfsux 3fe00094e0000359, 24 => 3f0004a700000000, 24
|
|
+ stfsux 8010000000000001, 32 => 8000000000000000, 32
|
|
+ stfsux 80100094e0000359, 40 => 8000000000000000, 40
|
|
+ stfsux bfe0000000000001, 48 => bf00000000000000, 48
|
|
+ stfsux bfe00094e0000359, 56 => bf0004a700000000, 56
|
|
+
|
|
+ stfdx 0010000000000001, 0 => 0010000000000001, 0
|
|
+ stfdx 00100094e0000359, 8 => 00100094e0000359, 0
|
|
+ stfdx 3fe0000000000001, 16 => 3fe0000000000001, 0
|
|
+ stfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0
|
|
+ stfdx 8010000000000001, 32 => 8010000000000001, 0
|
|
+ stfdx 80100094e0000359, 40 => 80100094e0000359, 0
|
|
+ stfdx bfe0000000000001, 48 => bfe0000000000001, 0
|
|
+ stfdx bfe00094e0000359, 56 => bfe00094e0000359, 0
|
|
+ stfdx 0000000000000000, 64 => 0000000000000000, 0
|
|
+ stfdx 8000000000000000, 72 => 8000000000000000, 0
|
|
+ stfdx 7ff0000000000000, 80 => 7ff0000000000000, 0
|
|
+ stfdx fff0000000000000, 88 => fff0000000000000, 0
|
|
+ stfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
|
|
+ stfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0
|
|
+ stfdx 7ff8000000000000, 112 => 7ff8000000000000, 0
|
|
+ stfdx fff8000000000000, 120 => fff8000000000000, 0
|
|
+
|
|
+ stfdux 0010000000000001, 0 => 0010000000000001, 0
|
|
+ stfdux 00100094e0000359, 8 => 00100094e0000359, 8
|
|
+ stfdux 3fe0000000000001, 16 => 3fe0000000000001, 16
|
|
+ stfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24
|
|
+ stfdux 8010000000000001, 32 => 8010000000000001, 32
|
|
+ stfdux 80100094e0000359, 40 => 80100094e0000359, 40
|
|
+ stfdux bfe0000000000001, 48 => bfe0000000000001, 48
|
|
+ stfdux bfe00094e0000359, 56 => bfe00094e0000359, 56
|
|
+ stfdux 0000000000000000, 64 => 0000000000000000, 64
|
|
+ stfdux 8000000000000000, 72 => 8000000000000000, 72
|
|
+ stfdux 7ff0000000000000, 80 => 7ff0000000000000, 80
|
|
+ stfdux fff0000000000000, 88 => fff0000000000000, 88
|
|
+ stfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
|
|
+ stfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104
|
|
+ stfdux 7ff8000000000000, 112 => 7ff8000000000000, 112
|
|
+ stfdux fff8000000000000, 120 => fff8000000000000, 120
|
|
+
|
|
+All done. Tested 71 different instructions
|
|
Index: none/tests/ppc32/jm-int.stdout.exp
|
|
===================================================================
|
|
--- none/tests/ppc32/jm-int.stdout.exp.orig
|
|
+++ none/tests/ppc32/jm-int.stdout.exp
|
|
@@ -1439,60 +1439,60 @@ PPC logical insns with special forms wit
|
|
PPC integer load insns
|
|
with one register + one 16 bits immediate args with flags update:
|
|
lbz 0, (00000000) => 00000000, 0 (00000000 00000000)
|
|
- lbz 4, (000f423f) => 00000000, 0 (00000000 00000000)
|
|
- lbz 8, (ffffffff) => 000000ff, 0 (00000000 00000000)
|
|
- lbz -8, (00000000) => 00000000, 0 (00000000 00000000)
|
|
- lbz -4, (000f423f) => 00000000, 0 (00000000 00000000)
|
|
- lbz 0, (ffffffff) => 000000ff, 0 (00000000 00000000)
|
|
+ lbz 3, (000f423f) => 00000000, 0 (00000000 00000000)
|
|
+ lbz 7, (ffffffff) => 0000003f, 0 (00000000 00000000)
|
|
+ lbz 1, (ffffffff) => 000000ff, 0 (00000000 00000000)
|
|
+ lbz -3, (000f423f) => 0000000f, 0 (00000000 00000000)
|
|
+ lbz -7, (00000000) => 00000000, 0 (00000000 00000000)
|
|
|
|
lbzu 0, (00000000) => 00000000, 0 (00000000 00000000)
|
|
- lbzu 4, (000f423f) => 00000000, 4 (00000000 00000000)
|
|
- lbzu 8, (ffffffff) => 000000ff, 8 (00000000 00000000)
|
|
- lbzu -8, (00000000) => 00000000, -8 (00000000 00000000)
|
|
- lbzu -4, (000f423f) => 00000000, -4 (00000000 00000000)
|
|
- lbzu 0, (ffffffff) => 000000ff, 0 (00000000 00000000)
|
|
+ lbzu 3, (000f423f) => 00000000, 3 (00000000 00000000)
|
|
+ lbzu 7, (ffffffff) => 0000003f, 7 (00000000 00000000)
|
|
+ lbzu 1, (ffffffff) => 000000ff, 1 (00000000 00000000)
|
|
+ lbzu -3, (000f423f) => 0000000f, -3 (00000000 00000000)
|
|
+ lbzu -7, (00000000) => 00000000, -7 (00000000 00000000)
|
|
|
|
lha 0, (00000000) => 00000000, 0 (00000000 00000000)
|
|
- lha 4, (000f423f) => 0000000f, 0 (00000000 00000000)
|
|
- lha 8, (ffffffff) => ffffffff, 0 (00000000 00000000)
|
|
- lha -8, (00000000) => 00000000, 0 (00000000 00000000)
|
|
- lha -4, (000f423f) => 0000000f, 0 (00000000 00000000)
|
|
- lha 0, (ffffffff) => ffffffff, 0 (00000000 00000000)
|
|
+ lha 3, (000f423f) => 00000000, 0 (00000000 00000000)
|
|
+ lha 7, (ffffffff) => 00003fff, 0 (00000000 00000000)
|
|
+ lha 1, (ffffffff) => ffffffff, 0 (00000000 00000000)
|
|
+ lha -3, (000f423f) => 00000f42, 0 (00000000 00000000)
|
|
+ lha -7, (00000000) => 00000000, 0 (00000000 00000000)
|
|
|
|
lhau 0, (00000000) => 00000000, 0 (00000000 00000000)
|
|
- lhau 4, (000f423f) => 0000000f, 4 (00000000 00000000)
|
|
- lhau 8, (ffffffff) => ffffffff, 8 (00000000 00000000)
|
|
- lhau -8, (00000000) => 00000000, -8 (00000000 00000000)
|
|
- lhau -4, (000f423f) => 0000000f, -4 (00000000 00000000)
|
|
- lhau 0, (ffffffff) => ffffffff, 0 (00000000 00000000)
|
|
+ lhau 3, (000f423f) => 00000000, 3 (00000000 00000000)
|
|
+ lhau 7, (ffffffff) => 00003fff, 7 (00000000 00000000)
|
|
+ lhau 1, (ffffffff) => ffffffff, 1 (00000000 00000000)
|
|
+ lhau -3, (000f423f) => 00000f42, -3 (00000000 00000000)
|
|
+ lhau -7, (00000000) => 00000000, -7 (00000000 00000000)
|
|
|
|
lhz 0, (00000000) => 00000000, 0 (00000000 00000000)
|
|
- lhz 4, (000f423f) => 0000000f, 0 (00000000 00000000)
|
|
- lhz 8, (ffffffff) => 0000ffff, 0 (00000000 00000000)
|
|
- lhz -8, (00000000) => 00000000, 0 (00000000 00000000)
|
|
- lhz -4, (000f423f) => 0000000f, 0 (00000000 00000000)
|
|
- lhz 0, (ffffffff) => 0000ffff, 0 (00000000 00000000)
|
|
+ lhz 3, (000f423f) => 00000000, 0 (00000000 00000000)
|
|
+ lhz 7, (ffffffff) => 00003fff, 0 (00000000 00000000)
|
|
+ lhz 1, (ffffffff) => 0000ffff, 0 (00000000 00000000)
|
|
+ lhz -3, (000f423f) => 00000f42, 0 (00000000 00000000)
|
|
+ lhz -7, (00000000) => 00000000, 0 (00000000 00000000)
|
|
|
|
lhzu 0, (00000000) => 00000000, 0 (00000000 00000000)
|
|
- lhzu 4, (000f423f) => 0000000f, 4 (00000000 00000000)
|
|
- lhzu 8, (ffffffff) => 0000ffff, 8 (00000000 00000000)
|
|
- lhzu -8, (00000000) => 00000000, -8 (00000000 00000000)
|
|
- lhzu -4, (000f423f) => 0000000f, -4 (00000000 00000000)
|
|
- lhzu 0, (ffffffff) => 0000ffff, 0 (00000000 00000000)
|
|
+ lhzu 3, (000f423f) => 00000000, 3 (00000000 00000000)
|
|
+ lhzu 7, (ffffffff) => 00003fff, 7 (00000000 00000000)
|
|
+ lhzu 1, (ffffffff) => 0000ffff, 1 (00000000 00000000)
|
|
+ lhzu -3, (000f423f) => 00000f42, -3 (00000000 00000000)
|
|
+ lhzu -7, (00000000) => 00000000, -7 (00000000 00000000)
|
|
|
|
lwz 0, (00000000) => 00000000, 0 (00000000 00000000)
|
|
- lwz 4, (000f423f) => 000f423f, 0 (00000000 00000000)
|
|
- lwz 8, (ffffffff) => ffffffff, 0 (00000000 00000000)
|
|
- lwz -8, (00000000) => 00000000, 0 (00000000 00000000)
|
|
- lwz -4, (000f423f) => 000f423f, 0 (00000000 00000000)
|
|
- lwz 0, (ffffffff) => ffffffff, 0 (00000000 00000000)
|
|
+ lwz 3, (000f423f) => 00000f42, 0 (00000000 00000000)
|
|
+ lwz 7, (ffffffff) => 3fffffff, 0 (00000000 00000000)
|
|
+ lwz 1, (ffffffff) => ffffff00, 0 (00000000 00000000)
|
|
+ lwz -3, (000f423f) => 0f423fff, 0 (00000000 00000000)
|
|
+ lwz -7, (00000000) => 00000000, 0 (00000000 00000000)
|
|
|
|
lwzu 0, (00000000) => 00000000, 0 (00000000 00000000)
|
|
- lwzu 4, (000f423f) => 000f423f, 4 (00000000 00000000)
|
|
- lwzu 8, (ffffffff) => ffffffff, 8 (00000000 00000000)
|
|
- lwzu -8, (00000000) => 00000000, -8 (00000000 00000000)
|
|
- lwzu -4, (000f423f) => 000f423f, -4 (00000000 00000000)
|
|
- lwzu 0, (ffffffff) => ffffffff, 0 (00000000 00000000)
|
|
+ lwzu 3, (000f423f) => 00000f42, 3 (00000000 00000000)
|
|
+ lwzu 7, (ffffffff) => 3fffffff, 7 (00000000 00000000)
|
|
+ lwzu 1, (ffffffff) => ffffff00, 1 (00000000 00000000)
|
|
+ lwzu -3, (000f423f) => 0f423fff, -3 (00000000 00000000)
|
|
+ lwzu -7, (00000000) => 00000000, -7 (00000000 00000000)
|
|
|
|
PPC integer load insns with two register args:
|
|
lbzx 0 (00000000) => 00000000, 0 (00000000 00000000)
|
|
Index: none/tests/ppc32/test_isa_2_06_part1.c
|
|
===================================================================
|
|
--- none/tests/ppc32/test_isa_2_06_part1.c.orig
|
|
+++ none/tests/ppc32/test_isa_2_06_part1.c
|
|
@@ -35,7 +35,12 @@ typedef uint32_t HWord_t;
|
|
typedef uint64_t HWord_t;
|
|
#endif /* __powerpc64__ */
|
|
|
|
-static int errors;
|
|
+#ifdef VGP_ppc64le_linux
|
|
+#define isLE 1
|
|
+#else
|
|
+#define isLE 0
|
|
+#endif
|
|
+
|
|
register HWord_t r14 __asm__ ("r14");
|
|
register HWord_t r15 __asm__ ("r15");
|
|
register HWord_t r16 __asm__ ("r16");
|
|
@@ -193,74 +198,14 @@ static void build_fargs_table(void)
|
|
}
|
|
|
|
|
|
-typedef struct ftdiv_test {
|
|
- int fra_idx;
|
|
- int frb_idx;
|
|
- int cr_flags;
|
|
-} ftdiv_test_args_t;
|
|
-
|
|
typedef struct fp_test_args {
|
|
int fra_idx;
|
|
int frb_idx;
|
|
int cr_flags;
|
|
- unsigned long long dp_bin_result;
|
|
} fp_test_args_t;
|
|
|
|
-unsigned long long xscvuxddp_results[] = {
|
|
- 0x43cfec0000000000ULL,
|
|
- 0x43d013c000000000ULL,
|
|
- 0x4338000000b77501ULL,
|
|
- 0x43dffa0000000001ULL,
|
|
- 0x4372321456990000ULL,
|
|
- 0x0000000000000000ULL,
|
|
- 0x43e0000000000000ULL,
|
|
- 0x43dffc0000000000ULL,
|
|
- 0x43effe0000000000ULL,
|
|
- 0x43dffe0000000000ULL,
|
|
- 0x43efff0000000000ULL,
|
|
- 0x43dffe0000000000ULL,
|
|
- 0x43efff0000000000ULL,
|
|
- 0x43e00106800000f0ULL,
|
|
- 0x43e81a0ca1eb40f6ULL
|
|
-};
|
|
-
|
|
-unsigned long long xscvsxddp_results[] = {
|
|
- 0x43cfec0000000000ULL,
|
|
- 0x43d013c000000000ULL,
|
|
- 0x4338000000b77501ULL,
|
|
- 0x43dffa0000000001ULL,
|
|
- 0x4372321456990000ULL,
|
|
- 0x0000000000000000ULL,
|
|
- 0xc3e0000000000000ULL,
|
|
- 0x43dffc0000000000ULL,
|
|
- 0xc330000000000000ULL,
|
|
- 0x43dffe0000000000ULL,
|
|
- 0xc320000000000002ULL,
|
|
- 0x43dffe0000000000ULL,
|
|
- 0xc320000000000000ULL,
|
|
- 0xc3dffdf2fffffe20ULL,
|
|
- 0xc3cf97cd7852fc26ULL,
|
|
-};
|
|
-
|
|
-unsigned long long xscvdpsxds_results[] = {
|
|
- 0x0000000000000000ULL,
|
|
- 0x000000000000003eULL,
|
|
- 0x0000000000000000ULL,
|
|
- 0x7fffffffffffffffULL,
|
|
- 0x0000000000000000ULL,
|
|
- 0x0000000000000000ULL,
|
|
- 0x0000000000000000ULL,
|
|
- 0x7fffffffffffffffULL,
|
|
- 0x8000000000000000ULL,
|
|
- 0x8000000000000000ULL,
|
|
- 0x8000000000000000ULL,
|
|
- 0x8000000000000000ULL,
|
|
- 0x8000000000000000ULL,
|
|
- 0x0000000000000000ULL,
|
|
- 0xffffffffffffbe6cULL
|
|
-};
|
|
|
|
-ftdiv_test_args_t ftdiv_tests[] = {
|
|
+fp_test_args_t ftdiv_tests[] = {
|
|
{0, 1, 0x8},
|
|
{9, 1, 0xa},
|
|
{1, 12, 0xa},
|
|
@@ -278,539 +223,539 @@ ftdiv_test_args_t ftdiv_tests[] = {
|
|
};
|
|
|
|
fp_test_args_t xscmpX_tests[] = {
|
|
- {8, 8, 0x2, 0ULL},
|
|
- {8, 14, 0x8, 0ULL},
|
|
- {8, 6, 0x8, 0ULL},
|
|
- {8, 5, 0x8, 0ULL},
|
|
- {8, 4, 0x8, 0ULL},
|
|
- {8, 7, 0x8, 0ULL},
|
|
- {8, 9, 0x1, 0ULL},
|
|
- {8, 11, 0x1, 0ULL},
|
|
- {14, 8, 0x4, 0ULL},
|
|
- {14, 14, 0x2, 0ULL},
|
|
- {14, 6, 0x8, 0ULL},
|
|
- {14, 5, 0x8, 0ULL},
|
|
- {14, 4, 0x8, 0ULL},
|
|
- {14, 7, 0x8, 0ULL},
|
|
- {14, 9, 0x1, 0ULL},
|
|
- {14, 11, 0x1, 0ULL},
|
|
- {6, 8, 0x4, 0ULL},
|
|
- {6, 14, 0x4, 0ULL},
|
|
- {6, 6, 0x2, 0ULL},
|
|
- {6, 5, 0x2, 0ULL},
|
|
- {6, 4, 0x8, 0ULL},
|
|
- {6, 7, 0x8, 0ULL},
|
|
- {6, 9, 0x1, 0ULL},
|
|
- {6, 11, 0x1, 0ULL},
|
|
- {5, 8, 0x4, 0ULL},
|
|
- {5, 14, 0x4, 0ULL},
|
|
- {5, 6, 0x2, 0ULL},
|
|
- {5, 5, 0x2, 0ULL},
|
|
- {5, 4, 0x8, 0ULL},
|
|
- {5, 7, 0x8, 0ULL},
|
|
- {5, 9, 0x1, 0ULL},
|
|
- {5, 11, 0x1, 0ULL},
|
|
- {4, 8, 0x4, 0ULL},
|
|
- {4, 14, 0x4, 0ULL},
|
|
- {4, 6, 0x4, 0ULL},
|
|
- {4, 5, 0x4, 0ULL},
|
|
- {4, 1, 0x8, 0ULL},
|
|
- {4, 7, 0x8, 0ULL},
|
|
- {4, 9, 0x1, 0ULL},
|
|
- {4, 11, 0x1, 0ULL},
|
|
- {7, 8, 0x4, 0ULL},
|
|
- {7, 14, 0x4, 0ULL},
|
|
- {7, 6, 0x4, 0ULL},
|
|
- {7, 5, 0x4, 0ULL},
|
|
- {7, 4, 0x4, 0ULL},
|
|
- {7, 7, 0x2, 0ULL},
|
|
- {7, 9, 0x1, 0ULL},
|
|
- {7, 11, 0x1, 0ULL},
|
|
- {10, 8, 0x1, 0ULL},
|
|
- {10, 14, 0x1, 0ULL},
|
|
- {10, 6, 0x1, 0ULL},
|
|
- {10, 5, 0x1, 0ULL},
|
|
- {10, 4, 0x1, 0ULL},
|
|
- {10, 7, 0x1, 0ULL},
|
|
- {10, 9, 0x1, 0ULL},
|
|
- {10, 11, 0x1, 0ULL},
|
|
- {12, 8, 0x1, 0ULL},
|
|
- {12, 14, 0x1, 0ULL},
|
|
- {12, 6, 0x1, 0ULL},
|
|
- {12, 5, 0x1, 0ULL},
|
|
- {12, 4, 0x1, 0ULL},
|
|
- {12, 7, 0x1, 0ULL},
|
|
- {12, 9, 0x1, 0ULL},
|
|
- {12, 11, 0x1, 0ULL},
|
|
+ {8, 8, 0x2},
|
|
+ {8, 14, 0x8},
|
|
+ {8, 6, 0x8},
|
|
+ {8, 5, 0x8},
|
|
+ {8, 4, 0x8},
|
|
+ {8, 7, 0x8},
|
|
+ {8, 9, 0x1},
|
|
+ {8, 11, 0x1},
|
|
+ {14, 8, 0x4},
|
|
+ {14, 14, 0x2},
|
|
+ {14, 6, 0x8},
|
|
+ {14, 5, 0x8},
|
|
+ {14, 4, 0x8},
|
|
+ {14, 7, 0x8},
|
|
+ {14, 9, 0x1},
|
|
+ {14, 11, 0x1},
|
|
+ {6, 8, 0x4},
|
|
+ {6, 14, 0x4},
|
|
+ {6, 6, 0x2},
|
|
+ {6, 5, 0x2},
|
|
+ {6, 4, 0x8},
|
|
+ {6, 7, 0x8},
|
|
+ {6, 9, 0x1},
|
|
+ {6, 11, 0x1},
|
|
+ {5, 8, 0x4},
|
|
+ {5, 14, 0x4},
|
|
+ {5, 6, 0x2},
|
|
+ {5, 5, 0x2},
|
|
+ {5, 4, 0x8},
|
|
+ {5, 7, 0x8},
|
|
+ {5, 9, 0x1},
|
|
+ {5, 11, 0x1},
|
|
+ {4, 8, 0x4},
|
|
+ {4, 14, 0x4},
|
|
+ {4, 6, 0x4},
|
|
+ {4, 5, 0x4},
|
|
+ {4, 1, 0x8},
|
|
+ {4, 7, 0x8},
|
|
+ {4, 9, 0x1},
|
|
+ {4, 11, 0x1},
|
|
+ {7, 8, 0x4},
|
|
+ {7, 14, 0x4},
|
|
+ {7, 6, 0x4},
|
|
+ {7, 5, 0x4},
|
|
+ {7, 4, 0x4},
|
|
+ {7, 7, 0x2},
|
|
+ {7, 9, 0x1},
|
|
+ {7, 11, 0x1},
|
|
+ {10, 8, 0x1},
|
|
+ {10, 14, 0x1},
|
|
+ {10, 6, 0x1},
|
|
+ {10, 5, 0x1},
|
|
+ {10, 4, 0x1},
|
|
+ {10, 7, 0x1},
|
|
+ {10, 9, 0x1},
|
|
+ {10, 11, 0x1},
|
|
+ {12, 8, 0x1},
|
|
+ {12, 14, 0x1},
|
|
+ {12, 6, 0x1},
|
|
+ {12, 5, 0x1},
|
|
+ {12, 4, 0x1},
|
|
+ {12, 7, 0x1},
|
|
+ {12, 9, 0x1},
|
|
+ {12, 11, 0x1},
|
|
};
|
|
|
|
fp_test_args_t xsadddp_tests[] = {
|
|
- {8, 8, 0x0, 0xfff0000000000000ULL},
|
|
- {8, 14, 0x0, 0xfff0000000000000ULL},
|
|
- {8, 6, 0x0, 0xfff0000000000000ULL},
|
|
- {8, 5, 0x0, 0xfff0000000000000ULL},
|
|
- {8, 4, 0x0, 0xfff0000000000000ULL},
|
|
- {8, 7, 0x0, 0x7ff8000000000000ULL},
|
|
- {8, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {8, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {14, 8, 0x0, 0xfff0000000000000ULL},
|
|
- {14, 14, 0x0, 0xc0e0650f5a07b353ULL},
|
|
- {14, 6, 0x0, 0xc0d0650f5a07b353ULL},
|
|
- {14, 5, 0x0, 0xc0d0650f5a07b353ULL},
|
|
- {14, 4, 0x0, 0xc0d0650f5a07b353ULL},
|
|
- {14, 7, 0x0, 0x7ff0000000000000ULL},
|
|
- {14, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {14, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {6, 8, 0x0, 0xfff0000000000000ULL},
|
|
- {6, 14, 0x0, 0xc0d0650f5a07b353ULL},
|
|
- {6, 6, 0x0, 0x8000000000000000ULL},
|
|
- {6, 5, 0x0, 0x0000000000000000ULL},
|
|
- {6, 4, 0x0, 0x0123214569900000ULL},
|
|
- {6, 7, 0x0, 0x7ff0000000000000ULL},
|
|
- {6, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {6, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {5, 8, 0x0, 0xfff0000000000000ULL},
|
|
- {5, 14, 0x0, 0xc0d0650f5a07b353ULL},
|
|
- {5, 6, 0x0, 0x0000000000000000ULL},
|
|
- {5, 5, 0x0, 0x0000000000000000ULL},
|
|
- {5, 4, 0x0, 0x0123214569900000ULL},
|
|
- {5, 7, 0x0, 0x7ff0000000000000ULL},
|
|
- {5, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {5, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {4, 8, 0x0, 0xfff0000000000000ULL},
|
|
- {4, 14, 0x0, 0xc0d0650f5a07b353ULL},
|
|
- {4, 6, 0x0, 0x0123214569900000ULL},
|
|
- {4, 5, 0x0, 0x0123214569900000ULL},
|
|
- {4, 1, 0x0, 0x404f000000000000ULL},
|
|
- {4, 7, 0x0, 0x7ff0000000000000ULL},
|
|
- {4, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {4, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {7, 8, 0x0, 0x7ff8000000000000ULL},
|
|
- {7, 14, 0x0, 0x7ff0000000000000ULL},
|
|
- {7, 6, 0x0, 0x7ff0000000000000ULL},
|
|
- {7, 5, 0x0, 0x7ff0000000000000ULL},
|
|
- {7, 4, 0x0, 0x7ff0000000000000ULL},
|
|
- {7, 7, 0x0, 0x7ff0000000000000ULL},
|
|
- {7, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {7, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {10, 8, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 14, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 6, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 5, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 4, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 7, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 9, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 11, 0x0, 0xffffffffffffffffULL},
|
|
- {12, 8, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 14, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 6, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 5, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 4, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 7, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 9, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 11, 0x0, 0xfff8000000000000ULL},
|
|
+ {8, 8, 0x0},
|
|
+ {8, 14, 0x0},
|
|
+ {8, 6, 0x0},
|
|
+ {8, 5, 0x0},
|
|
+ {8, 4, 0x0},
|
|
+ {8, 7, 0x0},
|
|
+ {8, 9, 0x0},
|
|
+ {8, 11, 0x0},
|
|
+ {14, 8, 0x0},
|
|
+ {14, 14, 0x0},
|
|
+ {14, 6, 0x0},
|
|
+ {14, 5, 0x0},
|
|
+ {14, 4, 0x0},
|
|
+ {14, 7, 0x0},
|
|
+ {14, 9, 0x0},
|
|
+ {14, 11, 0x0},
|
|
+ {6, 8, 0x0},
|
|
+ {6, 14, 0x0},
|
|
+ {6, 6, 0x0},
|
|
+ {6, 5, 0x0},
|
|
+ {6, 4, 0x0},
|
|
+ {6, 7, 0x0},
|
|
+ {6, 9, 0x0},
|
|
+ {6, 11, 0x0},
|
|
+ {5, 8, 0x0},
|
|
+ {5, 14, 0x0},
|
|
+ {5, 6, 0x0},
|
|
+ {5, 5, 0x0},
|
|
+ {5, 4, 0x0},
|
|
+ {5, 7, 0x0},
|
|
+ {5, 9, 0x0},
|
|
+ {5, 11, 0x0},
|
|
+ {4, 8, 0x0},
|
|
+ {4, 14, 0x0},
|
|
+ {4, 6, 0x0},
|
|
+ {4, 5, 0x0},
|
|
+ {4, 1, 0x0},
|
|
+ {4, 7, 0x0},
|
|
+ {4, 9, 0x0},
|
|
+ {4, 11, 0x0},
|
|
+ {7, 8, 0x0},
|
|
+ {7, 14, 0x0},
|
|
+ {7, 6, 0x0},
|
|
+ {7, 5, 0x0},
|
|
+ {7, 4, 0x0},
|
|
+ {7, 7, 0x0},
|
|
+ {7, 9, 0x0},
|
|
+ {7, 11, 0x0},
|
|
+ {10, 8, 0x0},
|
|
+ {10, 14, 0x0},
|
|
+ {10, 6, 0x0},
|
|
+ {10, 5, 0x0},
|
|
+ {10, 4, 0x0},
|
|
+ {10, 7, 0x0},
|
|
+ {10, 9, 0x0},
|
|
+ {10, 11, 0x0},
|
|
+ {12, 8, 0x0},
|
|
+ {12, 14, 0x0},
|
|
+ {12, 6, 0x0},
|
|
+ {12, 5, 0x0},
|
|
+ {12, 4, 0x0},
|
|
+ {12, 7, 0x0},
|
|
+ {12, 9, 0x0},
|
|
+ {12, 11, 0x0},
|
|
};
|
|
|
|
fp_test_args_t xsdivdp_tests[] = {
|
|
- {8, 8, 0x0, 0x7ff8000000000000ULL},
|
|
- {8, 14, 0x0, 0x7ff0000000000000ULL},
|
|
- {8, 6, 0x0, 0x7ff0000000000000ULL},
|
|
- {8, 5, 0x0, 0xfff0000000000000ULL},
|
|
- {8, 4, 0x0, 0xfff0000000000000ULL},
|
|
- {8, 7, 0x0, 0x7ff8000000000000ULL},
|
|
- {8, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {8, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {14, 8, 0x0, 0x0000000000000000ULL},
|
|
- {14, 14, 0x0, 0x3ff0000000000000ULL},
|
|
- {14, 6, 0x0, 0x7ff0000000000000ULL},
|
|
- {14, 5, 0x0, 0xfff0000000000000ULL},
|
|
- {14, 4, 0x0, 0xff9b6cb57ca13c00ULL},
|
|
- {14, 7, 0x0, 0x8000000000000000ULL},
|
|
- {14, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {14, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {6, 8, 0x0, 0x0000000000000000ULL},
|
|
- {6, 14, 0x0, 0x0000000000000000ULL},
|
|
- {6, 6, 0x0, 0x7ff8000000000000ULL},
|
|
- {6, 5, 0x0, 0x7ff8000000000000ULL},
|
|
- {6, 4, 0x0, 0x8000000000000000ULL},
|
|
- {6, 7, 0x0, 0x8000000000000000ULL},
|
|
- {6, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {6, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {5, 8, 0x0, 0x8000000000000000ULL},
|
|
- {5, 14, 0x0, 0x8000000000000000ULL},
|
|
- {5, 6, 0x0, 0x7ff8000000000000ULL},
|
|
- {5, 5, 0x0, 0x7ff8000000000000ULL},
|
|
- {5, 4, 0x0, 0x0000000000000000ULL},
|
|
- {5, 7, 0x0, 0x0000000000000000ULL},
|
|
- {5, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {5, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {4, 8, 0x0, 0x8000000000000000ULL},
|
|
- {4, 14, 0x0, 0x8042ab59d8b6ec87ULL},
|
|
- {4, 6, 0x0, 0xfff0000000000000ULL},
|
|
- {4, 5, 0x0, 0x7ff0000000000000ULL},
|
|
- {4, 1, 0x0, 0x00c3bf3f64b5ad6bULL},
|
|
- {4, 7, 0x0, 0x0000000000000000ULL},
|
|
- {4, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {4, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {7, 8, 0x0, 0x7ff8000000000000ULL},
|
|
- {7, 14, 0x0, 0xfff0000000000000ULL},
|
|
- {7, 6, 0x0, 0xfff0000000000000ULL},
|
|
- {7, 5, 0x0, 0x7ff0000000000000ULL},
|
|
- {7, 4, 0x0, 0x7ff0000000000000ULL},
|
|
- {7, 7, 0x0, 0x7ff8000000000000ULL},
|
|
- {7, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {7, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {10, 8, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 14, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 6, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 5, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 4, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 7, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 9, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 11, 0x0, 0xffffffffffffffffULL},
|
|
- {12, 8, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 14, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 6, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 5, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 4, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 7, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 9, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 11, 0x0, 0xfff8000000000000ULL},
|
|
+ {8, 8, 0x0},
|
|
+ {8, 14, 0x0},
|
|
+ {8, 6, 0x0},
|
|
+ {8, 5, 0x0},
|
|
+ {8, 4, 0x0},
|
|
+ {8, 7, 0x0},
|
|
+ {8, 9, 0x0},
|
|
+ {8, 11, 0x0},
|
|
+ {14, 8, 0x0},
|
|
+ {14, 14, 0x0},
|
|
+ {14, 6, 0x0},
|
|
+ {14, 5, 0x0},
|
|
+ {14, 4, 0x0},
|
|
+ {14, 7, 0x0},
|
|
+ {14, 9, 0x0},
|
|
+ {14, 11, 0x0},
|
|
+ {6, 8, 0x0},
|
|
+ {6, 14, 0x0},
|
|
+ {6, 6, 0x0},
|
|
+ {6, 5, 0x0},
|
|
+ {6, 4, 0x0},
|
|
+ {6, 7, 0x0},
|
|
+ {6, 9, 0x0},
|
|
+ {6, 11, 0x0},
|
|
+ {5, 8, 0x0},
|
|
+ {5, 14, 0x0},
|
|
+ {5, 6, 0x0},
|
|
+ {5, 5, 0x0},
|
|
+ {5, 4, 0x0},
|
|
+ {5, 7, 0x0},
|
|
+ {5, 9, 0x0},
|
|
+ {5, 11, 0x0},
|
|
+ {4, 8, 0x0},
|
|
+ {4, 14, 0x0},
|
|
+ {4, 6, 0x0},
|
|
+ {4, 5, 0x0},
|
|
+ {4, 1, 0x0},
|
|
+ {4, 7, 0x0},
|
|
+ {4, 9, 0x0},
|
|
+ {4, 11, 0x0},
|
|
+ {7, 8, 0x0},
|
|
+ {7, 14, 0x0},
|
|
+ {7, 6, 0x0},
|
|
+ {7, 5, 0x0},
|
|
+ {7, 4, 0x0},
|
|
+ {7, 7, 0x0},
|
|
+ {7, 9, 0x0},
|
|
+ {7, 11, 0x0},
|
|
+ {10, 8, 0x0},
|
|
+ {10, 14, 0x0},
|
|
+ {10, 6, 0x0},
|
|
+ {10, 5, 0x0},
|
|
+ {10, 4, 0x0},
|
|
+ {10, 7, 0x0},
|
|
+ {10, 9, 0x0},
|
|
+ {10, 11, 0x0},
|
|
+ {12, 8, 0x0},
|
|
+ {12, 14, 0x0},
|
|
+ {12, 6, 0x0},
|
|
+ {12, 5, 0x0},
|
|
+ {12, 4, 0x0},
|
|
+ {12, 7, 0x0},
|
|
+ {12, 9, 0x0},
|
|
+ {12, 11, 0x0},
|
|
};
|
|
|
|
fp_test_args_t xsmaddXdp_tests[] = {
|
|
- {8, 8, 0x0, 0x7ff8000000000000ULL},
|
|
- {8, 14, 0x0, 0xfff0000000000000ULL},
|
|
- {8, 6, 0x0, 0x7ff0000000000000ULL},
|
|
- {8, 5, 0x0, 0xfff0000000000000ULL},
|
|
- {8, 4, 0x0, 0x7ff0000000000000ULL},
|
|
- {8, 7, 0x0, 0x7ff8000000000000ULL},
|
|
- {8, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {8, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {14, 8, 0x0, 0xfff0000000000000ULL},
|
|
- {14, 14, 0x0, 0xc0d0650f5a07b353ULL},
|
|
- {14, 6, 0x0, 0x41b0cc9d05eec2a7ULL},
|
|
- {14, 5, 0x0, 0x82039a19ca8fcb5fULL},
|
|
- {14, 4, 0x0, 0x41b0cc9d05eec2a7ULL},
|
|
- {14, 7, 0x0, 0x7ff0000000000000ULL},
|
|
- {14, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {14, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {6, 8, 0x0, 0xfff0000000000000ULL},
|
|
- {6, 14, 0x0, 0xc0d0650f5a07b353ULL},
|
|
- {6, 6, 0x0, 0x0000000000000000ULL},
|
|
- {6, 5, 0x0, 0x0000000000000000ULL},
|
|
- {6, 4, 0x0, 0x0123214569900000ULL},
|
|
- {6, 7, 0x0, 0x7ff0000000000000ULL},
|
|
- {6, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {6, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {5, 8, 0x0, 0xfff0000000000000ULL},
|
|
- {5, 14, 0x0, 0xc0d0650f5a07b353ULL},
|
|
- {5, 6, 0x0, 0x8000000000000000ULL},
|
|
- {5, 5, 0x0, 0x0000000000000000ULL},
|
|
- {5, 4, 0x0, 0x0123214569900000ULL},
|
|
- {5, 7, 0x0, 0x7ff0000000000000ULL},
|
|
- {5, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {5, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {4, 8, 0x0, 0xfff0000000000000ULL},
|
|
- {4, 14, 0x0, 0xc0d0650f5a07b353ULL},
|
|
- {4, 6, 0x0, 0x82039a19ca8fcb5fULL},
|
|
- {4, 5, 0x0, 0x0000000000000000ULL},
|
|
- {4, 1, 0x0, 0x404f000000000000ULL},
|
|
- {4, 7, 0x0, 0x7ff0000000000000ULL},
|
|
- {4, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {4, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {7, 8, 0x0, 0xfff0000000000000ULL},
|
|
- {7, 14, 0x0, 0x7ff0000000000000ULL},
|
|
- {7, 6, 0x0, 0xfff0000000000000ULL},
|
|
- {7, 5, 0x0, 0x7ff0000000000000ULL},
|
|
- {7, 4, 0x0, 0xfff0000000000000ULL},
|
|
- {7, 7, 0x0, 0x7ff0000000000000ULL},
|
|
- {7, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {7, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {10, 8, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 14, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 6, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 5, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 4, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 7, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 9, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 11, 0x0, 0xffffffffffffffffULL},
|
|
- {12, 8, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 14, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 6, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 5, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 4, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 7, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 9, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 11, 0x0, 0xfff8000000000000ULL},
|
|
+ {8, 8, 0x0},
|
|
+ {8, 14, 0x0},
|
|
+ {8, 6, 0x0},
|
|
+ {8, 5, 0x0},
|
|
+ {8, 4, 0x0},
|
|
+ {8, 7, 0x0},
|
|
+ {8, 9, 0x0},
|
|
+ {8, 11, 0x0},
|
|
+ {14, 8, 0x0},
|
|
+ {14, 14, 0x0},
|
|
+ {14, 6, 0x0},
|
|
+ {14, 5, 0x0},
|
|
+ {14, 4, 0x0},
|
|
+ {14, 7, 0x0},
|
|
+ {14, 9, 0x0},
|
|
+ {14, 11, 0x0},
|
|
+ {6, 8, 0x0},
|
|
+ {6, 14, 0x0},
|
|
+ {6, 6, 0x0},
|
|
+ {6, 5, 0x0},
|
|
+ {6, 4, 0x0},
|
|
+ {6, 7, 0x0},
|
|
+ {6, 9, 0x0},
|
|
+ {6, 11, 0x0},
|
|
+ {5, 8, 0x0},
|
|
+ {5, 14, 0x0},
|
|
+ {5, 6, 0x0},
|
|
+ {5, 5, 0x0},
|
|
+ {5, 4, 0x0},
|
|
+ {5, 7, 0x0},
|
|
+ {5, 9, 0x0},
|
|
+ {5, 11, 0x0},
|
|
+ {4, 8, 0x0},
|
|
+ {4, 14, 0x0},
|
|
+ {4, 6, 0x0},
|
|
+ {4, 5, 0x0},
|
|
+ {4, 1, 0x0},
|
|
+ {4, 7, 0x0},
|
|
+ {4, 9, 0x0},
|
|
+ {4, 11, 0x0},
|
|
+ {7, 8, 0x0},
|
|
+ {7, 14, 0x0},
|
|
+ {7, 6, 0x0},
|
|
+ {7, 5, 0x0},
|
|
+ {7, 4, 0x0},
|
|
+ {7, 7, 0x0},
|
|
+ {7, 9, 0x0},
|
|
+ {7, 11, 0x0},
|
|
+ {10, 8, 0x0},
|
|
+ {10, 14, 0x0},
|
|
+ {10, 6, 0x0},
|
|
+ {10, 5, 0x0},
|
|
+ {10, 4, 0x0},
|
|
+ {10, 7, 0x0},
|
|
+ {10, 9, 0x0},
|
|
+ {10, 11, 0x0},
|
|
+ {12, 8, 0x0},
|
|
+ {12, 14, 0x0},
|
|
+ {12, 6, 0x0},
|
|
+ {12, 5, 0x0},
|
|
+ {12, 4, 0x0},
|
|
+ {12, 7, 0x0},
|
|
+ {12, 9, 0x0},
|
|
+ {12, 11, 0x0},
|
|
};
|
|
|
|
fp_test_args_t xsmsubXdp_tests[] = {
|
|
- {8, 8, 0x0, 0x7ff0000000000000ULL},
|
|
- {8, 14, 0x0, 0xfff0000000000000ULL},
|
|
- {8, 6, 0x0, 0x7ff0000000000000ULL},
|
|
- {8, 5, 0x0, 0xfff0000000000000ULL},
|
|
- {8, 4, 0x0, 0x7ff0000000000000ULL},
|
|
- {8, 7, 0x0, 0xfff0000000000000ULL},
|
|
- {8, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {8, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {14, 8, 0x0, 0x7ff0000000000000ULL},
|
|
- {14, 14, 0x0, 0x40d0650f5a07b353ULL},
|
|
- {14, 6, 0x0, 0x41b0cc9d05eec2a7ULL},
|
|
- {14, 5, 0x0, 0x82039a19ca8fcb5fULL},
|
|
- {14, 4, 0x0, 0x41b0cc9d05eec2a7ULL},
|
|
- {14, 7, 0x0, 0xfff0000000000000ULL},
|
|
- {14, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {14, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {6, 8, 0x0, 0x7ff0000000000000ULL},
|
|
- {6, 14, 0x0, 0x40d0650f5a07b353ULL},
|
|
- {6, 6, 0x0, 0x0000000000000000ULL},
|
|
- {6, 5, 0x0, 0x8000000000000000ULL},
|
|
- {6, 4, 0x0, 0x8123214569900000ULL},
|
|
- {6, 7, 0x0, 0xfff0000000000000ULL},
|
|
- {6, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {6, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {5, 8, 0x0, 0x7ff0000000000000ULL},
|
|
- {5, 14, 0x0, 0x40d0650f5a07b353ULL},
|
|
- {5, 6, 0x0, 0x0000000000000000ULL},
|
|
- {5, 5, 0x0, 0x0000000000000000ULL},
|
|
- {5, 4, 0x0, 0x8123214569900000ULL},
|
|
- {5, 7, 0x0, 0xfff0000000000000ULL},
|
|
- {5, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {5, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {4, 8, 0x0, 0x7ff0000000000000ULL},
|
|
- {4, 14, 0x0, 0x40d0650f5a07b353ULL},
|
|
- {4, 6, 0x0, 0x82039a19ca8fcb5fULL},
|
|
- {4, 5, 0x0, 0x0000000000000000ULL},
|
|
- {4, 1, 0x0, 0xc04f000000000000ULL},
|
|
- {4, 7, 0x0, 0xfff0000000000000ULL},
|
|
- {4, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {4, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {7, 8, 0x0, 0x7ff8000000000000ULL},
|
|
- {7, 14, 0x0, 0x7ff0000000000000ULL},
|
|
- {7, 6, 0x0, 0xfff0000000000000ULL},
|
|
- {7, 5, 0x0, 0x7ff0000000000000ULL},
|
|
- {7, 4, 0x0, 0xfff0000000000000ULL},
|
|
- {7, 7, 0x0, 0x7ff8000000000000ULL},
|
|
- {7, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {7, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {10, 8, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 14, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 6, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 5, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 4, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 7, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 9, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 11, 0x0, 0xffffffffffffffffULL},
|
|
- {12, 8, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 14, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 6, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 5, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 4, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 7, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 9, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 11, 0x0, 0xfff8000000000000ULL},
|
|
+ {8, 8, 0x0},
|
|
+ {8, 14, 0x0},
|
|
+ {8, 6, 0x0},
|
|
+ {8, 5, 0x0},
|
|
+ {8, 4, 0x0},
|
|
+ {8, 7, 0x0},
|
|
+ {8, 9, 0x0},
|
|
+ {8, 11, 0x0},
|
|
+ {14, 8, 0x0},
|
|
+ {14, 14, 0x0},
|
|
+ {14, 6, 0x0},
|
|
+ {14, 5, 0x0},
|
|
+ {14, 4, 0x0},
|
|
+ {14, 7, 0x0},
|
|
+ {14, 9, 0x0},
|
|
+ {14, 11, 0x0},
|
|
+ {6, 8, 0x0},
|
|
+ {6, 14, 0x0},
|
|
+ {6, 6, 0x0},
|
|
+ {6, 5, 0x0},
|
|
+ {6, 4, 0x0},
|
|
+ {6, 7, 0x0},
|
|
+ {6, 9, 0x0},
|
|
+ {6, 11, 0x0},
|
|
+ {5, 8, 0x0},
|
|
+ {5, 14, 0x0},
|
|
+ {5, 6, 0x0},
|
|
+ {5, 5, 0x0},
|
|
+ {5, 4, 0x0},
|
|
+ {5, 7, 0x0},
|
|
+ {5, 9, 0x0},
|
|
+ {5, 11, 0x0},
|
|
+ {4, 8, 0x0},
|
|
+ {4, 14, 0x0},
|
|
+ {4, 6, 0x0},
|
|
+ {4, 5, 0x0},
|
|
+ {4, 1, 0x0},
|
|
+ {4, 7, 0x0},
|
|
+ {4, 9, 0x0},
|
|
+ {4, 11, 0x0},
|
|
+ {7, 8, 0x0},
|
|
+ {7, 14, 0x0},
|
|
+ {7, 6, 0x0},
|
|
+ {7, 5, 0x0},
|
|
+ {7, 4, 0x0},
|
|
+ {7, 7, 0x0},
|
|
+ {7, 9, 0x0},
|
|
+ {7, 11, 0x0},
|
|
+ {10, 8, 0x0},
|
|
+ {10, 14, 0x0},
|
|
+ {10, 6, 0x0},
|
|
+ {10, 5, 0x0},
|
|
+ {10, 4, 0x0},
|
|
+ {10, 7, 0x0},
|
|
+ {10, 9, 0x0},
|
|
+ {10, 11, 0x0},
|
|
+ {12, 8, 0x0},
|
|
+ {12, 14, 0x0},
|
|
+ {12, 6, 0x0},
|
|
+ {12, 5, 0x0},
|
|
+ {12, 4, 0x0},
|
|
+ {12, 7, 0x0},
|
|
+ {12, 9, 0x0},
|
|
+ {12, 11, 0x0},
|
|
};
|
|
|
|
fp_test_args_t xsnmaddXdp_tests[] = {
|
|
- {8, 8, 0x0, 0x7ff8000000000000ULL},
|
|
- {8, 14, 0x0, 0x7ff0000000000000ULL},
|
|
- {8, 6, 0x0, 0xfff0000000000000ULL},
|
|
- {8, 5, 0x0, 0x7ff0000000000000ULL},
|
|
- {8, 4, 0x0, 0xfff0000000000000ULL},
|
|
- {8, 7, 0x0, 0x7ff8000000000000ULL},
|
|
- {8, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {8, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {14, 8, 0x0, 0x7ff0000000000000ULL},
|
|
- {14, 14, 0x0, 0x40d0650f5a07b353ULL},
|
|
- {14, 6, 0x0, 0xc1b0cc9d05eec2a7ULL},
|
|
- {14, 5, 0x0, 0x02039a19ca8fcb5fULL},
|
|
- {14, 4, 0x0, 0xc1b0cc9d05eec2a7ULL},
|
|
- {14, 7, 0x0, 0xfff0000000000000ULL},
|
|
- {14, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {14, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {6, 8, 0x0, 0x7ff0000000000000ULL},
|
|
- {6, 14, 0x0, 0x40d0650f5a07b353ULL},
|
|
- {6, 6, 0x0, 0x8000000000000000ULL},
|
|
- {6, 5, 0x0, 0x8000000000000000ULL},
|
|
- {6, 4, 0x0, 0x8123214569900000ULL},
|
|
- {6, 7, 0x0, 0xfff0000000000000ULL},
|
|
- {6, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {6, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {5, 8, 0x0, 0x7ff0000000000000ULL},
|
|
- {5, 14, 0x0, 0x40d0650f5a07b353ULL},
|
|
- {5, 6, 0x0, 0x0000000000000000ULL},
|
|
- {5, 5, 0x0, 0x8000000000000000ULL},
|
|
- {5, 4, 0x0, 0x8123214569900000ULL},
|
|
- {5, 7, 0x0, 0xfff0000000000000ULL},
|
|
- {5, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {5, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {4, 8, 0x0, 0x7ff0000000000000ULL},
|
|
- {4, 14, 0x0, 0x40d0650f5a07b353ULL},
|
|
- {4, 6, 0x0, 0x02039a19ca8fcb5fULL},
|
|
- {4, 5, 0x0, 0x8000000000000000ULL},
|
|
- {4, 1, 0x0, 0xc04f000000000000ULL},
|
|
- {4, 7, 0x0, 0xfff0000000000000ULL},
|
|
- {4, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {4, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {7, 8, 0x0, 0x7ff0000000000000ULL},
|
|
- {7, 14, 0x0, 0xfff0000000000000ULL},
|
|
- {7, 6, 0x0, 0x7ff0000000000000ULL},
|
|
- {7, 5, 0x0, 0xfff0000000000000ULL},
|
|
- {7, 4, 0x0, 0x7ff0000000000000ULL},
|
|
- {7, 7, 0x0, 0xfff0000000000000ULL},
|
|
- {7, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {7, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {10, 8, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 14, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 6, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 5, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 4, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 7, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 9, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 11, 0x0, 0xffffffffffffffffULL},
|
|
- {12, 8, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 14, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 6, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 5, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 4, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 7, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 9, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 11, 0x0, 0xfff8000000000000ULL},
|
|
+ {8, 8, 0x0},
|
|
+ {8, 14, 0x0},
|
|
+ {8, 6, 0x0},
|
|
+ {8, 5, 0x0},
|
|
+ {8, 4, 0x0},
|
|
+ {8, 7, 0x0},
|
|
+ {8, 9, 0x0},
|
|
+ {8, 11, 0x0},
|
|
+ {14, 8, 0x0},
|
|
+ {14, 14, 0x0},
|
|
+ {14, 6, 0x0},
|
|
+ {14, 5, 0x0},
|
|
+ {14, 4, 0x0},
|
|
+ {14, 7, 0x0},
|
|
+ {14, 9, 0x0},
|
|
+ {14, 11, 0x0},
|
|
+ {6, 8, 0x0},
|
|
+ {6, 14, 0x0},
|
|
+ {6, 6, 0x0},
|
|
+ {6, 5, 0x0},
|
|
+ {6, 4, 0x0},
|
|
+ {6, 7, 0x0},
|
|
+ {6, 9, 0x0},
|
|
+ {6, 11, 0x0},
|
|
+ {5, 8, 0x0},
|
|
+ {5, 14, 0x0},
|
|
+ {5, 6, 0x0},
|
|
+ {5, 5, 0x0},
|
|
+ {5, 4, 0x0},
|
|
+ {5, 7, 0x0},
|
|
+ {5, 9, 0x0},
|
|
+ {5, 11, 0x0},
|
|
+ {4, 8, 0x0},
|
|
+ {4, 14, 0x0},
|
|
+ {4, 6, 0x0},
|
|
+ {4, 5, 0x0},
|
|
+ {4, 1, 0x0},
|
|
+ {4, 7, 0x0},
|
|
+ {4, 9, 0x0},
|
|
+ {4, 11, 0x0},
|
|
+ {7, 8, 0x0},
|
|
+ {7, 14, 0x0},
|
|
+ {7, 6, 0x0},
|
|
+ {7, 5, 0x0},
|
|
+ {7, 4, 0x0},
|
|
+ {7, 7, 0x0},
|
|
+ {7, 9, 0x0},
|
|
+ {7, 11, 0x0},
|
|
+ {10, 8, 0x0},
|
|
+ {10, 14, 0x0},
|
|
+ {10, 6, 0x0},
|
|
+ {10, 5, 0x0},
|
|
+ {10, 4, 0x0},
|
|
+ {10, 7, 0x0},
|
|
+ {10, 9, 0x0},
|
|
+ {10, 11, 0x0},
|
|
+ {12, 8, 0x0},
|
|
+ {12, 14, 0x0},
|
|
+ {12, 6, 0x0},
|
|
+ {12, 5, 0x0},
|
|
+ {12, 4, 0x0},
|
|
+ {12, 7, 0x0},
|
|
+ {12, 9, 0x0},
|
|
+ {12, 11, 0x0},
|
|
};
|
|
|
|
fp_test_args_t xsmuldp_tests[] = {
|
|
- {8, 8, 0x0, 0x7ff0000000000000ULL},
|
|
- {8, 14, 0x0, 0x7ff0000000000000ULL},
|
|
- {8, 6, 0x0, 0x7ff8000000000000ULL},
|
|
- {8, 5, 0x0, 0x7ff8000000000000ULL},
|
|
- {8, 4, 0x0, 0xfff0000000000000ULL},
|
|
- {8, 7, 0x0, 0xfff0000000000000ULL},
|
|
- {8, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {8, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {14, 8, 0x0, 0x7ff0000000000000ULL},
|
|
- {14, 14, 0x0, 0x41b0cc9d05eec2a7ULL},
|
|
- {14, 6, 0x0, 0x0000000000000000ULL},
|
|
- {14, 5, 0x0, 0x8000000000000000ULL},
|
|
- {14, 4, 0x0, 0x82039a19ca8fcb5fULL},
|
|
- {14, 7, 0x0, 0xfff0000000000000ULL},
|
|
- {14, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {14, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {6, 8, 0x0, 0x7ff8000000000000ULL},
|
|
- {6, 14, 0x0, 0x0000000000000000ULL},
|
|
- {6, 6, 0x0, 0x0000000000000000ULL},
|
|
- {6, 5, 0x0, 0x8000000000000000ULL},
|
|
- {6, 4, 0x0, 0x8000000000000000ULL},
|
|
- {6, 7, 0x0, 0x7ff8000000000000ULL},
|
|
- {6, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {6, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {5, 8, 0x0, 0x7ff8000000000000ULL},
|
|
- {5, 14, 0x0, 0x8000000000000000ULL},
|
|
- {5, 6, 0x0, 0x8000000000000000ULL},
|
|
- {5, 5, 0x0, 0x0000000000000000ULL},
|
|
- {5, 4, 0x0, 0x0000000000000000ULL},
|
|
- {5, 7, 0x0, 0x7ff8000000000000ULL},
|
|
- {5, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {5, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {4, 8, 0x0, 0xfff0000000000000ULL},
|
|
- {4, 14, 0x0, 0x82039a19ca8fcb5fULL},
|
|
- {4, 6, 0x0, 0x8000000000000000ULL},
|
|
- {4, 5, 0x0, 0x0000000000000000ULL},
|
|
- {4, 1, 0x0, 0x0182883b3e438000ULL},
|
|
- {4, 7, 0x0, 0x7ff0000000000000ULL},
|
|
- {4, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {4, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {7, 8, 0x0, 0xfff0000000000000ULL},
|
|
- {7, 14, 0x0, 0xfff0000000000000ULL},
|
|
- {7, 6, 0x0, 0x7ff8000000000000ULL},
|
|
- {7, 5, 0x0, 0x7ff8000000000000ULL},
|
|
- {7, 4, 0x0, 0x7ff0000000000000ULL},
|
|
- {7, 7, 0x0, 0x7ff0000000000000ULL},
|
|
- {7, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {7, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {10, 8, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 14, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 6, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 5, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 4, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 7, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 9, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 11, 0x0, 0xffffffffffffffffULL},
|
|
- {12, 8, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 14, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 6, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 5, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 4, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 7, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 9, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 11, 0x0, 0xfff8000000000000ULL},
|
|
+ {8, 8, 0x0},
|
|
+ {8, 14, 0x0},
|
|
+ {8, 6, 0x0},
|
|
+ {8, 5, 0x0},
|
|
+ {8, 4, 0x0},
|
|
+ {8, 7, 0x0},
|
|
+ {8, 9, 0x0},
|
|
+ {8, 11, 0x0},
|
|
+ {14, 8, 0x0},
|
|
+ {14, 14, 0x0},
|
|
+ {14, 6, 0x0},
|
|
+ {14, 5, 0x0},
|
|
+ {14, 4, 0x0},
|
|
+ {14, 7, 0x0},
|
|
+ {14, 9, 0x0},
|
|
+ {14, 11, 0x0},
|
|
+ {6, 8, 0x0},
|
|
+ {6, 14, 0x0},
|
|
+ {6, 6, 0x0},
|
|
+ {6, 5, 0x0},
|
|
+ {6, 4, 0x0},
|
|
+ {6, 7, 0x0},
|
|
+ {6, 9, 0x0},
|
|
+ {6, 11, 0x0},
|
|
+ {5, 8, 0x0},
|
|
+ {5, 14, 0x0},
|
|
+ {5, 6, 0x0},
|
|
+ {5, 5, 0x0},
|
|
+ {5, 4, 0x0},
|
|
+ {5, 7, 0x0},
|
|
+ {5, 9, 0x0},
|
|
+ {5, 11, 0x0},
|
|
+ {4, 8, 0x0},
|
|
+ {4, 14, 0x0},
|
|
+ {4, 6, 0x0},
|
|
+ {4, 5, 0x0},
|
|
+ {4, 1, 0x0},
|
|
+ {4, 7, 0x0},
|
|
+ {4, 9, 0x0},
|
|
+ {4, 11, 0x0},
|
|
+ {7, 8, 0x0},
|
|
+ {7, 14, 0x0},
|
|
+ {7, 6, 0x0},
|
|
+ {7, 5, 0x0},
|
|
+ {7, 4, 0x0},
|
|
+ {7, 7, 0x0},
|
|
+ {7, 9, 0x0},
|
|
+ {7, 11, 0x0},
|
|
+ {10, 8, 0x0},
|
|
+ {10, 14, 0x0},
|
|
+ {10, 6, 0x0},
|
|
+ {10, 5, 0x0},
|
|
+ {10, 4, 0x0},
|
|
+ {10, 7, 0x0},
|
|
+ {10, 9, 0x0},
|
|
+ {10, 11, 0x0},
|
|
+ {12, 8, 0x0},
|
|
+ {12, 14, 0x0},
|
|
+ {12, 6, 0x0},
|
|
+ {12, 5, 0x0},
|
|
+ {12, 4, 0x0},
|
|
+ {12, 7, 0x0},
|
|
+ {12, 9, 0x0},
|
|
+ {12, 11, 0x0},
|
|
};
|
|
|
|
fp_test_args_t xssubdp_tests[] = {
|
|
- {8, 8, 0x0, 0x7ff8000000000000ULL},
|
|
- {8, 14, 0x0, 0xfff0000000000000ULL},
|
|
- {8, 6, 0x0, 0xfff0000000000000ULL},
|
|
- {8, 5, 0x0, 0xfff0000000000000ULL},
|
|
- {8, 4, 0x0, 0xfff0000000000000ULL},
|
|
- {8, 7, 0x0, 0xfff0000000000000ULL},
|
|
- {8, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {8, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {14, 8, 0x0, 0x7ff0000000000000ULL},
|
|
- {14, 14, 0x0, 0x0000000000000000ULL},
|
|
- {14, 6, 0x0, 0xc0d0650f5a07b353ULL},
|
|
- {14, 5, 0x0, 0xc0d0650f5a07b353ULL},
|
|
- {14, 4, 0x0, 0xc0d0650f5a07b353ULL},
|
|
- {14, 7, 0x0, 0xfff0000000000000ULL},
|
|
- {14, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {14, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {6, 8, 0x0, 0x7ff0000000000000ULL},
|
|
- {6, 14, 0x0, 0x40d0650f5a07b353ULL},
|
|
- {6, 6, 0x0, 0x0000000000000000ULL},
|
|
- {6, 5, 0x0, 0x8000000000000000ULL},
|
|
- {6, 4, 0x0, 0x8123214569900000ULL},
|
|
- {6, 7, 0x0, 0xfff0000000000000ULL},
|
|
- {6, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {6, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {5, 8, 0x0, 0x7ff0000000000000ULL},
|
|
- {5, 14, 0x0, 0x40d0650f5a07b353ULL},
|
|
- {5, 6, 0x0, 0x0000000000000000ULL},
|
|
- {5, 5, 0x0, 0x0000000000000000ULL},
|
|
- {5, 4, 0x0, 0x8123214569900000ULL},
|
|
- {5, 7, 0x0, 0xfff0000000000000ULL},
|
|
- {5, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {5, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {4, 8, 0x0, 0x7ff0000000000000ULL},
|
|
- {4, 14, 0x0, 0x40d0650f5a07b353ULL},
|
|
- {4, 6, 0x0, 0x0123214569900000ULL},
|
|
- {4, 5, 0x0, 0x0123214569900000ULL},
|
|
- {4, 1, 0x0, 0xc04f000000000000ULL},
|
|
- {4, 7, 0x0, 0xfff0000000000000ULL},
|
|
- {4, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {4, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {7, 8, 0x0, 0x7ff0000000000000ULL},
|
|
- {7, 14, 0x0, 0x7ff0000000000000ULL},
|
|
- {7, 6, 0x0, 0x7ff0000000000000ULL},
|
|
- {7, 5, 0x0, 0x7ff0000000000000ULL},
|
|
- {7, 4, 0x0, 0x7ff0000000000000ULL},
|
|
- {7, 7, 0x0, 0x7ff8000000000000ULL},
|
|
- {7, 9, 0x0, 0x7fffffffffffffffULL},
|
|
- {7, 11, 0x0, 0x7ff8000000000000ULL},
|
|
- {10, 8, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 14, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 6, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 5, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 4, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 7, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 9, 0x0, 0xffffffffffffffffULL},
|
|
- {10, 11, 0x0, 0xffffffffffffffffULL},
|
|
- {12, 8, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 14, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 6, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 5, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 4, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 7, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 9, 0x0, 0xfff8000000000000ULL},
|
|
- {12, 11, 0x0, 0xfff8000000000000ULL},
|
|
+ {8, 8, 0x0},
|
|
+ {8, 14, 0x0},
|
|
+ {8, 6, 0x0},
|
|
+ {8, 5, 0x0},
|
|
+ {8, 4, 0x0},
|
|
+ {8, 7, 0x0},
|
|
+ {8, 9, 0x0},
|
|
+ {8, 11, 0x0},
|
|
+ {14, 8, 0x0},
|
|
+ {14, 14, 0x0},
|
|
+ {14, 6, 0x0},
|
|
+ {14, 5, 0x0},
|
|
+ {14, 4, 0x0},
|
|
+ {14, 7, 0x0},
|
|
+ {14, 9, 0x0},
|
|
+ {14, 11, 0x0},
|
|
+ {6, 8, 0x0},
|
|
+ {6, 14, 0x0},
|
|
+ {6, 6, 0x0},
|
|
+ {6, 5, 0x0},
|
|
+ {6, 4, 0x0},
|
|
+ {6, 7, 0x0},
|
|
+ {6, 9, 0x0},
|
|
+ {6, 11, 0x0},
|
|
+ {5, 8, 0x0},
|
|
+ {5, 14, 0x0},
|
|
+ {5, 6, 0x0},
|
|
+ {5, 5, 0x0},
|
|
+ {5, 4, 0x0},
|
|
+ {5, 7, 0x0},
|
|
+ {5, 9, 0x0},
|
|
+ {5, 11, 0x0},
|
|
+ {4, 8, 0x0},
|
|
+ {4, 14, 0x0},
|
|
+ {4, 6, 0x0},
|
|
+ {4, 5, 0x0},
|
|
+ {4, 1, 0x0},
|
|
+ {4, 7, 0x0},
|
|
+ {4, 9, 0x0},
|
|
+ {4, 11, 0x0},
|
|
+ {7, 8, 0x0},
|
|
+ {7, 14, 0x0},
|
|
+ {7, 6, 0x0},
|
|
+ {7, 5, 0x0},
|
|
+ {7, 4, 0x0},
|
|
+ {7, 7, 0x0},
|
|
+ {7, 9, 0x0},
|
|
+ {7, 11, 0x0},
|
|
+ {10, 8, 0x0},
|
|
+ {10, 14, 0x0},
|
|
+ {10, 6, 0x0},
|
|
+ {10, 5, 0x0},
|
|
+ {10, 4, 0x0},
|
|
+ {10, 7, 0x0},
|
|
+ {10, 9, 0x0},
|
|
+ {10, 11, 0x0},
|
|
+ {12, 8, 0x0},
|
|
+ {12, 14, 0x0},
|
|
+ {12, 6, 0x0},
|
|
+ {12, 5, 0x0},
|
|
+ {12, 4, 0x0},
|
|
+ {12, 7, 0x0},
|
|
+ {12, 9, 0x0},
|
|
+ {12, 11, 0x0},
|
|
};
|
|
|
|
|
|
@@ -1091,7 +1036,6 @@ struct xs_conv_test
|
|
{
|
|
test_func_t test_func;
|
|
const char *name;
|
|
- unsigned long long * results;
|
|
int num_tests;
|
|
};
|
|
|
|
@@ -1130,8 +1074,6 @@ struct vsx_move_test
|
|
{
|
|
test_func_t test_func;
|
|
const char *name;
|
|
- int xa_idx, xb_idx;
|
|
- unsigned long long expected_result;
|
|
};
|
|
|
|
struct vsx_permute_test
|
|
@@ -1140,7 +1082,6 @@ struct vsx_permute_test
|
|
const char *name;
|
|
unsigned int xa[4];
|
|
unsigned int xb[4];
|
|
- unsigned int expected_output[4];
|
|
};
|
|
|
|
static vector unsigned int vec_out, vec_inA, vec_inB;
|
|
@@ -1402,13 +1343,13 @@ static logic_test_t logic_tests[] = { {
|
|
{ &test_xxlnor, "xxlnor", VSX_NOR },
|
|
{ &test_xxland, "xxland", VSX_AND },
|
|
{ &test_xxlandc, "xxlandc", VSX_ANDC },
|
|
- { NULL, NULL}};
|
|
+ { NULL, NULL, 0}};
|
|
|
|
-static move_test_t move_tests[] = { { &test_xsabsdp, "xsabsdp", 0, 4, 0x0899aabb91929394ULL },
|
|
- { &test_xscpsgndp, "xscpsgndp", 4, 0, 0x8123456789abcdefULL },
|
|
- { &test_xsnabsdp, "xsnabsdp", 7, 3, 0xc45566778899aabbULL, },
|
|
- { &test_xsnegdp, "xsnegdp", 0, 7, 0x31b2b3b4c1c2c3c4ULL, },
|
|
- { NULL, NULL, 0, 0, 0 }
|
|
+static move_test_t move_tests[] = { { &test_xsabsdp, "xsabsdp" },
|
|
+ { &test_xscpsgndp, "xscpsgndp" },
|
|
+ { &test_xsnabsdp, "xsnabsdp" },
|
|
+ { &test_xsnegdp, "xsnegdp" },
|
|
+ { NULL, NULL }
|
|
|
|
};
|
|
|
|
@@ -1417,62 +1358,50 @@ static permute_test_t permute_tests[] =
|
|
{ &test_xxmrghw, "xxmrghw",
|
|
{ 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
|
|
{ 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
|
|
- { 0x11111111, 0x55555555, 0x22222222, 0x66666666 } /* XT expected output */
|
|
},
|
|
{ &test_xxmrghw, "xxmrghw",
|
|
{ 0x00112233, 0x44556677, 0x8899aabb, 0xccddeeff }, /* XA input */
|
|
{ 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XB input */
|
|
- { 0x00112233, 0x11111111, 0x44556677, 0x22222222 } /* XT expected output */
|
|
},
|
|
{ &test_xxmrglw, "xxmrglw",
|
|
{ 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
|
|
{ 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
|
|
- { 0x33333333, 0x77777777, 0x44444444, 0x88888888 } /* XT expected output */
|
|
},
|
|
{ &test_xxmrglw, "xxmrglw",
|
|
{ 0x00112233, 0x44556677, 0x8899aabb, 0xccddeeff}, /* XA input */
|
|
{ 0x11111111, 0x22222222, 0x33333333, 0x44444444}, /* XB input */
|
|
- { 0x8899aabb, 0x33333333, 0xccddeeff, 0x44444444} /* XT expected output */
|
|
},
|
|
{ &test_xxpermdi_00, "xxpermdi DM=00",
|
|
{ 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
|
|
{ 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
|
|
- { 0x11111111, 0x22222222, 0x55555555, 0x66666666 } /* XT expected output */
|
|
},
|
|
{ &test_xxpermdi_01, "xxpermdi DM=01",
|
|
{ 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
|
|
{ 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
|
|
- { 0x11111111, 0x22222222, 0x77777777, 0x88888888 } /* XT expected output */
|
|
},
|
|
{ &test_xxpermdi_10, "xxpermdi DM=10",
|
|
{ 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
|
|
{ 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
|
|
- { 0x33333333, 0x44444444, 0x55555555, 0x66666666 } /* XT expected output */
|
|
},
|
|
{ &test_xxpermdi_11, "xxpermdi DM=11",
|
|
{ 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
|
|
{ 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
|
|
- { 0x33333333, 0x44444444, 0x77777777, 0x88888888 } /* XT expected output */
|
|
},
|
|
{ &test_xxsldwi_0, "xxsldwi SHW=0",
|
|
{ 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
|
|
{ 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
|
|
- { 0x11111111, 0x22222222, 0x33333333, 0x44444444 } /* XT expected output */
|
|
},
|
|
{ &test_xxsldwi_1, "xxsldwi SHW=1",
|
|
{ 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
|
|
{ 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
|
|
- { 0x22222222, 0x33333333, 0x44444444, 0x55555555 } /* XT expected output */
|
|
},
|
|
{ &test_xxsldwi_2, "xxsldwi SHW=2",
|
|
{ 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
|
|
{ 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
|
|
- { 0x33333333, 0x44444444, 0x55555555, 0x66666666 } /* XT expected output */
|
|
},
|
|
{ &test_xxsldwi_3, "xxsldwi SHW=3",
|
|
{ 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
|
|
{ 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
|
|
- { 0x44444444, 0x55555555, 0x66666666, 0x77777777 } /* XT expected output */
|
|
},
|
|
{ NULL, NULL }
|
|
};
|
|
@@ -1497,16 +1426,16 @@ static vx_fp_test_t vx_fp_tests[] = {
|
|
};
|
|
|
|
static xs_conv_test_t xs_conv_tests[] = {
|
|
- { &test_xscvdpsxds, "xscvdpsxds", xscvdpsxds_results, 15},
|
|
- { &test_xscvsxddp, "xscvsxddp", xscvsxddp_results, 15},
|
|
- { &test_xscvuxddp, "xscvuxddp", xscvuxddp_results, 15},
|
|
- { NULL, NULL, NULL, 0}
|
|
+ { &test_xscvdpsxds, "xscvdpsxds", 15},
|
|
+ { &test_xscvsxddp, "xscvsxddp", 15},
|
|
+ { &test_xscvuxddp, "xscvuxddp", 15},
|
|
+ { NULL, NULL, 0}
|
|
};
|
|
|
|
#ifdef __powerpc64__
|
|
static void test_ldbrx(void)
|
|
{
|
|
- int i, equality;
|
|
+ int i;
|
|
HWord_t reg_out;
|
|
unsigned char * byteIn, * byteOut;
|
|
r14 = (HWord_t)viargs;
|
|
@@ -1515,13 +1444,12 @@ static void test_ldbrx(void)
|
|
int j, k;
|
|
reg_out = 0;
|
|
r15 = i * 4;
|
|
- equality = 1;
|
|
__asm__ __volatile__ ("ldbrx %0, %1, %2" : "=r" (reg_out): "b" (r14),"r" (r15));
|
|
byteIn = ((unsigned char *)(r14 + r15));
|
|
byteOut = (unsigned char *)®_out;
|
|
|
|
printf("ldbrx:");
|
|
- for (k = 0; k < 7; k++) {
|
|
+ for (k = 0; k < 8; k++) {
|
|
printf( " %02x", (byteIn[k]));
|
|
}
|
|
printf(" (reverse) =>");
|
|
@@ -1529,13 +1457,6 @@ static void test_ldbrx(void)
|
|
printf( " %02x", (byteOut[j]));
|
|
}
|
|
printf("\n");
|
|
- for (j = 0, k = 7; j < 8; j++, k--) {
|
|
- equality &= (byteIn[k] == byteOut[j]);
|
|
- }
|
|
- if (!equality) {
|
|
- printf("FAILED: load with byte reversal is incorrect\n");
|
|
- errors++;
|
|
- }
|
|
}
|
|
printf( "\n" );
|
|
}
|
|
@@ -1545,18 +1466,9 @@ test_popcntd(void)
|
|
{
|
|
uint64_t res;
|
|
unsigned long long src = 0x9182736405504536ULL;
|
|
- int i, answer = 0;
|
|
r14 = src;
|
|
__asm__ __volatile__ ("popcntd %0, %1" : "=r" (res): "r" (r14));
|
|
- for (i = 0; i < 64; i++) {
|
|
- answer += (r14 & 1ULL);
|
|
- r14 = r14 >> 1;
|
|
- }
|
|
printf("popcntd: 0x%llx => %d\n", src, (int)res);
|
|
- if (res!= answer) {
|
|
- printf("Error: unexpected result from popcntd\n");
|
|
- errors++;
|
|
- }
|
|
printf( "\n" );
|
|
}
|
|
#endif
|
|
@@ -1576,10 +1488,6 @@ test_lfiwzx(void)
|
|
src = ((unsigned int *)(r14 + r15));
|
|
printf("lfiwzx: %u => %llu.00\n", *src, (unsigned long long)reg_out);
|
|
|
|
- if (reg_out > 0xFFFFFFFFULL || *src != (unsigned int)reg_out) {
|
|
- printf("FAILED: integer load to FP register is incorrect\n");
|
|
- errors++;
|
|
- }
|
|
}
|
|
printf( "\n" );
|
|
}
|
|
@@ -1635,6 +1543,9 @@ static void test_vx_fp_ops(void)
|
|
again:
|
|
for (i = 0; i < test_group.num_tests; i++) {
|
|
unsigned int * inA, * inB, * pv;
|
|
+ double * dpA = (double *)&vec_inA;
|
|
+ double * dpB = (double *)&vec_inB;
|
|
+ double * dpT = (double *)&vec_out;
|
|
|
|
fp_test_args_t aTest = test_group.targs[i];
|
|
inA = (unsigned int *)&spec_fargs[aTest.fra_idx];
|
|
@@ -1642,8 +1553,15 @@ again:
|
|
frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
|
|
frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
|
|
// Only need to copy one doubleword into each vector's element 0
|
|
- memcpy(&vec_inA, inA, 8);
|
|
- memcpy(&vec_inB, inB, 8);
|
|
+ if (isLE) {
|
|
+ // With LE, vector element 0 is the second doubleword from the left
|
|
+ memset(dpA, 0, 8);
|
|
+ memset(dpB, 0, 8);
|
|
+ dpA++;
|
|
+ dpB++;
|
|
+ }
|
|
+ memcpy(dpA, inA, 8);
|
|
+ memcpy(dpB, inB, 8);
|
|
|
|
switch (test_type) {
|
|
case VX_FP_CMP:
|
|
@@ -1656,7 +1574,6 @@ again:
|
|
// printf("\tFRA: %e; FRB: %e\n", spec_fargs[aTest.fra_idx], spec_fargs[aTest.frb_idx]);
|
|
if ( condreg != aTest.cr_flags) {
|
|
printf("Error: Expected CR flags 0x%x; actual flags: 0x%x\n", aTest.cr_flags, condreg);
|
|
- errors++;
|
|
}
|
|
break;
|
|
case VX_FP_SMA:
|
|
@@ -1676,7 +1593,7 @@ again:
|
|
* VSX[XT] -- i.e., vec_out. For the xs<ZZZ>mdp cases, VSX[XT] holds
|
|
* src3 and VSX[XB] holds src2; for the xs<ZZZ>adp cases, VSX[XT] holds
|
|
* src2 and VSX[XB] holds src3. The fp_test_args_t that holds the test
|
|
- * data (input args, result) contain only two inputs, so I arbitrarily
|
|
+ * data (input args) contain only two inputs, so I arbitrarily
|
|
* use spec_fargs elements 4 and 14 (alternating) for the third source
|
|
* argument. We can use the same input data for a given pair of
|
|
* adp/mdp-type instructions by swapping the src2 and src3 arguments; thus
|
|
@@ -1688,8 +1605,6 @@ again:
|
|
else
|
|
extra_arg_idx = 14;
|
|
|
|
- //memcpy(&vec_out, &spec_fargs[14], 8);
|
|
-
|
|
if (repeat) {
|
|
/* We're on the first time through of one of the VX_FP_SMx
|
|
* test types, meaning we're testing a xs<ZZZ>adp case, thus we
|
|
@@ -1697,28 +1612,30 @@ again:
|
|
* src2 <= VSX[XT]
|
|
* src3 <= VSX[XB]
|
|
*/
|
|
- memcpy(&vec_out, inB, 8); // src2
|
|
- memcpy(&vec_inB, &spec_fargs[extra_arg_idx], 8); //src3
|
|
+ if (isLE)
|
|
+ dpT++;
|
|
+ memcpy(dpT, inB, 8); // src2
|
|
+ memcpy(dpB, &spec_fargs[extra_arg_idx], 8); //src3
|
|
frbp = (unsigned long long *)&spec_fargs[extra_arg_idx];
|
|
} else {
|
|
// Don't need to init src2, as it's done before the switch()
|
|
- memcpy(&vec_out, &spec_fargs[extra_arg_idx], 8); //src3
|
|
+ if (isLE)
|
|
+ dpT++;
|
|
+ memcpy(dpT, &spec_fargs[extra_arg_idx], 8); //src3
|
|
}
|
|
- memcpy(&vsr_XT, &vec_out, 8);
|
|
+ memcpy(&vsr_XT, dpT, 8);
|
|
}
|
|
|
|
(*func)();
|
|
dst = (unsigned long long *) &vec_out;
|
|
+ if (isLE)
|
|
+ dst++;
|
|
if (test_type == VX_FP_OTHER)
|
|
printf("#%d: %s %016llx %016llx = %016llx\n", i, test_name, *frap, *frbp, *dst);
|
|
else
|
|
printf( "#%d: %s %016llx %016llx %016llx = %016llx\n", i,
|
|
test_name, vsr_XT, *frap, *frbp, *dst );
|
|
|
|
- if ( *dst != aTest.dp_bin_result) {
|
|
- printf("Error: Expected result %016llx; actual result %016llx\n", aTest.dp_bin_result, *dst);
|
|
- errors++;
|
|
- }
|
|
/*
|
|
{
|
|
// Debug code. Keep this block commented out except when debugging.
|
|
@@ -1774,6 +1691,11 @@ static void test_xs_conv_ops(void)
|
|
|
|
test_func_t func;
|
|
int k = 0;
|
|
+ double * dpB = (double *)&vec_inB;
|
|
+ if (isLE) {
|
|
+ memset(dpB, 0, 8);
|
|
+ dpB++;
|
|
+ }
|
|
|
|
build_special_fargs_table();
|
|
while ((func = xs_conv_tests[k].test_func)) {
|
|
@@ -1783,22 +1705,20 @@ static void test_xs_conv_ops(void)
|
|
for (i = 0; i < test_group.num_tests; i++) {
|
|
unsigned int * inB, * pv;
|
|
int idx;
|
|
- unsigned long long exp_result = test_group.results[i];
|
|
inB = (unsigned int *)&spec_fargs[i];
|
|
frbp = (unsigned long long *)&spec_fargs[i];
|
|
- memcpy(&vec_inB, inB, 8);
|
|
+
|
|
+ memcpy(dpB, inB, 8);
|
|
pv = (unsigned int *)&vec_out;
|
|
// clear vec_out
|
|
for (idx = 0; idx < 4; idx++, pv++)
|
|
*pv = 0;
|
|
(*func)();
|
|
dst = (unsigned long long *) &vec_out;
|
|
+ if (isLE)
|
|
+ dst++;
|
|
printf("#%d: %s %016llx => %016llx\n", i, test_group.name, *frbp, *dst);
|
|
|
|
- if ( *dst != exp_result) {
|
|
- printf("Error: Expected result %016llx; actual result %016llx\n", exp_result, *dst);
|
|
- errors++;
|
|
- }
|
|
}
|
|
k++;
|
|
printf("\n");
|
|
@@ -1811,7 +1731,7 @@ static void do_load_test(ldst_test_t loa
|
|
test_func_t func;
|
|
unsigned int *src, *dst;
|
|
int splat = loadTest.type == VSX_LOAD_SPLAT ? 1: 0;
|
|
- int i, j, m, equality;
|
|
+ int i, j, m, k;
|
|
i = j = 0;
|
|
|
|
func = loadTest.test_func;
|
|
@@ -1840,20 +1760,19 @@ static void do_load_test(ldst_test_t loa
|
|
printf( " %08x", src[splat ? m % 2 : m]);
|
|
}
|
|
printf( " =>");
|
|
- for (m = 0; m < loadTest.num_words_to_process; m++) {
|
|
- printf( " %08x", dst[m]);
|
|
- }
|
|
- printf("\n");
|
|
- equality = 1;
|
|
- for (m = 0; m < loadTest.num_words_to_process; m++) {
|
|
- equality = equality && (src[splat ? m % 2 : m] == dst[m]);
|
|
+ m = 0;
|
|
+ k = loadTest.num_words_to_process;
|
|
+ if (isLE) {
|
|
+ if (loadTest.num_words_to_process == 2) {
|
|
+ m = 2;
|
|
+ k += 2;
|
|
+ }
|
|
}
|
|
|
|
- if (!equality) {
|
|
- printf("FAILED: loaded vector is incorrect\n");
|
|
- errors++;
|
|
+ for (; m < k; m++) {
|
|
+ printf( " %08x", dst[m]);
|
|
}
|
|
-
|
|
+ printf("\n");
|
|
if (j == 0 && loadTest.offset) {
|
|
again = 1;
|
|
j += loadTest.offset;
|
|
@@ -1868,7 +1787,7 @@ do_store_test ( ldst_test_t storeTest )
|
|
{
|
|
test_func_t func;
|
|
unsigned int *src, *dst;
|
|
- int m, equality;
|
|
+ int m;
|
|
|
|
func = storeTest.test_func;
|
|
r14 = (HWord_t) storeTest.base_addr;
|
|
@@ -1895,16 +1814,6 @@ do_store_test ( ldst_test_t storeTest )
|
|
printf( " %08x", dst[m] );
|
|
}
|
|
printf( "\n" );
|
|
- equality = 1;
|
|
- for (m = 0; m < storeTest.num_words_to_process; m++) {
|
|
- equality = equality && (src[m] == dst[m]);
|
|
- }
|
|
-
|
|
- if (!equality) {
|
|
- printf( "FAILED: vector store result is incorrect\n" );
|
|
- errors++;
|
|
- }
|
|
-
|
|
}
|
|
|
|
|
|
@@ -1932,7 +1841,7 @@ static void test_ftdiv(void)
|
|
num_tests = sizeof ftdiv_tests/sizeof ftdiv_tests[0];
|
|
|
|
for (i = 0; i < num_tests; i++) {
|
|
- ftdiv_test_args_t aTest = ftdiv_tests[i];
|
|
+ fp_test_args_t aTest = ftdiv_tests[i];
|
|
f14 = spec_fargs[aTest.fra_idx];
|
|
f15 = spec_fargs[aTest.frb_idx];
|
|
frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
|
|
@@ -1946,7 +1855,6 @@ static void test_ftdiv(void)
|
|
// printf("\tFRA: %e; FRB: %e\n", f14, f15);
|
|
if ( crx != aTest.cr_flags) {
|
|
printf("Error: Expected CR flags 0x%x; actual flags: 0x%x\n", aTest.cr_flags, crx);
|
|
- errors++;
|
|
}
|
|
}
|
|
printf( "\n" );
|
|
@@ -1991,7 +1899,7 @@ static void test_vsx_logic(void)
|
|
{
|
|
logic_test_t aTest;
|
|
test_func_t func;
|
|
- int equality, k;
|
|
+ int k;
|
|
k = 0;
|
|
|
|
while ((func = logic_tests[k].test_func)) {
|
|
@@ -2021,82 +1929,68 @@ static void test_vsx_logic(void)
|
|
printf( " %08x %08x %08x %08x", inB[0], inB[1], inB[2], inB[3]);
|
|
printf(" => %08x %08x %08x %08x\n", dst[0], dst[1], dst[2], dst[3]);
|
|
|
|
- equality = 1;
|
|
- for (idx = 0; idx < 4; idx++) {
|
|
- switch (aTest.op) {
|
|
- case VSX_AND:
|
|
- equality &= (dst[idx] == (inA[idx] & inB[idx]));
|
|
- break;
|
|
- case VSX_ANDC:
|
|
- equality &= (dst[idx] == (inA[idx] & ~inB[idx]));
|
|
- break;
|
|
- case VSX_NOR:
|
|
- equality &= (dst[idx] == ~(inA[idx] | inB[idx]));
|
|
- break;
|
|
- case VSX_XOR:
|
|
- equality &= (dst[idx] == (inA[idx] ^ inB[idx]));
|
|
- break;
|
|
- case VSX_OR:
|
|
- equality &= (dst[idx] == (inA[idx] | inB[idx]));
|
|
- break;
|
|
- default:
|
|
- fprintf(stderr, "Error in test_vsx_logic(): unknown VSX logical op %d\n", aTest.op);
|
|
- exit(1);
|
|
- }
|
|
- }
|
|
- if (!equality) {
|
|
- printf( "FAILED: vector out is incorrect\n" );
|
|
- errors++;
|
|
- }
|
|
}
|
|
k++;
|
|
}
|
|
printf( "\n" );
|
|
}
|
|
|
|
+static vector unsigned long long vec_args[] __attribute__ ((aligned (16))) =
|
|
+{
|
|
+ { 0x0123456789abcdefULL, 0x0011223344556677ULL},
|
|
+ { 0x8899aabb19293942ULL, 0xa1a2a3a4b1b2b3b4ULL},
|
|
+ { 0xc1c2c3c4d1d2d3d4ULL, 0x7a6b5d3efc032778ULL}
|
|
+};
|
|
+#define NUM_VEC_ARGS_LONGS (sizeof vec_args/sizeof vec_args[0])
|
|
+
|
|
static void test_move_ops (void)
|
|
{
|
|
move_test_t aTest;
|
|
test_func_t func;
|
|
- int equality, k;
|
|
+ int k;
|
|
k = 0;
|
|
|
|
while ((func = move_tests[k].test_func)) {
|
|
unsigned int * pv;
|
|
int startA, startB;
|
|
- unsigned int * inA, * inB, * dst;
|
|
- unsigned long long exp_out;
|
|
+ unsigned long long * inA, * inB, * dst;
|
|
+ int use_vecA = (strcmp(move_tests[k].name, "xscpsgndp") == 0);
|
|
int idx;
|
|
+ inA = NULL;
|
|
aTest = move_tests[k];
|
|
- exp_out = aTest.expected_result;
|
|
- startA = aTest.xa_idx;
|
|
- startB = aTest.xb_idx;
|
|
- pv = (unsigned int *)&vec_out;
|
|
- inA = &viargs[startA];
|
|
- inB = &viargs[startB];
|
|
- memcpy(&vec_inA, inA, sizeof(vector unsigned char));
|
|
- memcpy(&vec_inB, inB, sizeof(vector unsigned char));
|
|
- // clear vec_out
|
|
- for (idx = 0; idx < 4; idx++, pv++)
|
|
- *pv = 0;
|
|
+ for (startB = 0; startB < NUM_VEC_ARGS_LONGS; startB++) {
|
|
+ inB = (unsigned long long *)&vec_args[startB];
|
|
+ memcpy(&vec_inB, inB, sizeof(vector unsigned char));
|
|
+ if (isLE)
|
|
+ inB++;
|
|
+ startA = 0;
|
|
+repeat:
|
|
+ if (use_vecA) {
|
|
+ inA = (unsigned long long *)&vec_args[startA];
|
|
+ memcpy(&vec_inA, inA, sizeof(vector unsigned char));
|
|
+ startA++;
|
|
+ }
|
|
+ pv = (unsigned int *)&vec_out;
|
|
+ // clear vec_out
|
|
+ for (idx = 0; idx < 4; idx++, pv++)
|
|
+ *pv = 0;
|
|
|
|
- // execute test insn
|
|
- (*func)();
|
|
- dst = (unsigned int*) &vec_out;
|
|
+ // execute test insn
|
|
+ (*func)();
|
|
+ dst = (unsigned long long *) &vec_out;
|
|
+ if (isLE) {
|
|
+ dst++;
|
|
+ inA++;
|
|
+ }
|
|
|
|
- printf( "%s:", aTest.name);
|
|
- printf( " %08x %08x %s", inA[0], inA[1], aTest.name);
|
|
- printf( " %08x %08xx", inB[0], inB[1]);
|
|
- printf(" => %08x %08x\n", dst[0], dst[1]);
|
|
-
|
|
- equality = 1;
|
|
- pv = (unsigned int *)&exp_out;
|
|
- for (idx = 0; idx < 2; idx++) {
|
|
- equality &= (dst[idx] == pv[idx]);
|
|
- }
|
|
- if (!equality) {
|
|
- printf( "FAILED: vector out is incorrect\n" );
|
|
- errors++;
|
|
+ printf( "%s:", aTest.name);
|
|
+ if (use_vecA)
|
|
+ printf( " X[A]: %016llx ", *inA);
|
|
+ printf( " X[B]: %016llx", *inB);
|
|
+ printf(" => %016llx\n", *dst);
|
|
+
|
|
+ if (use_vecA && startA < NUM_VEC_ARGS_LONGS)
|
|
+ goto repeat;
|
|
}
|
|
k++;
|
|
printf( "\n" );
|
|
@@ -2126,11 +2020,6 @@ static void test_permute_ops (void)
|
|
printf( " => XT[%08x,%08x,%08x,%08x]\n",
|
|
dst[0], dst[1], dst[2], dst[3]);
|
|
|
|
- if (memcmp (dst, &aTest->expected_output, sizeof(vec_out)))
|
|
- {
|
|
- printf( "FAILED: vector out is incorrect\n" );
|
|
- errors++;
|
|
- }
|
|
}
|
|
printf( "\n" );
|
|
}
|
|
@@ -2177,10 +2066,6 @@ int main(int argc, char *argv[])
|
|
(*func)();
|
|
i++;
|
|
}
|
|
- if (errors)
|
|
- printf("Testcase FAILED with %d errors \n", errors);
|
|
- else
|
|
- printf("Testcase PASSED\n");
|
|
|
|
#endif // HAS _VSX
|
|
|
|
Index: tests/is_ppc64_BE.c
|
|
===================================================================
|
|
--- /dev/null
|
|
+++ tests/is_ppc64_BE.c
|
|
@@ -0,0 +1,14 @@
|
|
+#include <stdio.h>
|
|
+#include <stdlib.h>
|
|
+#include <string.h>
|
|
+
|
|
+// This program returns 0 if executing on ppc64 big endian; otherwise returns 1
|
|
+
|
|
+int main(void)
|
|
+{
|
|
+#if defined(VGP_ppc64be_linux)
|
|
+ return 0;
|
|
+#else
|
|
+ return 1;
|
|
+#endif
|
|
+}
|
|
Index: tests/check_isa-2_06_cap
|
|
===================================================================
|
|
--- tests/check_isa-2_06_cap.orig
|
|
+++ tests/check_isa-2_06_cap
|
|
@@ -1,7 +1,7 @@
|
|
#!/bin/sh
|
|
|
|
# We use this script to check whether or not the processor supports Power ISA 2.06 or later.
|
|
-DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )"
|
|
+DIR="$( cd "$( dirname "$0" )" && pwd )"
|
|
LD_SHOW_AUXV=1 $DIR/true | grep arch_2_06 > /dev/null 2>&1
|
|
|
|
if [ "$?" -ne "0" ]; then
|
|
Index: tests/check_isa-2_07_cap
|
|
===================================================================
|
|
--- tests/check_isa-2_07_cap.orig
|
|
+++ tests/check_isa-2_07_cap
|
|
@@ -2,7 +2,7 @@
|
|
|
|
# We use this script to check whether or not the processor supports
|
|
# Power ISA 2.07.
|
|
-DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )"
|
|
+DIR="$( cd "$( dirname "$0" )" && pwd )"
|
|
LD_SHOW_AUXV=1 $DIR/true | grep arch_2_07 > /dev/null 2>&1
|
|
|
|
if [ "$?" -ne "0" ]; then
|
|
Index: memcheck/tests/atomic_incs.c
|
|
===================================================================
|
|
--- memcheck/tests/atomic_incs.c.orig
|
|
+++ memcheck/tests/atomic_incs.c
|
|
@@ -79,6 +79,23 @@ __attribute__((noinline)) void atomic_ad
|
|
: /*trash*/ "memory", "cc", "r15"
|
|
);
|
|
} while (success != 1);
|
|
+#elif defined(VGA_ppc64le)
|
|
+ /* Nasty hack. Does correctly atomically do *p += n, but only if p
|
|
+ is 8-aligned -- guaranteed by caller. */
|
|
+ unsigned long success;
|
|
+ do {
|
|
+ __asm__ __volatile__(
|
|
+ "ldarx 15,0,%1" "\n\t"
|
|
+ "add 15,15,%2" "\n\t"
|
|
+ "stdcx. 15,0,%1" "\n\t"
|
|
+ "mfcr %0" "\n\t"
|
|
+ "srwi %0,%0,29" "\n\t"
|
|
+ "andi. %0,%0,1" "\n"
|
|
+ : /*out*/"=b"(success)
|
|
+ : /*in*/ "b"(p), "b"(((unsigned long)n))
|
|
+ : /*trash*/ "memory", "cc", "r15"
|
|
+ );
|
|
+ } while (success != 1);
|
|
#elif defined(VGA_arm)
|
|
unsigned int block[3]
|
|
= { (unsigned int)p, (unsigned int)n, 0xFFFFFFFF };
|
|
@@ -260,6 +277,23 @@ __attribute__((noinline)) void atomic_ad
|
|
: /*trash*/ "memory", "cc", "r15"
|
|
);
|
|
} while (success != 1);
|
|
+#elif defined(VGA_ppc64le)
|
|
+ /* Nasty hack. Does correctly atomically do *p += n, but only if p
|
|
+ is 8-aligned -- guaranteed by caller. */
|
|
+ unsigned long success;
|
|
+ do {
|
|
+ __asm__ __volatile__(
|
|
+ "ldarx 15,0,%1" "\n\t"
|
|
+ "add 15,15,%2" "\n\t"
|
|
+ "stdcx. 15,0,%1" "\n\t"
|
|
+ "mfcr %0" "\n\t"
|
|
+ "srwi %0,%0,29" "\n\t"
|
|
+ "andi. %0,%0,1" "\n"
|
|
+ : /*out*/"=b"(success)
|
|
+ : /*in*/ "b"(p), "b"(((unsigned long)n))
|
|
+ : /*trash*/ "memory", "cc", "r15"
|
|
+ );
|
|
+ } while (success != 1);
|
|
#elif defined(VGA_arm)
|
|
unsigned int block[3]
|
|
= { (unsigned int)p, (unsigned int)n, 0xFFFFFFFF };
|
|
@@ -438,6 +472,23 @@ __attribute__((noinline)) void atomic_ad
|
|
: /*trash*/ "memory", "cc", "r15"
|
|
);
|
|
} while (success != 1);
|
|
+#elif defined(VGA_ppc64le)
|
|
+ /* Nasty hack. Does correctly atomically do *p += n, but only if p
|
|
+ is 8-aligned -- guaranteed by caller. */
|
|
+ unsigned long success;
|
|
+ do {
|
|
+ __asm__ __volatile__(
|
|
+ "ldarx 15,0,%1" "\n\t"
|
|
+ "add 15,15,%2" "\n\t"
|
|
+ "stdcx. 15,0,%1" "\n\t"
|
|
+ "mfcr %0" "\n\t"
|
|
+ "srwi %0,%0,29" "\n\t"
|
|
+ "andi. %0,%0,1" "\n"
|
|
+ : /*out*/"=b"(success)
|
|
+ : /*in*/ "b"(p), "b"(((unsigned long)n))
|
|
+ : /*trash*/ "memory", "cc", "r15"
|
|
+ );
|
|
+ } while (success != 1);
|
|
#elif defined(VGA_arm)
|
|
unsigned int block[3]
|
|
= { (unsigned int)p, (unsigned int)n, 0xFFFFFFFF };
|
|
@@ -520,7 +571,7 @@ __attribute__((noinline)) void atomic_ad
|
|
"lock; addq %%rbx,(%%rax)" "\n"
|
|
: : "S"(&block[0])/* S means "rsi only" */ : "memory","cc","rax","rbx"
|
|
);
|
|
-#elif defined(VGA_ppc64be)
|
|
+#elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
|
|
unsigned long success;
|
|
do {
|
|
__asm__ __volatile__(
|
|
Index: memcheck/tests/ppc64/power_ISA2_05.c
|
|
===================================================================
|
|
--- memcheck/tests/ppc64/power_ISA2_05.c.orig
|
|
+++ memcheck/tests/ppc64/power_ISA2_05.c
|
|
@@ -41,19 +41,25 @@ void test_parity_instrs()
|
|
void test_lfiwax()
|
|
{
|
|
unsigned long base;
|
|
+ float foo_s;
|
|
|
|
typedef struct {
|
|
+#if defined(VGP_ppc64le_linux)
|
|
+ unsigned int lo;
|
|
+ unsigned int hi;
|
|
+#else
|
|
unsigned int hi;
|
|
unsigned int lo;
|
|
+#endif
|
|
} int_pair_t;
|
|
|
|
int_pair_t *ip;
|
|
- foo = -1024.0;
|
|
- base = (unsigned long) &foo;
|
|
+ foo_s = -1024.0;
|
|
+ base = (unsigned long) &foo_s;
|
|
|
|
__asm__ volatile ("lfiwax %0, 0, %1":"=f" (FRT1):"r"(base));
|
|
ip = (int_pair_t *) & FRT1;
|
|
- printf("lfiwax (%f) => FRT=(%x, %x)\n", foo, ip->hi, ip->lo);
|
|
+ printf("lfiwax (%f) => FRT=(%x, %x)\n", foo_s, ip->hi, ip->lo);
|
|
|
|
|
|
}
|
|
@@ -167,24 +173,27 @@ void test_fcpsgn()
|
|
void test_reservation()
|
|
{
|
|
|
|
- int RT;
|
|
+ unsigned long long RT;
|
|
unsigned long base;
|
|
unsigned long offset;
|
|
- long arr[4] = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad };
|
|
+ long arrL[] __attribute__ ((aligned (8))) = { 0xdeadbeef00112233ULL, 0xbad0beef44556677ULL, 0xbeefdead8899aabbULL, 0xbeef0badccddeeffULL };
|
|
+ int arrI[] __attribute__ ((aligned (4))) = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad };
|
|
|
|
|
|
- base = (unsigned long) &arr;
|
|
- offset = (unsigned long) &arr[1] - base;
|
|
+ base = (unsigned long) &arrI;
|
|
+ offset = ((unsigned long) &arrI[1]) - base;
|
|
__asm__ volatile ("ori 20, %0, 0"::"r" (base));
|
|
__asm__ volatile ("ori 21, %0, 0"::"r" (offset));
|
|
__asm__ volatile ("lwarx %0, 20, 21, 1":"=r" (RT));
|
|
- printf("lwarx => %x\n", RT);
|
|
+ printf("lwarx => 0x%llx\n", RT);
|
|
|
|
#ifdef __powerpc64__
|
|
- offset = (unsigned long) &arr[1] - base;
|
|
+ base = (unsigned long) &arrL;
|
|
+ offset = ((unsigned long) &arrL[1]) - base;
|
|
+ __asm__ volatile ("ori 20, %0, 0"::"r" (base));
|
|
__asm__ volatile ("ori 21, %0, 0"::"r" (offset));
|
|
__asm__ volatile ("ldarx %0, 20, 21, 1":"=r" (RT));
|
|
- printf("ldarx => %x\n", RT);
|
|
+ printf("ldarx => 0x%llx\n", RT);
|
|
#endif
|
|
|
|
}
|
|
Index: memcheck/tests/ppc64/power_ISA2_05.stdout.exp
|
|
===================================================================
|
|
--- memcheck/tests/ppc64/power_ISA2_05.stdout.exp.orig
|
|
+++ memcheck/tests/ppc64/power_ISA2_05.stdout.exp
|
|
@@ -1,5 +1,5 @@
|
|
-lwarx => 0
|
|
-ldarx => bad0beef
|
|
+lwarx => 0xbad0beef
|
|
+ldarx => 0xbad0beef44556677
|
|
fcpsgn sign=10.101010, base=11.111111 => 11.111111
|
|
fcpsgn sign=10.101010, base=-0.000000 => 0.000000
|
|
fcpsgn sign=10.101010, base=0.000000 => 0.000000
|
|
@@ -20,7 +20,7 @@ lfdp (-1024.000000, 1025.000000) => F_hi
|
|
stfdp (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
|
|
lfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
|
|
stfdpx (2.204800, 2.204800) => F_hi=2.204800, F_lo=2.204800
|
|
-lfiwax (-1024.000000) => FRT=(ffffffff, c0900000)
|
|
+lfiwax (-1024.000000) => FRT=(ffffffff, c4800000)
|
|
prtyd (0) => parity=0
|
|
prtyw (0) => parity=0
|
|
prtyd (1) => parity=1
|
|
Index: memcheck/tests/badjump.c
|
|
===================================================================
|
|
--- memcheck/tests/badjump.c.orig
|
|
+++ memcheck/tests/badjump.c
|
|
@@ -2,7 +2,7 @@
|
|
|
|
int main ( void )
|
|
{
|
|
-#if defined(__powerpc64__)
|
|
+#if defined(__powerpc64__) && _CALL_ELF != 2
|
|
/* on ppc64-linux, a function pointer points to a function
|
|
descriptor, not to the function's entry point. Hence to get
|
|
uniform behaviour on all supported targets - a jump to an
|