valgrind/VEX-x86-pinsrd.patch
Dirk Mueller bc5496ffdb - update to 3.24.0 (jsc#PED-10260):
* Bad file descriptor usage now generates a real error with
    --track-fds=yes that is suppressible and shows up in the
    xml output with full execution backtrace. The warnings
    shown without using the option are deprecated and will be
    removed in a future valgrind version.
  * Ada name demangling is now supported in error messages.
- Bugs fixed:
  * 202770  open fd at exit --log-socket=127.0.0.1:1500 with
    --track-fds=yes
  * 276780  An instruction in fftw (Fast Fourier Transform) is
    unhandled by valgrind: vex x86->IR: unhandled instruction bytes:
    0x66 0xF 0x3A 0x2
  * 311655  --log-file=FILE leads to apparent fd leak
  * 317127  Fedora18/x86_64 --sanity-level=3 : aspacem segment
    mismatch
  * 337388  fcntl works on Valgrind's own file descriptors
  * 377966  arm64 unhandled instruction dc zva392146  aarch64:
    unhandled instruction 0xD5380001 (MRS rT, midr_el1)
  * 391148  Unhandled AVX instruction vmovq %xmm9,%xmm1
  * 392146  aarch64: unhandled instruction 0xD5380001 (MRS rT,
    midr_el1)
  * 412377  SIGILL on cache flushes on arm64
  * 417572  vex amd64->IR: unhandled instruction bytes: 0xC5 0x79
    0xD6 0xED 0xC5
  * 440180  s390x: Failed assertion in disassembler
  * 444781  MIPS: wrong syscall numbers used
  * 447989  Support Armv8.2 SHA-512 instructions
  * 445235  Java/Ada/D demangling is probably broken
  * 453044  gbserver_tests failures in aarch64

OBS-URL: https://build.opensuse.org/package/show/devel:tools/valgrind?expand=0&rev=283
2025-01-30 13:08:13 +00:00

68 lines
2.4 KiB
Diff

Index: valgrind-3.24.0/VEX/priv/guest_x86_toIR.c
===================================================================
--- valgrind-3.24.0.orig/VEX/priv/guest_x86_toIR.c
+++ valgrind-3.24.0/VEX/priv/guest_x86_toIR.c
@@ -12997,6 +12997,62 @@ DisResult disInstr_X86_WRK (
goto decode_success;
}
+ /* 66 0F 3A 22 /r ib = PINSRD xmm1, r/m32, imm8
+ Extract Doubleword int from gen.reg/mem32 and insert into xmm1 */
+ if ( sz == 2
+ && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x22 ) {
+
+ Int imm8_10;
+ IRTemp src_elems = newTemp(Ity_I32);
+ IRTemp src_vec = newTemp(Ity_V128);
+ IRTemp z32 = newTemp(Ity_I32);
+
+ modrm = insn[3];
+
+ if ( epartIsReg( modrm ) ) {
+ imm8_10 = (Int)(insn[3+1] & 3);
+ assign( src_elems, getIReg( 4, eregOfRM(modrm) ) );
+ delta += 3+1+1;
+ DIP( "pinsrd $%d, %s,%s\n", imm8_10,
+ nameIReg( 4, eregOfRM(modrm) ),
+ nameXMMReg( gregOfRM(modrm) ) );
+ } else {
+ addr = disAMode( &alen, sorb, delta+3, dis_buf );
+ imm8_10 = (Int)(insn[3+alen] & 3);
+ assign( src_elems, loadLE( Ity_I32, mkexpr(addr) ) );
+ delta += 3+alen+1;
+ DIP( "pinsrd $%d, %s,%s\n",
+ imm8_10, dis_buf, nameXMMReg( gregOfRM(modrm) ) );
+ }
+
+ assign(z32, mkU32(0));
+
+ UShort mask = 0;
+ switch (imm8_10) {
+ case 3: mask = 0x0FFF;
+ assign(src_vec, mk128from32s(src_elems, z32, z32, z32));
+ break;
+ case 2: mask = 0xF0FF;
+ assign(src_vec, mk128from32s(z32, src_elems, z32, z32));
+ break;
+ case 1: mask = 0xFF0F;
+ assign(src_vec, mk128from32s(z32, z32, src_elems, z32));
+ break;
+ case 0: mask = 0xFFF0;
+ assign(src_vec, mk128from32s(z32, z32, z32, src_elems));
+ break;
+ default: vassert(0);
+ }
+
+ putXMMReg( gregOfRM(modrm),
+ binop( Iop_OrV128, mkexpr(src_vec),
+ binop( Iop_AndV128,
+ getXMMReg( gregOfRM(modrm) ),
+ mkV128(mask) ) ) );
+
+ goto decode_success;
+ }
+
/* 66 0F 3A 0B /r ib = ROUNDSD imm8, xmm2/m64, xmm1
(Partial implementation only -- only deal with cases where
the rounding mode is specified directly by the immediate byte.)