49 lines
2.1 KiB
Diff
49 lines
2.1 KiB
Diff
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# Commit ee1cc4bfdca84d526805c4c72302c026f5e9cd94
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# Date 2016-09-01 15:23:46 +0200
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# Author Jan Beulich <jbeulich@suse.com>
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# Committer Jan Beulich <jbeulich@suse.com>
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x86/32on64: misc adjustments to call gate emulation
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- There's no 32-bit displacement in 16-bit addressing mode.
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- It is wrong to ASSERT() anything on parts of an instruction fetched
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from guest memory.
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- The two scaling bits of a SIB byte don't affect whether there is a
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scaled index register or not.
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Signed-off-by: Jan Beulich <jbeulich@suse.com>
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Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
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--- a/xen/arch/x86/traps.c
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+++ b/xen/arch/x86/traps.c
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@@ -3176,7 +3176,7 @@ static void emulate_gate_op(struct cpu_u
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sib = insn_fetch(u8, base, eip, limit);
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modrm = (modrm & ~7) | (sib & 7);
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- if ( (sib >>= 3) != 4 )
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+ if ( ((sib >>= 3) & 7) != 4 )
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opnd_off = *(unsigned long *)
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decode_register(sib & 7, regs, 0);
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opnd_off <<= sib >> 3;
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@@ -3236,7 +3236,10 @@ static void emulate_gate_op(struct cpu_u
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opnd_off += insn_fetch(s8, base, eip, limit);
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break;
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case 0x80:
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- opnd_off += insn_fetch(s32, base, eip, limit);
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+ if ( ad_bytes > 2 )
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+ opnd_off += insn_fetch(s32, base, eip, limit);
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+ else
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+ opnd_off += insn_fetch(s16, base, eip, limit);
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break;
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}
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if ( ad_bytes == 4 )
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@@ -3273,8 +3276,7 @@ static void emulate_gate_op(struct cpu_u
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#define ad_default ad_bytes
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opnd_sel = insn_fetch(u16, base, opnd_off, limit);
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#undef ad_default
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- ASSERT((opnd_sel & ~3) == regs->error_code);
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- if ( dpl < (opnd_sel & 3) )
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+ if ( (opnd_sel & ~3) != regs->error_code || dpl < (opnd_sel & 3) )
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{
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do_guest_trap(TRAP_gp_fault, regs, 1);
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return;
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