93 lines
3.5 KiB
Diff
93 lines
3.5 KiB
Diff
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# HG changeset patch
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# User Keir Fraser <keir.fraser@citrix.com>
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# Date 1226593868 0
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# Node ID a0910b1b5ec0c938f1c46437df6c28cbeff52c68
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# Parent d44ad6db638c1308e5ee4a47509769c3cccbe1e8
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x86: don't disable MSI in order to mask an IRQ
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... as that's not really correct, and there are devices which can't
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even cope with that. Instead, check whether an MSI IRQ can be masked,
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and if it can't, treat it just like a level triggered IO-APIC IRQ.
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There's one other bug fix in here, correcting an off-by-one error on
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the entry_nr range check in __pci_enable_msix().
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Signed-off-by: Jan Beulich <jbeulich@novell.com>
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Index: xen-3.3.1-testing/xen/arch/x86/irq.c
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===================================================================
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--- xen-3.3.1-testing.orig/xen/arch/x86/irq.c
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+++ xen-3.3.1-testing/xen/arch/x86/irq.c
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@@ -463,14 +463,19 @@ int pirq_acktype(struct domain *d, int i
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/*
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* Edge-triggered IO-APIC and LAPIC interrupts need no final
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* acknowledgement: we ACK early during interrupt processing.
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- * MSIs are treated as edge-triggered interrupts.
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*/
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if ( !strcmp(desc->handler->typename, "IO-APIC-edge") ||
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- !strcmp(desc->handler->typename, "local-APIC-edge") ||
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- !strcmp(desc->handler->typename, "PCI-MSI") )
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+ !strcmp(desc->handler->typename, "local-APIC-edge") )
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return ACKTYPE_NONE;
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/*
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+ * MSIs are treated as edge-triggered interrupts, except
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+ * when there is no proper way to mask them.
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+ */
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+ if ( desc->handler == &pci_msi_type )
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+ return msi_maskable_irq(desc->msi_desc) ? ACKTYPE_NONE : ACKTYPE_EOI;
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+
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+ /*
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* Level-triggered IO-APIC interrupts need to be acknowledged on the CPU
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* on which they were received. This is because we tickle the LAPIC to EOI.
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*/
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Index: xen-3.3.1-testing/xen/arch/x86/msi.c
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===================================================================
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--- xen-3.3.1-testing.orig/xen/arch/x86/msi.c
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+++ xen-3.3.1-testing/xen/arch/x86/msi.c
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@@ -303,6 +303,13 @@ static void msix_flush_writes(unsigned i
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}
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}
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+int msi_maskable_irq(const struct msi_desc *entry)
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+{
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+ BUG_ON(!entry);
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+ return entry->msi_attrib.type != PCI_CAP_ID_MSI
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+ || entry->msi_attrib.maskbit;
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+}
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+
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static void msi_set_mask_bit(unsigned int irq, int flag)
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{
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struct msi_desc *entry = irq_desc[irq].msi_desc;
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@@ -323,8 +330,6 @@ static void msi_set_mask_bit(unsigned in
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mask_bits &= ~(1);
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mask_bits |= flag;
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pci_conf_write32(bus, slot, func, pos, mask_bits);
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- } else {
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- msi_set_enable(entry->dev, !flag);
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}
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break;
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case PCI_CAP_ID_MSIX:
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@@ -654,7 +659,7 @@ static int __pci_enable_msix(struct msi_
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pos = pci_find_cap_offset(msi->bus, slot, func, PCI_CAP_ID_MSIX);
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control = pci_conf_read16(msi->bus, slot, func, msi_control_reg(pos));
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nr_entries = multi_msix_capable(control);
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- if (msi->entry_nr > nr_entries)
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+ if (msi->entry_nr >= nr_entries)
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{
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spin_unlock(&pdev->lock);
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return -EINVAL;
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Index: xen-3.3.1-testing/xen/include/asm-x86/msi.h
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===================================================================
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--- xen-3.3.1-testing.orig/xen/include/asm-x86/msi.h
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+++ xen-3.3.1-testing/xen/include/asm-x86/msi.h
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@@ -97,6 +97,8 @@ struct msi_desc {
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int remap_index; /* index in interrupt remapping table */
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};
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+int msi_maskable_irq(const struct msi_desc *);
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+
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/*
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* Assume the maximum number of hot plug slots supported by the system is about
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* ten. The worstcase is that each of these slots is hot-added with a device,
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