52 lines
1.6 KiB
Diff
52 lines
1.6 KiB
Diff
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# HG changeset patch
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# User Boris Ostrovsky <boris.ostrovsky@amd.com>
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# Date 1358508058 -3600
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# Node ID 8f6dd5dc5d6cdd56050ed917a0c30903bbddcbf0
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# Parent eb8e9a23925d7b77c344a4a99679a45f96754a17
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x86/AMD: Enable WC+ memory type on family 10 processors
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In some cases BIOS may not enable WC+ memory type on family 10 processors,
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instead converting what would be WC+ memory to CD type. On guests using
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nested pages this could result in performance degradation. This patch
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enables WC+.
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Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com>
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Committed-by: Jan Beulich <jbeulich@suse.com>
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--- a/xen/arch/x86/cpu/amd.c
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+++ b/xen/arch/x86/cpu/amd.c
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@@ -534,6 +534,19 @@ static void __devinit init_amd(struct cp
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}
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#endif
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+ if (c->x86 == 0x10) {
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+ /*
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+ * On family 10h BIOS may not have properly enabled WC+
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+ * support, causing it to be converted to CD memtype. This may
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+ * result in performance degradation for certain nested-paging
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+ * guests. Prevent this conversion by clearing bit 24 in
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+ * MSR_F10_BU_CFG2.
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+ */
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+ rdmsrl(MSR_F10_BU_CFG2, value);
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+ value &= ~(1ULL << 24);
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+ wrmsrl(MSR_F10_BU_CFG2, value);
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+ }
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+
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/*
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* Family 0x12 and above processors have APIC timer
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* running in deep C states.
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--- a/xen/include/asm-x86/msr-index.h
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+++ b/xen/include/asm-x86/msr-index.h
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@@ -215,8 +215,9 @@
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#define MSR_F10_MC4_MISC2 0xc0000409
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#define MSR_F10_MC4_MISC3 0xc000040A
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-/* AMD Family10h MMU control MSRs */
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-#define MSR_F10_BU_CFG 0xc0011023
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+/* AMD Family10h Bus Unit MSRs */
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+#define MSR_F10_BU_CFG 0xc0011023
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+#define MSR_F10_BU_CFG2 0xc001102a
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/* Other AMD Fam10h MSRs */
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#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
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