95 lines
4.4 KiB
Diff
95 lines
4.4 KiB
Diff
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# HG changeset patch
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# User Liu, Jinsong <jinsong.liu@intel.com>
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# Date 1323170838 0
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# Node ID a0befa32e927cc147aaee9bce42c51f53580a875
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# Parent 9961a6d5356a57685b06f65133c6ade5041e3356
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X86: expose Intel new features to pv/hvm
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Intel recently release some new features, including
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FMA/AVX2/BMI1/BMI2/LZCNT/MOVBE.
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Refer to http://software.intel.com/file/36945
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This patch expose these new features to pv and hvm.
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Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
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Committed-by: Keir Fraser <keir@xen.org>
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--- a/tools/libxc/xc_cpufeature.h
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+++ b/tools/libxc/xc_cpufeature.h
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@@ -74,6 +74,7 @@
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#define X86_FEATURE_TM2 8 /* Thermal Monitor 2 */
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#define X86_FEATURE_SSSE3 9 /* Supplemental Streaming SIMD Exts-3 */
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#define X86_FEATURE_CID 10 /* Context ID */
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+#define X86_FEATURE_FMA 12 /* Fused Multiply Add */
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#define X86_FEATURE_CX16 13 /* CMPXCHG16B */
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#define X86_FEATURE_XTPR 14 /* Send Task Priority Messages */
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#define X86_FEATURE_PDCM 15 /* Perf/Debug Capability MSR */
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@@ -81,6 +82,7 @@
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#define X86_FEATURE_SSE4_1 19 /* Streaming SIMD Extensions 4.1 */
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#define X86_FEATURE_SSE4_2 20 /* Streaming SIMD Extensions 4.2 */
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#define X86_FEATURE_X2APIC 21 /* x2APIC */
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+#define X86_FEATURE_MOVBE 22 /* movbe instruction */
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#define X86_FEATURE_POPCNT 23 /* POPCNT instruction */
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#define X86_FEATURE_TSC_DEADLINE 24 /* "tdt" TSC Deadline Timer */
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#define X86_FEATURE_AES 25 /* AES acceleration instructions */
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@@ -125,7 +127,10 @@
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/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */
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#define X86_FEATURE_FSGSBASE 0 /* {RD,WR}{FS,GS}BASE instructions */
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+#define X86_FEATURE_BMI1 3 /* 1st group bit manipulation extensions */
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+#define X86_FEATURE_AVX2 5 /* AVX2 instructions */
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#define X86_FEATURE_SMEP 7 /* Supervisor Mode Execution Protection */
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+#define X86_FEATURE_BMI2 8 /* 2nd group bit manipulation extensions */
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#define X86_FEATURE_ERMS 9 /* Enhanced REP MOVSB/STOSB */
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#endif /* __LIBXC_CPUFEATURE_H */
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--- a/tools/libxc/xc_cpuid_x86.c
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+++ b/tools/libxc/xc_cpuid_x86.c
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@@ -148,7 +148,8 @@ static void intel_xc_cpuid_policy(
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int is_64bit = hypervisor_is_64bit(xch) && is_pae;
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/* Only a few features are advertised in Intel's 0x80000001. */
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- regs[2] &= (is_64bit ? bitmaskof(X86_FEATURE_LAHF_LM) : 0);
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+ regs[2] &= (is_64bit ? bitmaskof(X86_FEATURE_LAHF_LM) : 0) |
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+ bitmaskof(X86_FEATURE_ABM);
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regs[3] &= ((is_pae ? bitmaskof(X86_FEATURE_NX) : 0) |
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(is_64bit ? bitmaskof(X86_FEATURE_LM) : 0) |
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(is_64bit ? bitmaskof(X86_FEATURE_SYSCALL) : 0) |
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@@ -256,9 +257,11 @@ static void xc_cpuid_hvm_policy(
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regs[2] &= (bitmaskof(X86_FEATURE_XMM3) |
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bitmaskof(X86_FEATURE_PCLMULQDQ) |
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bitmaskof(X86_FEATURE_SSSE3) |
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+ bitmaskof(X86_FEATURE_FMA) |
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bitmaskof(X86_FEATURE_CX16) |
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bitmaskof(X86_FEATURE_SSE4_1) |
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bitmaskof(X86_FEATURE_SSE4_2) |
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+ bitmaskof(X86_FEATURE_MOVBE) |
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bitmaskof(X86_FEATURE_POPCNT) |
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bitmaskof(X86_FEATURE_AES) |
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bitmaskof(X86_FEATURE_F16C) |
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@@ -303,7 +306,10 @@ static void xc_cpuid_hvm_policy(
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case 0x00000007: /* Intel-defined CPU features */
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if ( input[1] == 0 ) {
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- regs[1] &= (bitmaskof(X86_FEATURE_SMEP) |
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+ regs[1] &= (bitmaskof(X86_FEATURE_BMI1) |
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+ bitmaskof(X86_FEATURE_AVX2) |
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+ bitmaskof(X86_FEATURE_SMEP) |
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+ bitmaskof(X86_FEATURE_BMI2) |
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bitmaskof(X86_FEATURE_ERMS) |
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bitmaskof(X86_FEATURE_FSGSBASE));
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} else
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@@ -427,8 +433,11 @@ static void xc_cpuid_pv_policy(
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case 7:
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if ( input[1] == 0 )
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- regs[1] &= (bitmaskof(X86_FEATURE_FSGSBASE) |
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- bitmaskof(X86_FEATURE_ERMS));
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+ regs[1] &= (bitmaskof(X86_FEATURE_BMI1) |
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+ bitmaskof(X86_FEATURE_AVX2) |
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+ bitmaskof(X86_FEATURE_BMI2) |
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+ bitmaskof(X86_FEATURE_ERMS) |
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+ bitmaskof(X86_FEATURE_FSGSBASE));
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else
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regs[1] = 0;
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regs[0] = regs[2] = regs[3] = 0;
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