59 lines
2.6 KiB
Diff
59 lines
2.6 KiB
Diff
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# HG changeset patch
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# User Liu, Jinsong <jinsong.liu@intel.com>
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# Date 1322738484 -3600
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# Node ID 1f6b58c8e1ba8d27dfb97f0da96d18d3ad163317
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# Parent 89f7273681696022cc44db4f2ec5b22560482869
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X86: expose Intel new features to dom0
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This patch expose Intel new features to dom0, including
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FMA/AVX2/BMI1/BMI2/LZCNT/MOVBE.
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Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
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Committed-by: Jan Beulich <jbeulich@suse.com>
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--- a/xen/arch/x86/traps.c
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+++ b/xen/arch/x86/traps.c
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@@ -848,8 +848,11 @@ static void pv_cpuid(struct cpu_user_reg
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break;
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case 7:
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if ( regs->ecx == 0 )
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- b &= (cpufeat_mask(X86_FEATURE_FSGSBASE) |
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- cpufeat_mask(X86_FEATURE_ERMS));
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+ b &= (cpufeat_mask(X86_FEATURE_BMI1) |
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+ cpufeat_mask(X86_FEATURE_AVX2) |
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+ cpufeat_mask(X86_FEATURE_BMI2) |
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+ cpufeat_mask(X86_FEATURE_ERMS) |
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+ cpufeat_mask(X86_FEATURE_FSGSBASE));
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else
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b = 0;
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a = c = d = 0;
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--- a/xen/include/asm-x86/cpufeature.h
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+++ b/xen/include/asm-x86/cpufeature.h
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@@ -93,6 +93,7 @@
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#define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */
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#define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental Streaming SIMD Extensions-3 */
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#define X86_FEATURE_CID (4*32+10) /* Context ID */
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+#define X86_FEATURE_FMA (4*32+12) /* Fused Multiply Add */
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#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
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#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
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#define X86_FEATURE_PDCM (4*32+15) /* Perf/Debug Capability MSR */
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@@ -100,6 +101,7 @@
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#define X86_FEATURE_SSE4_1 (4*32+19) /* Streaming SIMD Extensions 4.1 */
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#define X86_FEATURE_SSE4_2 (4*32+20) /* Streaming SIMD Extensions 4.2 */
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#define X86_FEATURE_X2APIC (4*32+21) /* Extended xAPIC */
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+#define X86_FEATURE_MOVBE (4*32+22) /* movbe instruction */
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#define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */
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#define X86_FEATURE_TSC_DEADLINE (4*32+24) /* "tdt" TSC Deadline Timer */
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#define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
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@@ -144,7 +146,10 @@
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/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 7 */
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#define X86_FEATURE_FSGSBASE (7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */
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+#define X86_FEATURE_BMI1 (7*32+ 3) /* 1st bit manipulation extensions */
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+#define X86_FEATURE_AVX2 (7*32+ 5) /* AVX2 instructions */
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#define X86_FEATURE_SMEP (7*32+ 7) /* Supervisor Mode Execution Protection */
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+#define X86_FEATURE_BMI2 (7*32+ 8) /* 2nd bit manipulation extensions */
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#define X86_FEATURE_ERMS (7*32+ 9) /* Enhanced REP MOVSB/STOSB */
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#define cpu_has(c, bit) test_bit(bit, (c)->x86_capability)
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