50 lines
2.2 KiB
Diff
50 lines
2.2 KiB
Diff
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# HG changeset patch
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# User Liu, Jinsong <jinsong.liu@intel.com>
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# Date 1322738563 -3600
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# Node ID d9cb04ed55398ea4043c85573460afaf023aa1e9
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# Parent 1f6b58c8e1ba8d27dfb97f0da96d18d3ad163317
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X86: Disable PCID/INVPCID for dom0
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PCID (Process-context identifier) is a facility by which a logical
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processor may cache information for multiple linear-address spaces.
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INVPCID is an new instruction to invalidate TLB. Refer latest Intel SDM
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http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html
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We disable PCID/INVPCID for dom0 and pv. Exposing them into dom0 and pv
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may result in performance regression, and it would trigger GP or UD
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depending on whether platform suppport INVPCID or not.
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This patch disables PCID/INVPCID for dom0.
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Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
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Committed-by: Jan Beulich <jbeulich@suse.com>
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--- a/xen/arch/x86/traps.c
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+++ b/xen/arch/x86/traps.c
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@@ -836,6 +836,7 @@ static void pv_cpuid(struct cpu_user_reg
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__clear_bit(X86_FEATURE_CX16 % 32, &c);
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__clear_bit(X86_FEATURE_XTPR % 32, &c);
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__clear_bit(X86_FEATURE_PDCM % 32, &c);
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+ __clear_bit(X86_FEATURE_PCID % 32, &c);
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__clear_bit(X86_FEATURE_DCA % 32, &c);
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if ( !xsave_enabled(current) )
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{
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--- a/xen/include/asm-x86/cpufeature.h
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+++ b/xen/include/asm-x86/cpufeature.h
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@@ -97,6 +97,7 @@
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#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
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#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
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#define X86_FEATURE_PDCM (4*32+15) /* Perf/Debug Capability MSR */
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+#define X86_FEATURE_PCID (4*32+17) /* Process Context ID */
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#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
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#define X86_FEATURE_SSE4_1 (4*32+19) /* Streaming SIMD Extensions 4.1 */
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#define X86_FEATURE_SSE4_2 (4*32+20) /* Streaming SIMD Extensions 4.2 */
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@@ -151,6 +152,7 @@
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#define X86_FEATURE_SMEP (7*32+ 7) /* Supervisor Mode Execution Protection */
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#define X86_FEATURE_BMI2 (7*32+ 8) /* 2nd bit manipulation extensions */
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#define X86_FEATURE_ERMS (7*32+ 9) /* Enhanced REP MOVSB/STOSB */
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+#define X86_FEATURE_INVPCID (7*32+10) /* Invalidate Process Context ID */
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#define cpu_has(c, bit) test_bit(bit, (c)->x86_capability)
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#define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability)
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