89 lines
3.3 KiB
Diff
89 lines
3.3 KiB
Diff
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# HG changeset patch
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# User Jan Beulich <jbeulich@suse.com>
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# Date 1353575003 -3600
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# Node ID c139ca92edca2fab8ec95deb7fd9e4246c3fe28d
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# Parent af6b72a224e99a4a516fbc2eecc06ada569304e8
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x86/HPET: fix FSB interrupt masking
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HPET_TN_FSB is not really suitable for masking interrupts - it merely
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switches between the two delivery methods. The right way of masking is
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through the HPET_TN_ENABLE bit (which really is an interrupt enable,
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not a counter enable or some such). This is even more so with certain
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chip sets not even allowing HPET_TN_FSB to be cleared on some of the
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channels.
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Further, all the setup of the channel should happen before actually
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enabling the interrupt, which requires splitting legacy and FSB logic.
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Finally this also fixes an S3 resume problem (HPET_TN_FSB did not get
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set in hpet_broadcast_resume(), and hpet_msi_unmask() doesn't get
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called from the general resume code either afaict).
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Signed-off-by: Jan Beulich <jbeulich@suse.com>
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Acked-by: Keir Fraser <keir@xen.org>
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--- a/xen/arch/x86/hpet.c
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+++ b/xen/arch/x86/hpet.c
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@@ -236,7 +236,7 @@ static void hpet_msi_unmask(struct irq_d
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struct hpet_event_channel *ch = desc->action->dev_id;
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cfg = hpet_read32(HPET_Tn_CFG(ch->idx));
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- cfg |= HPET_TN_FSB;
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+ cfg |= HPET_TN_ENABLE;
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hpet_write32(cfg, HPET_Tn_CFG(ch->idx));
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}
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@@ -246,7 +246,7 @@ static void hpet_msi_mask(struct irq_des
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struct hpet_event_channel *ch = desc->action->dev_id;
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cfg = hpet_read32(HPET_Tn_CFG(ch->idx));
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- cfg &= ~HPET_TN_FSB;
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+ cfg &= ~HPET_TN_ENABLE;
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hpet_write32(cfg, HPET_Tn_CFG(ch->idx));
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}
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@@ -319,8 +319,14 @@ static void __hpet_setup_msi_irq(struct
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static int __init hpet_setup_msi_irq(unsigned int irq, struct hpet_event_channel *ch)
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{
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int ret;
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+ u32 cfg = hpet_read32(HPET_Tn_CFG(ch->idx));
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irq_desc_t *desc = irq_to_desc(irq);
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+ /* set HPET Tn as oneshot */
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+ cfg &= ~(HPET_TN_LEVEL | HPET_TN_PERIODIC);
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+ cfg |= HPET_TN_FSB | HPET_TN_32BIT;
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+ hpet_write32(cfg, HPET_Tn_CFG(ch->idx));
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+
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desc->handler = &hpet_msi_type;
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ret = request_irq(irq, hpet_interrupt_handler, 0, "HPET", ch);
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if ( ret < 0 )
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@@ -541,11 +547,14 @@ void __init hpet_broadcast_init(void)
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for ( i = 0; i < n; i++ )
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{
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- /* set HPET Tn as oneshot */
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- cfg = hpet_read32(HPET_Tn_CFG(hpet_events[i].idx));
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- cfg &= ~(HPET_TN_LEVEL | HPET_TN_PERIODIC);
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- cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
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- hpet_write32(cfg, HPET_Tn_CFG(hpet_events[i].idx));
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+ if ( i == 0 && (cfg & HPET_CFG_LEGACY) )
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+ {
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+ /* set HPET T0 as oneshot */
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+ cfg = hpet_read32(HPET_Tn_CFG(0));
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+ cfg &= ~(HPET_TN_LEVEL | HPET_TN_PERIODIC);
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+ cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
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+ hpet_write32(cfg, HPET_Tn_CFG(0));
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+ }
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/*
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* The period is a femto seconds value. We need to calculate the scaled
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@@ -602,6 +611,8 @@ void hpet_broadcast_resume(void)
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cfg = hpet_read32(HPET_Tn_CFG(hpet_events[i].idx));
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cfg &= ~(HPET_TN_LEVEL | HPET_TN_PERIODIC);
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cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
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+ if ( !(hpet_events[i].flags & HPET_EVT_LEGACY) )
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+ cfg |= HPET_TN_FSB;
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hpet_write32(cfg, HPET_Tn_CFG(hpet_events[i].idx));
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hpet_events[i].next_event = STIME_MAX;
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