92 lines
3.1 KiB
Diff
92 lines
3.1 KiB
Diff
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# HG changeset patch
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# User Keir Fraser <keir.fraser@citrix.com>
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# Date 1284537635 -3600
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# Node ID 1087f9a03ab61d3a8bb0a1c65e5b09f82f3a4277
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# Parent 62edd2611cbbe4c50574b6f6f73dda2ae1136dde
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C6 state with EOI issue fix for some Intel processors
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There is an errata in some of Intel processors.
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AAJ72. EOI Transaction May Not be Sent if Software Enters Core C6
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During an Interrupt Service Routine
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If core C6 is entered after the start of an interrupt service routine
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but before a write to the APIC EOI register, the core may not send an
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EOI transaction (if needed) and further interrupts from the same
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priority level or lower may be blocked.
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This patch fix this issue, by checking if ISR is pending before enter
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deep Cx state. If so, it would use power->safe_state instead of deep
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Cx state to prevent the above issue happen.
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Signed-off-by: Sheng Yang <sheng@linux.intel.com>
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Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
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--- a/xen/arch/x86/acpi/cpu_idle.c
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+++ b/xen/arch/x86/acpi/cpu_idle.c
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@@ -226,6 +226,31 @@ static int sched_has_urgent_vcpu(void)
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return atomic_read(&this_cpu(schedule_data).urgent_count);
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}
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+/*
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+ * "AAJ72. EOI Transaction May Not be Sent if Software Enters Core C6 During
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+ * an Interrupt Service Routine"
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+ *
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+ * There was an errata with some Core i7 processors that an EOI transaction
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+ * may not be sent if software enters core C6 during an interrupt service
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+ * routine. So we don't enter deep Cx state if there is an EOI pending.
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+ */
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+bool_t errata_c6_eoi_workaround(void)
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+{
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+ static bool_t fix_needed = -1;
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+
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+ if ( unlikely(fix_needed == -1) )
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+ {
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+ int model = boot_cpu_data.x86_model;
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+ fix_needed = (cpu_has_apic && !directed_eoi_enabled &&
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+ (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
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+ (boot_cpu_data.x86 == 6) &&
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+ ((model == 0x1a) || (model == 0x1e) || (model == 0x1f) ||
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+ (model == 0x25) || (model == 0x2c) || (model == 0x2f)));
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+ }
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+
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+ return (fix_needed && cpu_has_pending_apic_eoi());
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+}
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+
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static void acpi_processor_idle(void)
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{
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struct acpi_processor_power *power = processor_powers[smp_processor_id()];
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@@ -277,6 +302,9 @@ static void acpi_processor_idle(void)
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return;
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}
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+ if ( (cx->type == ACPI_STATE_C3) && errata_c6_eoi_workaround() )
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+ cx = power->safe_state;
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+
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power->last_state = cx;
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/*
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--- a/xen/arch/x86/irq.c
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+++ b/xen/arch/x86/irq.c
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@@ -752,6 +752,11 @@ struct pending_eoi {
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static DEFINE_PER_CPU(struct pending_eoi, pending_eoi[NR_DYNAMIC_VECTORS]);
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#define pending_eoi_sp(p) ((p)[NR_DYNAMIC_VECTORS-1].vector)
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+bool_t cpu_has_pending_apic_eoi(void)
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+{
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+ return (pending_eoi_sp(this_cpu(pending_eoi)) != 0);
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+}
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+
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static inline void set_pirq_eoi(struct domain *d, unsigned int irq)
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{
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if ( d->arch.pirq_eoi_map )
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--- a/xen/include/asm-x86/irq.h
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+++ b/xen/include/asm-x86/irq.h
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@@ -150,4 +150,6 @@ void irq_set_affinity(int irq, cpumask_t
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#define domain_pirq_to_irq(d, pirq) ((d)->arch.pirq_irq[pirq])
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#define domain_irq_to_pirq(d, irq) ((d)->arch.irq_pirq[irq])
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+bool_t cpu_has_pending_apic_eoi(void);
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+
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#endif /* _ASM_HW_IRQ_H */
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