24 lines
848 B
Diff
24 lines
848 B
Diff
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# Commit e1ab5c77b44b7bd835a2c032fa4963b36545fdb3
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# Date 2013-08-06 17:22:35 +0200
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# Author Yang Zhang <yang.z.zhang@Intel.com>
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# Committer Jan Beulich <jbeulich@suse.com>
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Nested VMX: Flush TLBs and Caches if paging mode changed
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According to SDM, if paging mode is changed, then whole TLBs and caches will
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be flushed. This is missed in nested handle logic. Also this fixed the issue
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that 64 bits windows cannot boot up on top of L1 kvm.
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Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com>
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Acked-by: Keir Fraser <keir@xen.org>
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--- a/xen/arch/x86/mm/paging.c
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+++ b/xen/arch/x86/mm/paging.c
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@@ -709,6 +709,7 @@ void paging_update_nestedmode(struct vcp
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else
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/* TODO: shadow-on-shadow */
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v->arch.paging.nestedmode = NULL;
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+ hvm_asid_flush_vcpu(v);
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}
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void paging_write_p2m_entry(struct p2m_domain *p2m, unsigned long gfn,
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