44 lines
1.6 KiB
Diff
44 lines
1.6 KiB
Diff
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# Commit 375a1035002fb257087756a86e6caeda649fc0f1
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# Date 2013-08-22 10:52:05 +0200
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# Author Yang Zhang <yang.z.zhang@Intel.com>
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# Committer Jan Beulich <jbeulich@suse.com>
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Nested VMX: Clear APIC-v control bit in vmcs02
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There is no vAPIC-v support, so mask APIC-v control bit when
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constructing vmcs02.
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Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com>
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Acked-by: "Dong, Eddie" <eddie.dong@intel.com>
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--- a/xen/arch/x86/hvm/vmx/vvmx.c
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+++ b/xen/arch/x86/hvm/vmx/vvmx.c
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@@ -613,8 +613,15 @@ void nvmx_update_secondary_exec_control(
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u32 shadow_cntrl;
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struct nestedvcpu *nvcpu = &vcpu_nestedhvm(v);
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struct nestedvmx *nvmx = &vcpu_2_nvmx(v);
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+ u32 apicv_bit = SECONDARY_EXEC_APIC_REGISTER_VIRT |
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+ SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
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+ host_cntrl &= ~apicv_bit;
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shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx, SECONDARY_VM_EXEC_CONTROL);
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+
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+ /* No vAPIC-v support, so it shouldn't be set in vmcs12. */
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+ ASSERT(!(shadow_cntrl & apicv_bit));
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+
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nvmx->ept.enabled = !!(shadow_cntrl & SECONDARY_EXEC_ENABLE_EPT);
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shadow_cntrl |= host_cntrl;
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__vmwrite(SECONDARY_VM_EXEC_CONTROL, shadow_cntrl);
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@@ -625,7 +632,12 @@ static void nvmx_update_pin_control(stru
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u32 shadow_cntrl;
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struct nestedvcpu *nvcpu = &vcpu_nestedhvm(v);
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+ host_cntrl &= ~PIN_BASED_POSTED_INTERRUPT;
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shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx, PIN_BASED_VM_EXEC_CONTROL);
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+
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+ /* No vAPIC-v support, so it shouldn't be set in vmcs12. */
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+ ASSERT(!(shadow_cntrl & PIN_BASED_POSTED_INTERRUPT));
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+
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shadow_cntrl |= host_cntrl;
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__vmwrite(PIN_BASED_VM_EXEC_CONTROL, shadow_cntrl);
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}
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