50 lines
1.7 KiB
Diff
50 lines
1.7 KiB
Diff
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References: bnc#745367
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# HG changeset patch
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# User Jan Beulich <jbeulich@suse.com>
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# Date 1330070623 -3600
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# Node ID e80b0bb4470b944a5b52a91c0ec85a1d65d18c55
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# Parent 0c3d19f40ab145d101de84051c3e00eef17fa1cb
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x86/vMCE: don't advertise features we don't support
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... or even know of. Apart from CMCI, which was masked off already,
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this now also suppresses the advertising of extended state registers
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(reading of which would likely be meaningless in a guest and represent
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an information leak).
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Signed-off-by: Jan Beulich <jbeulich@suse.com>
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Acked-by: Keir Fraser <keir@xen.org>
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--- a/xen/arch/x86/cpu/mcheck/vmce.c
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+++ b/xen/arch/x86/cpu/mcheck/vmce.c
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@@ -456,7 +456,7 @@ int vmce_init(struct cpuinfo_x86 *c)
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rdmsrl(MSR_IA32_MCG_CAP, value);
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/* For Guest vMCE usage */
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- g_mcg_cap = value & ~MCG_CMCI_P;
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+ g_mcg_cap = value & (MCG_CAP_COUNT | MCG_CTL_P | MCG_TES_P | MCG_SER_P);
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if (value & MCG_CTL_P)
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rdmsrl(MSR_IA32_MCG_CTL, h_mcg_ctl);
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--- a/xen/arch/x86/cpu/mcheck/x86_mca.h
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+++ b/xen/arch/x86/cpu/mcheck/x86_mca.h
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@@ -30,12 +30,13 @@
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/* Bitfield of the MSR_IA32_MCG_CAP register */
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-#define MCG_SER_P (1UL<<24)
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#define MCG_CAP_COUNT 0x00000000000000ffULL
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-#define MCG_CTL_P 0x0000000000000100ULL
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-#define MCG_EXT_P (1UL<<9)
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-#define MCG_EXT_CNT (16)
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-#define MCG_CMCI_P (1UL<<10)
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+#define MCG_CTL_P (1ULL<<8)
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+#define MCG_EXT_P (1ULL<<9)
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+#define MCG_CMCI_P (1ULL<<10)
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+#define MCG_TES_P (1ULL<<11)
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+#define MCG_EXT_CNT 16
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+#define MCG_SER_P (1ULL<<24)
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/* Other bits are reserved */
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/* Bitfield of the MSR_IA32_MCG_STATUS register */
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