40 lines
1.5 KiB
Diff
40 lines
1.5 KiB
Diff
|
References: FATE#313633
|
||
|
|
|
||
|
|
# HG changeset patch
|
||
|
|
# User Liu, Jinsong <jinsong.liu@intel.com>
|
||
|
|
# Date 1348654470 -7200
|
||
|
|
# Node ID 3aa66543a51ba77cb73e8c874e2416d065426a22
|
||
|
|
# Parent 56fb977ce6eb4626a02d4a7a34e85009bb8ee3e0
|
||
|
|
x86: Expose TSC adjust to HVM guest
|
||
|
|
|
||
|
|
Intel latest SDM (17.13.3) release a new MSR CPUID.7.0.EBX[1]=1
|
||
|
|
indicates TSC_ADJUST MSR 0x3b is supported.
|
||
|
|
|
||
|
|
This patch expose it to hvm guest.
|
||
|
|
|
||
|
|
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
|
||
|
|
Committed-by: Jan Beulich <jbeulich@suse.com>
|
||
|
|
|
||
|
|
--- a/tools/libxc/xc_cpufeature.h
|
||
|
|
+++ b/tools/libxc/xc_cpufeature.h
|
||
|
|
@@ -128,6 +128,7 @@
|
||
|
|
|
||
|
|
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */
|
||
|
|
#define X86_FEATURE_FSGSBASE 0 /* {RD,WR}{FS,GS}BASE instructions */
|
||
|
|
+#define X86_FEATURE_TSC_ADJUST 1 /* Tsc thread offset */
|
||
|
|
#define X86_FEATURE_BMI1 3 /* 1st group bit manipulation extensions */
|
||
|
|
#define X86_FEATURE_HLE 4 /* Hardware Lock Elision */
|
||
|
|
#define X86_FEATURE_AVX2 5 /* AVX2 instructions */
|
||
|
|
--- a/tools/libxc/xc_cpuid_x86.c
|
||
|
|
+++ b/tools/libxc/xc_cpuid_x86.c
|
||
|
|
@@ -362,7 +362,8 @@ static void xc_cpuid_hvm_policy(
|
||
|
|
|
||
|
|
case 0x00000007: /* Intel-defined CPU features */
|
||
|
|
if ( input[1] == 0 ) {
|
||
|
|
- regs[1] &= (bitmaskof(X86_FEATURE_BMI1) |
|
||
|
|
+ regs[1] &= (bitmaskof(X86_FEATURE_TSC_ADJUST) |
|
||
|
|
+ bitmaskof(X86_FEATURE_BMI1) |
|
||
|
|
bitmaskof(X86_FEATURE_HLE) |
|
||
|
|
bitmaskof(X86_FEATURE_AVX2) |
|
||
|
|
bitmaskof(X86_FEATURE_SMEP) |
|