70 lines
2.6 KiB
Diff
70 lines
2.6 KiB
Diff
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# HG changeset patch
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# User Wei Wang <wei.wang2@amd.com>
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# Date 1350306216 -7200
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# Node ID 983108e1b56bf809f3f5eaaebf18c4b613ff0865
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# Parent 137dfbd3190e849b3a498d8b2ea282ebbf12e77d
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x86/amd: Fix xen_apic_write warnings in Dom0
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[ 0.020294] ------------[ cut here ]------------
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[ 0.020311] WARNING: at arch/x86/xen/enlighten.c:730
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xen_apic_write+0x15/0x17()
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[ 0.020318] Hardware name: empty
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[ 0.020323] Modules linked in:
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[ 0.020334] Pid: 1, comm: swapper/0 Not tainted 3.3.8 #7
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[ 0.020340] Call Trace:
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[ 0.020354] [<ffffffff81050379>] warn_slowpath_common+0x80/0x98
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[ 0.020369] [<ffffffff810503a6>] warn_slowpath_null+0x15/0x17
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[ 0.020378] [<ffffffff810034df>] xen_apic_write+0x15/0x17
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[ 0.020392] [<ffffffff8101cb2b>] perf_events_lapic_init+0x2e/0x30
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[ 0.020410] [<ffffffff81ee4dd0>] init_hw_perf_events+0x250/0x407
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[ 0.020419] [<ffffffff81ee4b80>] ? check_bugs+0x2d/0x2d
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[ 0.020430] [<ffffffff81002181>] do_one_initcall+0x7a/0x131
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[ 0.020444] [<ffffffff81edbbf9>] kernel_init+0x91/0x15d
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[ 0.020456] [<ffffffff817caaa4>] kernel_thread_helper+0x4/0x10
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[ 0.020471] [<ffffffff817c347c>] ? retint_restore_args+0x5/0x6
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[ 0.020481] [<ffffffff817caaa0>] ? gs_change+0x13/0x13
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[ 0.020500] ---[ end trace a7919e7f17c0a725 ]---
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Kernel function check_hw_exists() writes 0xabcd to msr 0xc0010201 (Performance Event
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Counter 0) and read it again to check if it is running as dom0. Early amd cpus does
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not reset perf counters during warm reboot. If the kernel is booted with bare metal
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and then as a dom0, the content of msr 0xc0010201 will stay and the checking will
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pass and PMU will be enabled unexpectedly.
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Signed-off-by: Wei Wang <wei.wang2@amd.com>
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Don't reset the counters when used for the NMI watchdog.
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Signed-off-by: Jan Beulich <jbeulich@suse.com>
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Acked-by: Keir Fraser <keir@xen.org>
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Committed-by: Jan Beulich <jbeulich@suse.com>
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--- a/xen/arch/x86/cpu/amd.c
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+++ b/xen/arch/x86/cpu/amd.c
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@@ -11,6 +11,7 @@
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#include <asm/hvm/support.h>
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#include <asm/setup.h> /* amd_init_cpu */
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#include <asm/acpi.h>
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+#include <asm/apic.h>
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#include "cpu.h"
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@@ -532,6 +533,17 @@ static void __devinit init_amd(struct cp
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if (c->x86 > 0x11)
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set_bit(X86_FEATURE_ARAT, c->x86_capability);
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+ /*
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+ * Prior to Family 0x14, perf counters are not reset during warm reboot.
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+ * We have to reset them manually.
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+ */
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+ if (nmi_watchdog != NMI_LOCAL_APIC && c->x86 < 0x14) {
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+ wrmsrl(MSR_K7_PERFCTR0, 0);
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+ wrmsrl(MSR_K7_PERFCTR1, 0);
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+ wrmsrl(MSR_K7_PERFCTR2, 0);
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+ wrmsrl(MSR_K7_PERFCTR3, 0);
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+ }
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+
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if (cpuid_edx(0x80000007) & (1 << 10)) {
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rdmsr(MSR_K7_HWCR, l, h);
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l |= (1 << 27); /* Enable read-only APERF/MPERF bit */
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