74 lines
2.6 KiB
Diff
74 lines
2.6 KiB
Diff
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# Commit 0f8adcb2a7183bea5063f6fffba7d7e1aa14fc84
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# Date 2013-02-26 10:14:53 +0100
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# Author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
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# Committer Jan Beulich <jbeulich@suse.com>
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IOMMU, AMD Family15h Model10-1Fh erratum 746 Workaround
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The IOMMU may stop processing page translations due to a perceived lack
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of credits for writing upstream peripheral page service request (PPR)
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or event logs. If the L2B miscellaneous clock gating feature is enabled
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the IOMMU does not properly register credits after the log request has
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completed, leading to a potential system hang.
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BIOSes are supposed to disable L2B micellaneous clock gating by setting
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L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b. This
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patch corrects that for those which do not enable this workaround.
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Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
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Signed-off-by: Jan Beulich <jbeulich@suse.com>
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--- a/xen/drivers/passthrough/amd/iommu_init.c
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+++ b/xen/drivers/passthrough/amd/iommu_init.c
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@@ -795,6 +795,42 @@ static int __init set_iommu_interrupt_ha
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return irq;
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}
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+/*
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+ * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
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+ * Workaround:
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+ * BIOS should disable L2B micellaneous clock gating by setting
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+ * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
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+ */
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+static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
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+{
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+ u32 value;
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+ u8 bus = PCI_BUS(iommu->bdf);
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+ u8 dev = PCI_SLOT(iommu->bdf);
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+ u8 func = PCI_FUNC(iommu->bdf);
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+
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+ if ( (boot_cpu_data.x86 != 0x15) ||
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+ (boot_cpu_data.x86_model < 0x10) ||
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+ (boot_cpu_data.x86_model > 0x1f) )
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+ return;
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+
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+ pci_conf_write32(iommu->seg, bus, dev, func, 0xf0, 0x90);
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+ value = pci_conf_read32(iommu->seg, bus, dev, func, 0xf4);
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+
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+ if ( value & (1 << 2) )
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+ return;
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+
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+ /* Select NB indirect register 0x90 and enable writing */
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+ pci_conf_write32(iommu->seg, bus, dev, func, 0xf0, 0x90 | (1 << 8));
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+
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+ pci_conf_write32(iommu->seg, bus, dev, func, 0xf4, value | (1 << 2));
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+ printk(XENLOG_INFO
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+ "AMD-Vi: Applying erratum 746 workaround for IOMMU at %04x:%02x:%02x.%u\n",
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+ iommu->seg, bus, dev, func);
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+
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+ /* Clear the enable writing bit */
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+ pci_conf_write32(iommu->seg, bus, dev, func, 0xf0, 0x90);
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+}
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+
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static void enable_iommu(struct amd_iommu *iommu)
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{
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unsigned long flags;
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@@ -807,6 +843,8 @@ static void enable_iommu(struct amd_iomm
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return;
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}
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+ amd_iommu_erratum_746_workaround(iommu);
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+
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register_iommu_dev_table_in_mmio_space(iommu);
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register_iommu_cmd_buffer_in_mmio_space(iommu);
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register_iommu_event_log_in_mmio_space(iommu);
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