36 lines
1.6 KiB
Diff
36 lines
1.6 KiB
Diff
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# Commit 50df6f7429f73364bbddb0970a3a34faa01a7790
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# Date 2014-05-28 09:51:07 +0200
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# Author Jan Beulich <jbeulich@suse.com>
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# Committer Jan Beulich <jbeulich@suse.com>
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x86: don't use VA for cache flush when also flushing TLB
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Doing both flushes at once is a strong indication for the address
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mapping to either having got dropped (in which case the cache flush,
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when done via INVLPG, would fault) or its physical address having
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changed (in which case the cache flush would end up being done on the
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wrong address range). There is no adverse effect (other than the
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obvious performance one) using WBINVD in this case regardless of the
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range's size; only map_pages_to_xen() uses combined flushes at present.
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This problem was observed with the 2nd try backport of d6cb14b3 ("VT-d:
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suppress UR signaling for desktop chipsets") to 4.2 (where ioremap()
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needs to be replaced with set_fixmap_nocache(); the now commented out
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__set_fixmap(, 0, 0) there to undo the mapping resulted in the first of
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the above two scenarios).
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Signed-off-by: Jan Beulich <jbeulich@suse.com>
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Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
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--- a/xen/arch/x86/flushtlb.c
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+++ b/xen/arch/x86/flushtlb.c
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@@ -152,7 +152,8 @@ void flush_area_local(const void *va, un
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if ( order < (BITS_PER_LONG - PAGE_SHIFT) )
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sz = 1UL << (order + PAGE_SHIFT);
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- if ( c->x86_clflush_size && c->x86_cache_size && sz &&
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+ if ( !(flags & (FLUSH_TLB|FLUSH_TLB_GLOBAL)) &&
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+ c->x86_clflush_size && c->x86_cache_size && sz &&
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((sz >> 10) < c->x86_cache_size) )
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{
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va = (const void *)((unsigned long)va & ~(sz - 1));
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