89 lines
2.7 KiB
Diff
89 lines
2.7 KiB
Diff
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# HG changeset patch
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# User Jan Beulich <jbeulich@suse.com>
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# Date 1322725849 -3600
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# Node ID 76ea126f21724b72c120aff59460f7bbe9e6960d
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# Parent 07cf778d517fdf661a34027af653a489489bf222
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x86/emulator: properly handle lzcnt and tzcnt
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These instructions are prefix selected flavors of bsf and bsr
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respectively, and hence the presences of the F3 prefix must be handled
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in the emulation code in order to avoid running into problems on newer
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CPUs.
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Signed-off-by: Jan Beulich <jbeulich@suse.com>
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--- a/xen/arch/x86/x86_emulate/x86_emulate.c
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+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
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@@ -990,6 +990,9 @@ static bool_t vcpu_has(
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return rc == X86EMUL_OKAY;
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}
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+#define vcpu_has_lzcnt() vcpu_has(0x80000001, ECX, 5, ctxt, ops)
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+#define vcpu_has_bmi1() vcpu_has(0x00000007, EBX, 3, ctxt, ops)
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+
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#define vcpu_must_have(leaf, reg, bit) \
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generate_exception_if(!vcpu_has(leaf, reg, bit, ctxt, ops), EXC_UD, -1)
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#define vcpu_must_have_sse2() vcpu_must_have(0x00000001, EDX, 26)
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@@ -4114,13 +4117,24 @@ x86_emulate(
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dst.val = (uint8_t)src.val;
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break;
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- case 0xbc: /* bsf */ {
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- int zf;
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+ case 0xbc: /* bsf or tzcnt */ {
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+ bool_t zf;
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asm ( "bsf %2,%0; setz %b1"
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: "=r" (dst.val), "=q" (zf)
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- : "r" (src.val), "1" (0) );
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+ : "r" (src.val) );
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_regs.eflags &= ~EFLG_ZF;
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- if ( zf )
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+ if ( (rep_prefix == REPE_PREFIX) && vcpu_has_bmi1() )
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+ {
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+ _regs.eflags &= ~EFLG_CF;
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+ if ( zf )
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+ {
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+ _regs.eflags |= EFLG_CF;
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+ dst.val = op_bytes * 8;
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+ }
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+ else if ( !dst.val )
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+ _regs.eflags |= EFLG_ZF;
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+ }
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+ else if ( zf )
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{
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_regs.eflags |= EFLG_ZF;
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dst.type = OP_NONE;
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@@ -4128,13 +4142,28 @@ x86_emulate(
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break;
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}
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- case 0xbd: /* bsr */ {
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- int zf;
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+ case 0xbd: /* bsr or lzcnt */ {
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+ bool_t zf;
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asm ( "bsr %2,%0; setz %b1"
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: "=r" (dst.val), "=q" (zf)
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- : "r" (src.val), "1" (0) );
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+ : "r" (src.val) );
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_regs.eflags &= ~EFLG_ZF;
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- if ( zf )
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+ if ( (rep_prefix == REPE_PREFIX) && vcpu_has_lzcnt() )
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+ {
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+ _regs.eflags &= ~EFLG_CF;
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+ if ( zf )
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+ {
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+ _regs.eflags |= EFLG_CF;
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+ dst.val = op_bytes * 8;
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+ }
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+ else
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+ {
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+ dst.val = op_bytes * 8 - 1 - dst.val;
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+ if ( !dst.val )
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+ _regs.eflags |= EFLG_ZF;
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+ }
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+ }
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+ else if ( zf )
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{
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_regs.eflags |= EFLG_ZF;
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dst.type = OP_NONE;
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