61 lines
2.3 KiB
Diff
61 lines
2.3 KiB
Diff
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# Commit c58d9f2f4844c2ce8859a8d0f26a54cd058eb51f
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# Date 2013-08-05 18:42:37 +0200
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# Author Jan Beulich <jbeulich@suse.com>
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# Committer Jan Beulich <jbeulich@suse.com>
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x86: refine FPU selector handling code for XSAVEOPT
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Some extra tweaks are necessary to deal with the situation of XSAVEOPT
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not writing the FPU portion of the save image (due to it detecting that
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the register state did not get modified since the last XRSTOR).
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Signed-off-by: Jan Beulich <jbeulich@suse.com>
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Tested-by: Ben Guthro <ben.guthro@gmail.com>
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Acked-by: Keir Fraser <keir@xen.org>
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--- a/xen/arch/x86/xstate.c
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+++ b/xen/arch/x86/xstate.c
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@@ -71,10 +71,28 @@ void xsave(struct vcpu *v, uint64_t mask
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if ( word_size <= 0 || !is_pv_32bit_vcpu(v) )
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{
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+ typeof(ptr->fpu_sse.fip.sel) fcs = ptr->fpu_sse.fip.sel;
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+ typeof(ptr->fpu_sse.fdp.sel) fds = ptr->fpu_sse.fdp.sel;
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+
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if ( cpu_has_xsaveopt )
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+ {
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+ /*
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+ * xsaveopt may not write the FPU portion even when the respective
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+ * mask bit is set. For the check further down to work we hence
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+ * need to put the save image back into the state that it was in
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+ * right after the previous xsaveopt.
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+ */
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+ if ( word_size > 0 &&
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+ (ptr->fpu_sse.x[FPU_WORD_SIZE_OFFSET] == 4 ||
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+ ptr->fpu_sse.x[FPU_WORD_SIZE_OFFSET] == 2) )
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+ {
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+ ptr->fpu_sse.fip.sel = 0;
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+ ptr->fpu_sse.fdp.sel = 0;
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+ }
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asm volatile ( ".byte 0x48,0x0f,0xae,0x37"
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: "=m" (*ptr)
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: "a" (lmask), "d" (hmask), "D" (ptr) );
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+ }
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else
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asm volatile ( ".byte 0x48,0x0f,0xae,0x27"
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: "=m" (*ptr)
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@@ -87,7 +105,14 @@ void xsave(struct vcpu *v, uint64_t mask
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*/
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(!(ptr->fpu_sse.fsw & 0x0080) &&
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boot_cpu_data.x86_vendor == X86_VENDOR_AMD) )
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+ {
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+ if ( cpu_has_xsaveopt && word_size > 0 )
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+ {
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+ ptr->fpu_sse.fip.sel = fcs;
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+ ptr->fpu_sse.fdp.sel = fds;
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+ }
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return;
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+ }
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if ( word_size > 0 &&
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!((ptr->fpu_sse.fip.addr | ptr->fpu_sse.fdp.addr) >> 32) )
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