34 lines
1.3 KiB
Diff
34 lines
1.3 KiB
Diff
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# HG changeset 15433 patch
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# User Ian Campbell <ian.campbell@xensource.com>
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# Date 1183052420 -3600
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# Node ID a5360bf1866892498f4fda9fb86f96035143221d
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# Parent d0608ecb56bc9dd77740096fd734332c46c737bd
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Fix fixup of invalid PTE writes, broken by 13392:0fd65225e4c6.
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By the time we test if addr is the upper word it has already been
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aligned to the 8 byte pte size.
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Signed-off-by: Ian Campbell <ian.campbell@xensource.com>
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Index: 2007-05-14/xen/arch/x86/mm.c
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===================================================================
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--- 2007-05-14.orig/xen/arch/x86/mm.c 2007-07-02 10:39:23.000000000 +0200
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+++ 2007-05-14/xen/arch/x86/mm.c 2007-07-02 10:51:13.000000000 +0200
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@@ -3196,6 +3196,7 @@ static int ptwr_emulated_update(
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struct ptwr_emulate_ctxt *ptwr_ctxt)
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{
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unsigned long mfn;
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+ unsigned long unaligned_addr = addr;
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struct page_info *page;
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l1_pgentry_t pte, ol1e, nl1e, *pl1e;
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struct vcpu *v = current;
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@@ -3249,7 +3250,7 @@ static int ptwr_emulated_update(
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if ( unlikely(!get_page_from_l1e(gl1e_to_ml1e(d, nl1e), d)) )
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{
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if ( (CONFIG_PAGING_LEVELS >= 3) && is_pv_32bit_domain(d) &&
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- (bytes == 4) && (addr & 4) && !do_cmpxchg &&
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+ (bytes == 4) && (unaligned_addr & 4) && !do_cmpxchg &&
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(l1e_get_flags(nl1e) & _PAGE_PRESENT) )
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{
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/*
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