35 lines
1.4 KiB
Diff
35 lines
1.4 KiB
Diff
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# HG changeset patch
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# User Yang, Wei <wei.y.yang@intel.com>
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# Date 1308150408 -3600
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# Node ID 8c75f35d55f60cb2f374e3b5c7c520f8633d733f
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# Parent 35b4220c98bc89b7162d19ed6c858e027fabff69
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Enable RDWRGSFS feature support for HVM guests
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Write/read FS/GS base instructions enable user level code to
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read/write FS & GS segment base registers for thread local storage.
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Signed-off-by: Yang, Wei <wei.y.yang@intel.com>
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--- a/tools/libxc/xc_cpuid_x86.c
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+++ b/tools/libxc/xc_cpuid_x86.c
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@@ -304,7 +304,8 @@ static void xc_cpuid_hvm_policy(
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case 0x00000007: /* Intel-defined CPU features */
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if ( input[1] == 0 ) {
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regs[1] &= (bitmaskof(X86_FEATURE_SMEP) |
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- bitmaskof(X86_FEATURE_ERMS));
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+ bitmaskof(X86_FEATURE_ERMS) |
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+ bitmaskof(X86_FEATURE_FSGSBASE));
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} else
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regs[1] = 0;
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regs[0] = regs[2] = regs[3] = 0;
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--- a/xen/include/asm-x86/hvm/hvm.h
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+++ b/xen/include/asm-x86/hvm/hvm.h
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@@ -297,6 +297,7 @@ static inline int hvm_do_pmu_interrupt(s
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X86_CR4_MCE | X86_CR4_PGE | X86_CR4_PCE | \
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X86_CR4_OSFXSR | X86_CR4_OSXMMEXCPT | \
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(cpu_has_smep ? X86_CR4_SMEP : 0) | \
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+ (cpu_has_fsgsbase ? X86_CR4_FSGSBASE : 0) | \
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(xsave_enabled(_v) ? X86_CR4_OSXSAVE : 0))))
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/* These exceptions must always be intercepted. */
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