# HG changeset patch # User Keir Fraser # Date 1294648952 0 # Node ID 08bb0eefe87107c30a9bdc6d72f26b20c55ae687 # Parent 66e8062894641e5622aa6adc54297d5700b1cea3 x86-64: don't allow wrmsr to MSR_FAM10H_MMIO_CONF_BASE when Xen itself is using it Signed-off-by: Jan Beulich # HG changeset patch # User Keir Fraser # Date 1294741846 0 # Node ID a2dcebb88bc4571d64b3f30c1fbb33cfe4f6e2c5 # Parent 1ae74f060a39ae1305b3a434d0faa1a19853fdab x86-64: refine access permission check for wrmsr to MSR_FAM10H_MMIO_CONF_BASE We really don't want the mmconf window to move/disappear whenever we use is ourselves, not only when we enabled it. Signed-off-by: Jan Beulich --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -1704,6 +1704,10 @@ static int is_cpufreq_controller(struct (d->domain_id == 0)); } +#ifdef CONFIG_X86_64 +#include "x86_64/mmconfig.h" +#endif + static int emulate_privileged_op(struct cpu_user_regs *regs) { struct vcpu *v = current; @@ -2263,7 +2267,13 @@ static int emulate_privileged_op(struct goto fail; if ( !IS_PRIV(v->domain) ) break; - if ( (rdmsr_safe(MSR_FAM10H_MMIO_CONF_BASE, l, h) != 0) || + if ( (rdmsr_safe(MSR_FAM10H_MMIO_CONF_BASE, l, h) != 0) ) + goto fail; + if ( +#ifdef CONFIG_X86_64 + (pci_probe & PCI_PROBE_MASK) == PCI_PROBE_MMCONF ? + eax != l || edx != h : +#endif (((((u64)h << 32) | l) ^ val) & ~( FAM10H_MMIO_CONF_ENABLE | (FAM10H_MMIO_CONF_BUSRANGE_MASK << --- a/xen/arch/x86/x86_64/mmconfig.h +++ b/xen/arch/x86/x86_64/mmconfig.h @@ -34,6 +34,8 @@ #define PCI_VENDOR_ID_NVIDIA 0x10de +extern unsigned int pci_probe; + /* * AMD Fam10h CPUs are buggy, and cannot access MMIO config space * on their northbrige except through the * %eax register. As such, you MUST --- a/xen/arch/x86/x86_64/mmconfig-shared.c +++ b/xen/arch/x86/x86_64/mmconfig-shared.c @@ -24,7 +24,7 @@ #include "mmconfig.h" static int __initdata known_bridge; -static unsigned int pci_probe = PCI_PROBE_CONF1 | PCI_PROBE_MMCONF; +unsigned int pci_probe = PCI_PROBE_CONF1 | PCI_PROBE_MMCONF; static void __init parse_mmcfg(char *s) {