# HG changeset patch # User Jan Beulich # Date 1321604565 -3600 # Node ID 7b5e1cb94bfa43a9268479b9a255fb88c07e4ce2 # Parent f29b5bd6e25fd78409baa5461914c67065f7579f x86/xsave: provide guests with finit-like environment Without the use of xsave, guests get their initial floating point environment set up with finit. At least NetWare actually depends on this (in particular on all exceptions being masked), so to be consistent set the same environment also when using xsave. This is also in line with all SSE exceptions getting masked initially. To avoid further fragile casts in xstate_alloc_save_area() the patch also changes xsave_struct's fpu_see member to have actually usable fields. The patch was tested in its technically identical, but modified-file- wise different 4.1.2 version. Signed-off-by: Jan Beulich Tested-by: Charles Arnold Acked-by: Keir Fraser --- a/xen/arch/x86/i387.c +++ b/xen/arch/x86/i387.c @@ -92,11 +92,14 @@ void setup_fpu(struct vcpu *v) v->fpu_dirtied = 1; } +#define FCW_DEFAULT 0x037f +#define MXCSR_DEFAULT 0x1f80 + static void init_fpu(void) { asm volatile ( "fninit" ); if ( cpu_has_xmm ) - load_mxcsr(0x1f80); + load_mxcsr(MXCSR_DEFAULT); } void save_init_fpu(struct vcpu *v) @@ -287,7 +290,7 @@ void xsave_init(void) int xsave_alloc_save_area(struct vcpu *v) { - void *save_area; + struct xsave_struct *save_area; if ( !cpu_has_xsave || is_idle_vcpu(v) ) return 0; @@ -300,8 +303,9 @@ int xsave_alloc_save_area(struct vcpu *v return -ENOMEM; memset(save_area, 0, xsave_cntxt_size); - ((u32 *)save_area)[6] = 0x1f80; /* MXCSR */ - *(uint64_t *)(save_area + 512) = XSTATE_FP_SSE; /* XSETBV */ + save_area->fpu_sse.fcw = FCW_DEFAULT; + save_area->fpu_sse.mxcsr = MXCSR_DEFAULT; + save_area->xsave_hdr.xstate_bv = XSTATE_FP_SSE; v->arch.xsave_area = save_area; v->arch.xcr0 = XSTATE_FP_SSE; --- a/xen/include/asm-x86/i387.h +++ b/xen/include/asm-x86/i387.h @@ -37,7 +37,29 @@ bool_t xsave_enabled(const struct vcpu * struct xsave_struct { - struct { char x[512]; } fpu_sse; /* FPU/MMX, SSE */ + union { /* FPU/MMX, SSE */ + char x[512]; + struct { + uint16_t fcw; + uint16_t fsw; + uint8_t ftw; + uint8_t rsvd1; + uint16_t fop; + union { +#ifdef __x86_64__ + uint64_t addr; +#endif + struct { + uint32_t offs; + uint16_t sel; + uint16_t rsvd; + }; + } fip, fdp; + uint32_t mxcsr; + uint32_t mxcsr_mask; + /* data registers follow here */ + }; + } fpu_sse; struct { u64 xstate_bv;