References: FATE#309893

# HG changeset patch
# User Mark Langsdorf <mark.langsdorf@amd.com>
# Date 1308051989 -3600
# Node ID 450f1d198e1e299b69489d513f591f0301cc5166
# Parent  864a3dd1d9b4664f1ece44c9eaf390969253b7a8
x86/amd: Eliminate cache flushing when entering C3 on select AMD processors

AMD Fam15h processors have a shared cache. It does not need
to be be flushed when entering C3 and doing so causes reduces
performance. Modify acpi_processor_power_init_bm_check to
prevent these processors from flushing when entering C3.

Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>

Index: xen-4.1.2-testing/xen/arch/x86/acpi/cpu_idle.c
===================================================================
--- xen-4.1.2-testing.orig/xen/arch/x86/acpi/cpu_idle.c
+++ xen-4.1.2-testing/xen/arch/x86/acpi/cpu_idle.c
@@ -710,7 +710,8 @@ static void acpi_processor_power_init_bm
     flags->bm_check = 0;
     if ( num_online_cpus() == 1 )
         flags->bm_check = 1;
-    else if ( c->x86_vendor == X86_VENDOR_INTEL )
+    else if ( (c->x86_vendor == X86_VENDOR_INTEL) ||
+              ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 0x15)) )
     {
         /*
          * Today all MP CPUs that support C3 share cache.