# HG changeset patch
# User Jan Beulich <jbeulich@novell.com>
# Date 1311081291 -3600
# Node ID fd97ca086df6808bffc6ecf3f79cebca64c60bc3
# Parent  4dc6a9ba90d60fdf0cc0898fc9a8fe84ae9030fc
x86: update Intel CPUID masking code to latest spec

..., which adds masking of the xsave feature leaf.

Also add back (and fix to actually make it do what it was supposed to
do from the beginning) the printing of what specific masking couldn't
be done in case the user requested something the hardware doesn't
support.

Signed-off-by: Jan Beulich <jbeulich@novell.com>

# HG changeset patch
# User Jan Beulich <jbeulich@novell.com>
# Date 1311255291 -3600
# Node ID 48f72b389b04cfa8d44924577a69ed59e48fbe77
# Parent  dd5eecf739d152fb16bd44897875ea878d4c9d59
x86: add change missing in c/s 23726:fd97ca086df6

The early "do we need to do anything" check needs adjustment, too.
Thanks to Haitao Shan for pointing this out.

Signed-off-by: Jan Beulich <jbeulich@novell.com>

--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -27,10 +27,15 @@ boolean_param("noserialnumber", disable_
 
 static bool_t __cpuinitdata use_xsave;
 boolean_param("xsave", use_xsave);
+
 unsigned int __devinitdata opt_cpuid_mask_ecx = ~0u;
 integer_param("cpuid_mask_ecx", opt_cpuid_mask_ecx);
 unsigned int __devinitdata opt_cpuid_mask_edx = ~0u;
 integer_param("cpuid_mask_edx", opt_cpuid_mask_edx);
+
+unsigned int __devinitdata opt_cpuid_mask_xsave_eax = ~0u;
+integer_param("cpuid_mask_xsave_eax", opt_cpuid_mask_xsave_eax);
+
 unsigned int __devinitdata opt_cpuid_mask_ext_ecx = ~0u;
 integer_param("cpuid_mask_ext_ecx", opt_cpuid_mask_ext_ecx);
 unsigned int __devinitdata opt_cpuid_mask_ext_edx = ~0u;
--- a/xen/arch/x86/cpu/cpu.h
+++ b/xen/arch/x86/cpu/cpu.h
@@ -22,6 +22,7 @@ struct cpu_dev {
 extern struct cpu_dev * cpu_devs [X86_VENDOR_NUM];
 
 extern unsigned int opt_cpuid_mask_ecx, opt_cpuid_mask_edx;
+extern unsigned int opt_cpuid_mask_xsave_eax;
 extern unsigned int opt_cpuid_mask_ext_ecx, opt_cpuid_mask_ext_edx;
 
 extern int get_model_name(struct cpuinfo_x86 *c);
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -35,10 +35,12 @@ struct movsl_mask movsl_mask __read_most
  */
 static void __devinit set_cpuidmask(const struct cpuinfo_x86 *c)
 {
+	u32 eax, edx;
 	const char *extra = "";
 
 	if (!~(opt_cpuid_mask_ecx & opt_cpuid_mask_edx &
-	       opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx))
+	       opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx &
+	       opt_cpuid_mask_xsave_eax))
 		return;
 
 	/* Only family 6 supports this feature  */
@@ -51,9 +53,12 @@ static void __devinit set_cpuidmask(cons
 		wrmsr(MSR_INTEL_CPUID_FEATURE_MASK,
 		      opt_cpuid_mask_ecx,
 		      opt_cpuid_mask_edx);
-		if (!~(opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx))
+		if (~(opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx))
+			extra = "extended ";
+		else if (~opt_cpuid_mask_xsave_eax)
+			extra = "xsave ";
+		else
 			return;
-		extra = "extended ";
 		break;
 /* 
  * CPU supports this feature if the processor signature meets the following:
@@ -73,11 +78,25 @@ static void __devinit set_cpuidmask(cons
 		wrmsr(MSR_INTEL_CPUID80000001_FEATURE_MASK,
 		      opt_cpuid_mask_ext_ecx,
 		      opt_cpuid_mask_ext_edx);
+		if (!~opt_cpuid_mask_xsave_eax)
+			return;
+		extra = "xsave ";
+		break;
+	case 0x2a:
+		wrmsr(MSR_INTEL_CPUID1_FEATURE_MASK_V2,
+		      opt_cpuid_mask_ecx,
+		      opt_cpuid_mask_edx);
+		rdmsr(MSR_INTEL_CPUIDD_01_FEATURE_MASK, eax, edx);
+		wrmsr(MSR_INTEL_CPUIDD_01_FEATURE_MASK,
+		      opt_cpuid_mask_xsave_eax, edx);
+		wrmsr(MSR_INTEL_CPUID80000001_FEATURE_MASK_V2,
+		      opt_cpuid_mask_ext_ecx,
+		      opt_cpuid_mask_ext_edx);
 		return;
 	}
 
-	printk(XENLOG_ERR "Cannot set CPU feature mask on CPU#%d\n",
-	       smp_processor_id());
+	printk(XENLOG_ERR "Cannot set CPU %sfeature mask on CPU#%d\n",
+	       extra, smp_processor_id());
 }
 
 void __devinit early_intel_workaround(struct cpuinfo_x86 *c)
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -161,6 +161,10 @@
 #define MSR_INTEL_CPUID1_FEATURE_MASK	0x00000130
 #define MSR_INTEL_CPUID80000001_FEATURE_MASK 0x00000131
 
+#define MSR_INTEL_CPUID1_FEATURE_MASK_V2        0x00000132
+#define MSR_INTEL_CPUID80000001_FEATURE_MASK_V2 0x00000133
+#define MSR_INTEL_CPUIDD_01_FEATURE_MASK        0x00000134
+
 /* MSRs & bits used for VMX enabling */
 #define MSR_IA32_VMX_BASIC                      0x480
 #define MSR_IA32_VMX_PINBASED_CTLS              0x481