1b78387def
- fate#309901: Add Xen support for SVM TSC scaling in AMD family 15h - fate#311951: Ivy Bridge: XEN support for Supervisor Mode Execution Protection (SMEP) 23437-amd-fam15-TSC-scaling.patch 23462-libxc-cpu-feature.patch 23481-x86-SMEP.patch 23504-x86-SMEP-hvm.patch 23505-x86-cpu-add-arg-check.patch 23508-vmx-proc-based-ctls-probe.patch 23510-hvm-cpuid-DRNG.patch 23511-amd-fam15-no-flush-for-C3.patch 23516-cpuid-ERMS.patch 23538-hvm-pio-emul-no-host-crash.patch 23539-hvm-cpuid-FSGSBASE.patch 23543-x86_64-maddr_to_virt-assertion.patch 23546-fucomip.patch - Fix libxc reentrancy issues 23383-libxc-rm-static-vars.patch OBS-URL: https://build.opensuse.org/package/show/Virtualization/xen?expand=0&rev=128
126 lines
4.4 KiB
Diff
126 lines
4.4 KiB
Diff
References: FATE#309901
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# HG changeset patch
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# User Wei Huang <wei.huang2@amd.com>
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# Date 1306569488 -3600
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# Node ID d7c755c25bb9d6ed77d64cb6736b6c4f339db1bf
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# Parent f6ce871e568949f5817470f6c7bab6ed1f8f6c13
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HVM/SVM: enable tsc scaling ratio for SVM
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Future AMD CPUs support TSC scaling. It allows guests to have a
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different TSC frequency from host system using this formula: guest_tsc
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= host_tsc * tsc_ratio + vmcb_offset. The tsc_ratio is a 64bit MSR
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contains a fixed-point number in 8.32 format (8 bits for integer part
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and 32bits for fractional part). For instance 0x00000003_80000000
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means tsc_ratio=3.5.
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This patch enables TSC scaling ratio for SVM. With it, guest VMs don't
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need take #VMEXIT to calculate a translated TSC value when it is
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running under TSC emulation mode. This can substancially reduce the
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rdtsc overhead.
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Signed-off-by: Wei Huang <wei.huang2@amd.com>
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--- a/xen/arch/x86/hvm/svm/svm.c
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+++ b/xen/arch/x86/hvm/svm/svm.c
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@@ -588,6 +588,22 @@ static void svm_set_segment_register(str
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static void svm_set_tsc_offset(struct vcpu *v, u64 offset)
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{
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struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
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+ struct domain *d = v->domain;
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+
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+ /* Re-adjust the offset value when TSC_RATIO is available */
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+ if ( cpu_has_tsc_ratio && d->arch.vtsc )
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+ {
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+ uint64_t host_tsc, guest_tsc;
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+
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+ rdtscll(host_tsc);
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+ guest_tsc = hvm_get_guest_tsc(v);
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+
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+ /* calculate hi,lo parts in 64bits to prevent overflow */
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+ offset = (((host_tsc >> 32) * d->arch.tsc_khz / cpu_khz) << 32) +
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+ (host_tsc & 0xffffffffULL) * d->arch.tsc_khz / cpu_khz;
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+ offset = guest_tsc - offset;
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+ }
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+
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vmcb_set_tsc_offset(vmcb, offset);
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}
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@@ -638,6 +654,19 @@ static void svm_init_hypercall_page(stru
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*(u16 *)(hypercall_page + (__HYPERVISOR_iret * 32)) = 0x0b0f; /* ud2 */
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}
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+static inline void svm_tsc_ratio_save(struct vcpu *v)
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+{
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+ /* Other vcpus might not have vtsc enabled. So disable TSC_RATIO here. */
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+ if ( cpu_has_tsc_ratio && v->domain->arch.vtsc )
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+ wrmsrl(MSR_AMD64_TSC_RATIO, DEFAULT_TSC_RATIO);
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+}
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+
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+static inline void svm_tsc_ratio_load(struct vcpu *v)
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+{
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+ if ( cpu_has_tsc_ratio && v->domain->arch.vtsc )
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+ wrmsrl(MSR_AMD64_TSC_RATIO, vcpu_tsc_ratio(v));
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+}
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+
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static void svm_ctxt_switch_from(struct vcpu *v)
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{
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int cpu = smp_processor_id();
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@@ -646,6 +675,7 @@ static void svm_ctxt_switch_from(struct
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svm_save_dr(v);
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vpmu_save(v);
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+ svm_tsc_ratio_save(v);
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svm_sync_vmcb(v);
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svm_vmload(per_cpu(root_vmcb, cpu));
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@@ -689,6 +719,7 @@ static void svm_ctxt_switch_to(struct vc
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svm_vmload(vmcb);
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vmcb->cleanbits.bytes = 0;
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vpmu_load(v);
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+ svm_tsc_ratio_load(v);
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if ( cpu_has_rdtscp )
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wrmsrl(MSR_TSC_AUX, hvm_msr_tsc_aux(v));
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--- a/xen/arch/x86/hvm/svm/vmcb.c
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+++ b/xen/arch/x86/hvm/svm/vmcb.c
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@@ -165,7 +165,9 @@ static int construct_vmcb(struct vcpu *v
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/* TSC. */
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vmcb->_tsc_offset = 0;
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- if ( v->domain->arch.vtsc )
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+
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+ /* Don't need to intercept RDTSC if CPU supports TSC rate scaling */
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+ if ( v->domain->arch.vtsc && !cpu_has_tsc_ratio )
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{
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vmcb->_general1_intercepts |= GENERAL1_INTERCEPT_RDTSC;
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vmcb->_general2_intercepts |= GENERAL2_INTERCEPT_RDTSCP;
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--- a/xen/include/asm-x86/hvm/svm/svm.h
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+++ b/xen/include/asm-x86/hvm/svm/svm.h
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@@ -91,5 +91,13 @@ extern u32 svm_feature_flags;
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#define cpu_has_svm_cleanbits cpu_has_svm_feature(SVM_FEATURE_VMCBCLEAN)
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#define cpu_has_svm_decode cpu_has_svm_feature(SVM_FEATURE_DECODEASSISTS)
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#define cpu_has_pause_filter cpu_has_svm_feature(SVM_FEATURE_PAUSEFILTER)
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+#define cpu_has_tsc_ratio cpu_has_svm_feature(SVM_FEATURE_TSCRATEMSR)
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+
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+/* TSC rate */
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+#define DEFAULT_TSC_RATIO 0x0000000100000000ULL
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+#define TSC_RATIO_RSVD_BITS 0xffffff0000000000ULL
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+#define TSC_RATIO(g_khz, h_khz) ( (((u64)(g_khz)<<32)/(u64)(h_khz)) & \
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+ ~TSC_RATIO_RSVD_BITS )
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+#define vcpu_tsc_ratio(v) TSC_RATIO((v)->domain->arch.tsc_khz, cpu_khz)
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#endif /* __ASM_X86_HVM_SVM_H__ */
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--- a/xen/include/asm-x86/msr-index.h
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+++ b/xen/include/asm-x86/msr-index.h
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@@ -266,6 +266,9 @@
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#define MSR_AMD_PATCHLEVEL 0x0000008b
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#define MSR_AMD_PATCHLOADER 0xc0010020
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+/* AMD TSC RATE MSR */
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+#define MSR_AMD64_TSC_RATIO 0xc0000104
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+
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/* AMD OS Visible Workaround MSRs */
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#define MSR_AMD_OSVW_ID_LENGTH 0xc0010140
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#define MSR_AMD_OSVW_STATUS 0xc0010141
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