ed105f0f54
topology - fate#311376: EFI support in SP2 - fate#311529: Native UEFI booting under Xen (installation) 23074-pfn.h.patch 23571-vtd-fault-verbosity.patch 23574-x86-dom0-compressed-ELF.patch 23575-x86-DMI.patch 23610-x86-topology-info.patch 23611-amd-fam15-topology.patch 23613-EFI-headers.patch 23614-x86_64-EFI-boot.patch 23615-x86_64-EFI-runtime.patch 23616-x86_64-EFI-MPS.patch - Mark xen-scsi.ko supported (bnc#582265, fate#309459). - fate#310308: Hypervisor assisted watchdog driver ioemu-watchdog-support.patch ioemu-watchdog-linkage.patch ioemu-watchdog-ib700-timer.patch tools-watchdog-support.patch - bnc#702025 - VUL-0: xen: VT-d (PCI passthrough) MSI trap injection (CVE-2011-1898) Fixed in Xen version 4.1.1 - fate#310956: Support Direct Kernel Boot for FV guests kernel-boot-hvm.patch OBS-URL: https://build.opensuse.org/package/show/Virtualization/xen?expand=0&rev=130
169 lines
5.8 KiB
Diff
169 lines
5.8 KiB
Diff
References: fate#309894
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# HG changeset patch
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# User Wei Huang <wei.huang2@amd.com>
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# Date 1309248833 -3600
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# Node ID c2c12b2dafb5b1d3bfcc4c05a60ca4f9051c90e7
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# Parent 87c2013c2aa2d4874f892507e6cc7b52219a3acf
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x86: AMD core-pair topology detection code
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This patch is to support core-pair topology introduced by AMD CPUs,
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which introduces a new concept of [core, compute unit]. There is a new
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feature bit for topology extension in CPUID:0x80000001. Also a new
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CPUID 0x8000001E is introduced for CPU topology enumeration. This
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patch collects the sibling information from the new CPUID and will be
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stored in the sibling map in Xen hypervisor.
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Signed-off-by: Wei Huang <wei.huang2@amd.com>
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--- a/xen/arch/x86/cpu/amd.c
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+++ b/xen/arch/x86/cpu/amd.c
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@@ -344,6 +344,49 @@ static void check_syscfg_dram_mod_en(voi
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wrmsrl(MSR_K8_SYSCFG, syscfg);
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}
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+static void __devinit amd_get_topology(struct cpuinfo_x86 *c)
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+{
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+#ifdef CONFIG_X86_HT
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+ int cpu;
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+ unsigned bits;
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+
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+ if (c->x86_max_cores <= 1)
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+ return;
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+ /*
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+ * On a AMD multi core setup the lower bits of the APIC id
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+ * distingush the cores.
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+ */
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+ cpu = smp_processor_id();
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+ bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;
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+
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+ if (bits == 0) {
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+ while ((1 << bits) < c->x86_max_cores)
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+ bits++;
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+ }
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+
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+ /* Low order bits define the core id */
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+ c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
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+ /* Convert local APIC ID into the socket ID */
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+ c->phys_proc_id >>= bits;
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+ /* Collect compute unit ID if available */
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+ if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
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+ u32 eax, ebx, ecx, edx;
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+
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+ cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
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+ c->compute_unit_id = ebx & 0xFF;
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+ c->x86_num_siblings = ((ebx >> 8) & 0x3) + 1;
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+ }
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+
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+ if (opt_cpu_info)
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+ printk("CPU %d(%d) -> Processor %d, %s %d\n",
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+ cpu, c->x86_max_cores, c->phys_proc_id,
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+ cpu_has(c, X86_FEATURE_TOPOEXT) ? "Compute Unit" :
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+ "Core",
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+ cpu_has(c, X86_FEATURE_TOPOEXT) ? c->compute_unit_id :
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+ c->cpu_core_id);
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+#endif
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+}
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+
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static void __devinit init_amd(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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@@ -566,26 +609,7 @@ static void __devinit init_amd(struct cp
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}
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}
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-#ifdef CONFIG_X86_HT
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- /*
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- * On a AMD multi core setup the lower bits of the APIC id
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- * distingush the cores.
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- */
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- if (c->x86_max_cores > 1) {
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- int cpu = smp_processor_id();
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- unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;
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-
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- if (bits == 0) {
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- while ((1 << bits) < c->x86_max_cores)
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- bits++;
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- }
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- c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
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- c->phys_proc_id >>= bits;
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- if (opt_cpu_info)
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- printk("CPU %d(%d) -> Core %d\n",
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- cpu, c->x86_max_cores, c->cpu_core_id);
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- }
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-#endif
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+ amd_get_topology(c);
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/* Pointless to use MWAIT on Family10 as it does not deep sleep. */
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if (c->x86 >= 0x10 && !force_mwait)
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--- a/xen/arch/x86/cpu/common.c
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+++ b/xen/arch/x86/cpu/common.c
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@@ -364,6 +364,7 @@ void __cpuinit identify_cpu(struct cpuin
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c->x86_clflush_size = 0;
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c->phys_proc_id = BAD_APICID;
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c->cpu_core_id = BAD_APICID;
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+ c->compute_unit_id = BAD_APICID;
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memset(&c->x86_capability, 0, sizeof c->x86_capability);
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if (!have_cpuid_p()) {
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--- a/xen/arch/x86/smpboot.c
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+++ b/xen/arch/x86/smpboot.c
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@@ -241,6 +241,14 @@ static int booting_cpu;
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/* CPUs for which sibling maps can be computed. */
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static cpumask_t cpu_sibling_setup_map;
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+static void link_thread_siblings(int cpu1, int cpu2)
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+{
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+ cpu_set(cpu1, per_cpu(cpu_sibling_map, cpu2));
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+ cpu_set(cpu2, per_cpu(cpu_sibling_map, cpu1));
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+ cpu_set(cpu1, per_cpu(cpu_core_map, cpu2));
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+ cpu_set(cpu2, per_cpu(cpu_core_map, cpu1));
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+}
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+
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static void set_cpu_sibling_map(int cpu)
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{
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int i;
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@@ -252,13 +260,13 @@ static void set_cpu_sibling_map(int cpu)
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{
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for_each_cpu_mask ( i, cpu_sibling_setup_map )
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{
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- if ( (c[cpu].phys_proc_id == c[i].phys_proc_id) &&
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- (c[cpu].cpu_core_id == c[i].cpu_core_id) )
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- {
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- cpu_set(i, per_cpu(cpu_sibling_map, cpu));
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- cpu_set(cpu, per_cpu(cpu_sibling_map, i));
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- cpu_set(i, per_cpu(cpu_core_map, cpu));
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- cpu_set(cpu, per_cpu(cpu_core_map, i));
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+ if ( cpu_has(c, X86_FEATURE_TOPOEXT) ) {
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+ if ( (c[cpu].phys_proc_id == c[i].phys_proc_id) &&
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+ (c[cpu].compute_unit_id == c[i].compute_unit_id) )
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+ link_thread_siblings(cpu, i);
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+ } else if ( (c[cpu].phys_proc_id == c[i].phys_proc_id) &&
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+ (c[cpu].cpu_core_id == c[i].cpu_core_id) ) {
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+ link_thread_siblings(cpu, i);
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}
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}
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}
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@@ -839,6 +847,7 @@ remove_siblinginfo(int cpu)
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cpus_clear(per_cpu(cpu_core_map, cpu));
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c[cpu].phys_proc_id = BAD_APICID;
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c[cpu].cpu_core_id = BAD_APICID;
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+ c[cpu].compute_unit_id = BAD_APICID;
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cpu_clear(cpu, cpu_sibling_setup_map);
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}
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--- a/xen/include/asm-x86/processor.h
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+++ b/xen/include/asm-x86/processor.h
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@@ -175,9 +175,10 @@ struct cpuinfo_x86 {
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__u32 x86_max_cores; /* cpuid returned max cores value */
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__u32 booted_cores; /* number of cores as seen by OS */
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__u32 x86_num_siblings; /* cpuid logical cpus per chip value */
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+ __u32 apicid;
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int phys_proc_id; /* package ID of each logical CPU */
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int cpu_core_id; /* core ID of each logical CPU*/
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- __u32 apicid;
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+ int compute_unit_id; /* AMD compute unit ID of each logical CPU */
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unsigned short x86_clflush_size;
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} __cacheline_aligned;
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