8724a18868
config handling stack overflow 55a62eb0-xl-correct-handling-of-extra_config-in-main_cpupoolcreate.patch - bsc#907514 - Bus fatal error & sles12 sudden reboot has been observed - bsc#910258 - SLES12 Xen host crashes with FATAL NMI after shutdown of guest with VT-d NIC - bsc#918984 - Bus fatal error & sles11-SP4 sudden reboot has been observed - bsc#923967 - Partner-L3: Bus fatal error & sles11-SP3 sudden reboot has been observed 552d293b-x86-vMSI-X-honor-all-mask-requests.patch 552d2966-x86-vMSI-X-add-valid-bits-for-read-acceleration.patch 5576f143-x86-adjust-PV-I-O-emulation-functions-types.patch 55795a52-x86-vMSI-X-support-qword-MMIO-access.patch 5583d9c5-x86-MSI-X-cleanup.patch 5583da09-x86-MSI-track-host-and-guest-masking-separately.patch 55b0a218-x86-PCI-CFG-write-intercept.patch 55b0a255-x86-MSI-X-maskall.patch 55b0a283-x86-MSI-X-teardown.patch 55b0a2ab-x86-MSI-X-enable.patch 55b0a2db-x86-MSI-track-guest-masking.patch - Upstream patches from Jan 552d0f49-x86-traps-identify-the-vcpu-in-context-when-dumping-regs.patch 559bc633-x86-cpupool-clear-proper-cpu_valid-bit-on-CPU-teardown.patch 559bc64e-credit1-properly-deal-with-CPUs-not-in-any-pool.patch 559bc87f-x86-hvmloader-avoid-data-corruption-with-xenstore-rw.patch 55a66a1e-make-rangeset_report_ranges-report-all-ranges.patch 55a77e4f-dmar-device-scope-mem-leak-fix.patch OBS-URL: https://build.opensuse.org/package/show/Virtualization/xen?expand=0&rev=373
65 lines
2.8 KiB
Diff
65 lines
2.8 KiB
Diff
# Commit 890674d13feb4a270aa112ca452dcf62fdd53f34
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# Date 2015-05-13 15:01:25 +0200
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# Author David Vrabel <david.vrabel@citrix.com>
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# Committer Jan Beulich <jbeulich@suse.com>
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arm: provide add_sized()
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add_sized(ptr, inc) adds inc to the value at ptr using only the correct
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size of loads and stores for the type of *ptr. The add is /not/ atomic.
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This is needed for ticket locks to ensure the increment of the head ticket
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does not affect the tail ticket.
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Signed-off-by: David Vrabel <david.vrabel@citrix.com>
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Acked-by: Ian Campbell <ian.campbell@citrix.com>
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--- a/xen/include/asm-arm/atomic.h
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+++ b/xen/include/asm-arm/atomic.h
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@@ -23,6 +23,17 @@ static inline void name(volatile type *a
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: reg (val)); \
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}
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+#define build_add_sized(name, size, width, type, reg) \
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+static inline void name(volatile type *addr, type val) \
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+{ \
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+ type t; \
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+ asm volatile("ldr" size " %"width"1,%0\n" \
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+ "add %"width"1,%"width"1,%"width"2\n" \
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+ "str" size " %"width"1,%0" \
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+ : "=m" (*(volatile type *)addr), "=r" (t) \
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+ : reg (val)); \
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+}
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+
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#if defined (CONFIG_ARM_32)
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#define BYTE ""
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#define WORD ""
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@@ -46,6 +57,10 @@ build_atomic_read(read_u64_atomic, "x",
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build_atomic_write(write_u64_atomic, "x", uint64_t, "r")
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#endif
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+build_add_sized(add_u8_sized, "b", BYTE, uint8_t, "ri")
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+build_add_sized(add_u16_sized, "h", WORD, uint16_t, "ri")
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+build_add_sized(add_u32_sized, "", WORD, uint32_t, "ri")
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+
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void __bad_atomic_size(void);
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#define read_atomic(p) ({ \
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@@ -70,6 +85,17 @@ void __bad_atomic_size(void);
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__x; \
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})
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+#define add_sized(p, x) ({ \
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+ typeof(*(p)) __x = (x); \
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+ switch ( sizeof(*(p)) ) \
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+ { \
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+ case 1: add_u8_sized((uint8_t *)(p), __x); break; \
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+ case 2: add_u16_sized((uint16_t *)(p), __x); break; \
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+ case 4: add_u32_sized((uint32_t *)(p), __x); break; \
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+ default: __bad_atomic_size(); break; \
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+ } \
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+})
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+
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/*
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* NB. I've pushed the volatile qualifier into the operations. This allows
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* fast accessors such as _atomic_read() and _atomic_set() which don't give
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