3c2f525a91
libxl.pvscsi.patch - bnc#875668 - VUL-0: CVE-2014-3124: xen: XSA-92: HVMOP_set_mem_type allows invalid P2M entries to be created 535fa503-x86-HVM-restrict-HVMOP_set_mem_type.patch (replaces xsa92.patch) - bnc#826717 - VUL-0: CVE-2013-3495: XSA-59: xen: Intel VT-d Interrupt Remapping engines can be evaded by native NMI interrupts 535a34eb-VT-d-suppress-UR-signaling-for-server-chipsets.patch 535a3516-VT-d-suppress-UR-signaling-for-desktop-chipsets.patch - Upstream patches from Jan 535a354b-passthrough-allow-to-suppress-SERR-and-PERR-signaling.patch 535e31bc-x86-HVM-correct-the-SMEP-logic-for-HVM_CR0_GUEST_RESERVED_BITS.patch 53636978-hvm_set_ioreq_page-releases-wrong-page-in-error-path.patch 53636ebf-x86-fix-guest-CPUID-handling.patch - Fix pygrub to handle VM with no grub/menu.lst file. - Don't use /var/run/xend/boot for temporary boot directory pygrub-boot-legacy-sles.patch OBS-URL: https://build.opensuse.org/package/show/Virtualization/xen?expand=0&rev=314
188 lines
5.8 KiB
Diff
188 lines
5.8 KiB
Diff
# Commit 1a2a390a560e8319a6be98c7ab6cfaebd230f67e
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# Date 2014-04-25 12:13:31 +0200
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# Author Jan Beulich <jbeulich@suse.com>
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# Committer Jan Beulich <jbeulich@suse.com>
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passthrough: allow to suppress SERR and PERR signaling altogether
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This is just to have a workaround at hand in case other chipsets (not
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covered by the previous two patches) also have similar issues.
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Signed-off-by: Jan Beulich <jbeulich@suse.com>
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Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
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Acked-by: Don Dugger <donald.d.dugger@intel.com>
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Acked-by: Tim Deegan <tim@xen.org>
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Acked-by: Xiantao Zhang <xiantao.zhang@intel.com>
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--- a/docs/misc/xen-command-line.markdown
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+++ b/docs/misc/xen-command-line.markdown
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@@ -772,6 +772,14 @@ Defaults to booting secondary processors
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Default: `on`
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+### pci
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+> `= {no-}serr | {no-}perr`
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+
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+Disable signaling of SERR (system errors) and/or PERR (parity errors)
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+on all PCI devices.
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+
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+Default: Signaling left as set by firmware.
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+
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### pci-phantom
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> `=[<seg>:]<bus>:<device>,<stride>`
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--- a/xen/drivers/passthrough/pci.c
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+++ b/xen/drivers/passthrough/pci.c
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@@ -154,6 +154,115 @@ static void __init parse_phantom_dev(cha
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}
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custom_param("pci-phantom", parse_phantom_dev);
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+static u16 __read_mostly command_mask;
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+static u16 __read_mostly bridge_ctl_mask;
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+
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+/*
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+ * The 'pci' parameter controls certain PCI device aspects.
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+ * Optional comma separated value may contain:
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+ *
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+ * serr don't suppress system errors (default)
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+ * no-serr suppress system errors
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+ * perr don't suppress parity errors (default)
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+ * no-perr suppress parity errors
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+ */
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+static void __init parse_pci_param(char *s)
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+{
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+ char *ss;
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+
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+ do {
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+ bool_t on = !!strncmp(s, "no-", 3);
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+ u16 cmd_mask = 0, brctl_mask = 0;
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+
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+ if ( !on )
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+ s += 3;
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+
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+ ss = strchr(s, ',');
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+ if ( ss )
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+ *ss = '\0';
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+
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+ if ( !strcmp(s, "serr") )
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+ {
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+ cmd_mask = PCI_COMMAND_SERR;
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+ brctl_mask = PCI_BRIDGE_CTL_SERR | PCI_BRIDGE_CTL_DTMR_SERR;
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+ }
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+ else if ( !strcmp(s, "perr") )
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+ {
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+ cmd_mask = PCI_COMMAND_PARITY;
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+ brctl_mask = PCI_BRIDGE_CTL_PARITY;
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+ }
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+
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+ if ( on )
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+ {
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+ command_mask &= ~cmd_mask;
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+ bridge_ctl_mask &= ~brctl_mask;
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+ }
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+ else
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+ {
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+ command_mask |= cmd_mask;
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+ bridge_ctl_mask |= brctl_mask;
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+ }
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+
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+ s = ss + 1;
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+ } while ( ss );
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+}
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+custom_param("pci", parse_pci_param);
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+
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+static void check_pdev(const struct pci_dev *pdev)
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+{
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+#define PCI_STATUS_CHECK \
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+ (PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | \
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+ PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | \
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+ PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY)
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+ u16 seg = pdev->seg;
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+ u8 bus = pdev->bus;
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+ u8 dev = PCI_SLOT(pdev->devfn);
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+ u8 func = PCI_FUNC(pdev->devfn);
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+ u16 val;
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+
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+ if ( command_mask )
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+ {
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+ val = pci_conf_read16(seg, bus, dev, func, PCI_COMMAND);
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+ if ( val & command_mask )
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+ pci_conf_write16(seg, bus, dev, func, PCI_COMMAND,
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+ val & ~command_mask);
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+ val = pci_conf_read16(seg, bus, dev, func, PCI_STATUS);
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+ if ( val & PCI_STATUS_CHECK )
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+ {
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+ printk(XENLOG_INFO "%04x:%02x:%02x.%u status %04x -> %04x\n",
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+ seg, bus, dev, func, val, val & ~PCI_STATUS_CHECK);
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+ pci_conf_write16(seg, bus, dev, func, PCI_STATUS,
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+ val & PCI_STATUS_CHECK);
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+ }
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+ }
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+
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+ switch ( pci_conf_read8(seg, bus, dev, func, PCI_HEADER_TYPE) & 0x7f )
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+ {
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+ case PCI_HEADER_TYPE_BRIDGE:
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+ if ( !bridge_ctl_mask )
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+ break;
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+ val = pci_conf_read16(seg, bus, dev, func, PCI_BRIDGE_CONTROL);
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+ if ( val & bridge_ctl_mask )
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+ pci_conf_write16(seg, bus, dev, func, PCI_BRIDGE_CONTROL,
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+ val & ~bridge_ctl_mask);
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+ val = pci_conf_read16(seg, bus, dev, func, PCI_SEC_STATUS);
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+ if ( val & PCI_STATUS_CHECK )
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+ {
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+ printk(XENLOG_INFO
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+ "%04x:%02x:%02x.%u secondary status %04x -> %04x\n",
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+ seg, bus, dev, func, val, val & ~PCI_STATUS_CHECK);
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+ pci_conf_write16(seg, bus, dev, func, PCI_SEC_STATUS,
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+ val & PCI_STATUS_CHECK);
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+ }
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+ break;
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+
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+ case PCI_HEADER_TYPE_CARDBUS:
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+ /* TODO */
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+ break;
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+ }
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+#undef PCI_STATUS_CHECK
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+}
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+
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static struct pci_dev *alloc_pdev(struct pci_seg *pseg, u8 bus, u8 devfn)
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{
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struct pci_dev *pdev;
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@@ -252,6 +361,8 @@ static struct pci_dev *alloc_pdev(struct
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break;
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}
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+ check_pdev(pdev);
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+
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return pdev;
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}
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@@ -566,6 +677,8 @@ int pci_add_device(u16 seg, u8 bus, u8 d
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seg, bus, slot, func, ctrl);
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}
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+ check_pdev(pdev);
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+
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ret = 0;
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if ( !pdev->domain )
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{
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--- a/xen/include/xen/pci_regs.h
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+++ b/xen/include/xen/pci_regs.h
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@@ -125,7 +125,7 @@
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#define PCI_IO_RANGE_TYPE_16 0x00
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#define PCI_IO_RANGE_TYPE_32 0x01
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#define PCI_IO_RANGE_MASK (~0x0fUL)
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-#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
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+#define PCI_SEC_STATUS 0x1e /* Secondary status register */
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#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
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#define PCI_MEMORY_LIMIT 0x22
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#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
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@@ -152,6 +152,7 @@
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#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
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#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
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#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
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+#define PCI_BRIDGE_CTL_DTMR_SERR 0x800 /* SERR upon discard timer expiry */
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/* Header type 2 (CardBus bridges) */
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#define PCI_CB_CAPABILITY_LIST 0x14
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