42c5e53074
capslock_enable.patch - bnc#607219 - AMD Erratum 383 workaround for Xen 21408-amd-erratum-383.patch OBS-URL: https://build.opensuse.org/package/show/Virtualization/xen?expand=0&rev=51
142 lines
4.3 KiB
Diff
142 lines
4.3 KiB
Diff
# HG changeset patch
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# User Keir Fraser <keir.fraser@citrix.com>
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# Date 1274178085 -3600
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# Node ID f40acba36be886e4b4e87afeacf39688f316dfe4
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# Parent e4028345ad48c442eb55b7bc08afdf1aede0aa2e
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svm: Fix for AMD erratum 383 on Family 10h CPUs
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This patches implements the workaround of AMD erratum 383 on family
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10h CPUs. It destroys the guest VM when a MC error with a special
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pattern is detected. Without this patch, a guest VM failure can
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potentially crash Xen hypervisor and the whole system. The erratum
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will be published in next version of guide.
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Signed-off-by: Wei Huang <wei.huang2@amd.com>
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Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
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Signed-off-by: Christoph Egger <christoph.egger@amd.com>
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Index: xen-4.0.0-testing/xen/arch/x86/hvm/svm/svm.c
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===================================================================
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--- xen-4.0.0-testing.orig/xen/arch/x86/hvm/svm/svm.c
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+++ xen-4.0.0-testing/xen/arch/x86/hvm/svm/svm.c
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@@ -72,6 +72,8 @@ static void *hsa[NR_CPUS] __read_mostly;
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/* vmcb used for extended host state */
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static void *root_vmcb[NR_CPUS] __read_mostly;
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+static bool_t amd_erratum383_found __read_mostly;
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+
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static void inline __update_guest_eip(
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struct cpu_user_regs *regs, unsigned int inst_len)
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{
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@@ -822,6 +824,20 @@ static int svm_cpu_prepare(unsigned int
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return 0;
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}
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+static void svm_init_erratum_383(struct cpuinfo_x86 *c)
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+{
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+ uint64_t msr_content;
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+
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+ /* only family 10h is affected */
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+ if ( c->x86 != 0x10 )
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+ return;
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+
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+ rdmsrl(MSR_AMD64_DC_CFG, msr_content);
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+ wrmsrl(MSR_AMD64_DC_CFG, msr_content | (1ULL << 47));
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+
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+ amd_erratum383_found = 1;
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+}
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+
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static int svm_cpu_up(struct cpuinfo_x86 *c)
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{
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u32 eax, edx, phys_hsa_lo, phys_hsa_hi;
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@@ -847,6 +863,9 @@ static int svm_cpu_up(struct cpuinfo_x86
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phys_hsa_hi = (u32)(phys_hsa >> 32);
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wrmsr(MSR_K8_VM_HSAVE_PA, phys_hsa_lo, phys_hsa_hi);
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+ /* check for erratum 383 */
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+ svm_init_erratum_383(c);
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+
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/* Initialize core's ASID handling. */
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svm_asid_init(c);
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@@ -1244,6 +1263,47 @@ static void svm_vmexit_ud_intercept(stru
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}
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}
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+extern unsigned int nr_mce_banks; /* from mce.h */
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+
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+static int svm_is_erratum_383(struct cpu_user_regs *regs)
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+{
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+ uint64_t msr_content;
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+ uint32_t i;
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+ struct vcpu *v = current;
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+
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+ if ( !amd_erratum383_found )
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+ return 0;
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+
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+ rdmsrl(MSR_IA32_MC0_STATUS, msr_content);
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+ /* Bit 62 may or may not be set for this mce */
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+ msr_content &= ~(1ULL << 62);
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+
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+ if ( msr_content != 0xb600000000010015ULL )
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+ return 0;
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+
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+ /* Clear MCi_STATUS registers */
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+ for (i = 0; i < nr_mce_banks; i++)
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+ wrmsrl(MSR_IA32_MCx_STATUS(i), 0ULL);
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+
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+ rdmsrl(MSR_IA32_MCG_STATUS, msr_content);
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+ wrmsrl(MSR_IA32_MCG_STATUS, msr_content & ~(1ULL << 2));
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+
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+ /* flush TLB */
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+ flush_tlb_mask(&v->domain->domain_dirty_cpumask);
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+
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+ return 1;
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+}
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+
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+static void svm_vmexit_mce_intercept(
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+ struct vcpu *v, struct cpu_user_regs *regs)
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+{
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+ if ( svm_is_erratum_383(regs) )
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+ {
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+ gdprintk(XENLOG_ERR, "SVM hits AMD erratum 383\n");
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+ domain_crash(v->domain);
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+ }
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+}
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+
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static void wbinvd_ipi(void *info)
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{
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wbinvd();
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@@ -1432,6 +1492,7 @@ asmlinkage void svm_vmexit_handler(struc
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/* Asynchronous event, handled when we STGI'd after the VMEXIT. */
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case VMEXIT_EXCEPTION_MC:
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HVMTRACE_0D(MCE);
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+ svm_vmexit_mce_intercept(v, regs);
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break;
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case VMEXIT_VINTR:
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Index: xen-4.0.0-testing/xen/include/asm-x86/msr-index.h
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===================================================================
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--- xen-4.0.0-testing.orig/xen/include/asm-x86/msr-index.h
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+++ xen-4.0.0-testing/xen/include/asm-x86/msr-index.h
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@@ -146,6 +146,11 @@
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#define MSR_IA32_MC8_ADDR 0x00000422
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#define MSR_IA32_MC8_MISC 0x00000423
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+#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
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+#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
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+#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
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+#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
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+
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#define MSR_P6_PERFCTR0 0x000000c1
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#define MSR_P6_PERFCTR1 0x000000c2
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#define MSR_P6_EVNTSEL0 0x00000186
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@@ -224,6 +229,7 @@
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/* AMD64 MSRs */
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#define MSR_AMD64_NB_CFG 0xc001001f
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+#define MSR_AMD64_DC_CFG 0xc0011022
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#define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT 46
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/* AMD Family10h machine check MSRs */
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