53 lines
1.9 KiB
Diff
53 lines
1.9 KiB
Diff
# HG changeset patch
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# User Jan Beulich <jbeulich@suse.com>
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# Date 1354697534 -3600
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# Node ID 670b07e8d7382229639af0d1df30071e6c1ebb19
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# Parent bc624b00d6d601f00a53c2f7502a82dcef60f882
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IOMMU/ATS: fix maximum queue depth calculation
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The capabilities register field is a 5-bit value, and the 5 bits all
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being zero actually means 32 entries.
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Under the assumption that amd_iommu_flush_iotlb() really just tried
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to correct for the miscalculation above when adding 32 to the value,
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that adjustment is also being removed.
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Signed-off-by: Jan Beulich <jbeulich@suse.com>
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Acked-by Xiantao Zhang <xiantao.zhang@intel.com>
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Acked-by: Wei Huang <wei.huang2@amd.com>
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--- a/xen/drivers/passthrough/amd/iommu_cmd.c
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+++ b/xen/drivers/passthrough/amd/iommu_cmd.c
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@@ -321,7 +321,7 @@ void amd_iommu_flush_iotlb(struct pci_de
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req_id = get_dma_requestor_id(iommu->seg, bdf);
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queueid = req_id;
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- maxpend = (ats_pdev->ats_queue_depth + 32) & 0xff;
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+ maxpend = ats_pdev->ats_queue_depth & 0xff;
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/* send INVALIDATE_IOTLB_PAGES command */
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spin_lock_irqsave(&iommu->lock, flags);
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--- a/xen/drivers/passthrough/ats.h
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+++ b/xen/drivers/passthrough/ats.h
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@@ -30,7 +30,7 @@ struct pci_ats_dev {
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#define ATS_REG_CAP 4
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#define ATS_REG_CTL 6
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-#define ATS_QUEUE_DEPTH_MASK 0xF
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+#define ATS_QUEUE_DEPTH_MASK 0x1f
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#define ATS_ENABLE (1<<15)
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extern struct list_head ats_devices;
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--- a/xen/drivers/passthrough/x86/ats.c
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+++ b/xen/drivers/passthrough/x86/ats.c
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@@ -93,7 +93,8 @@ int enable_ats_device(int seg, int bus,
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pdev->devfn = devfn;
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value = pci_conf_read16(seg, bus, PCI_SLOT(devfn),
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PCI_FUNC(devfn), pos + ATS_REG_CAP);
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- pdev->ats_queue_depth = value & ATS_QUEUE_DEPTH_MASK;
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+ pdev->ats_queue_depth = value & ATS_QUEUE_DEPTH_MASK ?:
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+ ATS_QUEUE_DEPTH_MASK + 1;
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list_add(&pdev->list, &ats_devices);
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}
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