3ab5d775a1
OBS-URL: https://build.opensuse.org/package/show/Virtualization/xen?expand=0&rev=4293852b248e1f267831a4305b1c05a9
26 lines
904 B
Diff
26 lines
904 B
Diff
# HG changeset patch
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# User Keir Fraser <keir.fraser@citrix.com>
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# Date 1277110750 -3600
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# Node ID 31708477f0a92be70a940d1c8ff1aa721051bba8
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# Parent 46a4c936b77e483971d2b3eb0b544c61700f824a
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vmx: Fix bug in VMX VPMU fixed function PMC offset
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This is a minor fix to the calculation of bit-width of fixed function
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perfmon counters in Intel processors. Bits 5-12 of edx register
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should be calculated as (edx & 0x1fe0) >>5 instead of using 0x1f70.
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From: "John, Jaiber J" <jaiber.j.john@intel.com>
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Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
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--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
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+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
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@@ -82,7 +82,7 @@ static int core2_get_bitwidth_fix_count(
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{
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u32 eax, ebx, ecx, edx;
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cpuid(0xa, &eax, &ebx, &ecx, &edx);
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- return ((edx & 0x1f70) >> 5);
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+ return ((edx & 0x1fe0) >> 5);
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}
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static int is_core2_vpmu_msr(u32 msr_index, int *type, int *index)
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