7f6bd728fd
xend-cpuid.patch - Rename 2XXXX-vif-bridge.patch -> vif-bridge-tap-fix.patch - bnc#747331 - XEN: standard "newburn" kernel QA stress test on guest (+ smartd on Dom0?) freezes the guest 24883-x86-guest-walk-not-present.patch - bnc#745367 - MCE bank handling during migration 24781-x86-vmce-mcg_ctl.patch 24886-x86-vmce-mcg_ctl-default.patch 24887-x86-vmce-sr.patch - bnc#744771 - L3: VM with passed through PCI card fails to reboot under dom0 load 24888-pci-release-devices.patch - Upstream patches from Jan 24517-VT-d-fault-softirq.patch 24527-AMD-Vi-fault-softirq.patch 24535-x86-vMSI-misc.patch 24615-VESA-lfb-flush.patch 24690-x86-PCI-SERR-no-deadlock.patch 24701-gnttab-map-grant-ref-recovery.patch 24742-gnttab-misc.patch 24780-x86-paging-use-clear_guest.patch 24805-x86-MSI-X-dom0-ro.patch ioemu-9869-MSI-X-init.patch ioemu-9873-MSI-X-fix-unregister_iomem.patch - bnc#745005 - Update vif configuration examples in xmexample* Updated xen-xmexample.diff OBS-URL: https://build.opensuse.org/package/show/Virtualization/xen?expand=0&rev=172
125 lines
4.3 KiB
Diff
125 lines
4.3 KiB
Diff
References: bnc#712051, CVE-2011-3131
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# HG changeset patch
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# User Dario Faggioli <dario.faggioli@citrix.com>
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# Date 1327054832 0
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# Node ID 028230eb2359f33da48b3b7f85173a1b49b9c7d6
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# Parent d600a3d7faeeee3cf947bf1658b873e966fc0f16
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iommu: Move IOMMU faults handling into softirq for AMD-Vi.
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Dealing with interrupts from AMD-Vi IOMMU(s) is deferred to a
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softirq-tasklet, raised by the actual IRQ handler. To avoid more
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interrupts being generated (because of further faults), they must be
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masked in the IOMMU within the low level IRQ handler and enabled back
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in the tasklet body. Notice that this may cause the log to overflow,
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but none of the existing entry will be overwritten.
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Signed-off-by: Dario Faggioli <dario.faggioli@citrix.com>
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Committed-by: Keir Fraser <keir@xen.org>
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--- a/xen/drivers/passthrough/amd/iommu_init.c
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+++ b/xen/drivers/passthrough/amd/iommu_init.c
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@@ -33,6 +33,8 @@ static int nr_amd_iommus;
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static long amd_iommu_cmd_buffer_entries = IOMMU_CMD_BUFFER_DEFAULT_ENTRIES;
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static long amd_iommu_event_log_entries = IOMMU_EVENT_LOG_DEFAULT_ENTRIES;
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+static struct tasklet amd_iommu_irq_tasklet;
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+
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unsigned short ivrs_bdf_entries;
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struct ivrs_mappings *ivrs_mappings;
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struct list_head amd_iommu_head;
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@@ -517,34 +519,70 @@ static void parse_event_log_entry(u32 en
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}
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}
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+static void do_amd_iommu_irq(unsigned long data)
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+{
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+ struct amd_iommu *iommu;
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+
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+ if ( !iommu_found() )
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+ {
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+ AMD_IOMMU_DEBUG("no device found, something must be very wrong!\n");
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+ return;
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+ }
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+
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+ /*
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+ * No matter from where the interrupt came from, check all the
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+ * IOMMUs present in the system. This allows for having just one
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+ * tasklet (instead of one per each IOMMUs).
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+ */
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+ for_each_amd_iommu ( iommu )
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+ {
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+ u32 entry;
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+ unsigned long flags;
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+ int of;
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+
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+ spin_lock_irqsave(&iommu->lock, flags);
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+ amd_iommu_read_event_log(iommu);
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+
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+ /* check event overflow */
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+ entry = readl(iommu->mmio_base + IOMMU_STATUS_MMIO_OFFSET);
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+ of = get_field_from_reg_u32(entry,
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+ IOMMU_STATUS_EVENT_OVERFLOW_MASK,
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+ IOMMU_STATUS_EVENT_OVERFLOW_SHIFT);
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+
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+ /* reset event log if event overflow */
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+ if ( of )
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+ amd_iommu_reset_event_log(iommu);
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+
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+ /* reset interrupt status bit */
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+ entry = readl(iommu->mmio_base + IOMMU_STATUS_MMIO_OFFSET);
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+ set_field_in_reg_u32(IOMMU_CONTROL_ENABLED, entry,
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+ IOMMU_STATUS_EVENT_LOG_INT_MASK,
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+ IOMMU_STATUS_EVENT_LOG_INT_SHIFT, &entry);
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+ writel(entry, iommu->mmio_base+IOMMU_STATUS_MMIO_OFFSET);
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+ spin_unlock_irqrestore(&iommu->lock, flags);
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+ }
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+}
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+
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static void amd_iommu_page_fault(int irq, void *dev_id,
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struct cpu_user_regs *regs)
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{
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u32 entry;
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unsigned long flags;
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- int of;
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struct amd_iommu *iommu = dev_id;
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spin_lock_irqsave(&iommu->lock, flags);
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- amd_iommu_read_event_log(iommu);
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- /*check event overflow */
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+ /* Silence interrupts from both event logging */
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entry = readl(iommu->mmio_base + IOMMU_STATUS_MMIO_OFFSET);
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- of = get_field_from_reg_u32(entry,
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- IOMMU_STATUS_EVENT_OVERFLOW_MASK,
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- IOMMU_STATUS_EVENT_OVERFLOW_SHIFT);
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-
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- /* reset event log if event overflow */
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- if ( of )
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- amd_iommu_reset_event_log(iommu);
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-
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- /* reset interrupt status bit */
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- entry = readl(iommu->mmio_base + IOMMU_STATUS_MMIO_OFFSET);
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- set_field_in_reg_u32(IOMMU_CONTROL_ENABLED, entry,
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+ set_field_in_reg_u32(IOMMU_CONTROL_DISABLED, entry,
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IOMMU_STATUS_EVENT_LOG_INT_MASK,
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IOMMU_STATUS_EVENT_LOG_INT_SHIFT, &entry);
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writel(entry, iommu->mmio_base+IOMMU_STATUS_MMIO_OFFSET);
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+
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spin_unlock_irqrestore(&iommu->lock, flags);
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+
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+ /* It is the tasklet that will clear the logs and re-enable interrupts */
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+ tasklet_schedule(&amd_iommu_irq_tasklet);
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}
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static int set_iommu_interrupt_handler(struct amd_iommu *iommu)
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@@ -689,6 +727,8 @@ static int __init amd_iommu_init_one(str
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printk("AMD-Vi: IOMMU %d Enabled.\n", nr_amd_iommus );
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nr_amd_iommus++;
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+ softirq_tasklet_init(&amd_iommu_irq_tasklet, do_amd_iommu_irq, 0);
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+
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return 0;
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error_out:
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