1b78387def
- fate#309901: Add Xen support for SVM TSC scaling in AMD family 15h - fate#311951: Ivy Bridge: XEN support for Supervisor Mode Execution Protection (SMEP) 23437-amd-fam15-TSC-scaling.patch 23462-libxc-cpu-feature.patch 23481-x86-SMEP.patch 23504-x86-SMEP-hvm.patch 23505-x86-cpu-add-arg-check.patch 23508-vmx-proc-based-ctls-probe.patch 23510-hvm-cpuid-DRNG.patch 23511-amd-fam15-no-flush-for-C3.patch 23516-cpuid-ERMS.patch 23538-hvm-pio-emul-no-host-crash.patch 23539-hvm-cpuid-FSGSBASE.patch 23543-x86_64-maddr_to_virt-assertion.patch 23546-fucomip.patch - Fix libxc reentrancy issues 23383-libxc-rm-static-vars.patch OBS-URL: https://build.opensuse.org/package/show/Virtualization/xen?expand=0&rev=128
68 lines
2.6 KiB
Diff
68 lines
2.6 KiB
Diff
# HG changeset patch
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# User Yang, Wei <wei.y.yang@intel.com>
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# Date 1308053598 -3600
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# Node ID f4a47275aebf383cf565e0a265a56a8c1110d45e
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# Parent 337520d94cba906e64dbd3089d65cda8cf97d1d0
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x86: Pass through ERMS CPUID feature for HVM and PV guests
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This patch exposes ERMS feature to HVM and PV guests.
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The REP MOVSB/STOSB instruction can enhance fast strings attempts to
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move as much of the data with larger size load/stores as possible.
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Signed-off-by: Yang, Wei <wei.y.yang@intel.com>
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--- a/tools/libxc/xc_cpufeature.h
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+++ b/tools/libxc/xc_cpufeature.h
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@@ -126,5 +126,6 @@
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/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */
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#define X86_FEATURE_FSGSBASE 0 /* {RD,WR}{FS,GS}BASE instructions */
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#define X86_FEATURE_SMEP 7 /* Supervisor Mode Execution Protection */
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+#define X86_FEATURE_ERMS 9 /* Enhanced REP MOVSB/STOSB */
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#endif /* __LIBXC_CPUFEATURE_H */
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--- a/tools/libxc/xc_cpuid_x86.c
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+++ b/tools/libxc/xc_cpuid_x86.c
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@@ -303,7 +303,8 @@ static void xc_cpuid_hvm_policy(
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case 0x00000007: /* Intel-defined CPU features */
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if ( input[1] == 0 ) {
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- regs[1] &= bitmaskof(X86_FEATURE_SMEP);
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+ regs[1] &= (bitmaskof(X86_FEATURE_SMEP) |
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+ bitmaskof(X86_FEATURE_ERMS));
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} else
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regs[1] = 0;
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regs[0] = regs[2] = regs[3] = 0;
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@@ -425,7 +426,8 @@ static void xc_cpuid_pv_policy(
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case 7:
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if ( input[1] == 0 )
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- regs[1] &= bitmaskof(X86_FEATURE_FSGSBASE);
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+ regs[1] &= (bitmaskof(X86_FEATURE_FSGSBASE) |
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+ bitmaskof(X86_FEATURE_ERMS));
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else
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regs[1] = 0;
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regs[0] = regs[2] = regs[3] = 0;
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--- a/xen/arch/x86/traps.c
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+++ b/xen/arch/x86/traps.c
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@@ -812,7 +812,8 @@ static void pv_cpuid(struct cpu_user_reg
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break;
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case 7:
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if ( regs->ecx == 0 )
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- b &= cpufeat_mask(X86_FEATURE_FSGSBASE);
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+ b &= (cpufeat_mask(X86_FEATURE_FSGSBASE) |
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+ cpufeat_mask(X86_FEATURE_ERMS));
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else
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b = 0;
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a = c = d = 0;
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--- a/xen/include/asm-x86/cpufeature.h
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+++ b/xen/include/asm-x86/cpufeature.h
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@@ -144,6 +144,7 @@
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/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 7 */
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#define X86_FEATURE_FSGSBASE (7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */
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#define X86_FEATURE_SMEP (7*32+ 7) /* Supervisor Mode Execution Protection */
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+#define X86_FEATURE_ERMS (7*32+ 9) /* Enhanced REP MOVSB/STOSB */
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#define cpu_has(c, bit) test_bit(bit, (c)->x86_capability)
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#define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability)
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