163148b426
OBS-URL: https://build.opensuse.org/package/show/Virtualization/xen?expand=0&rev=87c8ac43897718b61dbcbca0296d6c2a
49 lines
1.6 KiB
Diff
49 lines
1.6 KiB
Diff
# HG changeset patch
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# User Keir Fraser <keir.fraser@citrix.com>
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# Date 1280486194 -3600
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# Node ID c9e7850ec9a18d7085c7468407e175bb64513846
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# Parent 754877be695ba3050f140002dbd185a27a437fcc
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x86: unmask CPUID levels on Intel CPUs
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References: bnc#640773
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If the CPUID limit bit in MSR_IA32_MISC_ENABLE is set, clear it to
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make all CPUID information available. This is required for some
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features to work, such as MWAIT in cpuidle, get cpu topology, XSAVE,
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etc.
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Signed-off-by: Wei Gang <gang.wei@intel.com>
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--- a/xen/arch/x86/cpu/intel.c
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+++ b/xen/arch/x86/cpu/intel.c
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@@ -90,6 +90,20 @@ void __devinit early_intel_workaround(st
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/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
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if (c->x86 == 15 && c->x86_cache_alignment == 64)
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c->x86_cache_alignment = 128;
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+
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+ /* Unmask CPUID levels if masked: */
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+ if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
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+ u64 misc_enable;
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+
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+ rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
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+
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+ if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
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+ misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
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+ wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
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+ c->cpuid_level = cpuid_eax(0);
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+ printk("revised cpuid_level = %d\n", c->cpuid_level);
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+ }
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+ }
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}
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/*
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--- a/xen/include/asm-x86/msr-index.h
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+++ b/xen/include/asm-x86/msr-index.h
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@@ -324,6 +324,7 @@
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#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1<<11)
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#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
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#define MSR_IA32_MISC_ENABLE_MONITOR_ENABLE (1<<18)
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+#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1<<22)
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#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1<<23)
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/* Intel Model 6 */
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