7143fd3903
Fixes error because of missing autoconf.h when building os11.2 Factory. - bnc#609153 - xm migrate <domain_name> localhost -l fails on Windows VMs 21615-dont-save-xen-heap-pages.patch - Upstream fixes from Jan 21446-iommu-graceful-generic-fail.patch 21453-shadow-avoid-remove-all-after-teardown.patch 21456-compat-hvm-addr-check.patch 21492-x86-pirq-unbind.patch 21526-x86-nehalem-cpuid-mask.patch 21620-x86-signed-domain-irq.patch OBS-URL: https://build.opensuse.org/package/show/Virtualization/xen?expand=0&rev=59
100 lines
3.2 KiB
Diff
100 lines
3.2 KiB
Diff
# HG changeset patch
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# User Keir Fraser <keir.fraser@citrix.com>
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# Date 1275643111 -3600
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# Node ID 48e2b07cf01c044bf483bd7fa5408a6f9801416b
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# Parent f2b1924f20281bc42fa3532c7d82b3ee0700aff4
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Intel: Add CPUID feature mask support for NHM processors.
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Signed-off-by: Jun Nakajima <jun.nakajima@intel.com>
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Signed-off-by: Liping Ke <liping.ke@intel.com>
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--- a/xen/arch/x86/cpu/intel.c
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+++ b/xen/arch/x86/cpu/intel.c
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@@ -29,6 +29,9 @@ extern int trap_init_f00f_bug(void);
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static unsigned int opt_cpuid_mask_ecx, opt_cpuid_mask_edx;
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integer_param("cpuid_mask_ecx", opt_cpuid_mask_ecx);
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integer_param("cpuid_mask_edx", opt_cpuid_mask_edx);
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+static unsigned int opt_cpuid_mask_ext_ecx, opt_cpuid_mask_ext_edx;
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+integer_param("cpuid_mask_ext_ecx", opt_cpuid_mask_ext_ecx);
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+integer_param("cpuid_mask_ext_edx", opt_cpuid_mask_ext_edx);
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static int use_xsave = 1;
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boolean_param("xsave", use_xsave);
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@@ -40,24 +43,46 @@ boolean_param("xsave", use_xsave);
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struct movsl_mask movsl_mask __read_mostly;
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#endif
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-static void __devinit set_cpuidmask(void)
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+static void __devinit set_cpuidmask(struct cpuinfo_x86 *c)
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{
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- unsigned int eax, ebx, ecx, edx, model;
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+ unsigned int model = c->x86_model;
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- if (!(opt_cpuid_mask_ecx | opt_cpuid_mask_edx))
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+ if (!(opt_cpuid_mask_ecx | opt_cpuid_mask_edx |
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+ opt_cpuid_mask_ext_ecx | opt_cpuid_mask_ext_edx))
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return;
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- cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
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- model = ((eax & 0xf0000) >> 12) | ((eax & 0xf0) >> 4);
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- if (!((model == 0x1d) || ((model == 0x17) && ((eax & 0xf) >= 4)))) {
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+ if (c->x86 != 0x6) /* Only family 6 supports this feature */
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+ return;
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+
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+ if ((model == 0x1d) || ((model == 0x17) && (c->x86_mask >= 4))) {
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+ wrmsr(MSR_IA32_CPUID_FEATURE_MASK1,
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+ opt_cpuid_mask_ecx ? : ~0u,
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+ opt_cpuid_mask_edx ? : ~0u);
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+ }
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+/*
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+ * CPU supports this feature if the processor signature meets the following:
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+ * (CPUID.(EAX=01h):EAX) > 000106A2h, or
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+ * (CPUID.(EAX=01h):EAX) == 000106Exh, 0002065xh, 000206Cxh, 000206Exh, or 000206Fxh
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+ *
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+ */
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+ else if (((model == 0x1a) && (c->x86_mask > 2))
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+ || model == 0x1e
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+ || model == 0x25
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+ || model == 0x2c
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+ || model == 0x2e
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+ || model == 0x2f) {
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+ wrmsr(MSR_IA32_CPUID1_FEATURE_MASK,
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+ opt_cpuid_mask_ecx ? : ~0u,
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+ opt_cpuid_mask_edx ? : ~0u);
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+ wrmsr(MSR_IA32_CPUID80000001_FEATURE_MASK,
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+ opt_cpuid_mask_ext_ecx ? : ~0u,
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+ opt_cpuid_mask_ext_edx ? : ~0u);
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+ }
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+ else {
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printk(XENLOG_ERR "Cannot set CPU feature mask on CPU#%d\n",
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smp_processor_id());
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return;
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}
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-
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- wrmsr(MSR_IA32_CPUID_FEATURE_MASK1,
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- opt_cpuid_mask_ecx ? : ~0u,
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- opt_cpuid_mask_edx ? : ~0u);
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}
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void __devinit early_intel_workaround(struct cpuinfo_x86 *c)
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@@ -179,7 +204,7 @@ static void __devinit init_intel(struct
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detect_ht(c);
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- set_cpuidmask();
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+ set_cpuidmask(c);
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/* Work around errata */
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Intel_errata_workarounds(c);
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--- a/xen/include/asm-x86/msr-index.h
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+++ b/xen/include/asm-x86/msr-index.h
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@@ -158,6 +158,8 @@
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/* MSR for cpuid feature mask */
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#define MSR_IA32_CPUID_FEATURE_MASK1 0x00000478
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+#define MSR_IA32_CPUID1_FEATURE_MASK 0x00000130
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+#define MSR_IA32_CPUID80000001_FEATURE_MASK 0x00000131
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/* MSRs & bits used for VMX enabling */
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#define MSR_IA32_VMX_BASIC 0x480
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