34 lines
1.6 KiB
Diff
34 lines
1.6 KiB
Diff
Index: 2007-02-20/xen/arch/x86/mm.c
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===================================================================
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--- 2007-02-20.orig/xen/arch/x86/mm.c 2007-02-20 10:56:12.000000000 +0100
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+++ 2007-02-20/xen/arch/x86/mm.c 2007-02-20 10:56:25.000000000 +0100
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@@ -3252,14 +3252,15 @@ static int ptwr_emulated_update(
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{
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if ( (CONFIG_PAGING_LEVELS == 3 || IS_COMPAT(d)) &&
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(bytes == 4) &&
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+ (addr & 4) &&
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!do_cmpxchg &&
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(l1e_get_flags(nl1e) & _PAGE_PRESENT) )
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{
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/*
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- * If this is a half-write to a PAE PTE then we assume that the
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- * guest has simply got the two writes the wrong way round. We
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- * zap the PRESENT bit on the assumption the bottom half will be
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- * written immediately after we return to the guest.
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+ * If this is an upper half write to a PAE PTE then we assume
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+ * that the guest has simply got the two writes the wrong way
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+ * round. We zap the PRESENT bit on the assumption the bottom
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+ * half will be written immediately after we return to the guest.
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*/
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MEM_LOG("ptwr_emulate: fixing up invalid PAE PTE %"PRIpte,
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l1e_get_intpte(nl1e));
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@@ -3391,7 +3392,7 @@ int ptwr_do_page_fault(struct vcpu *v, u
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(page_get_owner(page) != d) )
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goto bail;
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- ptwr_ctxt.ctxt.regs = guest_cpu_user_regs();
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+ ptwr_ctxt.ctxt.regs = regs;
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ptwr_ctxt.ctxt.mode = !IS_COMPAT(d) ? X86EMUL_MODE_HOST : X86EMUL_MODE_PROT32;
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ptwr_ctxt.cr2 = addr;
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ptwr_ctxt.pte = pte;
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