9fd34708c1
guest 21971-pod-accounting.patch - bnc#584204 - xm usb-list broken usb-list.patch - bnc#625520 - TP-L3: NMI cannot be triggered for xen kernel 21926-x86-pv-NMI-inject.patch - bnc#613529 - TP-L3: kdump kernel hangs when crash was initiated from xen kernel 21886-kexec-shutdown.patch - Upstream Intel patches to improve X2APIC handling. 21716-iommu-alloc.patch 21717-ir-qi.patch 21718-x2apic-logic.patch 21933-vtd-ioapic-write.patch 21953-msi-enable.patch OBS-URL: https://build.opensuse.org/package/show/Virtualization/xen?expand=0&rev=71
221 lines
7.6 KiB
Diff
221 lines
7.6 KiB
Diff
# HG changeset patch
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# User Keir Fraser <keir.fraser@citrix.com>
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# Date 1275643111 -3600
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# Node ID 48e2b07cf01c044bf483bd7fa5408a6f9801416b
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# Parent f2b1924f20281bc42fa3532c7d82b3ee0700aff4
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Intel: Add CPUID feature mask support for NHM processors.
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Signed-off-by: Jun Nakajima <jun.nakajima@intel.com>
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Signed-off-by: Liping Ke <liping.ke@intel.com>
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# HG changeset patch
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# User Keir Fraser <keir.fraser@citrix.com>
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# Date 1276604335 -3600
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# Node ID 2501732e291b001711a0dc1c474bb89ce77f3110
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# Parent a2cc1db1af9c8f9b148c80f8b2c3f64bde7542f9
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x86: fix pv cpuid masking
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Invert initial values of the variables parsed into from the command
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line, so that completely clearing out one or more of the four bit
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fields is possible.
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Further, consolidate the command line parameter specifications into
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a single place.
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Finally, as per "Intel Virtualization Technology FlexMigration
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Application Note" (http://www.intel.com/Assets/PDF/manual/323850.pdf),
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also handle family 6 model 0x1f.
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What remains open is the question whether pv_cpuid() shouldn't also
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consume these masks.
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Signed-off-by: Jan Beulich <jbeulich@novell.com>
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--- a/xen/arch/x86/cpu/amd.c
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+++ b/xen/arch/x86/cpu/amd.c
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@@ -33,14 +33,6 @@ void start_svm(struct cpuinfo_x86 *c);
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static char opt_famrev[14];
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string_param("cpuid_mask_cpu", opt_famrev);
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-/* Finer-grained CPUID feature control. */
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-static unsigned int opt_cpuid_mask_ecx, opt_cpuid_mask_edx;
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-integer_param("cpuid_mask_ecx", opt_cpuid_mask_ecx);
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-integer_param("cpuid_mask_edx", opt_cpuid_mask_edx);
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-static unsigned int opt_cpuid_mask_ext_ecx, opt_cpuid_mask_ext_edx;
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-integer_param("cpuid_mask_ext_ecx", opt_cpuid_mask_ext_ecx);
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-integer_param("cpuid_mask_ext_edx", opt_cpuid_mask_ext_edx);
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-
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static inline void wrmsr_amd(unsigned int index, unsigned int lo,
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unsigned int hi)
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{
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@@ -61,7 +53,7 @@ static inline void wrmsr_amd(unsigned in
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*
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* The processor revision string parameter has precedene.
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*/
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-static void __devinit set_cpuidmask(struct cpuinfo_x86 *c)
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+static void __devinit set_cpuidmask(const struct cpuinfo_x86 *c)
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{
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static unsigned int feat_ecx, feat_edx;
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static unsigned int extfeat_ecx, extfeat_edx;
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@@ -76,12 +68,12 @@ static void __devinit set_cpuidmask(stru
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ASSERT((status == not_parsed) && (smp_processor_id() == 0));
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status = no_mask;
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- if (opt_cpuid_mask_ecx | opt_cpuid_mask_edx |
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- opt_cpuid_mask_ext_ecx | opt_cpuid_mask_ext_edx) {
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- feat_ecx = opt_cpuid_mask_ecx ? : ~0U;
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- feat_edx = opt_cpuid_mask_edx ? : ~0U;
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- extfeat_ecx = opt_cpuid_mask_ext_ecx ? : ~0U;
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- extfeat_edx = opt_cpuid_mask_ext_edx ? : ~0U;
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+ if (~(opt_cpuid_mask_ecx & opt_cpuid_mask_edx &
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+ opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx)) {
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+ feat_ecx = opt_cpuid_mask_ecx;
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+ feat_edx = opt_cpuid_mask_edx;
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+ extfeat_ecx = opt_cpuid_mask_ext_ecx;
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+ extfeat_edx = opt_cpuid_mask_ext_edx;
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} else if (*opt_famrev == '\0') {
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return;
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} else if (!strcmp(opt_famrev, "fam_0f_rev_c")) {
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--- a/xen/arch/x86/cpu/common.c
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+++ b/xen/arch/x86/cpu/common.c
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@@ -22,6 +22,15 @@ static int cachesize_override __cpuinitd
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static int disable_x86_fxsr __cpuinitdata;
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static int disable_x86_serial_nr __cpuinitdata;
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+unsigned int __devinitdata opt_cpuid_mask_ecx = ~0u;
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+integer_param("cpuid_mask_ecx", opt_cpuid_mask_ecx);
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+unsigned int __devinitdata opt_cpuid_mask_edx = ~0u;
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+integer_param("cpuid_mask_edx", opt_cpuid_mask_edx);
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+unsigned int __devinitdata opt_cpuid_mask_ext_ecx = ~0u;
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+integer_param("cpuid_mask_ext_ecx", opt_cpuid_mask_ext_ecx);
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+unsigned int __devinitdata opt_cpuid_mask_ext_edx = ~0u;
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+integer_param("cpuid_mask_ext_edx", opt_cpuid_mask_ext_edx);
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+
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struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
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/*
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--- a/xen/arch/x86/cpu/cpu.h
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+++ b/xen/arch/x86/cpu/cpu.h
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@@ -21,6 +21,9 @@ struct cpu_dev {
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extern struct cpu_dev * cpu_devs [X86_VENDOR_NUM];
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+extern unsigned int opt_cpuid_mask_ecx, opt_cpuid_mask_edx;
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+extern unsigned int opt_cpuid_mask_ext_ecx, opt_cpuid_mask_ext_edx;
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+
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extern int get_model_name(struct cpuinfo_x86 *c);
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extern void display_cacheinfo(struct cpuinfo_x86 *c);
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--- a/xen/arch/x86/cpu/intel.c
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+++ b/xen/arch/x86/cpu/intel.c
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@@ -20,16 +20,6 @@
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extern int trap_init_f00f_bug(void);
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-/*
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- * opt_cpuid_mask_ecx/edx: cpuid.1[ecx, edx] feature mask.
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- * For example, E8400[Intel Core 2 Duo Processor series] ecx = 0x0008E3FD,
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- * edx = 0xBFEBFBFF when executing CPUID.EAX = 1 normally. If you want to
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- * 'rev down' to E8400, you can set these values in these Xen boot parameters.
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- */
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-static unsigned int opt_cpuid_mask_ecx, opt_cpuid_mask_edx;
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-integer_param("cpuid_mask_ecx", opt_cpuid_mask_ecx);
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-integer_param("cpuid_mask_edx", opt_cpuid_mask_edx);
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-
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static int use_xsave = 1;
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boolean_param("xsave", use_xsave);
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@@ -40,24 +30,57 @@ boolean_param("xsave", use_xsave);
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struct movsl_mask movsl_mask __read_mostly;
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#endif
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-static void __devinit set_cpuidmask(void)
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+/*
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+ * opt_cpuid_mask_ecx/edx: cpuid.1[ecx, edx] feature mask.
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+ * For example, E8400[Intel Core 2 Duo Processor series] ecx = 0x0008E3FD,
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+ * edx = 0xBFEBFBFF when executing CPUID.EAX = 1 normally. If you want to
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+ * 'rev down' to E8400, you can set these values in these Xen boot parameters.
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+ */
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+static void __devinit set_cpuidmask(const struct cpuinfo_x86 *c)
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{
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- unsigned int eax, ebx, ecx, edx, model;
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+ const char *extra = "";
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- if (!(opt_cpuid_mask_ecx | opt_cpuid_mask_edx))
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+ if (!~(opt_cpuid_mask_ecx & opt_cpuid_mask_edx &
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+ opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx))
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return;
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- cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
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- model = ((eax & 0xf0000) >> 12) | ((eax & 0xf0) >> 4);
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- if (!((model == 0x1d) || ((model == 0x17) && ((eax & 0xf) >= 4)))) {
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- printk(XENLOG_ERR "Cannot set CPU feature mask on CPU#%d\n",
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- smp_processor_id());
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+ /* Only family 6 supports this feature */
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+ switch ((c->x86 == 6) * c->x86_model) {
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+ case 0x17:
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+ if ((c->x86_mask & 0x0f) < 4)
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+ break;
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+ /* fall through */
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+ case 0x1d:
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+ wrmsr(MSR_INTEL_CPUID_FEATURE_MASK,
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+ opt_cpuid_mask_ecx,
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+ opt_cpuid_mask_edx);
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+ if (!~(opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx))
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+ return;
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+ extra = "extended ";
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+ break;
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+/*
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+ * CPU supports this feature if the processor signature meets the following:
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+ * (CPUID.(EAX=01h):EAX) > 000106A2h, or
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+ * (CPUID.(EAX=01h):EAX) == 000106Exh, 0002065xh, 000206Cxh, 000206Exh, or 000206Fxh
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+ *
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+ */
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+ case 0x1a:
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+ if ((c->x86_mask & 0x0f) <= 2)
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+ break;
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+ /* fall through */
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+ case 0x1e: case 0x1f:
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+ case 0x25: case 0x2c: case 0x2e: case 0x2f:
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+ wrmsr(MSR_INTEL_CPUID1_FEATURE_MASK,
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+ opt_cpuid_mask_ecx,
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+ opt_cpuid_mask_edx);
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+ wrmsr(MSR_INTEL_CPUID80000001_FEATURE_MASK,
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+ opt_cpuid_mask_ext_ecx,
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+ opt_cpuid_mask_ext_edx);
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return;
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}
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- wrmsr(MSR_IA32_CPUID_FEATURE_MASK1,
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- opt_cpuid_mask_ecx ? : ~0u,
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- opt_cpuid_mask_edx ? : ~0u);
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+ printk(XENLOG_ERR "Cannot set CPU feature mask on CPU#%d\n",
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+ smp_processor_id());
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}
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void __devinit early_intel_workaround(struct cpuinfo_x86 *c)
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@@ -179,7 +202,7 @@ static void __devinit init_intel(struct
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detect_ht(c);
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- set_cpuidmask();
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+ set_cpuidmask(c);
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/* Work around errata */
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Intel_errata_workarounds(c);
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--- a/xen/include/asm-x86/msr-index.h
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+++ b/xen/include/asm-x86/msr-index.h
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@@ -156,8 +156,10 @@
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#define MSR_P6_EVNTSEL0 0x00000186
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#define MSR_P6_EVNTSEL1 0x00000187
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-/* MSR for cpuid feature mask */
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-#define MSR_IA32_CPUID_FEATURE_MASK1 0x00000478
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+/* MSRs for Intel cpuid feature mask */
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+#define MSR_INTEL_CPUID_FEATURE_MASK 0x00000478
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+#define MSR_INTEL_CPUID1_FEATURE_MASK 0x00000130
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+#define MSR_INTEL_CPUID80000001_FEATURE_MASK 0x00000131
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/* MSRs & bits used for VMX enabling */
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#define MSR_IA32_VMX_BASIC 0x480
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