a428832eb0
xl-check-for-libvirt-managed-domain.patch - bnc#878841 - VUL-0: XSA-96: Xen: Vulnerabilities in HVM MSI injection 538dcada-x86-HVM-eliminate-vulnerabilities-from-hvm_inject_msi.patch - Upstream patches from Jan 537cd0b0-hvmloader-also-cover-PCI-MMIO-ranges-above-4G-with-UC-MTRR-ranges.patch 537cd0cc-hvmloader-PA-range-0xfc000000-0xffffffff-should-be-UC.patch 5383167d-ACPI-ERST-fix-table-mapping.patch 5383175e-VT-d-fix-mask-applied-to-DMIBAR-in-desktop-chipset-XSA-59-workaround.patch 53859549-AMD-IOMMU-don-t-free-page-table-prematurely.patch 5385956b-x86-don-t-use-VA-for-cache-flush-when-also-flushing-TLB.patch 53859956-timers-set-the-deadline-more-accurately.patch OBS-URL: https://build.opensuse.org/package/show/Virtualization/xen?expand=0&rev=318
35 lines
1.4 KiB
Diff
35 lines
1.4 KiB
Diff
# Commit c22bd567ce22f6ad9bd93318ad0d7fd1c2eadb0d
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# Date 2014-05-21 18:14:04 +0200
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# Author Jan Beulich <jbeulich@suse.com>
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# Committer Jan Beulich <jbeulich@suse.com>
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hvmloader: PA range 0xfc000000-0xffffffff should be UC
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Rather than leaving the range from PCI_MEM_END (0xfc000000) to 4G
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uncovered, we should include this in the UC range created for the (low)
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PCI range. Besides being more correct, this also has the advantage that
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with the way pci_setup() currently works the range will always be
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mappable with a single variable range MTRR (rather than from 2 to 5
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depending on how much the lower boundary gets shifted down to
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accommodate all devices).
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Signed-off-by: Jan Beulich <jbeulich@suse.com>
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Acked-by: Ian Campbell <ian.campbell@citrix.com>
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--- a/tools/firmware/hvmloader/cacheattr.c
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+++ b/tools/firmware/hvmloader/cacheattr.c
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@@ -99,12 +99,12 @@ void cacheattr_init(void)
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{
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uint64_t base = pci_mem_start, size;
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- for ( i = 0; (base != pci_mem_end) && (i < nr_var_ranges); i++ )
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+ for ( i = 0; !(base >> 32) && (i < nr_var_ranges); i++ )
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{
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size = PAGE_SIZE;
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while ( !(base & size) )
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size <<= 1;
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- while ( ((base + size) < base) || ((base + size) > pci_mem_end) )
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+ while ( ((base + size) < base) || ((base + size - 1) >> 32) )
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size >>= 1;
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wrmsr(MSR_MTRRphysBase(i), base);
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