edf6bf0381
23955-x86-pv-cpuid-xsave.patch 23957-cpufreq-error-paths.patch - Upstream patches from Jan 23933-pt-bus2bridge-update.patch 23726-x86-intel-flexmigration-v2.patch 23925-x86-AMD-ARAT-Fam12.patch 23246-x86-xsave-enable.patch 23897-x86-mce-offline-again.patch - Update to Xen 4.1.2_rc3 c/s 23171 - bnc#720054 - Changed /etc/udev/rules.d/40-xen.rules to not run Xen's vif-bridge script when not running Xen. This is not a solution to the bug but an improvement in the rules regardless. Updated udev-rules.patch - Upstream patches from Jan 23868-vtd-RMRR-validation.patch 23871-x86-microcode-amd-silent.patch 23898-cc-option-grep.patch - Add pciback init script and sysconf file, giving users a simple mechanism to configure pciback. init.pciback sysconfig.pciback - update scripts to use xl -f, or xm if xend is running: xen-updown.sh, init.xendomains, xmclone.sh OBS-URL: https://build.opensuse.org/package/show/Virtualization/xen?expand=0&rev=146
128 lines
4.4 KiB
Diff
128 lines
4.4 KiB
Diff
# HG changeset patch
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# User Jan Beulich <jbeulich@novell.com>
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# Date 1311081291 -3600
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# Node ID fd97ca086df6808bffc6ecf3f79cebca64c60bc3
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# Parent 4dc6a9ba90d60fdf0cc0898fc9a8fe84ae9030fc
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x86: update Intel CPUID masking code to latest spec
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..., which adds masking of the xsave feature leaf.
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Also fix the printing (to actually make it do what it was supposed to
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do from the beginning) of what specific masking couldn't be done in
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case the user requested something the hardware doesn't support.
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Signed-off-by: Jan Beulich <jbeulich@novell.com>
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# HG changeset patch
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# User Jan Beulich <jbeulich@novell.com>
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# Date 1311255291 -3600
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# Node ID 48f72b389b04cfa8d44924577a69ed59e48fbe77
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# Parent dd5eecf739d152fb16bd44897875ea878d4c9d59
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x86: add change missing in c/s 23726:fd97ca086df6
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The early "do we need to do anything" check needs adjustment, too.
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Thanks to Haitao Shan for pointing this out.
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Signed-off-by: Jan Beulich <jbeulich@novell.com>
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--- a/xen/arch/x86/cpu/common.c
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+++ b/xen/arch/x86/cpu/common.c
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@@ -27,10 +27,15 @@ boolean_param("noserialnumber", disable_
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static bool_t __cpuinitdata use_xsave = 1;
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boolean_param("xsave", use_xsave);
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+
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unsigned int __devinitdata opt_cpuid_mask_ecx = ~0u;
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integer_param("cpuid_mask_ecx", opt_cpuid_mask_ecx);
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unsigned int __devinitdata opt_cpuid_mask_edx = ~0u;
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integer_param("cpuid_mask_edx", opt_cpuid_mask_edx);
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+
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+unsigned int __devinitdata opt_cpuid_mask_xsave_eax = ~0u;
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+integer_param("cpuid_mask_xsave_eax", opt_cpuid_mask_xsave_eax);
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+
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unsigned int __devinitdata opt_cpuid_mask_ext_ecx = ~0u;
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integer_param("cpuid_mask_ext_ecx", opt_cpuid_mask_ext_ecx);
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unsigned int __devinitdata opt_cpuid_mask_ext_edx = ~0u;
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--- a/xen/arch/x86/cpu/cpu.h
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+++ b/xen/arch/x86/cpu/cpu.h
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@@ -22,6 +22,7 @@ struct cpu_dev {
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extern struct cpu_dev * cpu_devs [X86_VENDOR_NUM];
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extern unsigned int opt_cpuid_mask_ecx, opt_cpuid_mask_edx;
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+extern unsigned int opt_cpuid_mask_xsave_eax;
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extern unsigned int opt_cpuid_mask_ext_ecx, opt_cpuid_mask_ext_edx;
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extern int get_model_name(struct cpuinfo_x86 *c);
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--- a/xen/arch/x86/cpu/intel.c
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+++ b/xen/arch/x86/cpu/intel.c
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@@ -59,10 +59,12 @@ void set_cpuid_faulting(bool_t enable)
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*/
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static void __devinit set_cpuidmask(const struct cpuinfo_x86 *c)
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{
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+ u32 eax, edx;
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const char *extra = "";
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if (!~(opt_cpuid_mask_ecx & opt_cpuid_mask_edx &
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- opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx))
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+ opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx &
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+ opt_cpuid_mask_xsave_eax))
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return;
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/* Only family 6 supports this feature */
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@@ -75,9 +77,12 @@ static void __devinit set_cpuidmask(cons
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wrmsr(MSR_INTEL_CPUID_FEATURE_MASK,
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opt_cpuid_mask_ecx,
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opt_cpuid_mask_edx);
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- if (!~(opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx))
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+ if (~(opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx))
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+ extra = "extended ";
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+ else if (~opt_cpuid_mask_xsave_eax)
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+ extra = "xsave ";
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+ else
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return;
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- extra = "extended ";
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break;
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/*
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* CPU supports this feature if the processor signature meets the following:
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@@ -97,11 +102,25 @@ static void __devinit set_cpuidmask(cons
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wrmsr(MSR_INTEL_CPUID80000001_FEATURE_MASK,
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opt_cpuid_mask_ext_ecx,
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opt_cpuid_mask_ext_edx);
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+ if (!~opt_cpuid_mask_xsave_eax)
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+ return;
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+ extra = "xsave ";
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+ break;
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+ case 0x2a:
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+ wrmsr(MSR_INTEL_CPUID1_FEATURE_MASK_V2,
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+ opt_cpuid_mask_ecx,
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+ opt_cpuid_mask_edx);
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+ rdmsr(MSR_INTEL_CPUIDD_01_FEATURE_MASK, eax, edx);
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+ wrmsr(MSR_INTEL_CPUIDD_01_FEATURE_MASK,
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+ opt_cpuid_mask_xsave_eax, edx);
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+ wrmsr(MSR_INTEL_CPUID80000001_FEATURE_MASK_V2,
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+ opt_cpuid_mask_ext_ecx,
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+ opt_cpuid_mask_ext_edx);
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return;
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}
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- printk(XENLOG_ERR "Cannot set CPU feature mask on CPU#%d\n",
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- smp_processor_id());
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+ printk(XENLOG_ERR "Cannot set CPU %sfeature mask on CPU#%d\n",
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+ extra, smp_processor_id());
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}
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void __devinit early_intel_workaround(struct cpuinfo_x86 *c)
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--- a/xen/include/asm-x86/msr-index.h
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+++ b/xen/include/asm-x86/msr-index.h
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@@ -488,6 +488,10 @@
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#define MSR_INTEL_CPUID1_FEATURE_MASK 0x00000130
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#define MSR_INTEL_CPUID80000001_FEATURE_MASK 0x00000131
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+#define MSR_INTEL_CPUID1_FEATURE_MASK_V2 0x00000132
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+#define MSR_INTEL_CPUID80000001_FEATURE_MASK_V2 0x00000133
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+#define MSR_INTEL_CPUIDD_01_FEATURE_MASK 0x00000134
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+
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/* Intel cpuid faulting MSRs */
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#define MSR_INTEL_PLATFORM_INFO 0x000000ce
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#define MSR_INTEL_MISC_FEATURES_ENABLES 0x00000140
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