c9e3853c04
24448-x86-pt-irq-leak.patch - Upstream patches from Jan 24261-x86-cpuidle-Westmere-EX.patch 24417-amd-erratum-573.patch 24429-mceinj-tool.patch 24447-x86-TXT-INIT-SIPI-delay.patch ioemu-9868-MSI-X.patch - bnc#732884 - remove private runlevel 4 from init scripts xen.no-default-runlevel-4.patch - bnc#727515 - Fragmented packets hang network boot of HVM guest ipxe-gcc45-warnings.patch ipxe-ipv4-fragment.patch ipxe-enable-nics.patch - fate#310510 - fix xenpaging update xenpaging.autostart.patch, make changes with mem-swap-target permanent update xenpaging.doc.patch, mention issues with live migration - fate#310510 - fix xenpaging add xenpaging.evict_mmap_readonly.patch update xenpaging.error-handling.patch, reduce debug output - bnc#736824 - Microcode patches for AMD's 15h processors panic the system 24189-x86-p2m-pod-locking.patch 24412-x86-AMD-errata-model-shift.patch OBS-URL: https://build.opensuse.org/package/show/Virtualization/xen?expand=0&rev=164
110 lines
3.2 KiB
Diff
110 lines
3.2 KiB
Diff
# HG changeset patch
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# User Jan Beulich <jbeulich@suse.com>
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# Date 1323765911 -3600
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# Node ID 868d82faf6511de3b3edce18cc6a9e1c938f0b8f
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# Parent 7ca56cca09ade16645fb4806be2c5b2b0bc3332b
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x86, amd: Disable GartTlbWlkErr when BIOS forgets it
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This patch disables GartTlbWlk errors on AMD Fam10h CPUs if the BIOS
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forgets to do is (or is just too old). Letting these errors enabled
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can cause a sync-flood on the CPU causing a reboot.
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The AMD BKDG recommends disabling GART TLB Wlk Error completely.
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Based on a Linux patch from Joerg Roedel <joerg.roedel@amd.com>; see e.g.
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https://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=patch;h=5bbc097d890409d8eff4e3f1d26f11a9d6b7c07e
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Signed-off-by: Jan Beulich <jbeulich@suse.com>
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Acked-by: Keir Fraser <keir@xen.org>
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--- a/xen/arch/x86/cpu/mcheck/amd_f10.c
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+++ b/xen/arch/x86/cpu/mcheck/amd_f10.c
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@@ -46,6 +46,7 @@
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#include <asm/msr.h>
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#include "mce.h"
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+#include "mce_quirks.h"
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#include "x86_mca.h"
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@@ -91,9 +92,14 @@ amd_f10_handler(struct mc_info *mi, uint
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/* AMD Family10 machine check */
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enum mcheck_type amd_f10_mcheck_init(struct cpuinfo_x86 *c)
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{
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+ enum mcequirk_amd_flags quirkflag = mcequirk_lookup_amd_quirkdata(c);
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+
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if (amd_k8_mcheck_init(c) == mcheck_none)
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return mcheck_none;
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+ if (quirkflag == MCEQUIRK_F10_GART)
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+ mcequirk_amd_apply(quirkflag);
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+
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x86_mce_callback_register(amd_f10_handler);
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return mcheck_amd_famXX;
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--- a/xen/arch/x86/cpu/mcheck/mce_amd_quirks.c
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+++ b/xen/arch/x86/cpu/mcheck/mce_amd_quirks.c
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@@ -29,6 +29,8 @@ static const struct mce_quirkdata mce_am
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MCEQUIRK_K7_BANK0 },
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{ 0xf /* cpu family */, ANY /* all models */, ANY /* all steppings */,
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MCEQUIRK_K8_GART },
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+ { 0x10 /* cpu family */, ANY /* all models */, ANY /* all steppings */,
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+ MCEQUIRK_F10_GART },
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};
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enum mcequirk_amd_flags
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@@ -54,6 +56,8 @@ mcequirk_lookup_amd_quirkdata(struct cpu
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int mcequirk_amd_apply(enum mcequirk_amd_flags flags)
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{
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+ u64 val;
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+
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switch (flags) {
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case MCEQUIRK_K7_BANK0:
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return 1; /* first bank */
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@@ -67,6 +71,10 @@ int mcequirk_amd_apply(enum mcequirk_amd
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wrmsrl(MSR_IA32_MC4_CTL, ~(1ULL << 10));
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wrmsrl(MSR_IA32_MC4_STATUS, 0ULL);
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break;
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+ case MCEQUIRK_F10_GART:
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+ if (rdmsr_safe(MSR_AMD64_MCx_MASK(4), val) == 0)
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+ wrmsr_safe(MSR_AMD64_MCx_MASK(4), val | (1 << 10));
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+ break;
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}
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return 0;
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--- a/xen/arch/x86/cpu/mcheck/mce_quirks.h
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+++ b/xen/arch/x86/cpu/mcheck/mce_quirks.h
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@@ -33,8 +33,9 @@ struct mce_quirkdata {
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*/
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enum mcequirk_amd_flags {
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- MCEQUIRK_K7_BANK0 = 0x1,
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- MCEQUIRK_K8_GART = 0x2,
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+ MCEQUIRK_K7_BANK0 = 1,
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+ MCEQUIRK_K8_GART,
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+ MCEQUIRK_F10_GART
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};
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enum mcequirk_intel_flags {
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--- a/xen/include/asm-x86/msr-index.h
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+++ b/xen/include/asm-x86/msr-index.h
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@@ -98,6 +98,8 @@
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#define CMCI_EN (1UL<<30)
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#define CMCI_THRESHOLD_MASK 0x7FFF
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+#define MSR_AMD64_MC0_MASK 0xc0010044
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+
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#define MSR_IA32_MC1_CTL 0x00000404
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#define MSR_IA32_MC1_CTL2 0x00000281
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#define MSR_IA32_MC1_STATUS 0x00000405
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@@ -151,6 +153,8 @@
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#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
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#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
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+#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
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+
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#define MSR_P6_PERFCTR0 0x000000c1
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#define MSR_P6_PERFCTR1 0x000000c2
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#define MSR_P6_EVNTSEL0 0x00000186
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