1b78387def
- fate#309901: Add Xen support for SVM TSC scaling in AMD family 15h - fate#311951: Ivy Bridge: XEN support for Supervisor Mode Execution Protection (SMEP) 23437-amd-fam15-TSC-scaling.patch 23462-libxc-cpu-feature.patch 23481-x86-SMEP.patch 23504-x86-SMEP-hvm.patch 23505-x86-cpu-add-arg-check.patch 23508-vmx-proc-based-ctls-probe.patch 23510-hvm-cpuid-DRNG.patch 23511-amd-fam15-no-flush-for-C3.patch 23516-cpuid-ERMS.patch 23538-hvm-pio-emul-no-host-crash.patch 23539-hvm-cpuid-FSGSBASE.patch 23543-x86_64-maddr_to_virt-assertion.patch 23546-fucomip.patch - Fix libxc reentrancy issues 23383-libxc-rm-static-vars.patch OBS-URL: https://build.opensuse.org/package/show/Virtualization/xen?expand=0&rev=128
46 lines
1.8 KiB
Diff
46 lines
1.8 KiB
Diff
# HG changeset patch
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# User Keir Fraser <keir@xen.org>
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# Date 1307691167 -3600
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# Node ID 2ef6bbee50371e1135236035ed1a9a7b8748e09f
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# Parent 0a29c8c3ddf7395ea8e68c5f4cd8633023490022
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x86/vmx: Small fixes to MSR_IA32_VMX_PROCBASED_CTLS feature probing.
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Should check for VIRTUAL_INTR_PENDING as we unconditionally make use
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of it. Also check for CR8 exiting unconditionally on x86/64, as this
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is of use to nestedvmx, and every 64-bit cpu should support it.
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Signed-off-by: Eddie Dong <eddie.dong@intel.com>
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Signed-off-by: Keir Fraser <keir@xen.org>
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--- a/xen/arch/x86/hvm/vmx/vmcs.c
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+++ b/xen/arch/x86/hvm/vmx/vmcs.c
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@@ -147,6 +147,11 @@ static int vmx_init_vmcs_config(void)
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MSR_IA32_VMX_PINBASED_CTLS, &mismatch);
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min = (CPU_BASED_HLT_EXITING |
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+ CPU_BASED_VIRTUAL_INTR_PENDING |
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+#ifdef __x86_64__
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+ CPU_BASED_CR8_LOAD_EXITING |
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+ CPU_BASED_CR8_STORE_EXITING |
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+#endif
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CPU_BASED_INVLPG_EXITING |
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CPU_BASED_CR3_LOAD_EXITING |
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CPU_BASED_CR3_STORE_EXITING |
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@@ -165,13 +170,9 @@ static int vmx_init_vmcs_config(void)
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MSR_IA32_VMX_PROCBASED_CTLS, &mismatch);
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_vmx_cpu_based_exec_control &= ~CPU_BASED_RDTSC_EXITING;
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#ifdef __x86_64__
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- if ( !(_vmx_cpu_based_exec_control & CPU_BASED_TPR_SHADOW) )
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- {
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- min |= CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING;
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- _vmx_cpu_based_exec_control = adjust_vmx_controls(
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- "CPU-Based Exec Control", min, opt,
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- MSR_IA32_VMX_PROCBASED_CTLS, &mismatch);
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- }
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+ if ( _vmx_cpu_based_exec_control & CPU_BASED_TPR_SHADOW )
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+ _vmx_cpu_based_exec_control &=
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+ ~(CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING);
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#endif
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if ( _vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS )
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