0891920741
51e517e6-AMD-IOMMU-allocate-IRTEs.patch 51e5183f-AMD-IOMMU-untie-remap-and-vector-maps.patch 51e63df6-VMX-fix-interaction-of-APIC-V-and-Viridian-emulation.patch 52146070-ACPI-fix-acpi_os_map_memory.patch 5214d26a-VT-d-warn-about-CFI-being-enabled-by-firmware.patch 5215d094-Nested-VMX-Check-whether-interrupt-is-blocked-by-TPR.patch 5215d0c5-Nested-VMX-Force-check-ISR-when-L2-is-running.patch 5215d135-Nested-VMX-Clear-APIC-v-control-bit-in-vmcs02.patch 5215d2d5-Nested-VMX-Update-APIC-v-RVI-SVI-when-vmexit-to-L1.patch 5215d8b0-Correct-X2-APIC-HVM-emulation.patch - Dropped 520d417d-xen-Add-stdbool.h-workaround-for-BSD.patch OBS-URL: https://build.opensuse.org/package/show/Virtualization/xen?expand=0&rev=267
37 lines
1.3 KiB
Diff
37 lines
1.3 KiB
Diff
# Commit b35d0a26983843c092bfa353fd6b9aa8c3bf4886
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# Date 2013-08-22 10:50:13 +0200
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# Author Yang Zhang <yang.z.zhang@Intel.com>
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# Committer Jan Beulich <jbeulich@suse.com>
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Nested VMX: Force check ISR when L2 is running
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External interrupt is allowed to notify CPU only when it has higher
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priority than current in servicing interrupt. With APIC-v, the priority
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comparing is done by hardware and hardware will inject the interrupt to
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VCPU when it recognizes an interrupt. Currently, there is no virtual
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APIC-v feature available for L1 to use, so when L2 is running, we still need
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to compare interrupt priority with ISR in hypervisor instead via hardware.
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Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com>
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Acked-by: "Dong, Eddie" <eddie.dong@intel.com>
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--- a/xen/arch/x86/hvm/vlapic.c
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+++ b/xen/arch/x86/hvm/vlapic.c
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@@ -37,6 +37,7 @@
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#include <asm/hvm/io.h>
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#include <asm/hvm/support.h>
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#include <asm/hvm/vmx/vmx.h>
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+#include <asm/hvm/nestedhvm.h>
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#include <public/hvm/ioreq.h>
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#include <public/hvm/params.h>
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@@ -1037,7 +1038,8 @@ int vlapic_has_pending_irq(struct vcpu *
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if ( irr == -1 )
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return -1;
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- if ( vlapic_virtual_intr_delivery_enabled() )
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+ if ( vlapic_virtual_intr_delivery_enabled() &&
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+ !nestedhvm_vcpu_in_guestmode(v) )
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return irr;
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isr = vlapic_find_highest_isr(vlapic);
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