4b4fa7f68d
21317-xend-blkif-util-tap2.patch suse-disable-tap2-default.patch - Match upstreams cpu pools switch from domctl to sysctl - Upstream replacements for two of our custom patches (to ease applying further backports) - Fixed dump-exec-state.patch (could previously hang the system, as could - with lower probability - the un-patched implementation) - bnc#593536 - xen hypervisor takes very long to initialize Dom0 on 128 CPUs and 256Gb 21272-x86-dom0-alloc-performance.patch 21266-vmx-disabled-check.patch 21271-x86-cache-flush-global.patch - bnc#558815 - using multiple npiv luns with same wwpn/wwnn broken - bnc#601104 - Xen /etc/xen/scripts/block-npiv script fails when accessing multiple disks using NPIV block-npiv - bnc#595124 - VT-d can not be enabled on 32PAE Xen on Nehalem-EX platform 21234-x86-bad-srat-clear-pxm2node.patch bnc#585371 - kdump fails to load with xen: locate_hole failed 21235-crashkernel-advanced.patch - bnc#588918 - Attaching a U-disk to domain's failed by "xm usb-attach" init.xend OBS-URL: https://build.opensuse.org/package/show/Virtualization/xen?expand=0&rev=44
95 lines
3.1 KiB
Diff
95 lines
3.1 KiB
Diff
# HG changeset patch
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# User Keir Fraser <keir.fraser@citrix.com>
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# Date 1273142634 -3600
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# Node ID 69c85f5b0a07e7a95945d117ea478a80d21c6b9e
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# Parent 26da9bb87405c64c02def8d5f11c66f15847bd02
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svm: support EFER.LMSLE for guests
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Now that the feature is officially documented (see
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http://support.amd.com/us/Processor_TechDocs/24593.pdf), I think it
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makes sense to also allow HVM guests to make use of it.
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Signed-off-by: Jan Beulich <jbeulich@novell.com>
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--- a/xen/arch/x86/hvm/hvm.c
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+++ b/xen/arch/x86/hvm/hvm.c
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@@ -629,11 +629,12 @@ static int hvm_load_cpu_ctxt(struct doma
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return -EINVAL;
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}
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- if ( (ctxt.msr_efer & ~(EFER_FFXSE | EFER_LME | EFER_LMA |
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+ if ( (ctxt.msr_efer & ~(EFER_FFXSE | EFER_LMSLE | EFER_LME | EFER_LMA |
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EFER_NX | EFER_SCE)) ||
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((sizeof(long) != 8) && (ctxt.msr_efer & EFER_LME)) ||
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(!cpu_has_nx && (ctxt.msr_efer & EFER_NX)) ||
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(!cpu_has_syscall && (ctxt.msr_efer & EFER_SCE)) ||
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+ (!cpu_has_lmsl && (ctxt.msr_efer & EFER_LMSLE)) ||
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(!cpu_has_ffxsr && (ctxt.msr_efer & EFER_FFXSE)) ||
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((ctxt.msr_efer & (EFER_LME|EFER_LMA)) == EFER_LMA) )
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{
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@@ -984,10 +985,11 @@ int hvm_set_efer(uint64_t value)
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value &= ~EFER_LMA;
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- if ( (value & ~(EFER_FFXSE | EFER_LME | EFER_NX | EFER_SCE)) ||
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+ if ( (value & ~(EFER_FFXSE | EFER_LMSLE | EFER_LME | EFER_NX | EFER_SCE)) ||
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((sizeof(long) != 8) && (value & EFER_LME)) ||
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(!cpu_has_nx && (value & EFER_NX)) ||
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(!cpu_has_syscall && (value & EFER_SCE)) ||
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+ (!cpu_has_lmsl && (value & EFER_LMSLE)) ||
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(!cpu_has_ffxsr && (value & EFER_FFXSE)) )
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{
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gdprintk(XENLOG_WARNING, "Trying to set reserved bit in "
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--- a/xen/arch/x86/hvm/svm/svm.c
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+++ b/xen/arch/x86/hvm/svm/svm.c
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@@ -56,6 +56,9 @@
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u32 svm_feature_flags;
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+/* Indicates whether guests may use EFER.LMSLE. */
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+bool_t cpu_has_lmsl;
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+
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#define set_segment_register(name, value) \
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asm volatile ( "movw %%ax ,%%" STR(name) "" : : "a" (value) )
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@@ -847,6 +850,29 @@ static int svm_cpu_up(struct cpuinfo_x86
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/* Initialize core's ASID handling. */
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svm_asid_init(c);
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+#ifdef __x86_64__
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+ /*
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+ * Check whether EFER.LMSLE can be written.
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+ * Unfortunately there's no feature bit defined for this.
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+ */
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+ eax = read_efer();
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+ edx = read_efer() >> 32;
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+ if ( wrmsr_safe(MSR_EFER, eax | EFER_LMSLE, edx) == 0 )
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+ rdmsr(MSR_EFER, eax, edx);
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+ if ( eax & EFER_LMSLE )
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+ {
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+ if ( c == &boot_cpu_data )
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+ cpu_has_lmsl = 1;
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+ wrmsr(MSR_EFER, eax ^ EFER_LMSLE, edx);
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+ }
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+ else
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+ {
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+ if ( cpu_has_lmsl )
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+ printk(XENLOG_WARNING "Inconsistent LMLSE support across CPUs!\n");
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+ cpu_has_lmsl = 0;
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+ }
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+#endif
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+
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return 1;
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}
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--- a/xen/include/asm-x86/hvm/hvm.h
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+++ b/xen/include/asm-x86/hvm/hvm.h
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@@ -131,6 +131,7 @@ struct hvm_function_table {
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extern struct hvm_function_table hvm_funcs;
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extern int hvm_enabled;
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+extern bool_t cpu_has_lmsl;
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int hvm_domain_initialise(struct domain *d);
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void hvm_domain_relinquish_resources(struct domain *d);
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