Stefan Dirsch
ac37d6ba51
New package, split from xorg-x11-driver-video OBS-URL: https://build.opensuse.org/request/show/114520 OBS-URL: https://build.opensuse.org/package/show/X11:XOrg/xf86-video-ati?expand=0&rev=1
107 lines
3.3 KiB
Diff
107 lines
3.3 KiB
Diff
Index: xorg-x11-driver-video-7.5/xf86-video-ati-6.13.0/src/radeon_driver.c
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===================================================================
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--- xorg-x11-driver-video-7.5/xf86-video-ati-6.13.0.orig/src/radeon_driver.c
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+++ xorg-x11-driver-video-7.5/xf86-video-ati-6.13.0/src/radeon_driver.c
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@@ -224,6 +224,7 @@ struct RADEONInt10Save {
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uint32_t MEMSIZE;
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uint32_t MPP_TB_CONFIG;
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unsigned char MISC_OUT;
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+ unsigned char ATTR[0x10];
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};
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static Bool RADEONMapMMIO(ScrnInfoPtr pScrn);
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@@ -273,13 +274,67 @@ RADEONEntPtr RADEONEntPriv(ScrnInfoPtr p
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return pPriv->ptr;
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}
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+#if !defined(__powerpc__) && !defined(__sparc__)
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+/*
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+ *
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+ */
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+void
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+RADEONPreInt10SaveVGA(ScrnInfoPtr pScrn, struct RADEONInt10Save *pSave)
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+{
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+ IOADDRESS Base = pScrn->domainIOBase;
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+ unsigned int Stat1Reg;
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+ int i;
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+
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+ pSave->MISC_OUT = inb(pScrn->domainIOBase + RADEON_GENMO_RD);
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+ Stat1Reg = (pSave->MISC_OUT & 0x1) ? 0x3DA : 0x3BA;
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+ {
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+ for (i = 0; i < 0x10; i++) {
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+ inb(Base + Stat1Reg);
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+ outb(Base + RADEON_ATTRX, i);
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+ pSave->ATTR[i] = inb(Base + RADEON_ATTRDR);
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+ }
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+ }
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+}
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+
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+/*
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+ *
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+ */
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+void
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+RADEONPostInt10CheckVGA(ScrnInfoPtr pScrn, struct RADEONInt10Save *pSave)
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+{
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+ IOADDRESS Base = pScrn->domainIOBase;
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+ unsigned int Stat1Reg = (pSave->MISC_OUT & 0x1) ? 0x3DA : 0x3BA;
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+ unsigned char CardTmp = inb(pScrn->domainIOBase + RADEON_GENMO_RD);
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+ int i;
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+
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+ if (CardTmp != pSave->MISC_OUT) {
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+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
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+ "Restoring MiscOut (%x), setting to %x\n",
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+ CardTmp, pSave->MEM_CNTL);
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+ outb(pScrn->domainIOBase + RADEON_GENMO_WT, pSave->MISC_OUT);
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+ }
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+
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+ for (i = 0; i < 0x10; i++) {
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+ inb(Base + Stat1Reg);
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+ outb(Base + RADEON_ATTRX, i);
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+ CardTmp = inb(Base + RADEON_ATTRDR);
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+ if ( CardTmp != pSave->ATTR[i] ) {
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+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
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+ "Restoring AttrReg[0x%i]: 0x%x to 0x%x\n",
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+ i, CardTmp, pSave->ATTR[i]);
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+ outb(Base + RADEON_ATTRDW, pSave->ATTR[i]);
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+ }
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+ }
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+}
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+#endif
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+
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static void
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RADEONPreInt10Save(ScrnInfoPtr pScrn, void **pPtr)
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{
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RADEONInfoPtr info = RADEONPTR(pScrn);
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unsigned char *RADEONMMIO = info->MMIO;
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uint32_t CardTmp;
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- static struct RADEONInt10Save SaveStruct = { 0, 0, 0, 0 };
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+ static struct RADEONInt10Save SaveStruct = { 0, 0, 0, 0, {0} };
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if (!IS_AVIVO_VARIANT) {
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OUTREG(0,RADEON_MEM_CNTL);
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@@ -287,8 +342,9 @@ RADEONPreInt10Save(ScrnInfoPtr pScrn, vo
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SaveStruct.MEM_CNTL = INREG(RADEON_MEM_CNTL);
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SaveStruct.MEMSIZE = INREG(RADEON_CONFIG_MEMSIZE);
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SaveStruct.MPP_TB_CONFIG = INREG(RADEON_MPP_TB_CONFIG);
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+
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#if !defined(__powerpc__) && !defined(__sparc__)
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- SaveStruct.MISC_OUT = inb(pScrn->domainIOBase + RADEON_GENMO_RD);
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+ RADEONPreInt10SaveVGA(pScrn, &SaveStruct);
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#endif
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/*
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* Zap MEM_CNTL and set MPP_TB_CONFIG<31:24> to 4
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@@ -352,12 +408,7 @@ RADEONPostInt10Check(ScrnInfoPtr pScrn,
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OUTREG(RADEON_MPP_TB_CONFIG, CardTmp);
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}
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#if !defined(__powerpc__) && !defined(__sparc__)
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- if (CardTmp != pSave->MISC_OUT) {
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- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
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- "Restoring MiscOut (%x), setting to %x\n",
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- CardTmp, pSave->MEM_CNTL);
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- outb(pScrn->domainIOBase + RADEON_GENMO_WT, pSave->MISC_OUT);
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- }
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+ RADEONPostInt10CheckVGA(pScrn, pSave);
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#endif
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}
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