diff --git a/x86/adler32.c b/x86/adler32.c
index 3f66f54..a941438 100644
--- a/x86/adler32.c
+++ b/x86/adler32.c
@@ -20,6 +20,19 @@
 #  define VEC_NO_GO
 #endif
 
+#if GCC_VERSION_GE(404)
+#define GCC_ATTR_MMX    __attribute__((__target__("mmx")))
+#define GCC_ATTR_SSE    __attribute__((__target__("sse")))
+#define GCC_ATTR_SSE2   __attribute__((__target__("sse2")))
+#define GCC_ATTR_SSSE3  __attribute__((__target__("ssse3")))
+#else
+#define GCC_ATTR_MMX
+#define GCC_ATTR_SSE
+#define GCC_ATTR_SSE2
+#define GCC_ATTR_SSSE3
+#endif
+
+
 /* inline asm, so only on GCC (or compatible) */
 #if defined(__GNUC__) && !defined(VEC_NO_GO)
 #  define HAVE_ADLER32_VEC
@@ -240,7 +253,7 @@ local noinline const Bytef *adler32_jumped(buf, s1, s2, k)
 #endif
 
 /* ========================================================================= */
-local uLong adler32_SSSE3(adler, buf, len)
+local GCC_ATTR_SSSE3 uLong adler32_SSSE3(adler, buf, len)
     uLong adler;
     const Bytef *buf;
     uInt len;
@@ -383,7 +396,7 @@ local uLong adler32_SSSE3(adler, buf, len)
 }
 
 /* ========================================================================= */
-local uLong adler32_SSE2(adler, buf, len)
+local GCC_ATTR_SSE2 uLong adler32_SSE2(adler, buf, len)
     uLong adler;
     const Bytef *buf;
     uInt len;
@@ -604,7 +617,7 @@ local noinline uLong adler32_SSE2_no_oooe(adler, buf, len)
 /*
  * SSE version to help VIA-C3_2, P2 & P3
  */
-local uLong adler32_SSE(adler, buf, len)
+local GCC_ATTR_SSE uLong adler32_SSE(adler, buf, len)
     uLong adler;
     const Bytef *buf;
     uInt len;
@@ -740,7 +753,7 @@ local uLong adler32_SSE(adler, buf, len)
  * (maybe except AMD K6, Cyrix, Winchip/VIA).
  * I did my best to get at least 1 instruction between result -> use
  */
-local uLong adler32_MMX(adler, buf, len)
+local GCC_ATTR_MMX uLong adler32_MMX(adler, buf, len)
     uLong adler;
     const Bytef *buf;
     uInt len;