diff --git a/Mesa.changes b/Mesa.changes index deab0b2..5ecc891 100644 --- a/Mesa.changes +++ b/Mesa.changes @@ -1,3 +1,11 @@ +------------------------------------------------------------------- +Mon Jul 29 12:55:23 UTC 2013 - sndirsch@suse.com + +- Make a symlink to libGL.so.1.2 for compatibility (bnc#809359, + bnc#831306) +- u_mesa-9.0-i965-Make-sure-we-do-render-between-two-hiz-flushes.patch + * Prevent hangs with rc6. (bnc#804910, bnc#831306) + ------------------------------------------------------------------- Thu Jul 25 15:41:25 UTC 2013 - dvaleev@suse.com diff --git a/Mesa.spec b/Mesa.spec index b2311e4..65c2e00 100644 --- a/Mesa.spec +++ b/Mesa.spec @@ -108,6 +108,7 @@ Patch14: u_mesa-glapi_dispatch.patch Patch15: u_mesa-8.0-llvmpipe-shmget.patch # PATCH-FIX-UPSTREAM gallium-egl-gbm-use-wayland-cflags.patch -- use pkgconfig for finding wayland Patch16: U_gallium-egl-gbm-use-wayland-cflags.patch +Patch17: u_mesa-9.0-i965-Make-sure-we-do-render-between-two-hiz-flushes.patch BuildRoot: %{_tmppath}/%{name}-%{version}-build @@ -542,6 +543,7 @@ rm -rf docs/README.{VMS,WIN32,OS2} %if %egl_gallium %patch16 -p1 %endif +%patch17 -p1 %build @@ -606,6 +608,11 @@ autoreconf -fi make %{?_smp_mflags} make install DESTDIR=$RPM_BUILD_ROOT find $RPM_BUILD_ROOT -name "*.la" -exec rm {} \; + +# Make a symlink to libGL.so.1.2 for compatibility (bnc#809359, bnc#831306) +test -f $RPM_BUILD_ROOT%{_libdir}/libGL.so.1.2 || \ + ln -s `readlink $RPM_BUILD_ROOT%{_libdir}/libGL.so.1` $RPM_BUILD_ROOT%{_libdir}/libGL.so.1.2 + # build and install Indirect Rendering only libGL #### make distclean-generic diff --git a/u_mesa-9.0-i965-Make-sure-we-do-render-between-two-hiz-flushes.patch b/u_mesa-9.0-i965-Make-sure-we-do-render-between-two-hiz-flushes.patch new file mode 100644 index 0000000..8594f7a --- /dev/null +++ b/u_mesa-9.0-i965-Make-sure-we-do-render-between-two-hiz-flushes.patch @@ -0,0 +1,81 @@ +From 1547bb37e97c8d7069d5be4e8b9b0d34ac28f7e1 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?St=C3=A9phane=20Marchesin?= +Date: Tue, 17 Apr 2012 18:17:35 -0700 +Subject: [PATCH 2/2] i965: Make sure we do render between two hiz flushes + +Hiz flushes touch the URB allocation, which doesn't work if you don't +draw in between. This includes on startup where the GPU hasn't been +used and we lockup. To avoid this situation make sure that some +primitives get rendered before every hiz flush. +--- + src/mesa/drivers/dri/i965/brw_context.c | 1 + + src/mesa/drivers/dri/i965/brw_context.h | 1 + + src/mesa/drivers/dri/i965/brw_draw.c | 12 +++++++++--- + 3 files changed, 11 insertions(+), 3 deletions(-) + +Index: mesa-9.1.98.01/src/mesa/drivers/dri/i965/brw_context.c +=================================================================== +--- mesa-9.1.98.01.orig/src/mesa/drivers/dri/i965/brw_context.c ++++ mesa-9.1.98.01/src/mesa/drivers/dri/i965/brw_context.c +@@ -410,6 +410,7 @@ brwCreateContext(int api, + brw->urb.max_gs_entries = 256; + } + brw->urb.gen6_gs_previously_active = false; ++ brw->urb.prims_since_last_flush = 0; + } else if (brw->gen == 5) { + brw->urb.size = 1024; + brw->max_vs_threads = 72; +Index: mesa-9.1.98.01/src/mesa/drivers/dri/i965/brw_context.h +=================================================================== +--- mesa-9.1.98.01.orig/src/mesa/drivers/dri/i965/brw_context.h ++++ mesa-9.1.98.01/src/mesa/drivers/dri/i965/brw_context.h +@@ -1000,6 +1000,7 @@ struct brw_context + * URB space for the GS. + */ + bool gen6_gs_previously_active; ++ int prims_since_last_flush; + } urb; + + +Index: mesa-9.1.98.01/src/mesa/drivers/dri/i965/brw_draw.c +=================================================================== +--- mesa-9.1.98.01.orig/src/mesa/drivers/dri/i965/brw_draw.c ++++ mesa-9.1.98.01/src/mesa/drivers/dri/i965/brw_draw.c +@@ -294,10 +294,14 @@ static void brw_merge_inputs( struct brw + * Resolve the depth buffer's HiZ buffer and resolve the depth buffer of each + * enabled depth texture. + * ++ * We don't resolve the depth buffer's HiZ if no primitives have been drawn ++ * since the last flush. This avoids a case where we lockup the GPU on boot ++ * when this is the first thing we do. ++ * + * (In the future, this will also perform MSAA resolves). + */ + static void +-brw_predraw_resolve_buffers(struct brw_context *brw) ++brw_predraw_resolve_buffers(struct brw_context *brw, int nr_prims) + { + struct gl_context *ctx = &brw->ctx; + struct intel_renderbuffer *depth_irb; +@@ -305,9 +309,11 @@ brw_predraw_resolve_buffers(struct brw_c + + /* Resolve the depth buffer's HiZ buffer. */ + depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH); +- if (depth_irb) ++ if (depth_irb && brw->urb.prims_since_last_flush > 0 ) + intel_renderbuffer_resolve_hiz(brw, depth_irb); + ++ brw->urb.prims_since_last_flush = nr_prims; ++ + /* Resolve depth buffer of each enabled depth texture, and color buffer of + * each fast-clear-enabled color texture. + */ +@@ -390,7 +396,7 @@ static bool brw_try_draw_prims( struct g + * and finalizing textures but before setting up any hardware state for + * this draw call. + */ +- brw_predraw_resolve_buffers(brw); ++ brw_predraw_resolve_buffers(brw, nr_prims); + + /* Bind all inputs, derive varying and size information: + */