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- u_llvmpipe-lp_build_gather_elem_vec-BE-fix-for-3x16-lo.patch

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updated; fixes three of the four regressions observed (PPC64, S390)
  [fdo#100613, comment#42]

OBS-URL: https://build.opensuse.org/package/show/X11:XOrg/Mesa?expand=0&rev=638
This commit is contained in:
Stefan Dirsch 2017-08-23 09:26:16 +00:00 committed by Git OBS Bridge
parent 68b1e7965c
commit 85877492fd
2 changed files with 83 additions and 49 deletions
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Mesa.changes
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@ -1,3 +1,10 @@
-------------------------------------------------------------------
Wed Aug 23 09:01:46 UTC 2017 - sndirsch@suse.com
- u_llvmpipe-lp_build_gather_elem_vec-BE-fix-for-3x16-lo.patch
updated; fixes three of the four regressions observed (PPC64, S390)
[fdo#100613, comment#42]
------------------------------------------------------------------- -------------------------------------------------------------------
Mon Aug 14 17:16:34 UTC 2017 - jberry@suse.com Mon Aug 14 17:16:34 UTC 2017 - jberry@suse.com

43
u_llvmpipe-lp_build_gather_elem_vec-BE-fix-for-3x16-lo.patch
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@ -1,21 +1,35 @@
From 3f993cdf6db5cf344179fcb4fbf899f6ef9a6b2b Mon Sep 17 00:00:00 2001 From d3135d11bb77235324a21ccaa23be6df836c9870 Mon Sep 17 00:00:00 2001
From: Ben Crocker <bcrocker@redhat.com> From: Ben Crocker <bcrocker@redhat.com>
Date: Tue, 30 May 2017 12:34:23 -0400 Date: Tue, 22 Aug 2017 13:43:29 -0400
Subject: [PATCH] llvmpipe: lp_build_gather_elem_vec BE fix for 3x16 load Subject: [PATCH] llvmpipe: lp_build_gather_elem_vec BE fix for 3x16 load
Fix loading of a 3x16 vector as a single 48-bit load Fix loading of a 3x16 vector as a single 48-bit load
on big-endian systems (PPC64, S390). on big-endian systems (PPC64, S390).
Roland Scheidegger's commit e827d9175675aaa6cfc0b981e2a80685fb7b3a74
plus Ray Strode's patch reduce pre-Roland Piglit failures from ~4000 to ~2000.
This patch fixes three of the four regressions observed by Ray:
- draw-vertices
- draw-vertices-half-float
- draw-vertices-half-float_gles2
One regression remains:
- draw-vertices-2101010
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100613
Cc: "17.2" "17.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ben Crocker <bcrocker@redhat.com> Signed-off-by: Ben Crocker <bcrocker@redhat.com>
--- ---
src/gallium/auxiliary/gallivm/lp_bld_gather.c | 17 +++++++++++++++-- src/gallium/auxiliary/gallivm/lp_bld_gather.c | 30 +++++++++++++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-) 1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_gather.c b/src/gallium/auxiliary/gallivm/lp_bld_gather.c diff --git a/src/gallium/auxiliary/gallivm/lp_bld_gather.c b/src/gallium/auxiliary/gallivm/lp_bld_gather.c
index ccd0376..8e56e42 100644 index ccd0376..7d11dcd 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_gather.c --- a/src/gallium/auxiliary/gallivm/lp_bld_gather.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_gather.c +++ b/src/gallium/auxiliary/gallivm/lp_bld_gather.c
@@ -234,13 +234,26 @@ lp_build_gather_elem_vec(struct gallivm_state *gallivm, @@ -234,13 +234,39 @@ lp_build_gather_elem_vec(struct gallivm_state *gallivm,
*/ */
res = LLVMBuildZExt(gallivm->builder, res, dst_elem_type, ""); res = LLVMBuildZExt(gallivm->builder, res, dst_elem_type, "");
@ -28,15 +42,28 @@ index ccd0376..8e56e42 100644
-#endif -#endif
} }
+ if (src_width == 48) { + if (src_width == 48) {
+ /* Load 3x16 bit vector.
+ * The sequence of loads on big-endian hardware proceeds as follows.
+ * 16-bit fields are denoted by X, Y, Z, and 0. In memory, the sequence
+ * of three fields appears in the order X, Y, Z.
+ *
+ * Load 32-bit word: 0.0.X.Y
+ * Load 16-bit halfword: 0.0.0.Z
+ * Rotate left: 0.X.Y.0
+ * Bitwise OR: 0.X.Y.Z
+ *
+ * The order in which we need the fields in the result is 0.Z.Y.X,
+ * the same as on little-endian; permute 16-bit fields accordingly
+ * within 64-bit register:
+ */
+ LLVMValueRef shuffles[4] = { + LLVMValueRef shuffles[4] = {
+ lp_build_const_int32(gallivm, 2), + lp_build_const_int32(gallivm, 2),
+ lp_build_const_int32(gallivm, 1), + lp_build_const_int32(gallivm, 1),
+ lp_build_const_int32(gallivm, 0), + lp_build_const_int32(gallivm, 0),
+ lp_build_const_int32(gallivm, 3), + lp_build_const_int32(gallivm, 3),
+ }; + };
+ struct lp_type type16 = {FALSE, FALSE, TRUE, FALSE, 16, 4};
+ res = LLVMBuildBitCast(gallivm->builder, res, + res = LLVMBuildBitCast(gallivm->builder, res,
+ lp_build_vec_type(gallivm, type16), ""); + lp_build_vec_type(gallivm, lp_type_uint_vec(16, 4*16)), "");
+ res = LLVMBuildShuffleVector(gallivm->builder, res, res, LLVMConstVector(shuffles, 4), ""); + res = LLVMBuildShuffleVector(gallivm->builder, res, res, LLVMConstVector(shuffles, 4), "");
+ res = LLVMBuildBitCast(gallivm->builder, res, dst_elem_type, ""); + res = LLVMBuildBitCast(gallivm->builder, res, dst_elem_type, "");
+ } + }