Stefan Dirsch
34c3675d67
Added U_radeon-pad-CS-to-8-DW.patch from upstream -- aligns the IB to 8 DWs. r6xx also require at least 4 DW alignment to avoid a hw bug. OBS-URL: https://build.opensuse.org/request/show/199428 OBS-URL: https://build.opensuse.org/package/show/X11:XOrg/Mesa?expand=0&rev=327
69 lines
2.5 KiB
Diff
69 lines
2.5 KiB
Diff
From a81beee37e0dd7b75422448420e8e8b0b4b76c1e Mon Sep 17 00:00:00 2001
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From: Alex Deucher <alexander.deucher@amd.com>
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Date: Fri, 6 Sep 2013 16:43:34 -0400
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Subject: [PATCH 1/1] radeon/winsys: pad IBs to a multiple of 8 DWs
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This aligns the gfx, compute, and dma IBs to 8 DW boundries.
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This aligns the the IB to the fetch size of the CP for optimal
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performance. Additionally, r6xx hardware requires at least 4
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DW alignment to avoid a hw bug. This also aligns the DMA
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IBs to 8 DW which is required for the DMA engine. This
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alignment is already handled in the gallium driver, but that
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patch can be removed now that it's done in the winsys.
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Reviewed-by: Marek Olšák <marek.olsak@amd.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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CC: "9.2" <mesa-stable@lists.freedesktop.org>
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CC: "9.1" <mesa-stable@lists.freedesktop.org>
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---
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src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 30 +++++++++++++++++++++++++++
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1 file changed, 30 insertions(+)
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diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
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index ea0c99d..38a9209 100644
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--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
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+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
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@@ -466,6 +466,36 @@ static void radeon_drm_cs_flush(struct radeon_winsys_cs *rcs, unsigned flags, ui
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struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
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struct radeon_cs_context *tmp;
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+ switch (cs->base.ring_type) {
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+ case RING_DMA:
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+ /* pad DMA ring to 8 DWs */
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+ if (cs->ws->info.chip_class <= SI) {
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+ while (rcs->cdw & 7)
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+ OUT_CS(&cs->base, 0xf0000000); /* NOP packet */
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+ } else {
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+ while (rcs->cdw & 7)
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+ OUT_CS(&cs->base, 0x00000000); /* NOP packet */
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+ }
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+ break;
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+ case RING_GFX:
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+ /* pad DMA ring to 8 DWs to meet CP fetch alignment requirements
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+ * r6xx, requires at least 4 dw alignment to avoid a hw bug.
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+ */
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+ if (flags & RADEON_FLUSH_COMPUTE) {
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+ if (cs->ws->info.chip_class <= SI) {
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+ while (rcs->cdw & 7)
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+ OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */
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+ } else {
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+ while (rcs->cdw & 7)
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+ OUT_CS(&cs->base, 0xffff1000); /* type3 nop packet */
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+ }
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+ } else {
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+ while (rcs->cdw & 7)
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+ OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */
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+ }
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+ break;
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+ }
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+
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if (rcs->cdw > RADEON_MAX_CMDBUF_DWORDS) {
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fprintf(stderr, "radeon: command stream overflowed\n");
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}
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--
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1.8.4
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