diff --git a/0001-S-390-Add-support-for-IBM-z13.patch b/0001-S-390-Add-support-for-IBM-z13.patch deleted file mode 100644 index def19d6..0000000 --- a/0001-S-390-Add-support-for-IBM-z13.patch +++ /dev/null @@ -1,3882 +0,0 @@ -From cc5ebfb54ec5d26e0ff2f1c01f833eb8d6b09e69 Mon Sep 17 00:00:00 2001 -From: Andreas Krebbel -Date: Fri, 16 Jan 2015 12:19:21 +0100 -Subject: [PATCH 1/5] S/390: Add support for IBM z13. - -- 32 128 bit vector registers (overlapping with the existing 16 64 bit - floating point registers) -- vector double instructions -- vector integer instructions -- scalar vector instructions (allowing to have more floating point - registers for scalar operations) -- vector string instructions - -gas/ChangeLog: - - * config/tc-s390.c (struct pd_reg): Remove. - (pre_defined_registers): Remove. - (REG_NAME_CNT): Remove. - (reg_name_search): Calculate the register number instead of doing - a lookup. - (register_name, tc_s390_regname_to_dw2regnum): Adopt to the new - reg_name_search signature. - (s390_parse_cpu): Support the new arch string z13. - (s390_insert_operand): Support for vector registers with the extra - field for the fifth bit of each vector register operand. - (md_gather_operand): Adjust to the new handling of optional - parameters. - - * doc/as.texinfo: Document the z13 cpu string. - -gas/testsuite/ChangeLog: - - * gas/s390/esa-g5.d: Add a variant without the optional operand. - * gas/s390/esa-g5.s: Likewise. - * gas/s390/esa-z9-109.d: Likewise. - * gas/s390/esa-z9-109.s: Likewise. - * gas/s390/zarch-z9-109.d: Likewise. - * gas/s390/zarch-z9-109.s: Likewise. - * gas/s390/zarch-z10.d: For variants with a zero optional argument - it is not dumped by objdump anymore. - * gas/s390/zarch-zEC12.d: Likewise. - - * gas/s390/zarch-z13.d: New file. - * gas/s390/zarch-z13.s: New file. - * gas/s390/s390.exp: Run the test for the z13 files. - -include/opcode/ChangeLog: - - * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13. - -ld/testsuite/ChangeLog: - - * ld-s390/tlsbin.dd: The nopr register operand is optional and not - printed if 0 anymore. - -opcodes/ChangeLog: - - * s390-dis.c (s390_extract_operand): Support vector register - operands. - (s390_print_insn_with_opcode): Support new operands types and add - new handling of optional operands. - * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove - and include opcode/s390.h instead. - (struct op_struct): New field `flags'. - (insertOpcode, insertExpandedMnemonic): New parameter `flags'. - (dumpTable): Dump flags. - (main): Parse flags from the s390-opc.txt file. Add z13 as cpu - string. - * s390-opc.c: Add new operands types, instruction formats, and - instruction masks. - (s390_opformats): Add new formats for .insn. - * s390-opc.txt: Add new instructions. - -# Conflicts: -# gas/ChangeLog -# gas/testsuite/ChangeLog -# include/opcode/ChangeLog -# ld/testsuite/ChangeLog -# opcodes/ChangeLog ---- - gas/config/tc-s390.c | 202 +++---- - gas/doc/as.texinfo | 2 +- - gas/doc/c-s390.texi | 8 +- - gas/testsuite/gas/s390/esa-g5.d | 44 +- - gas/testsuite/gas/s390/esa-g5.s | 2 + - gas/testsuite/gas/s390/esa-z9-109.d | 4 + - gas/testsuite/gas/s390/esa-z9-109.s | 4 + - gas/testsuite/gas/s390/s390.exp | 1 + - gas/testsuite/gas/s390/zarch-z10.d | 4 +- - gas/testsuite/gas/s390/zarch-z13.d | 548 +++++++++++++++++++ - gas/testsuite/gas/s390/zarch-z13.s | 542 +++++++++++++++++++ - gas/testsuite/gas/s390/zarch-z9-109.d | 5 + - gas/testsuite/gas/s390/zarch-z9-109.s | 5 + - gas/testsuite/gas/s390/zarch-zEC12.d | 2 +- - include/opcode/s390.h | 23 +- - ld/testsuite/ld-s390/tlsbin.dd | 12 +- - opcodes/s390-dis.c | 50 +- - opcodes/s390-mkopc.c | 151 +++--- - opcodes/s390-opc.c | 965 +++++++++++++++++++--------------- - opcodes/s390-opc.txt | 549 ++++++++++++++++++- - 20 files changed, 2432 insertions(+), 691 deletions(-) - create mode 100644 gas/testsuite/gas/s390/zarch-z13.d - create mode 100644 gas/testsuite/gas/s390/zarch-z13.s - -diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c -index 59f6ab6..052baf1 100644 ---- a/gas/config/tc-s390.c -+++ b/gas/config/tc-s390.c -@@ -109,138 +109,35 @@ const pseudo_typeS md_pseudo_table[] = - { NULL, NULL, 0 } - }; - -- --/* Structure to hold information about predefined registers. */ --struct pd_reg -- { -- char *name; -- int value; -- }; -- --/* List of registers that are pre-defined: -- -- Each access register has a predefined name of the form: -- a which has the value . -- -- Each control register has a predefined name of the form: -- c which has the value . -- -- Each general register has a predefined name of the form: -- r which has the value . -- -- Each floating point register a has predefined name of the form: -- f which has the value . -- -- There are individual registers as well: -- sp has the value 15 -- lit has the value 12 -- -- The table is sorted. Suitable for searching by a binary search. */ -- --static const struct pd_reg pre_defined_registers[] = --{ -- { "a0", 0 }, /* Access registers */ -- { "a1", 1 }, -- { "a10", 10 }, -- { "a11", 11 }, -- { "a12", 12 }, -- { "a13", 13 }, -- { "a14", 14 }, -- { "a15", 15 }, -- { "a2", 2 }, -- { "a3", 3 }, -- { "a4", 4 }, -- { "a5", 5 }, -- { "a6", 6 }, -- { "a7", 7 }, -- { "a8", 8 }, -- { "a9", 9 }, -- -- { "c0", 0 }, /* Control registers */ -- { "c1", 1 }, -- { "c10", 10 }, -- { "c11", 11 }, -- { "c12", 12 }, -- { "c13", 13 }, -- { "c14", 14 }, -- { "c15", 15 }, -- { "c2", 2 }, -- { "c3", 3 }, -- { "c4", 4 }, -- { "c5", 5 }, -- { "c6", 6 }, -- { "c7", 7 }, -- { "c8", 8 }, -- { "c9", 9 }, -- -- { "f0", 0 }, /* Floating point registers */ -- { "f1", 1 }, -- { "f10", 10 }, -- { "f11", 11 }, -- { "f12", 12 }, -- { "f13", 13 }, -- { "f14", 14 }, -- { "f15", 15 }, -- { "f2", 2 }, -- { "f3", 3 }, -- { "f4", 4 }, -- { "f5", 5 }, -- { "f6", 6 }, -- { "f7", 7 }, -- { "f8", 8 }, -- { "f9", 9 }, -- -- { "lit", 13 }, /* Pointer to literal pool */ -- -- { "r0", 0 }, /* General purpose registers */ -- { "r1", 1 }, -- { "r10", 10 }, -- { "r11", 11 }, -- { "r12", 12 }, -- { "r13", 13 }, -- { "r14", 14 }, -- { "r15", 15 }, -- { "r2", 2 }, -- { "r3", 3 }, -- { "r4", 4 }, -- { "r5", 5 }, -- { "r6", 6 }, -- { "r7", 7 }, -- { "r8", 8 }, -- { "r9", 9 }, -- -- { "sp", 15 }, /* Stack pointer */ -- --}; -- --#define REG_NAME_CNT (sizeof (pre_defined_registers) / sizeof (struct pd_reg)) -- - /* Given NAME, find the register number associated with that name, return - the integer value associated with the given name or -1 on failure. */ - - static int --reg_name_search (const struct pd_reg *regs, int regcount, const char *name) -+reg_name_search (const char *name) - { -- int middle, low, high; -- int cmp; -+ int val = -1; - -- low = 0; -- high = regcount - 1; -+ if (strcasecmp (name, "lit") == 0) -+ return 13; - -- do -+ if (strcasecmp (name, "sp") == 0) -+ return 15; -+ -+ if (name[0] != 'a' && name[0] != 'c' && name[0] != 'f' -+ && name[0] != 'r' && name[0] != 'v') -+ return -1; -+ -+ if (ISDIGIT (name[1])) - { -- middle = (low + high) / 2; -- cmp = strcasecmp (name, regs[middle].name); -- if (cmp < 0) -- high = middle - 1; -- else if (cmp > 0) -- low = middle + 1; -- else -- return regs[middle].value; -+ val = name[1] - '0'; -+ if (ISDIGIT (name[2])) -+ val = val * 10 + name[2] - '0'; - } -- while (low <= high); - -- return -1; -+ if ((name[0] != 'v' && val > 15) || val > 31) -+ val = -1; -+ -+ return val; - } - - -@@ -272,7 +169,7 @@ register_name (expressionS *expressionP) - return FALSE; - - c = get_symbol_end (); -- reg_number = reg_name_search (pre_defined_registers, REG_NAME_CNT, name); -+ reg_number = reg_name_search (name); - - /* Put back the delimiting char. */ - *input_line_pointer = c; -@@ -382,6 +279,8 @@ s390_parse_cpu (char *arg) - return S390_OPCODE_Z196; - else if (strcmp (arg, "zEC12") == 0) - return S390_OPCODE_ZEC12; -+ else if (strcmp (arg, "z13") == 0) -+ return S390_OPCODE_Z13; - else if (strcmp (arg, "all") == 0) - return S390_OPCODE_MAXCPU - 1; - else -@@ -633,6 +532,12 @@ s390_insert_operand (unsigned char *insn, - max = (((addressT) 1 << (operand->bits - 1)) << 1) - 1; - min = (offsetT) 0; - uval = (addressT) val; -+ -+ /* Vector register operands have an additional bit in the RXB -+ field. */ -+ if (operand->flags & S390_OPERAND_VR) -+ max = (max << 1) | 1; -+ - /* Length x in an instructions has real length x+1. */ - if (operand->flags & S390_OPERAND_LENGTH) - uval--; -@@ -652,6 +557,43 @@ s390_insert_operand (unsigned char *insn, - } - } - -+ if (operand->flags & S390_OPERAND_VR) -+ { -+ /* Insert the extra bit into the RXB field. */ -+ switch (operand->shift) -+ { -+ case 8: -+ insn[4] |= (uval & 0x10) >> 1; -+ break; -+ case 12: -+ insn[4] |= (uval & 0x10) >> 2; -+ break; -+ case 16: -+ insn[4] |= (uval & 0x10) >> 3; -+ break; -+ case 32: -+ insn[4] |= (uval & 0x10) >> 4; -+ break; -+ } -+ uval &= 0xf; -+ } -+ -+ if (operand->flags & S390_OPERAND_OR1) -+ uval |= 1; -+ if (operand->flags & S390_OPERAND_OR2) -+ uval |= 2; -+ if (operand->flags & S390_OPERAND_OR8) -+ uval |= 8; -+ -+ /* Duplicate the operand at bit pos 12 to 16. */ -+ if (operand->flags & S390_OPERAND_CP16) -+ { -+ /* Copy VR operand at bit pos 12 to bit pos 16. */ -+ insn[2] |= uval << 4; -+ /* Copy the flag in the RXB field. */ -+ insn[4] |= (insn[4] & 4) >> 1; -+ } -+ - /* Insert fragments of the operand byte for byte. */ - offset = operand->shift + operand->bits; - uval <<= (-offset) & 7; -@@ -1206,6 +1148,14 @@ md_gather_operands (char *str, - - operand = s390_operands + *opindex_ptr; - -+ if ((opcode->flags & S390_INSTR_FLAG_OPTPARM) && *str == '\0') -+ { -+ /* Optional parameters might need to be ORed with a -+ value so calling s390_insert_operand is needed. */ -+ s390_insert_operand (insn, operand, 0, NULL, 0); -+ break; -+ } -+ - if (skip_optional && (operand->flags & S390_OPERAND_INDEX)) - { - /* We do an early skip. For D(X,B) constructions the index -@@ -1477,6 +1427,10 @@ md_gather_operands (char *str, - as_bad (_("syntax error; ')' not allowed here")); - str++; - } -+ -+ if ((opcode->flags & S390_INSTR_FLAG_OPTPARM) && *str == '\0') -+ continue; -+ - /* If there is a next operand it must be separated by a comma. */ - if (opindex_ptr[1] != '\0') - { -@@ -2499,7 +2453,7 @@ tc_s390_regname_to_dw2regnum (char *regname) - - if (regname[0] != 'c' && regname[0] != 'a') - { -- regnum = reg_name_search (pre_defined_registers, REG_NAME_CNT, regname); -+ regnum = reg_name_search (regname); - if (regname[0] == 'f' && regnum != -1) - regnum += 16; - } -diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo -index 243851b..2c7d71e 100644 ---- a/gas/doc/as.texinfo -+++ b/gas/doc/as.texinfo -@@ -1589,7 +1589,7 @@ Architecture (esa) or the z/Architecture mode (zarch). - @item -march=@var{processor} - Specify which s390 processor variant is the target, @samp{g6}, @samp{g6}, - @samp{z900}, @samp{z990}, @samp{z9-109}, @samp{z9-ec}, @samp{z10}, --@samp{z196}, or @samp{zEC12}. -+@samp{z196}, @samp{zEC12}, or @samp{z13}. - @item -mregnames - @itemx -mno-regnames - Allow or disallow symbolic names for registers. -diff --git a/gas/doc/c-s390.texi b/gas/doc/c-s390.texi -index a4fdf4a..a70f21b 100644 ---- a/gas/doc/c-s390.texi -+++ b/gas/doc/c-s390.texi -@@ -16,7 +16,7 @@ - The s390 version of @code{@value{AS}} supports two architectures modes - and seven chip levels. The architecture modes are the Enterprise System - Architecture (ESA) and the newer z/Architecture mode. The chip levels --are g5, g6, z900, z990, z9-109, z9-ec, z10, z196, and zEC12. -+are g5, g6, z900, z990, z9-109, z9-ec, z10, z196, zEC12, and z13. - - @menu - * s390 Options:: Command-line Options. -@@ -64,8 +64,10 @@ are recognized: - @code{z990}, - @code{z9-109}, - @code{z9-ec}, --@code{z10} and --@code{z196}. -+@code{z10}, -+@code{z196}, -+@code{zEC12}, and -+@code{z13}. - Assembling an instruction that is not supported on the target processor - results in an error message. Do not specify @code{g5} or @code{g6} - with @samp{-mzarch}. -diff --git a/gas/testsuite/gas/s390/esa-g5.d b/gas/testsuite/gas/s390/esa-g5.d -index 2896966..2ea72b1 100644 ---- a/gas/testsuite/gas/s390/esa-g5.d -+++ b/gas/testsuite/gas/s390/esa-g5.d -@@ -157,6 +157,7 @@ Disassembly of section .text: - .*: de ff 5f ff af ff [ ]*ed 4095\(256,%r5\),4095\(%r10\) - .*: df ff 5f ff af ff [ ]*edmk 4095\(256,%r5\),4095\(%r10\) - .*: b3 8c 00 69 [ ]*efpc %r6,%r9 -+.*: b3 8c 00 60 [ ]*efpc %r6 - .*: b2 26 00 60 [ ]*epar %r6 - .*: b2 49 00 69 [ ]*ereg %r6,%r9 - .*: b2 27 00 60 [ ]*esar %r6 -@@ -179,27 +180,27 @@ Disassembly of section .text: - .*: b2 21 00 69 [ ]*ipte %r6,%r9 - .*: b2 29 00 69 [ ]*iske %r6,%r9 - .*: b2 23 00 69 [ ]*ivsk %r6,%r9 --.*: a7 f4 00 00 [ ]*j 274 --.*: a7 84 00 00 [ ]*je 278 --.*: a7 24 00 00 [ ]*jh 27c --.*: a7 a4 00 00 [ ]*jhe 280 --.*: a7 44 00 00 [ ]*jl 284 --.*: a7 c4 00 00 [ ]*jle 288 --.*: a7 64 00 00 [ ]*jlh 28c --.*: a7 44 00 00 [ ]*jl 290 --.*: a7 74 00 00 [ ]*jne 294 --.*: a7 d4 00 00 [ ]*jnh 298 --.*: a7 54 00 00 [ ]*jnhe 29c --.*: a7 b4 00 00 [ ]*jnl 2a0 --.*: a7 34 00 00 [ ]*jnle 2a4 --.*: a7 94 00 00 [ ]*jnlh 2a8 --.*: a7 b4 00 00 [ ]*jnl 2ac --.*: a7 e4 00 00 [ ]*jno 2b0 --.*: a7 d4 00 00 [ ]*jnh 2b4 --.*: a7 74 00 00 [ ]*jne 2b8 --.*: a7 14 00 00 [ ]*jo 2bc --.*: a7 24 00 00 [ ]*jh 2c0 --.*: a7 84 00 00 [ ]*je 2c4 -+.*: a7 f4 00 00 [ ]*j 278 -+.*: a7 84 00 00 [ ]*je 27c -+.*: a7 24 00 00 [ ]*jh 280 -+.*: a7 a4 00 00 [ ]*jhe 284 -+.*: a7 44 00 00 [ ]*jl 288 -+.*: a7 c4 00 00 [ ]*jle 28c -+.*: a7 64 00 00 [ ]*jlh 290 -+.*: a7 44 00 00 [ ]*jl 294 -+.*: a7 74 00 00 [ ]*jne 298 -+.*: a7 d4 00 00 [ ]*jnh 29c -+.*: a7 54 00 00 [ ]*jnhe 2a0 -+.*: a7 b4 00 00 [ ]*jnl 2a4 -+.*: a7 34 00 00 [ ]*jnle 2a8 -+.*: a7 94 00 00 [ ]*jnlh 2ac -+.*: a7 b4 00 00 [ ]*jnl 2b0 -+.*: a7 e4 00 00 [ ]*jno 2b4 -+.*: a7 d4 00 00 [ ]*jnh 2b8 -+.*: a7 74 00 00 [ ]*jne 2bc -+.*: a7 14 00 00 [ ]*jo 2c0 -+.*: a7 24 00 00 [ ]*jh 2c4 -+.*: a7 84 00 00 [ ]*je 2c8 - .*: ed 65 af ff 00 18 [ ]*kdb %f6,4095\(%r5,%r10\) - .*: b3 18 00 69 [ ]*kdbr %f6,%f9 - .*: ed 65 af ff 00 08 [ ]*keb %f6,4095\(%r5,%r10\) -@@ -372,6 +373,7 @@ Disassembly of section .text: - .*: b3 0b 00 69 [ ]*sebr %f6,%f9 - .*: 3b 69 [ ]*ser %f6,%f9 - .*: b3 84 00 69 [ ]*sfpc %r6,%r9 -+.*: b3 84 00 60 [ ]*sfpc %r6 - .*: 4b 65 af ff [ ]*sh %r6,4095\(%r5,%r10\) - .*: b2 14 5f ff [ ]*sie 4095\(%r5\) - .*: b2 74 5f ff [ ]*siga 4095\(%r5\) -diff --git a/gas/testsuite/gas/s390/esa-g5.s b/gas/testsuite/gas/s390/esa-g5.s -index d0bfb20..1bdc4da 100644 ---- a/gas/testsuite/gas/s390/esa-g5.s -+++ b/gas/testsuite/gas/s390/esa-g5.s -@@ -151,6 +151,7 @@ foo: - ed 4095(256,%r5),4095(%r10) - edmk 4095(256,%r5),4095(%r10) - efpc %r6,%r9 -+ efpc %r6 - epar %r6 - ereg %r6,%r9 - esar %r6 -@@ -366,6 +367,7 @@ foo: - sebr %f6,%f9 - ser %f6,%f9 - sfpc %r6,%r9 -+ sfpc %r6 - sh %r6,4095(%r5,%r10) - sie 4095(%r5) - siga 4095(%r5) -diff --git a/gas/testsuite/gas/s390/esa-z9-109.d b/gas/testsuite/gas/s390/esa-z9-109.d -index c379c46..d9cfcae 100644 ---- a/gas/testsuite/gas/s390/esa-z9-109.d -+++ b/gas/testsuite/gas/s390/esa-z9-109.d -@@ -7,7 +7,11 @@ Disassembly of section .text: - - .* : - .*: b9 93 f0 68 [ ]*troo %r6,%r8,15 -+.*: b9 93 00 68 [ ]*troo %r6,%r8 - .*: b9 92 f0 68 [ ]*trot %r6,%r8,15 -+.*: b9 92 00 68 [ ]*trot %r6,%r8 - .*: b9 91 f0 68 [ ]*trto %r6,%r8,15 -+.*: b9 91 00 68 [ ]*trto %r6,%r8 - .*: b9 90 f0 68 [ ]*trtt %r6,%r8,15 -+.*: b9 90 00 68 [ ]*trtt %r6,%r8 - .*: b2 2b 00 69 [ ]*sske %r6,%r9 -diff --git a/gas/testsuite/gas/s390/esa-z9-109.s b/gas/testsuite/gas/s390/esa-z9-109.s -index 438f76e..c11fd38 100644 ---- a/gas/testsuite/gas/s390/esa-z9-109.s -+++ b/gas/testsuite/gas/s390/esa-z9-109.s -@@ -1,9 +1,13 @@ - .text - foo: - troo %r6,%r8,15 -+ troo %r6,%r8 - trot %r6,%r8,15 -+ trot %r6,%r8 - trto %r6,%r8,15 -+ trto %r6,%r8 - trtt %r6,%r8,15 -+ trtt %r6,%r8 - # z9-109 z/Architecture mode extended sske with an additional parameter - # make sure the old version still works for esa - sske %r6,%r9 -diff --git a/gas/testsuite/gas/s390/s390.exp b/gas/testsuite/gas/s390/s390.exp -index 8dee249..734e86c 100644 ---- a/gas/testsuite/gas/s390/s390.exp -+++ b/gas/testsuite/gas/s390/s390.exp -@@ -27,6 +27,7 @@ if [expr [istarget "s390-*-*"] || [istarget "s390x-*-*"]] then { - run_dump_test "zarch-z10" "{as -m64} {as -march=z10}" - run_dump_test "zarch-z196" "{as -m64} {as -march=z196}" - run_dump_test "zarch-zEC12" "{as -m64} {as -march=zEC12}" -+ run_dump_test "zarch-z13" "{as -m64} {as -march=z13}" - run_dump_test "zarch-reloc" "{as -m64}" - run_dump_test "zarch-operands" "{as -m64} {as -march=z9-109}" - run_dump_test "zarch-machine" "{as -m64} {as -march=z900}" -diff --git a/gas/testsuite/gas/s390/zarch-z10.d b/gas/testsuite/gas/s390/zarch-z10.d -index 9f94875..50a7138 100644 ---- a/gas/testsuite/gas/s390/zarch-z10.d -+++ b/gas/testsuite/gas/s390/zarch-z10.d -@@ -371,9 +371,9 @@ Disassembly of section .text: - .*: b9 a2 00 60 [ ]*ptf %r6 - .*: b9 af 00 67 [ ]*pfmf %r6,%r7 - .*: b9 bf a0 67 [ ]*trte %r6,%r7,10 --.*: b9 bf 00 67 [ ]*trte %r6,%r7,0 -+.*: b9 bf 00 67 [ ]*trte %r6,%r7 - .*: b9 bd a0 67 [ ]*trtre %r6,%r7,10 --.*: b9 bd 00 67 [ ]*trtre %r6,%r7,0 -+.*: b9 bd 00 67 [ ]*trtre %r6,%r7 - .*: b2 ed 00 67 [ ]*ecpga %r6,%r7 - .*: b2 e4 00 67 [ ]*ecctr %r6,%r7 - .*: b2 e5 00 67 [ ]*epctr %r6,%r7 -diff --git a/gas/testsuite/gas/s390/zarch-z13.d b/gas/testsuite/gas/s390/zarch-z13.d -new file mode 100644 -index 0000000..f74b9f8 ---- /dev/null -+++ b/gas/testsuite/gas/s390/zarch-z13.d -@@ -0,0 +1,548 @@ -+#name: s390x opcode -+#objdump: -dr -+ -+.*: +file format .* -+ -+Disassembly of section .text: -+ -+.* : -+.*: e7 69 bf a0 d0 27 [ ]*lcbb %r6,4000\(%r9,%r11\),13 -+.*: e7 f6 9f a0 d0 13 [ ]*vgef %v15,4000\(%v6,%r9\),13 -+.*: e7 f6 9f a0 d0 12 [ ]*vgeg %v15,4000\(%v6,%r9\),13 -+.*: e7 f0 ff fd 00 44 [ ]*vgbm %v15,65533 -+.*: e7 f0 00 00 00 44 [ ]*vzero %v15 -+.*: e7 f0 ff ff 00 44 [ ]*vone %v15 -+.*: e7 f0 fd fc b0 46 [ ]*vgm %v15,253,252,11 -+.*: e7 f0 fd fc 00 46 [ ]*vgmb %v15,253,252 -+.*: e7 f0 fd fc 10 46 [ ]*vgmh %v15,253,252 -+.*: e7 f0 fd fc 20 46 [ ]*vgmf %v15,253,252 -+.*: e7 f0 fd fc 30 46 [ ]*vgmg %v15,253,252 -+.*: e7 f6 9f a0 00 06 [ ]*vl %v15,4000\(%r6,%r9\) -+.*: e7 f1 00 00 04 56 [ ]*vlr %v15,%v17 -+.*: e7 f6 9f a0 d0 05 [ ]*vlrep %v15,4000\(%r6,%r9\),13 -+.*: e7 f6 9f a0 00 05 [ ]*vlrepb %v15,4000\(%r6,%r9\) -+.*: e7 f6 9f a0 10 05 [ ]*vlreph %v15,4000\(%r6,%r9\) -+.*: e7 f6 9f a0 20 05 [ ]*vlrepf %v15,4000\(%r6,%r9\) -+.*: e7 f6 9f a0 30 05 [ ]*vlrepg %v15,4000\(%r6,%r9\) -+.*: e7 f6 9f a0 d0 00 [ ]*vleb %v15,4000\(%r6,%r9\),13 -+.*: e7 f6 9f a0 d0 01 [ ]*vleh %v15,4000\(%r6,%r9\),13 -+.*: e7 f6 9f a0 d0 03 [ ]*vlef %v15,4000\(%r6,%r9\),13 -+.*: e7 f6 9f a0 d0 02 [ ]*vleg %v15,4000\(%r6,%r9\),13 -+.*: e7 f0 80 03 c0 40 [ ]*vleib %v15,-32765,12 -+.*: e7 f0 80 03 c0 41 [ ]*vleih %v15,-32765,12 -+.*: e7 f0 80 03 c0 43 [ ]*vleif %v15,-32765,12 -+.*: e7 f0 80 03 c0 42 [ ]*vleig %v15,-32765,12 -+.*: e7 6f 9f a0 d0 21 [ ]*vlgv %r6,%v15,4000\(%r9\),13 -+.*: e7 6f 9f a0 00 21 [ ]*vlgvb %r6,%v15,4000\(%r9\) -+.*: e7 6f 9f a0 10 21 [ ]*vlgvh %r6,%v15,4000\(%r9\) -+.*: e7 6f 9f a0 20 21 [ ]*vlgvf %r6,%v15,4000\(%r9\) -+.*: e7 6f 9f a0 30 21 [ ]*vlgvg %r6,%v15,4000\(%r9\) -+.*: e7 f6 9f a0 d0 04 [ ]*vllez %v15,4000\(%r6,%r9\),13 -+.*: e7 f6 9f a0 00 04 [ ]*vllezb %v15,4000\(%r6,%r9\) -+.*: e7 f6 9f a0 10 04 [ ]*vllezh %v15,4000\(%r6,%r9\) -+.*: e7 f6 9f a0 20 04 [ ]*vllezf %v15,4000\(%r6,%r9\) -+.*: e7 f6 9f a0 30 04 [ ]*vllezg %v15,4000\(%r6,%r9\) -+.*: e7 f1 6f a0 04 36 [ ]*vlm %v15,%v17,4000\(%r6\) -+.*: e7 f6 9f a0 d0 07 [ ]*vlbb %v15,4000\(%r6,%r9\),13 -+.*: e7 f6 9f a0 d0 22 [ ]*vlvg %v15,%r6,4000\(%r9\),13 -+.*: e7 f6 9f a0 00 22 [ ]*vlvgb %v15,%r6,4000\(%r9\) -+.*: e7 f6 9f a0 10 22 [ ]*vlvgh %v15,%r6,4000\(%r9\) -+.*: e7 f6 9f a0 20 22 [ ]*vlvgf %v15,%r6,4000\(%r9\) -+.*: e7 f6 9f a0 30 22 [ ]*vlvgg %v15,%r6,4000\(%r9\) -+.*: e7 f6 90 00 00 62 [ ]*vlvgp %v15,%r6,%r9 -+.*: e7 f6 9f a0 00 37 [ ]*vll %v15,%r6,4000\(%r9\) -+.*: e7 f1 40 00 d6 61 [ ]*vmrh %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 61 [ ]*vmrhb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 61 [ ]*vmrhh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 61 [ ]*vmrhf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 61 [ ]*vmrhg %v15,%v17,%v20 -+.*: e7 f1 40 00 d6 60 [ ]*vmrl %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 60 [ ]*vmrlb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 60 [ ]*vmrlh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 60 [ ]*vmrlf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 60 [ ]*vmrlg %v15,%v17,%v20 -+.*: e7 f1 40 00 d6 94 [ ]*vpk %v15,%v17,%v20,13 -+.*: e7 f1 40 00 16 94 [ ]*vpkh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 94 [ ]*vpkf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 94 [ ]*vpkg %v15,%v17,%v20 -+.*: e7 f1 40 c0 d6 97 [ ]*vpks %v15,%v17,%v20,13,12 -+.*: e7 f1 40 00 16 97 [ ]*vpksh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 97 [ ]*vpksf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 97 [ ]*vpksg %v15,%v17,%v20 -+.*: e7 f1 40 10 16 97 [ ]*vpkshs %v15,%v17,%v20 -+.*: e7 f1 40 10 26 97 [ ]*vpksfs %v15,%v17,%v20 -+.*: e7 f1 40 10 36 97 [ ]*vpksgs %v15,%v17,%v20 -+.*: e7 f1 40 c0 d6 95 [ ]*vpkls %v15,%v17,%v20,13,12 -+.*: e7 f1 40 00 16 95 [ ]*vpklsh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 95 [ ]*vpklsf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 95 [ ]*vpklsg %v15,%v17,%v20 -+.*: e7 f1 40 10 16 95 [ ]*vpklshs %v15,%v17,%v20 -+.*: e7 f1 40 10 26 95 [ ]*vpklsfs %v15,%v17,%v20 -+.*: e7 f1 40 10 36 95 [ ]*vpklsgs %v15,%v17,%v20 -+.*: e7 f1 40 00 87 8c [ ]*vperm %v15,%v17,%v20,%v24 -+.*: e7 f1 40 00 d6 84 [ ]*vpdi %v15,%v17,%v20,13 -+.*: e7 f1 ff fd c4 4d [ ]*vrep %v15,%v17,65533,12 -+.*: e7 f1 ff fd 04 4d [ ]*vrepb %v15,%v17,65533 -+.*: e7 f1 ff fd 14 4d [ ]*vreph %v15,%v17,65533 -+.*: e7 f1 ff fd 24 4d [ ]*vrepf %v15,%v17,65533 -+.*: e7 f1 ff fd 34 4d [ ]*vrepg %v15,%v17,65533 -+.*: e7 f0 80 03 c0 45 [ ]*vrepi %v15,-32765,12 -+.*: e7 f0 80 03 00 45 [ ]*vrepib %v15,-32765 -+.*: e7 f0 80 03 10 45 [ ]*vrepih %v15,-32765 -+.*: e7 f0 80 03 20 45 [ ]*vrepif %v15,-32765 -+.*: e7 f0 80 03 30 45 [ ]*vrepig %v15,-32765 -+.*: e7 f6 9f a0 d0 1b [ ]*vscef %v15,4000\(%v6,%r9\),13 -+.*: e7 f6 9f a0 d0 1a [ ]*vsceg %v15,4000\(%v6,%r9\),13 -+.*: e7 f1 40 00 87 8d [ ]*vsel %v15,%v17,%v20,%v24 -+.*: e7 f1 00 00 d4 5f [ ]*vseg %v15,%v17,13 -+.*: e7 f1 00 00 04 5f [ ]*vsegb %v15,%v17 -+.*: e7 f1 00 00 14 5f [ ]*vsegh %v15,%v17 -+.*: e7 f1 00 00 24 5f [ ]*vsegf %v15,%v17 -+.*: e7 f6 9f a0 00 0e [ ]*vst %v15,4000\(%r6,%r9\) -+.*: e7 f6 9f a0 d0 08 [ ]*vsteb %v15,4000\(%r6,%r9\),13 -+.*: e7 f6 9f a0 d0 09 [ ]*vsteh %v15,4000\(%r6,%r9\),13 -+.*: e7 f6 9f a0 d0 0b [ ]*vstef %v15,4000\(%r6,%r9\),13 -+.*: e7 f6 9f a0 d0 0a [ ]*vsteg %v15,4000\(%r6,%r9\),13 -+.*: e7 f1 6f a0 04 3e [ ]*vstm %v15,%v17,4000\(%r6\) -+.*: e7 f6 9f a0 00 3f [ ]*vstl %v15,%r6,4000\(%r9\) -+.*: e7 f1 00 00 d4 d7 [ ]*vuph %v15,%v17,13 -+.*: e7 f1 00 00 04 d7 [ ]*vuphb %v15,%v17 -+.*: e7 f1 00 00 14 d7 [ ]*vuphh %v15,%v17 -+.*: e7 f1 00 00 24 d7 [ ]*vuphf %v15,%v17 -+.*: e7 f1 00 00 d4 d5 [ ]*vuplh %v15,%v17,13 -+.*: e7 f1 00 00 04 d5 [ ]*vuplhb %v15,%v17 -+.*: e7 f1 00 00 14 d5 [ ]*vuplhh %v15,%v17 -+.*: e7 f1 00 00 24 d5 [ ]*vuplhf %v15,%v17 -+.*: e7 f1 00 00 d4 d6 [ ]*vupl %v15,%v17,13 -+.*: e7 f1 00 00 04 d6 [ ]*vuplb %v15,%v17 -+.*: e7 f1 00 00 14 d6 [ ]*vuplhw %v15,%v17 -+.*: e7 f1 00 00 24 d6 [ ]*vuplf %v15,%v17 -+.*: e7 f1 00 00 d4 d4 [ ]*vupll %v15,%v17,13 -+.*: e7 f1 00 00 04 d4 [ ]*vupllb %v15,%v17 -+.*: e7 f1 00 00 14 d4 [ ]*vupllh %v15,%v17 -+.*: e7 f1 00 00 24 d4 [ ]*vupllf %v15,%v17 -+.*: e7 f1 40 00 d6 f3 [ ]*va %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 f3 [ ]*vab %v15,%v17,%v20 -+.*: e7 f1 40 00 16 f3 [ ]*vah %v15,%v17,%v20 -+.*: e7 f1 40 00 26 f3 [ ]*vaf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 f3 [ ]*vag %v15,%v17,%v20 -+.*: e7 f1 40 00 46 f3 [ ]*vaq %v15,%v17,%v20 -+.*: e7 f1 40 00 d6 f1 [ ]*vacc %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 f1 [ ]*vaccb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 f1 [ ]*vacch %v15,%v17,%v20 -+.*: e7 f1 40 00 26 f1 [ ]*vaccf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 f1 [ ]*vaccg %v15,%v17,%v20 -+.*: e7 f1 40 00 46 f1 [ ]*vaccq %v15,%v17,%v20 -+.*: e7 f1 4d 00 87 bb [ ]*vac %v15,%v17,%v20,%v24,13 -+.*: e7 f1 44 00 87 bb [ ]*vacq %v15,%v17,%v20,%v24 -+.*: e7 f1 4d 00 87 b9 [ ]*vaccc %v15,%v17,%v20,%v24,13 -+.*: e7 f1 44 00 87 b9 [ ]*vacccq %v15,%v17,%v20,%v24 -+.*: e7 f1 40 00 06 68 [ ]*vn %v15,%v17,%v20 -+.*: e7 f1 40 00 06 69 [ ]*vnc %v15,%v17,%v20 -+.*: e7 f1 40 00 d6 f2 [ ]*vavg %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 f2 [ ]*vavgb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 f2 [ ]*vavgh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 f2 [ ]*vavgf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 f2 [ ]*vavgg %v15,%v17,%v20 -+.*: e7 f1 40 00 d6 f0 [ ]*vavgl %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 f0 [ ]*vavglb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 f0 [ ]*vavglh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 f0 [ ]*vavglf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 f0 [ ]*vavglg %v15,%v17,%v20 -+.*: e7 f1 40 00 06 66 [ ]*vcksm %v15,%v17,%v20 -+.*: e7 f1 00 00 d4 db [ ]*vec %v15,%v17,13 -+.*: e7 f1 00 00 04 db [ ]*vecb %v15,%v17 -+.*: e7 f1 00 00 14 db [ ]*vech %v15,%v17 -+.*: e7 f1 00 00 24 db [ ]*vecf %v15,%v17 -+.*: e7 f1 00 00 34 db [ ]*vecg %v15,%v17 -+.*: e7 f1 00 00 d4 d9 [ ]*vecl %v15,%v17,13 -+.*: e7 f1 00 00 04 d9 [ ]*veclb %v15,%v17 -+.*: e7 f1 00 00 14 d9 [ ]*veclh %v15,%v17 -+.*: e7 f1 00 00 24 d9 [ ]*veclf %v15,%v17 -+.*: e7 f1 00 00 34 d9 [ ]*veclg %v15,%v17 -+.*: e7 f1 40 c0 d6 f8 [ ]*vceq %v15,%v17,%v20,13,12 -+.*: e7 f1 40 00 06 f8 [ ]*vceqb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 f8 [ ]*vceqh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 f8 [ ]*vceqf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 f8 [ ]*vceqg %v15,%v17,%v20 -+.*: e7 f1 40 10 06 f8 [ ]*vceqbs %v15,%v17,%v20 -+.*: e7 f1 40 10 16 f8 [ ]*vceqhs %v15,%v17,%v20 -+.*: e7 f1 40 10 26 f8 [ ]*vceqfs %v15,%v17,%v20 -+.*: e7 f1 40 10 36 f8 [ ]*vceqgs %v15,%v17,%v20 -+.*: e7 f1 40 c0 d6 fb [ ]*vch %v15,%v17,%v20,13,12 -+.*: e7 f1 40 00 06 fb [ ]*vchb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 fb [ ]*vchh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 fb [ ]*vchf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 fb [ ]*vchg %v15,%v17,%v20 -+.*: e7 f1 40 10 06 fb [ ]*vchbs %v15,%v17,%v20 -+.*: e7 f1 40 10 16 fb [ ]*vchhs %v15,%v17,%v20 -+.*: e7 f1 40 10 26 fb [ ]*vchfs %v15,%v17,%v20 -+.*: e7 f1 40 10 36 fb [ ]*vchgs %v15,%v17,%v20 -+.*: e7 f1 40 c0 d6 f9 [ ]*vchl %v15,%v17,%v20,13,12 -+.*: e7 f1 40 00 06 f9 [ ]*vchlb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 f9 [ ]*vchlh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 f9 [ ]*vchlf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 f9 [ ]*vchlg %v15,%v17,%v20 -+.*: e7 f1 40 10 06 f9 [ ]*vchlbs %v15,%v17,%v20 -+.*: e7 f1 40 10 16 f9 [ ]*vchlhs %v15,%v17,%v20 -+.*: e7 f1 40 10 26 f9 [ ]*vchlfs %v15,%v17,%v20 -+.*: e7 f1 40 10 36 f9 [ ]*vchlgs %v15,%v17,%v20 -+.*: e7 f1 00 00 d4 53 [ ]*vclz %v15,%v17,13 -+.*: e7 f1 00 00 04 53 [ ]*vclzb %v15,%v17 -+.*: e7 f1 00 00 14 53 [ ]*vclzh %v15,%v17 -+.*: e7 f1 00 00 24 53 [ ]*vclzf %v15,%v17 -+.*: e7 f1 00 00 34 53 [ ]*vclzg %v15,%v17 -+.*: e7 f1 00 00 d4 52 [ ]*vctz %v15,%v17,13 -+.*: e7 f1 00 00 04 52 [ ]*vctzb %v15,%v17 -+.*: e7 f1 00 00 14 52 [ ]*vctzh %v15,%v17 -+.*: e7 f1 00 00 24 52 [ ]*vctzf %v15,%v17 -+.*: e7 f1 00 00 34 52 [ ]*vctzg %v15,%v17 -+.*: e7 f1 40 00 06 6d [ ]*vx %v15,%v17,%v20 -+.*: e7 f1 40 00 d6 b4 [ ]*vgfm %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 b4 [ ]*vgfmb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 b4 [ ]*vgfmh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 b4 [ ]*vgfmf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 b4 [ ]*vgfmg %v15,%v17,%v20 -+.*: e7 f1 4d 00 87 bc [ ]*vgfma %v15,%v17,%v20,%v24,13 -+.*: e7 f1 40 00 87 bc [ ]*vgfmab %v15,%v17,%v20,%v24 -+.*: e7 f1 41 00 87 bc [ ]*vgfmah %v15,%v17,%v20,%v24 -+.*: e7 f1 42 00 87 bc [ ]*vgfmaf %v15,%v17,%v20,%v24 -+.*: e7 f1 43 00 87 bc [ ]*vgfmag %v15,%v17,%v20,%v24 -+.*: e7 f1 00 00 d4 de [ ]*vlc %v15,%v17,13 -+.*: e7 f1 00 00 04 de [ ]*vlcb %v15,%v17 -+.*: e7 f1 00 00 14 de [ ]*vlch %v15,%v17 -+.*: e7 f1 00 00 24 de [ ]*vlcf %v15,%v17 -+.*: e7 f1 00 00 34 de [ ]*vlcg %v15,%v17 -+.*: e7 f1 00 00 d4 df [ ]*vlp %v15,%v17,13 -+.*: e7 f1 00 00 04 df [ ]*vlpb %v15,%v17 -+.*: e7 f1 00 00 14 df [ ]*vlph %v15,%v17 -+.*: e7 f1 00 00 24 df [ ]*vlpf %v15,%v17 -+.*: e7 f1 00 00 34 df [ ]*vlpg %v15,%v17 -+.*: e7 f1 40 00 d6 ff [ ]*vmx %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 ff [ ]*vmxb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 ff [ ]*vmxh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 ff [ ]*vmxf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 ff [ ]*vmxg %v15,%v17,%v20 -+.*: e7 f1 40 00 d6 fd [ ]*vmxl %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 fd [ ]*vmxlb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 fd [ ]*vmxlh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 fd [ ]*vmxlf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 fd [ ]*vmxlg %v15,%v17,%v20 -+.*: e7 f1 40 00 d6 fe [ ]*vmn %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 fe [ ]*vmnb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 fe [ ]*vmnh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 fe [ ]*vmnf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 fe [ ]*vmng %v15,%v17,%v20 -+.*: e7 f1 40 00 d6 fc [ ]*vmnl %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 fc [ ]*vmnlb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 fc [ ]*vmnlh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 fc [ ]*vmnlf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 fc [ ]*vmnlg %v15,%v17,%v20 -+.*: e7 f1 4d 00 87 aa [ ]*vmal %v15,%v17,%v20,%v24,13 -+.*: e7 f1 40 00 87 aa [ ]*vmalb %v15,%v17,%v20,%v24 -+.*: e7 f1 41 00 87 aa [ ]*vmalhw %v15,%v17,%v20,%v24 -+.*: e7 f1 42 00 87 aa [ ]*vmalf %v15,%v17,%v20,%v24 -+.*: e7 f1 4d 00 87 ab [ ]*vmah %v15,%v17,%v20,%v24,13 -+.*: e7 f1 40 00 87 ab [ ]*vmahb %v15,%v17,%v20,%v24 -+.*: e7 f1 41 00 87 ab [ ]*vmahh %v15,%v17,%v20,%v24 -+.*: e7 f1 42 00 87 ab [ ]*vmahf %v15,%v17,%v20,%v24 -+.*: e7 f1 4d 00 87 a9 [ ]*vmalh %v15,%v17,%v20,%v24,13 -+.*: e7 f1 40 00 87 a9 [ ]*vmalhb %v15,%v17,%v20,%v24 -+.*: e7 f1 41 00 87 a9 [ ]*vmalhh %v15,%v17,%v20,%v24 -+.*: e7 f1 42 00 87 a9 [ ]*vmalhf %v15,%v17,%v20,%v24 -+.*: e7 f1 4d 00 87 ae [ ]*vmae %v15,%v17,%v20,%v24,13 -+.*: e7 f1 40 00 87 ae [ ]*vmaeb %v15,%v17,%v20,%v24 -+.*: e7 f1 41 00 87 ae [ ]*vmaeh %v15,%v17,%v20,%v24 -+.*: e7 f1 42 00 87 ae [ ]*vmaef %v15,%v17,%v20,%v24 -+.*: e7 f1 4d 00 87 ac [ ]*vmale %v15,%v17,%v20,%v24,13 -+.*: e7 f1 40 00 87 ac [ ]*vmaleb %v15,%v17,%v20,%v24 -+.*: e7 f1 41 00 87 ac [ ]*vmaleh %v15,%v17,%v20,%v24 -+.*: e7 f1 42 00 87 ac [ ]*vmalef %v15,%v17,%v20,%v24 -+.*: e7 f1 4d 00 87 af [ ]*vmao %v15,%v17,%v20,%v24,13 -+.*: e7 f1 40 00 87 af [ ]*vmaob %v15,%v17,%v20,%v24 -+.*: e7 f1 41 00 87 af [ ]*vmaoh %v15,%v17,%v20,%v24 -+.*: e7 f1 42 00 87 af [ ]*vmaof %v15,%v17,%v20,%v24 -+.*: e7 f1 4d 00 87 ad [ ]*vmalo %v15,%v17,%v20,%v24,13 -+.*: e7 f1 40 00 87 ad [ ]*vmalob %v15,%v17,%v20,%v24 -+.*: e7 f1 41 00 87 ad [ ]*vmaloh %v15,%v17,%v20,%v24 -+.*: e7 f1 42 00 87 ad [ ]*vmalof %v15,%v17,%v20,%v24 -+.*: e7 f1 40 00 d6 a3 [ ]*vmh %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 a3 [ ]*vmhb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 a3 [ ]*vmhh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 a3 [ ]*vmhf %v15,%v17,%v20 -+.*: e7 f1 40 00 d6 a1 [ ]*vmlh %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 a1 [ ]*vmlhb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 a1 [ ]*vmlhh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 a1 [ ]*vmlhf %v15,%v17,%v20 -+.*: e7 f1 40 00 d6 a2 [ ]*vml %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 a2 [ ]*vmlb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 a2 [ ]*vmlhw %v15,%v17,%v20 -+.*: e7 f1 40 00 26 a2 [ ]*vmlf %v15,%v17,%v20 -+.*: e7 f1 40 00 d6 a6 [ ]*vme %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 a6 [ ]*vmeb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 a6 [ ]*vmeh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 a6 [ ]*vmef %v15,%v17,%v20 -+.*: e7 f1 40 00 d6 a4 [ ]*vmle %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 a4 [ ]*vmleb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 a4 [ ]*vmleh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 a4 [ ]*vmlef %v15,%v17,%v20 -+.*: e7 f1 40 00 d6 a7 [ ]*vmo %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 a7 [ ]*vmob %v15,%v17,%v20 -+.*: e7 f1 40 00 16 a7 [ ]*vmoh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 a7 [ ]*vmof %v15,%v17,%v20 -+.*: e7 f1 40 00 d6 a5 [ ]*vmlo %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 a5 [ ]*vmlob %v15,%v17,%v20 -+.*: e7 f1 40 00 16 a5 [ ]*vmloh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 a5 [ ]*vmlof %v15,%v17,%v20 -+.*: e7 f1 40 00 06 6b [ ]*vno %v15,%v17,%v20 -+.*: e7 f1 10 00 06 6b [ ]*vno %v15,%v17,%v17 -+.*: e7 f1 40 00 06 6a [ ]*vo %v15,%v17,%v20 -+.*: e7 f1 00 00 d4 50 [ ]*vpopct %v15,%v17,13 -+.*: e7 f1 40 00 d6 73 [ ]*verllv %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 73 [ ]*verllvb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 73 [ ]*verllvh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 73 [ ]*verllvf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 73 [ ]*verllvg %v15,%v17,%v20 -+.*: e7 f1 6f a0 d4 33 [ ]*verll %v15,%v17,4000\(%r6\),13 -+.*: e7 f1 6f a0 04 33 [ ]*verllb %v15,%v17,4000\(%r6\) -+.*: e7 f1 6f a0 14 33 [ ]*verllh %v15,%v17,4000\(%r6\) -+.*: e7 f1 6f a0 24 33 [ ]*verllf %v15,%v17,4000\(%r6\) -+.*: e7 f1 6f a0 34 33 [ ]*verllg %v15,%v17,4000\(%r6\) -+.*: e7 f1 40 fd c6 72 [ ]*verim %v15,%v17,%v20,253,12 -+.*: e7 f1 40 fd 06 72 [ ]*verimb %v15,%v17,%v20,253 -+.*: e7 f1 40 fd 16 72 [ ]*verimh %v15,%v17,%v20,253 -+.*: e7 f1 40 fd 26 72 [ ]*verimf %v15,%v17,%v20,253 -+.*: e7 f1 40 fd 36 72 [ ]*verimg %v15,%v17,%v20,253 -+.*: e7 f1 40 00 d6 70 [ ]*veslv %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 70 [ ]*veslvb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 70 [ ]*veslvh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 70 [ ]*veslvf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 70 [ ]*veslvg %v15,%v17,%v20 -+.*: e7 f1 6f a0 d4 30 [ ]*vesl %v15,%v17,4000\(%r6\),13 -+.*: e7 f1 6f a0 04 30 [ ]*veslb %v15,%v17,4000\(%r6\) -+.*: e7 f1 6f a0 14 30 [ ]*veslh %v15,%v17,4000\(%r6\) -+.*: e7 f1 6f a0 24 30 [ ]*veslf %v15,%v17,4000\(%r6\) -+.*: e7 f1 6f a0 34 30 [ ]*veslg %v15,%v17,4000\(%r6\) -+.*: e7 f1 40 00 d6 7a [ ]*vesrav %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 7a [ ]*vesravb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 7a [ ]*vesravh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 7a [ ]*vesravf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 7a [ ]*vesravg %v15,%v17,%v20 -+.*: e7 f1 6f a0 d4 3a [ ]*vesra %v15,%v17,4000\(%r6\),13 -+.*: e7 f1 6f a0 04 3a [ ]*vesrab %v15,%v17,4000\(%r6\) -+.*: e7 f1 6f a0 14 3a [ ]*vesrah %v15,%v17,4000\(%r6\) -+.*: e7 f1 6f a0 24 3a [ ]*vesraf %v15,%v17,4000\(%r6\) -+.*: e7 f1 6f a0 34 3a [ ]*vesrag %v15,%v17,4000\(%r6\) -+.*: e7 f1 40 00 d6 78 [ ]*vesrlv %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 78 [ ]*vesrlvb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 78 [ ]*vesrlvh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 78 [ ]*vesrlvf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 78 [ ]*vesrlvg %v15,%v17,%v20 -+.*: e7 f1 6f a0 d4 38 [ ]*vesrl %v15,%v17,4000\(%r6\),13 -+.*: e7 f1 6f a0 04 38 [ ]*vesrlb %v15,%v17,4000\(%r6\) -+.*: e7 f1 6f a0 14 38 [ ]*vesrlh %v15,%v17,4000\(%r6\) -+.*: e7 f1 6f a0 24 38 [ ]*vesrlf %v15,%v17,4000\(%r6\) -+.*: e7 f1 6f a0 34 38 [ ]*vesrlg %v15,%v17,4000\(%r6\) -+.*: e7 f1 40 00 06 74 [ ]*vsl %v15,%v17,%v20 -+.*: e7 f1 40 00 06 75 [ ]*vslb %v15,%v17,%v20 -+.*: e7 f1 40 fd 06 77 [ ]*vsldb %v15,%v17,%v20,253 -+.*: e7 f1 40 00 06 7e [ ]*vsra %v15,%v17,%v20 -+.*: e7 f1 40 00 06 7f [ ]*vsrab %v15,%v17,%v20 -+.*: e7 f1 40 00 06 7c [ ]*vsrl %v15,%v17,%v20 -+.*: e7 f1 40 00 06 7d [ ]*vsrlb %v15,%v17,%v20 -+.*: e7 f1 40 00 d6 f7 [ ]*vs %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 f7 [ ]*vsb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 f7 [ ]*vsh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 f7 [ ]*vsf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 f7 [ ]*vsg %v15,%v17,%v20 -+.*: e7 f1 40 00 46 f7 [ ]*vsq %v15,%v17,%v20 -+.*: e7 f1 40 00 d6 f5 [ ]*vscbi %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 f5 [ ]*vscbib %v15,%v17,%v20 -+.*: e7 f1 40 00 16 f5 [ ]*vscbih %v15,%v17,%v20 -+.*: e7 f1 40 00 26 f5 [ ]*vscbif %v15,%v17,%v20 -+.*: e7 f1 40 00 36 f5 [ ]*vscbig %v15,%v17,%v20 -+.*: e7 f1 40 00 46 f5 [ ]*vscbiq %v15,%v17,%v20 -+.*: e7 f1 4d 00 87 bf [ ]*vsbi %v15,%v17,%v20,%v24,13 -+.*: e7 f1 44 00 87 bf [ ]*vsbiq %v15,%v17,%v20,%v24 -+.*: e7 f1 4d 00 87 bd [ ]*vsbcbi %v15,%v17,%v20,%v24,13 -+.*: e7 f1 44 00 87 bd [ ]*vsbcbiq %v15,%v17,%v20,%v24 -+.*: e7 f1 40 00 d6 65 [ ]*vsumg %v15,%v17,%v20,13 -+.*: e7 f1 40 00 16 65 [ ]*vsumgh %v15,%v17,%v20 -+.*: e7 f1 40 00 26 65 [ ]*vsumgf %v15,%v17,%v20 -+.*: e7 f1 40 00 d6 67 [ ]*vsumq %v15,%v17,%v20,13 -+.*: e7 f1 40 00 26 67 [ ]*vsumqf %v15,%v17,%v20 -+.*: e7 f1 40 00 36 67 [ ]*vsumqg %v15,%v17,%v20 -+.*: e7 f1 40 00 d6 64 [ ]*vsum %v15,%v17,%v20,13 -+.*: e7 f1 40 00 06 64 [ ]*vsumb %v15,%v17,%v20 -+.*: e7 f1 40 00 16 64 [ ]*vsumh %v15,%v17,%v20 -+.*: e7 f1 00 00 04 d8 [ ]*vtm %v15,%v17 -+.*: e7 f1 40 00 d6 82 [ ]*vfae %v15,%v17,%v20,13 -+.*: e7 f1 40 c0 d6 82 [ ]*vfae %v15,%v17,%v20,13,12 -+.*: e7 f1 40 00 06 82 [ ]*vfaeb %v15,%v17,%v20 -+.*: e7 f1 40 d0 06 82 [ ]*vfaebs %v15,%v17,%v20,12 -+.*: e7 f1 40 00 16 82 [ ]*vfaeh %v15,%v17,%v20 -+.*: e7 f1 40 d0 16 82 [ ]*vfaehs %v15,%v17,%v20,12 -+.*: e7 f1 40 00 26 82 [ ]*vfaef %v15,%v17,%v20 -+.*: e7 f1 40 d0 26 82 [ ]*vfaefs %v15,%v17,%v20,12 -+.*: e7 f1 40 10 06 82 [ ]*vfaebs %v15,%v17,%v20 -+.*: e7 f1 40 d0 06 82 [ ]*vfaebs %v15,%v17,%v20,12 -+.*: e7 f1 40 10 16 82 [ ]*vfaehs %v15,%v17,%v20 -+.*: e7 f1 40 d0 16 82 [ ]*vfaehs %v15,%v17,%v20,12 -+.*: e7 f1 40 10 26 82 [ ]*vfaefs %v15,%v17,%v20 -+.*: e7 f1 40 d0 26 82 [ ]*vfaefs %v15,%v17,%v20,12 -+.*: e7 f1 40 20 06 82 [ ]*vfaezb %v15,%v17,%v20 -+.*: e7 f1 40 f0 06 82 [ ]*vfaezbs %v15,%v17,%v20,12 -+.*: e7 f1 40 20 16 82 [ ]*vfaezh %v15,%v17,%v20 -+.*: e7 f1 40 f0 16 82 [ ]*vfaezhs %v15,%v17,%v20,12 -+.*: e7 f1 40 20 26 82 [ ]*vfaezf %v15,%v17,%v20 -+.*: e7 f1 40 f0 26 82 [ ]*vfaezfs %v15,%v17,%v20,12 -+.*: e7 f1 40 30 06 82 [ ]*vfaezbs %v15,%v17,%v20 -+.*: e7 f1 40 f0 06 82 [ ]*vfaezbs %v15,%v17,%v20,12 -+.*: e7 f1 40 30 16 82 [ ]*vfaezhs %v15,%v17,%v20 -+.*: e7 f1 40 f0 16 82 [ ]*vfaezhs %v15,%v17,%v20,12 -+.*: e7 f1 40 30 26 82 [ ]*vfaezfs %v15,%v17,%v20 -+.*: e7 f1 40 f0 26 82 [ ]*vfaezfs %v15,%v17,%v20,12 -+.*: e7 f1 40 00 d6 80 [ ]*vfee %v15,%v17,%v20,13 -+.*: e7 f1 40 c0 d6 80 [ ]*vfee %v15,%v17,%v20,13,12 -+.*: e7 f1 40 00 06 80 [ ]*vfeeb %v15,%v17,%v20 -+.*: e7 f1 40 d0 06 80 [ ]*vfeeb %v15,%v17,%v20,13 -+.*: e7 f1 40 00 16 80 [ ]*vfeeh %v15,%v17,%v20 -+.*: e7 f1 40 d0 16 80 [ ]*vfeeh %v15,%v17,%v20,13 -+.*: e7 f1 40 00 26 80 [ ]*vfeef %v15,%v17,%v20 -+.*: e7 f1 40 d0 26 80 [ ]*vfeef %v15,%v17,%v20,13 -+.*: e7 f1 40 10 06 80 [ ]*vfeebs %v15,%v17,%v20 -+.*: e7 f1 40 10 16 80 [ ]*vfeehs %v15,%v17,%v20 -+.*: e7 f1 40 10 26 80 [ ]*vfeefs %v15,%v17,%v20 -+.*: e7 f1 40 20 06 80 [ ]*vfeezb %v15,%v17,%v20 -+.*: e7 f1 40 20 16 80 [ ]*vfeezh %v15,%v17,%v20 -+.*: e7 f1 40 20 26 80 [ ]*vfeezf %v15,%v17,%v20 -+.*: e7 f1 40 30 06 80 [ ]*vfeezbs %v15,%v17,%v20 -+.*: e7 f1 40 30 16 80 [ ]*vfeezhs %v15,%v17,%v20 -+.*: e7 f1 40 30 26 80 [ ]*vfeezfs %v15,%v17,%v20 -+.*: e7 f1 40 00 d6 81 [ ]*vfene %v15,%v17,%v20,13 -+.*: e7 f1 40 c0 d6 81 [ ]*vfene %v15,%v17,%v20,13,12 -+.*: e7 f1 40 00 06 81 [ ]*vfeneb %v15,%v17,%v20 -+.*: e7 f1 40 d0 06 81 [ ]*vfeneb %v15,%v17,%v20,13 -+.*: e7 f1 40 00 16 81 [ ]*vfeneh %v15,%v17,%v20 -+.*: e7 f1 40 d0 16 81 [ ]*vfeneh %v15,%v17,%v20,13 -+.*: e7 f1 40 00 26 81 [ ]*vfenef %v15,%v17,%v20 -+.*: e7 f1 40 d0 26 81 [ ]*vfenef %v15,%v17,%v20,13 -+.*: e7 f1 40 10 06 81 [ ]*vfenebs %v15,%v17,%v20 -+.*: e7 f1 40 10 16 81 [ ]*vfenehs %v15,%v17,%v20 -+.*: e7 f1 40 10 26 81 [ ]*vfenefs %v15,%v17,%v20 -+.*: e7 f1 40 20 06 81 [ ]*vfenezb %v15,%v17,%v20 -+.*: e7 f1 40 20 16 81 [ ]*vfenezh %v15,%v17,%v20 -+.*: e7 f1 40 20 26 81 [ ]*vfenezf %v15,%v17,%v20 -+.*: e7 f1 40 30 06 81 [ ]*vfenezbs %v15,%v17,%v20 -+.*: e7 f1 40 30 16 81 [ ]*vfenezhs %v15,%v17,%v20 -+.*: e7 f1 40 30 26 81 [ ]*vfenezfs %v15,%v17,%v20 -+.*: e7 f1 00 00 d4 5c [ ]*vistr %v15,%v17,13 -+.*: e7 f1 00 c0 d4 5c [ ]*vistr %v15,%v17,13,12 -+.*: e7 f1 00 00 04 5c [ ]*vistrb %v15,%v17 -+.*: e7 f1 00 d0 04 5c [ ]*vistrb %v15,%v17,13 -+.*: e7 f1 00 00 14 5c [ ]*vistrh %v15,%v17 -+.*: e7 f1 00 d0 14 5c [ ]*vistrh %v15,%v17,13 -+.*: e7 f1 00 00 24 5c [ ]*vistrf %v15,%v17 -+.*: e7 f1 00 d0 24 5c [ ]*vistrf %v15,%v17,13 -+.*: e7 f1 00 10 04 5c [ ]*vistrbs %v15,%v17 -+.*: e7 f1 00 10 14 5c [ ]*vistrhs %v15,%v17 -+.*: e7 f1 00 10 24 5c [ ]*vistrfs %v15,%v17 -+.*: e7 f1 4d 00 87 8a [ ]*vstrc %v15,%v17,%v20,%v24,13 -+.*: e7 f1 4d c0 87 8a [ ]*vstrc %v15,%v17,%v20,%v24,13,12 -+.*: e7 f1 40 00 87 8a [ ]*vstrcb %v15,%v17,%v20,%v24 -+.*: e7 f1 40 d0 87 8a [ ]*vstrcbs %v15,%v17,%v20,%v24,12 -+.*: e7 f1 41 00 87 8a [ ]*vstrch %v15,%v17,%v20,%v24 -+.*: e7 f1 41 d0 87 8a [ ]*vstrchs %v15,%v17,%v20,%v24,12 -+.*: e7 f1 42 00 87 8a [ ]*vstrcf %v15,%v17,%v20,%v24 -+.*: e7 f1 42 d0 87 8a [ ]*vstrcfs %v15,%v17,%v20,%v24,12 -+.*: e7 f1 40 10 87 8a [ ]*vstrcbs %v15,%v17,%v20,%v24 -+.*: e7 f1 40 d0 87 8a [ ]*vstrcbs %v15,%v17,%v20,%v24,12 -+.*: e7 f1 41 10 87 8a [ ]*vstrchs %v15,%v17,%v20,%v24 -+.*: e7 f1 41 d0 87 8a [ ]*vstrchs %v15,%v17,%v20,%v24,12 -+.*: e7 f1 42 10 87 8a [ ]*vstrcfs %v15,%v17,%v20,%v24 -+.*: e7 f1 42 d0 87 8a [ ]*vstrcfs %v15,%v17,%v20,%v24,12 -+.*: e7 f1 40 20 87 8a [ ]*vstrczb %v15,%v17,%v20,%v24 -+.*: e7 f1 40 f0 87 8a [ ]*vstrczbs %v15,%v17,%v20,%v24,12 -+.*: e7 f1 41 20 87 8a [ ]*vstrczh %v15,%v17,%v20,%v24 -+.*: e7 f1 41 f0 87 8a [ ]*vstrczhs %v15,%v17,%v20,%v24,12 -+.*: e7 f1 42 20 87 8a [ ]*vstrczf %v15,%v17,%v20,%v24 -+.*: e7 f1 42 f0 87 8a [ ]*vstrczfs %v15,%v17,%v20,%v24,12 -+.*: e7 f1 40 30 87 8a [ ]*vstrczbs %v15,%v17,%v20,%v24 -+.*: e7 f1 40 f0 87 8a [ ]*vstrczbs %v15,%v17,%v20,%v24,12 -+.*: e7 f1 41 30 87 8a [ ]*vstrczhs %v15,%v17,%v20,%v24 -+.*: e7 f1 41 f0 87 8a [ ]*vstrczhs %v15,%v17,%v20,%v24,12 -+.*: e7 f1 42 30 87 8a [ ]*vstrczfs %v15,%v17,%v20,%v24 -+.*: e7 f1 42 f0 87 8a [ ]*vstrczfs %v15,%v17,%v20,%v24,12 -+.*: e7 f1 40 0c d6 e3 [ ]*vfa %v15,%v17,%v20,13,12 -+.*: e7 f1 40 00 36 e3 [ ]*vfadb %v15,%v17,%v20 -+.*: e7 f1 40 08 36 e3 [ ]*wfadb %v15,%v17,%v20 -+.*: e7 f1 00 cd 04 cb [ ]*wfc %v15,%v17,13,12 -+.*: e7 f1 00 00 34 cb [ ]*wfcdb %v15,%v17 -+.*: e7 f1 00 cd 04 ca [ ]*wfk %v15,%v17,13,12 -+.*: e7 f1 00 00 34 ca [ ]*wfkdb %v15,%v17 -+.*: e7 f1 40 00 06 e8 [ ]*vfce %v15,%v17,%v20 -+.*: e7 f1 40 00 36 e8 [ ]*vfcedb %v15,%v17,%v20 -+.*: e7 f1 40 10 36 e8 [ ]*vfcedbs %v15,%v17,%v20 -+.*: e7 f1 40 08 36 e8 [ ]*wfcedb %v15,%v17,%v20 -+.*: e7 f1 40 18 36 e8 [ ]*wfcedbs %v15,%v17,%v20 -+.*: e7 f1 40 bc d6 eb [ ]*vfch %v15,%v17,%v20,13,12,11 -+.*: e7 f1 40 00 36 eb [ ]*vfchdb %v15,%v17,%v20 -+.*: e7 f1 40 10 36 eb [ ]*vfchdbs %v15,%v17,%v20 -+.*: e7 f1 40 08 36 eb [ ]*wfchdb %v15,%v17,%v20 -+.*: e7 f1 40 18 36 eb [ ]*wfchdbs %v15,%v17,%v20 -+.*: e7 f1 40 bc d6 ea [ ]*vfche %v15,%v17,%v20,13,12,11 -+.*: e7 f1 40 00 36 ea [ ]*vfchedb %v15,%v17,%v20 -+.*: e7 f1 40 10 36 ea [ ]*vfchedbs %v15,%v17,%v20 -+.*: e7 f1 40 08 36 ea [ ]*wfchedb %v15,%v17,%v20 -+.*: e7 f1 40 18 36 ea [ ]*wfchedbs %v15,%v17,%v20 -+.*: e7 f1 00 bc d4 c3 [ ]*vcdg %v15,%v17,13,12,11 -+.*: e7 f1 00 cd 34 c3 [ ]*wcdgb %v15,%v17,5,12 -+.*: e7 f1 00 cd 34 c3 [ ]*wcdgb %v15,%v17,5,12 -+.*: e7 f1 00 bc d4 c1 [ ]*vcdlg %v15,%v17,13,12,11 -+.*: e7 f1 00 cd 34 c1 [ ]*wcdlgb %v15,%v17,5,12 -+.*: e7 f1 00 cd 34 c1 [ ]*wcdlgb %v15,%v17,5,12 -+.*: e7 f1 00 bc d4 c2 [ ]*vcgd %v15,%v17,13,12,11 -+.*: e7 f1 00 cd 34 c2 [ ]*wcgdb %v15,%v17,5,12 -+.*: e7 f1 00 cd 34 c2 [ ]*wcgdb %v15,%v17,5,12 -+.*: e7 f1 00 bc d4 c0 [ ]*vclgd %v15,%v17,13,12,11 -+.*: e7 f1 00 cd 34 c0 [ ]*wclgdb %v15,%v17,5,12 -+.*: e7 f1 00 cd 34 c0 [ ]*wclgdb %v15,%v17,5,12 -+.*: e7 f1 40 0c d6 e5 [ ]*vfd %v15,%v17,%v20,13,12 -+.*: e7 f1 40 00 36 e5 [ ]*vfddb %v15,%v17,%v20 -+.*: e7 f1 40 08 36 e5 [ ]*wfddb %v15,%v17,%v20 -+.*: e7 f1 00 bc d4 c7 [ ]*vfi %v15,%v17,13,12,11 -+.*: e7 f1 00 cd 34 c7 [ ]*wfidb %v15,%v17,5,12 -+.*: e7 f1 00 cd 34 c7 [ ]*wfidb %v15,%v17,5,12 -+.*: e7 f1 00 cd 04 c4 [ ]*vlde %v15,%v17,13,12 -+.*: e7 f1 00 00 24 c4 [ ]*vldeb %v15,%v17 -+.*: e7 f1 00 08 24 c4 [ ]*wldeb %v15,%v17 -+.*: e7 f1 00 bc d4 c5 [ ]*vled %v15,%v17,13,12,11 -+.*: e7 f1 00 cd 34 c5 [ ]*wledb %v15,%v17,5,12 -+.*: e7 f1 00 cd 34 c5 [ ]*wledb %v15,%v17,5,12 -+.*: e7 f1 40 0c d6 e7 [ ]*vfm %v15,%v17,%v20,13,12 -+.*: e7 f1 40 00 36 e7 [ ]*vfmdb %v15,%v17,%v20 -+.*: e7 f1 40 08 36 e7 [ ]*wfmdb %v15,%v17,%v20 -+.*: e7 f1 4c 0d 87 8f [ ]*vfma %v15,%v17,%v20,%v24,13,12 -+.*: e7 f1 43 00 87 8f [ ]*vfmadb %v15,%v17,%v20,%v24 -+.*: e7 f1 43 08 87 8f [ ]*wfmadb %v15,%v17,%v20,%v24 -+.*: e7 f1 4c 0d 87 8e [ ]*vfms %v15,%v17,%v20,%v24,13,12 -+.*: e7 f1 43 00 87 8e [ ]*vfmsdb %v15,%v17,%v20,%v24 -+.*: e7 f1 43 08 87 8e [ ]*wfmsdb %v15,%v17,%v20,%v24 -+.*: e7 f1 00 bc d4 cc [ ]*vfpso %v15,%v17,13,12,11 -+.*: e7 f1 00 d0 34 cc [ ]*vfpsodb %v15,%v17,13 -+.*: e7 f1 00 d8 34 cc [ ]*wfpsodb %v15,%v17,13 -+.*: e7 f1 00 00 34 cc [ ]*vflcdb %v15,%v17 -+.*: e7 f1 00 08 34 cc [ ]*wflcdb %v15,%v17 -+.*: e7 f1 00 10 34 cc [ ]*vflndb %v15,%v17 -+.*: e7 f1 00 18 34 cc [ ]*wflndb %v15,%v17 -+.*: e7 f1 00 20 34 cc [ ]*vflpdb %v15,%v17 -+.*: e7 f1 00 28 34 cc [ ]*wflpdb %v15,%v17 -+.*: e7 f1 00 cd 04 ce [ ]*vfsq %v15,%v17,13,12 -+.*: e7 f1 00 00 34 ce [ ]*vfsqdb %v15,%v17 -+.*: e7 f1 00 08 34 ce [ ]*wfsqdb %v15,%v17 -+.*: e7 f1 40 0c d6 e2 [ ]*vfs %v15,%v17,%v20,13,12 -+.*: e7 f1 40 00 36 e2 [ ]*vfsdb %v15,%v17,%v20 -+.*: e7 f1 40 08 36 e2 [ ]*wfsdb %v15,%v17,%v20 -+.*: e7 f1 ff db c4 4a [ ]*vftci %v15,%v17,4093,12,11 -+.*: e7 f1 ff d0 34 4a [ ]*vftcidb %v15,%v17,4093 -+.*: e7 f1 ff d8 34 4a [ ]*wftcidb %v15,%v17,4093 -diff --git a/gas/testsuite/gas/s390/zarch-z13.s b/gas/testsuite/gas/s390/zarch-z13.s -new file mode 100644 -index 0000000..812e3e8 ---- /dev/null -+++ b/gas/testsuite/gas/s390/zarch-z13.s -@@ -0,0 +1,542 @@ -+.text -+foo: -+ lcbb %r6,4000(%r9,%r11),13 -+ vgef %v15,4000(%r6,%r9),13 -+ vgeg %v15,4000(%r6,%r9),13 -+ vgbm %v15,65533 -+ vzero %v15 -+ vone %v15 -+ vgm %v15,253,252,11 -+ vgmb %v15,253,252 -+ vgmh %v15,253,252 -+ vgmf %v15,253,252 -+ vgmg %v15,253,252 -+ vl %v15,4000(%r6,%r9) -+ vlr %v15,%v17 -+ vlrep %v15,4000(%r6,%r9),13 -+ vlrepb %v15,4000(%r6,%r9) -+ vlreph %v15,4000(%r6,%r9) -+ vlrepf %v15,4000(%r6,%r9) -+ vlrepg %v15,4000(%r6,%r9) -+ vleb %v15,4000(%r6,%r9),13 -+ vleh %v15,4000(%r6,%r9),13 -+ vlef %v15,4000(%r6,%r9),13 -+ vleg %v15,4000(%r6,%r9),13 -+ vleib %v15,-32765,12 -+ vleih %v15,-32765,12 -+ vleif %v15,-32765,12 -+ vleig %v15,-32765,12 -+ vlgv %r6,%v15,4000(%r9),13 -+ vlgvb %r6,%v15,4000(%r9) -+ vlgvh %r6,%v15,4000(%r9) -+ vlgvf %r6,%v15,4000(%r9) -+ vlgvg %r6,%v15,4000(%r9) -+ vllez %v15,4000(%r6,%r9),13 -+ vllezb %v15,4000(%r6,%r9) -+ vllezh %v15,4000(%r6,%r9) -+ vllezf %v15,4000(%r6,%r9) -+ vllezg %v15,4000(%r6,%r9) -+ vlm %v15,%v17,4000(%r6) -+ vlbb %v15,4000(%r6,%r9),13 -+ vlvg %v15,%r6,4000(%r9),13 -+ vlvgb %v15,%r6,4000(%r9) -+ vlvgh %v15,%r6,4000(%r9) -+ vlvgf %v15,%r6,4000(%r9) -+ vlvgg %v15,%r6,4000(%r9) -+ vlvgp %v15,%r6,%r9 -+ vll %v15,%r6,4000(%r9) -+ vmrh %v15,%v17,%v20,13 -+ vmrhb %v15,%v17,%v20 -+ vmrhh %v15,%v17,%v20 -+ vmrhf %v15,%v17,%v20 -+ vmrhg %v15,%v17,%v20 -+ vmrl %v15,%v17,%v20,13 -+ vmrlb %v15,%v17,%v20 -+ vmrlh %v15,%v17,%v20 -+ vmrlf %v15,%v17,%v20 -+ vmrlg %v15,%v17,%v20 -+ vpk %v15,%v17,%v20,13 -+ vpkh %v15,%v17,%v20 -+ vpkf %v15,%v17,%v20 -+ vpkg %v15,%v17,%v20 -+ vpks %v15,%v17,%v20,13,12 -+ vpksh %v15,%v17,%v20 -+ vpksf %v15,%v17,%v20 -+ vpksg %v15,%v17,%v20 -+ vpkshs %v15,%v17,%v20 -+ vpksfs %v15,%v17,%v20 -+ vpksgs %v15,%v17,%v20 -+ vpkls %v15,%v17,%v20,13,12 -+ vpklsh %v15,%v17,%v20 -+ vpklsf %v15,%v17,%v20 -+ vpklsg %v15,%v17,%v20 -+ vpklshs %v15,%v17,%v20 -+ vpklsfs %v15,%v17,%v20 -+ vpklsgs %v15,%v17,%v20 -+ vperm %v15,%v17,%v20,%v24 -+ vpdi %v15,%v17,%v20,13 -+ vrep %v15,%v17,65533,12 -+ vrepb %v15,%v17,65533 -+ vreph %v15,%v17,65533 -+ vrepf %v15,%v17,65533 -+ vrepg %v15,%v17,65533 -+ vrepi %v15,-32765,12 -+ vrepib %v15,-32765 -+ vrepih %v15,-32765 -+ vrepif %v15,-32765 -+ vrepig %v15,-32765 -+ vscef %v15,4000(%r6,%r9),13 -+ vsceg %v15,4000(%r6,%r9),13 -+ vsel %v15,%v17,%v20,%v24 -+ vseg %v15,%v17,13 -+ vsegb %v15,%v17 -+ vsegh %v15,%v17 -+ vsegf %v15,%v17 -+ vst %v15,4000(%r6,%r9) -+ vsteb %v15,4000(%r6,%r9),13 -+ vsteh %v15,4000(%r6,%r9),13 -+ vstef %v15,4000(%r6,%r9),13 -+ vsteg %v15,4000(%r6,%r9),13 -+ vstm %v15,%v17,4000(%r6) -+ vstl %v15,%r6,4000(%r9) -+ vuph %v15,%v17,13 -+ vuphb %v15,%v17 -+ vuphh %v15,%v17 -+ vuphf %v15,%v17 -+ vuplh %v15,%v17,13 -+ vuplhb %v15,%v17 -+ vuplhh %v15,%v17 -+ vuplhf %v15,%v17 -+ vupl %v15,%v17,13 -+ vuplb %v15,%v17 -+ vuplhw %v15,%v17 -+ vuplf %v15,%v17 -+ vupll %v15,%v17,13 -+ vupllb %v15,%v17 -+ vupllh %v15,%v17 -+ vupllf %v15,%v17 -+ va %v15,%v17,%v20,13 -+ vab %v15,%v17,%v20 -+ vah %v15,%v17,%v20 -+ vaf %v15,%v17,%v20 -+ vag %v15,%v17,%v20 -+ vaq %v15,%v17,%v20 -+ vacc %v15,%v17,%v20,13 -+ vaccb %v15,%v17,%v20 -+ vacch %v15,%v17,%v20 -+ vaccf %v15,%v17,%v20 -+ vaccg %v15,%v17,%v20 -+ vaccq %v15,%v17,%v20 -+ vac %v15,%v17,%v20,%v24,13 -+ vacq %v15,%v17,%v20,%v24 -+ vaccc %v15,%v17,%v20,%v24,13 -+ vacccq %v15,%v17,%v20,%v24 -+ vn %v15,%v17,%v20 -+ vnc %v15,%v17,%v20 -+ vavg %v15,%v17,%v20,13 -+ vavgb %v15,%v17,%v20 -+ vavgh %v15,%v17,%v20 -+ vavgf %v15,%v17,%v20 -+ vavgg %v15,%v17,%v20 -+ vavgl %v15,%v17,%v20,13 -+ vavglb %v15,%v17,%v20 -+ vavglh %v15,%v17,%v20 -+ vavglf %v15,%v17,%v20 -+ vavglg %v15,%v17,%v20 -+ vcksm %v15,%v17,%v20 -+ vec %v15,%v17,13 -+ vecb %v15,%v17 -+ vech %v15,%v17 -+ vecf %v15,%v17 -+ vecg %v15,%v17 -+ vecl %v15,%v17,13 -+ veclb %v15,%v17 -+ veclh %v15,%v17 -+ veclf %v15,%v17 -+ veclg %v15,%v17 -+ vceq %v15,%v17,%v20,13,12 -+ vceqb %v15,%v17,%v20 -+ vceqh %v15,%v17,%v20 -+ vceqf %v15,%v17,%v20 -+ vceqg %v15,%v17,%v20 -+ vceqbs %v15,%v17,%v20 -+ vceqhs %v15,%v17,%v20 -+ vceqfs %v15,%v17,%v20 -+ vceqgs %v15,%v17,%v20 -+ vch %v15,%v17,%v20,13,12 -+ vchb %v15,%v17,%v20 -+ vchh %v15,%v17,%v20 -+ vchf %v15,%v17,%v20 -+ vchg %v15,%v17,%v20 -+ vchbs %v15,%v17,%v20 -+ vchhs %v15,%v17,%v20 -+ vchfs %v15,%v17,%v20 -+ vchgs %v15,%v17,%v20 -+ vchl %v15,%v17,%v20,13,12 -+ vchlb %v15,%v17,%v20 -+ vchlh %v15,%v17,%v20 -+ vchlf %v15,%v17,%v20 -+ vchlg %v15,%v17,%v20 -+ vchlbs %v15,%v17,%v20 -+ vchlhs %v15,%v17,%v20 -+ vchlfs %v15,%v17,%v20 -+ vchlgs %v15,%v17,%v20 -+ vclz %v15,%v17,13 -+ vclzb %v15,%v17 -+ vclzh %v15,%v17 -+ vclzf %v15,%v17 -+ vclzg %v15,%v17 -+ vctz %v15,%v17,13 -+ vctzb %v15,%v17 -+ vctzh %v15,%v17 -+ vctzf %v15,%v17 -+ vctzg %v15,%v17 -+ vx %v15,%v17,%v20 -+ vgfm %v15,%v17,%v20,13 -+ vgfmb %v15,%v17,%v20 -+ vgfmh %v15,%v17,%v20 -+ vgfmf %v15,%v17,%v20 -+ vgfmg %v15,%v17,%v20 -+ vgfma %v15,%v17,%v20,%v24,13 -+ vgfmab %v15,%v17,%v20,%v24 -+ vgfmah %v15,%v17,%v20,%v24 -+ vgfmaf %v15,%v17,%v20,%v24 -+ vgfmag %v15,%v17,%v20,%v24 -+ vlc %v15,%v17,13 -+ vlcb %v15,%v17 -+ vlch %v15,%v17 -+ vlcf %v15,%v17 -+ vlcg %v15,%v17 -+ vlp %v15,%v17,13 -+ vlpb %v15,%v17 -+ vlph %v15,%v17 -+ vlpf %v15,%v17 -+ vlpg %v15,%v17 -+ vmx %v15,%v17,%v20,13 -+ vmxb %v15,%v17,%v20 -+ vmxh %v15,%v17,%v20 -+ vmxf %v15,%v17,%v20 -+ vmxg %v15,%v17,%v20 -+ vmxl %v15,%v17,%v20,13 -+ vmxlb %v15,%v17,%v20 -+ vmxlh %v15,%v17,%v20 -+ vmxlf %v15,%v17,%v20 -+ vmxlg %v15,%v17,%v20 -+ vmn %v15,%v17,%v20,13 -+ vmnb %v15,%v17,%v20 -+ vmnh %v15,%v17,%v20 -+ vmnf %v15,%v17,%v20 -+ vmng %v15,%v17,%v20 -+ vmnl %v15,%v17,%v20,13 -+ vmnlb %v15,%v17,%v20 -+ vmnlh %v15,%v17,%v20 -+ vmnlf %v15,%v17,%v20 -+ vmnlg %v15,%v17,%v20 -+ vmal %v15,%v17,%v20,%v24,13 -+ vmalb %v15,%v17,%v20,%v24 -+ vmalhw %v15,%v17,%v20,%v24 -+ vmalf %v15,%v17,%v20,%v24 -+ vmah %v15,%v17,%v20,%v24,13 -+ vmahb %v15,%v17,%v20,%v24 -+ vmahh %v15,%v17,%v20,%v24 -+ vmahf %v15,%v17,%v20,%v24 -+ vmalh %v15,%v17,%v20,%v24,13 -+ vmalhb %v15,%v17,%v20,%v24 -+ vmalhh %v15,%v17,%v20,%v24 -+ vmalhf %v15,%v17,%v20,%v24 -+ vmae %v15,%v17,%v20,%v24,13 -+ vmaeb %v15,%v17,%v20,%v24 -+ vmaeh %v15,%v17,%v20,%v24 -+ vmaef %v15,%v17,%v20,%v24 -+ vmale %v15,%v17,%v20,%v24,13 -+ vmaleb %v15,%v17,%v20,%v24 -+ vmaleh %v15,%v17,%v20,%v24 -+ vmalef %v15,%v17,%v20,%v24 -+ vmao %v15,%v17,%v20,%v24,13 -+ vmaob %v15,%v17,%v20,%v24 -+ vmaoh %v15,%v17,%v20,%v24 -+ vmaof %v15,%v17,%v20,%v24 -+ vmalo %v15,%v17,%v20,%v24,13 -+ vmalob %v15,%v17,%v20,%v24 -+ vmaloh %v15,%v17,%v20,%v24 -+ vmalof %v15,%v17,%v20,%v24 -+ vmh %v15,%v17,%v20,13 -+ vmhb %v15,%v17,%v20 -+ vmhh %v15,%v17,%v20 -+ vmhf %v15,%v17,%v20 -+ vmlh %v15,%v17,%v20,13 -+ vmlhb %v15,%v17,%v20 -+ vmlhh %v15,%v17,%v20 -+ vmlhf %v15,%v17,%v20 -+ vml %v15,%v17,%v20,13 -+ vmlb %v15,%v17,%v20 -+ vmlhw %v15,%v17,%v20 -+ vmlf %v15,%v17,%v20 -+ vme %v15,%v17,%v20,13 -+ vmeb %v15,%v17,%v20 -+ vmeh %v15,%v17,%v20 -+ vmef %v15,%v17,%v20 -+ vmle %v15,%v17,%v20,13 -+ vmleb %v15,%v17,%v20 -+ vmleh %v15,%v17,%v20 -+ vmlef %v15,%v17,%v20 -+ vmo %v15,%v17,%v20,13 -+ vmob %v15,%v17,%v20 -+ vmoh %v15,%v17,%v20 -+ vmof %v15,%v17,%v20 -+ vmlo %v15,%v17,%v20,13 -+ vmlob %v15,%v17,%v20 -+ vmloh %v15,%v17,%v20 -+ vmlof %v15,%v17,%v20 -+ vno %v15,%v17,%v20 -+ vnot %v15,%v17 -+ vo %v15,%v17,%v20 -+ vpopct %v15,%v17,13 -+ verllv %v15,%v17,%v20,13 -+ verllvb %v15,%v17,%v20 -+ verllvh %v15,%v17,%v20 -+ verllvf %v15,%v17,%v20 -+ verllvg %v15,%v17,%v20 -+ verll %v15,%v17,4000(%r6),13 -+ verllb %v15,%v17,4000(%r6) -+ verllh %v15,%v17,4000(%r6) -+ verllf %v15,%v17,4000(%r6) -+ verllg %v15,%v17,4000(%r6) -+ verim %v15,%v17,%v20,253,12 -+ verimb %v15,%v17,%v20,253 -+ verimh %v15,%v17,%v20,253 -+ verimf %v15,%v17,%v20,253 -+ verimg %v15,%v17,%v20,253 -+ veslv %v15,%v17,%v20,13 -+ veslvb %v15,%v17,%v20 -+ veslvh %v15,%v17,%v20 -+ veslvf %v15,%v17,%v20 -+ veslvg %v15,%v17,%v20 -+ vesl %v15,%v17,4000(%r6),13 -+ veslb %v15,%v17,4000(%r6) -+ veslh %v15,%v17,4000(%r6) -+ veslf %v15,%v17,4000(%r6) -+ veslg %v15,%v17,4000(%r6) -+ vesrav %v15,%v17,%v20,13 -+ vesravb %v15,%v17,%v20 -+ vesravh %v15,%v17,%v20 -+ vesravf %v15,%v17,%v20 -+ vesravg %v15,%v17,%v20 -+ vesra %v15,%v17,4000(%r6),13 -+ vesrab %v15,%v17,4000(%r6) -+ vesrah %v15,%v17,4000(%r6) -+ vesraf %v15,%v17,4000(%r6) -+ vesrag %v15,%v17,4000(%r6) -+ vesrlv %v15,%v17,%v20,13 -+ vesrlvb %v15,%v17,%v20 -+ vesrlvh %v15,%v17,%v20 -+ vesrlvf %v15,%v17,%v20 -+ vesrlvg %v15,%v17,%v20 -+ vesrl %v15,%v17,4000(%r6),13 -+ vesrlb %v15,%v17,4000(%r6) -+ vesrlh %v15,%v17,4000(%r6) -+ vesrlf %v15,%v17,4000(%r6) -+ vesrlg %v15,%v17,4000(%r6) -+ vsl %v15,%v17,%v20 -+ vslb %v15,%v17,%v20 -+ vsldb %v15,%v17,%v20,253 -+ vsra %v15,%v17,%v20 -+ vsrab %v15,%v17,%v20 -+ vsrl %v15,%v17,%v20 -+ vsrlb %v15,%v17,%v20 -+ vs %v15,%v17,%v20,13 -+ vsb %v15,%v17,%v20 -+ vsh %v15,%v17,%v20 -+ vsf %v15,%v17,%v20 -+ vsg %v15,%v17,%v20 -+ vsq %v15,%v17,%v20 -+ vscbi %v15,%v17,%v20,13 -+ vscbib %v15,%v17,%v20 -+ vscbih %v15,%v17,%v20 -+ vscbif %v15,%v17,%v20 -+ vscbig %v15,%v17,%v20 -+ vscbiq %v15,%v17,%v20 -+ vsbi %v15,%v17,%v20,%v24,13 -+ vsbiq %v15,%v17,%v20,%v24 -+ vsbcbi %v15,%v17,%v20,%v24,13 -+ vsbcbiq %v15,%v17,%v20,%v24 -+ vsumg %v15,%v17,%v20,13 -+ vsumgh %v15,%v17,%v20 -+ vsumgf %v15,%v17,%v20 -+ vsumq %v15,%v17,%v20,13 -+ vsumqf %v15,%v17,%v20 -+ vsumqg %v15,%v17,%v20 -+ vsum %v15,%v17,%v20,13 -+ vsumb %v15,%v17,%v20 -+ vsumh %v15,%v17,%v20 -+ vtm %v15,%v17 -+ vfae %v15,%v17,%v20,13 -+ vfae %v15,%v17,%v20,13,12 -+ vfaeb %v15,%v17,%v20 -+ vfaeb %v15,%v17,%v20,13 -+ vfaeh %v15,%v17,%v20 -+ vfaeh %v15,%v17,%v20,13 -+ vfaef %v15,%v17,%v20 -+ vfaef %v15,%v17,%v20,13 -+ vfaebs %v15,%v17,%v20 -+ vfaebs %v15,%v17,%v20,13 -+ vfaehs %v15,%v17,%v20 -+ vfaehs %v15,%v17,%v20,13 -+ vfaefs %v15,%v17,%v20 -+ vfaefs %v15,%v17,%v20,13 -+ vfaezb %v15,%v17,%v20 -+ vfaezb %v15,%v17,%v20,13 -+ vfaezh %v15,%v17,%v20 -+ vfaezh %v15,%v17,%v20,13 -+ vfaezf %v15,%v17,%v20 -+ vfaezf %v15,%v17,%v20,13 -+ vfaezbs %v15,%v17,%v20 -+ vfaezbs %v15,%v17,%v20,13 -+ vfaezhs %v15,%v17,%v20 -+ vfaezhs %v15,%v17,%v20,13 -+ vfaezfs %v15,%v17,%v20 -+ vfaezfs %v15,%v17,%v20,13 -+ vfee %v15,%v17,%v20,13 -+ vfee %v15,%v17,%v20,13,12 -+ vfeeb %v15,%v17,%v20 -+ vfeeb %v15,%v17,%v20,13 -+ vfeeh %v15,%v17,%v20 -+ vfeeh %v15,%v17,%v20,13 -+ vfeef %v15,%v17,%v20 -+ vfeef %v15,%v17,%v20,13 -+ vfeebs %v15,%v17,%v20 -+ vfeehs %v15,%v17,%v20 -+ vfeefs %v15,%v17,%v20 -+ vfeezb %v15,%v17,%v20 -+ vfeezh %v15,%v17,%v20 -+ vfeezf %v15,%v17,%v20 -+ vfeezbs %v15,%v17,%v20 -+ vfeezhs %v15,%v17,%v20 -+ vfeezfs %v15,%v17,%v20 -+ vfene %v15,%v17,%v20,13 -+ vfene %v15,%v17,%v20,13,12 -+ vfeneb %v15,%v17,%v20 -+ vfeneb %v15,%v17,%v20,13 -+ vfeneh %v15,%v17,%v20 -+ vfeneh %v15,%v17,%v20,13 -+ vfenef %v15,%v17,%v20 -+ vfenef %v15,%v17,%v20,13 -+ vfenebs %v15,%v17,%v20 -+ vfenehs %v15,%v17,%v20 -+ vfenefs %v15,%v17,%v20 -+ vfenezb %v15,%v17,%v20 -+ vfenezh %v15,%v17,%v20 -+ vfenezf %v15,%v17,%v20 -+ vfenezbs %v15,%v17,%v20 -+ vfenezhs %v15,%v17,%v20 -+ vfenezfs %v15,%v17,%v20 -+ vistr %v15,%v17,13 -+ vistr %v15,%v17,13,12 -+ vistrb %v15,%v17 -+ vistrb %v15,%v17,13 -+ vistrh %v15,%v17 -+ vistrh %v15,%v17,13 -+ vistrf %v15,%v17 -+ vistrf %v15,%v17,13 -+ vistrbs %v15,%v17 -+ vistrhs %v15,%v17 -+ vistrfs %v15,%v17 -+ vstrc %v15,%v17,%v20,%v24,13 -+ vstrc %v15,%v17,%v20,%v24,13,12 -+ vstrcb %v15,%v17,%v20,%v24 -+ vstrcb %v15,%v17,%v20,%v24,13 -+ vstrch %v15,%v17,%v20,%v24 -+ vstrch %v15,%v17,%v20,%v24,13 -+ vstrcf %v15,%v17,%v20,%v24 -+ vstrcf %v15,%v17,%v20,%v24,13 -+ vstrcbs %v15,%v17,%v20,%v24 -+ vstrcbs %v15,%v17,%v20,%v24,13 -+ vstrchs %v15,%v17,%v20,%v24 -+ vstrchs %v15,%v17,%v20,%v24,13 -+ vstrcfs %v15,%v17,%v20,%v24 -+ vstrcfs %v15,%v17,%v20,%v24,13 -+ vstrczb %v15,%v17,%v20,%v24 -+ vstrczb %v15,%v17,%v20,%v24,13 -+ vstrczh %v15,%v17,%v20,%v24 -+ vstrczh %v15,%v17,%v20,%v24,13 -+ vstrczf %v15,%v17,%v20,%v24 -+ vstrczf %v15,%v17,%v20,%v24,13 -+ vstrczbs %v15,%v17,%v20,%v24 -+ vstrczbs %v15,%v17,%v20,%v24,13 -+ vstrczhs %v15,%v17,%v20,%v24 -+ vstrczhs %v15,%v17,%v20,%v24,13 -+ vstrczfs %v15,%v17,%v20,%v24 -+ vstrczfs %v15,%v17,%v20,%v24,13 -+ vfa %v15,%v17,%v20,13,12 -+ vfadb %v15,%v17,%v20 -+ wfadb %v15,%v17,%v20 -+ wfc %v15,%v17,13,12 -+ wfcdb %v15,%v17 -+ wfk %v15,%v17,13,12 -+ wfkdb %v15,%v17 -+ vfce %v15,%v17,%v20 -+ vfcedb %v15,%v17,%v20 -+ vfcedbs %v15,%v17,%v20 -+ wfcedb %v15,%v17,%v20 -+ wfcedbs %v15,%v17,%v20 -+ vfch %v15,%v17,%v20,13,12,11 -+ vfchdb %v15,%v17,%v20 -+ vfchdbs %v15,%v17,%v20 -+ wfchdb %v15,%v17,%v20 -+ wfchdbs %v15,%v17,%v20 -+ vfche %v15,%v17,%v20,13,12,11 -+ vfchedb %v15,%v17,%v20 -+ vfchedbs %v15,%v17,%v20 -+ wfchedb %v15,%v17,%v20 -+ wfchedbs %v15,%v17,%v20 -+ vcdg %v15,%v17,13,12,11 -+ vcdgb %v15,%v17,13,12 -+ wcdgb %v15,%v17,13,12 -+ vcdlg %v15,%v17,13,12,11 -+ vcdlgb %v15,%v17,13,12 -+ wcdlgb %v15,%v17,13,12 -+ vcgd %v15,%v17,13,12,11 -+ vcgdb %v15,%v17,13,12 -+ wcgdb %v15,%v17,13,12 -+ vclgd %v15,%v17,13,12,11 -+ vclgdb %v15,%v17,13,12 -+ wclgdb %v15,%v17,13,12 -+ vfd %v15,%v17,%v20,13,12 -+ vfddb %v15,%v17,%v20 -+ wfddb %v15,%v17,%v20 -+ vfi %v15,%v17,13,12,11 -+ vfidb %v15,%v17,13,12 -+ wfidb %v15,%v17,13,12 -+ vlde %v15,%v17,13,12 -+ vldeb %v15,%v17 -+ wldeb %v15,%v17 -+ vled %v15,%v17,13,12,11 -+ vledb %v15,%v17,13,12 -+ wledb %v15,%v17,13,12 -+ vfm %v15,%v17,%v20,13,12 -+ vfmdb %v15,%v17,%v20 -+ wfmdb %v15,%v17,%v20 -+ vfma %v15,%v17,%v20,%v24,13,12 -+ vfmadb %v15,%v17,%v20,%v24 -+ wfmadb %v15,%v17,%v20,%v24 -+ vfms %v15,%v17,%v20,%v24,13,12 -+ vfmsdb %v15,%v17,%v20,%v24 -+ wfmsdb %v15,%v17,%v20,%v24 -+ vfpso %v15,%v17,13,12,11 -+ vfpsodb %v15,%v17,13 -+ wfpsodb %v15,%v17,13 -+ vflcdb %v15,%v17 -+ wflcdb %v15,%v17 -+ vflndb %v15,%v17 -+ wflndb %v15,%v17 -+ vflpdb %v15,%v17 -+ wflpdb %v15,%v17 -+ vfsq %v15,%v17,13,12 -+ vfsqdb %v15,%v17 -+ wfsqdb %v15,%v17 -+ vfs %v15,%v17,%v20,13,12 -+ vfsdb %v15,%v17,%v20 -+ wfsdb %v15,%v17,%v20 -+ vftci %v15,%v17,4093,12,11 -+ vftcidb %v15,%v17,4093 -+ wftcidb %v15,%v17,4093 -diff --git a/gas/testsuite/gas/s390/zarch-z9-109.d b/gas/testsuite/gas/s390/zarch-z9-109.d -index 3715b42..5a9717c 100644 ---- a/gas/testsuite/gas/s390/zarch-z9-109.d -+++ b/gas/testsuite/gas/s390/zarch-z9-109.d -@@ -45,12 +45,17 @@ Disassembly of section .text: - .*: c8 60 5f ff af ff [ ]*mvcos 4095\(%r5\),4095\(%r10\),%r6 - .*: b9 aa 9f 65 [ ]*lptea %r6,%r9,%r5,15 - .*: b2 2b f0 69 [ ]*sske %r6,%r9,15 -+.*: b2 2b 00 69 [ ]*sske %r6,%r9 - .*: b9 b1 f0 68 [ ]*cu24 %r6,%r8,15 -+.*: b9 b1 00 68 [ ]*cu24 %r6,%r8 - .*: b2 a6 f0 68 [ ]*cu21 %r6,%r8,15 -+.*: b2 a6 00 68 [ ]*cuutf %r6,%r8 - .*: b9 b3 00 68 [ ]*cu42 %r6,%r8 - .*: b9 b2 00 68 [ ]*cu41 %r6,%r8 - .*: b2 a7 f0 68 [ ]*cu12 %r6,%r8,15 -+.*: b2 a7 00 68 [ ]*cutfu %r6,%r8 - .*: b9 b0 f0 68 [ ]*cu14 %r6,%r8,15 -+.*: b9 b0 00 68 [ ]*cu14 %r6,%r8 - .*: b3 3b 60 95 [ ]*myr %f6,%f9,%f5 - .*: b3 3d 60 95 [ ]*myhr %f6,%f9,%f5 - .*: b3 39 60 95 [ ]*mylr %f6,%f9,%f5 -diff --git a/gas/testsuite/gas/s390/zarch-z9-109.s b/gas/testsuite/gas/s390/zarch-z9-109.s -index 9a70d90..10d77ac 100644 ---- a/gas/testsuite/gas/s390/zarch-z9-109.s -+++ b/gas/testsuite/gas/s390/zarch-z9-109.s -@@ -39,12 +39,17 @@ foo: - mvcos 4095(%r5),4095(%r10),%r6 - lptea %r6,%r9,%r5,15 - sske %r6,%r9,15 -+ sske %r6,%r9 - cu24 %r6,%r8,15 -+ cu24 %r6,%r8 - cu21 %r6,%r8,15 -+ cu21 %r6,%r8 - cu42 %r6,%r8 - cu41 %r6,%r8 - cu12 %r6,%r8,15 -+ cu12 %r6,%r8 - cu14 %r6,%r8,15 -+ cu14 %r6,%r8 - myr %f6,%f9,%f5 - myhr %f6,%f9,%f5 - mylr %f6,%f9,%f5 -diff --git a/gas/testsuite/gas/s390/zarch-zEC12.d b/gas/testsuite/gas/s390/zarch-zEC12.d -index 5a6d5f1..2989dda 100644 ---- a/gas/testsuite/gas/s390/zarch-zEC12.d -+++ b/gas/testsuite/gas/s390/zarch-zEC12.d -@@ -52,7 +52,7 @@ Disassembly of section .text: - .*: ed 0f 8f a0 6d a8 [ ]*czdt %f6,4000\(16,%r8\),13 - .*: ed 21 8f a0 4d a9 [ ]*czxt %f4,4000\(34,%r8\),13 - .*: b2 e8 c0 56 [ ]*ppa %r5,%r6,12 --.*: b9 8f 60 59 [ ]*crdte %r5,%r6,%r9,0 -+.*: b9 8f 60 59 [ ]*crdte %r5,%r6,%r9 - .*: b9 8f 61 59 [ ]*crdte %r5,%r6,%r9,1 - .*: c5 a0 06 00 00 06 [ ]*bprp 10,11e ,11e - .*: c5 a0 00 00 00 00 [ ]*bprp 10,118 ,118 -diff --git a/include/opcode/s390.h b/include/opcode/s390.h -index 0884eb6..12b740a 100644 ---- a/include/opcode/s390.h -+++ b/include/opcode/s390.h -@@ -41,9 +41,13 @@ enum s390_opcode_cpu_val - S390_OPCODE_Z10, - S390_OPCODE_Z196, - S390_OPCODE_ZEC12, -+ S390_OPCODE_Z13, - S390_OPCODE_MAXCPU - }; - -+/* Instruction specific flags. */ -+#define S390_INSTR_FLAG_OPTPARM 0x1 -+ - /* The opcode table is an array of struct s390_opcode. */ - - struct s390_opcode -@@ -74,6 +78,9 @@ struct s390_opcode - - /* First cpu this opcode is available for. */ - enum s390_opcode_cpu_val min_cpu; -+ -+ /* Instruction specific flags. */ -+ unsigned int flags; - }; - - /* The table itself is sorted by major opcode number, and is otherwise -@@ -86,7 +93,7 @@ extern const int s390_num_opcodes; - extern const struct s390_opcode s390_opformats[]; - extern const int s390_num_opformats; - --/* Values defined for the flags field of a struct powerpc_opcode. */ -+/* Values defined for the flags field of a struct s390_opcode. */ - - /* The operands table is an array of struct s390_operand. */ - -@@ -103,7 +110,7 @@ struct s390_operand - }; - - /* Elements in the table are retrieved by indexing with values from -- the operands field of the powerpc_opcodes table. */ -+ the operands field of the s390_opcodes table. */ - - extern const struct s390_operand s390_operands[]; - -@@ -151,4 +158,14 @@ extern const struct s390_operand s390_operands[]; - /* The operand needs to be a valid GP or FP register pair. */ - #define S390_OPERAND_REG_PAIR 0x800 - -- #endif /* S390_H */ -+/* This operand names a vector register. The disassembler uses this -+ to print register names with a leading 'v'. */ -+#define S390_OPERAND_VR 0x1000 -+ -+#define S390_OPERAND_CP16 0x2000 -+ -+#define S390_OPERAND_OR1 0x4000 -+#define S390_OPERAND_OR2 0x8000 -+#define S390_OPERAND_OR8 0x10000 -+ -+#endif /* S390_H */ -diff --git a/ld/testsuite/ld-s390/tlsbin.dd b/ld/testsuite/ld-s390/tlsbin.dd -index 0e824da..c1dbd07 100644 ---- a/ld/testsuite/ld-s390/tlsbin.dd -+++ b/ld/testsuite/ld-s390/tlsbin.dd -@@ -109,17 +109,17 @@ Disassembly of section .text: - # IE -> LE against global var defined in exec - +[0-9a-f]+: 58 30 d0 38 l %r3,56\(%r13\) - +[0-9a-f]+: 18 43 lr %r4,%r3 -- +[0-9a-f]+: 07 00 nopr %r0 -+ +[0-9a-f]+: 07 00 nopr - +[0-9a-f]+: 41 54 90 00 la %r5,0\(%r4,%r9\) - # IE -> LE against local var - +[0-9a-f]+: 58 30 d0 3c l %r3,60\(%r13\) - +[0-9a-f]+: 18 43 lr %r4,%r3 -- +[0-9a-f]+: 07 00 nopr %r0 -+ +[0-9a-f]+: 07 00 nopr - +[0-9a-f]+: 41 54 90 00 la %r5,0\(%r4,%r9\) - # IE -> LE against hidden var - +[0-9a-f]+: 58 30 d0 40 l %r3,64\(%r13\) - +[0-9a-f]+: 18 43 lr %r4,%r3 -- +[0-9a-f]+: 07 00 nopr %r0 -+ +[0-9a-f]+: 07 00 nopr - +[0-9a-f]+: 41 54 90 00 la %r5,0\(%r4,%r9\) - # IE against global var with small got access (no optimization) - +[0-9a-f]+: 58 30 c0 14 l %r3,20\(%r12\) -@@ -173,17 +173,17 @@ Disassembly of section .text: - # IE -> LE against global var defined in exec - +[0-9a-f]+: 58 30 d0 04 l %r3,4\(%r13\) - +[0-9a-f]+: 18 43 lr %r4,%r3 -- +[0-9a-f]+: 07 00 nopr %r0 -+ +[0-9a-f]+: 07 00 nopr - +[0-9a-f]+: 41 54 90 00 la %r5,0\(%r4,%r9\) - # IE -> LE against local var - +[0-9a-f]+: 58 30 d0 08 l %r3,8\(%r13\) - +[0-9a-f]+: 18 43 lr %r4,%r3 -- +[0-9a-f]+: 07 00 nopr %r0 -+ +[0-9a-f]+: 07 00 nopr - +[0-9a-f]+: 41 54 90 00 la %r5,0\(%r4,%r9\) - # IE -> LE against hidden but not local var - +[0-9a-f]+: 58 30 d0 0c l %r3,12\(%r13\) - +[0-9a-f]+: 18 43 lr %r4,%r3 -- +[0-9a-f]+: 07 00 nopr %r0 -+ +[0-9a-f]+: 07 00 nopr - +[0-9a-f]+: 41 54 90 00 la %r5,0\(%r4,%r9\) - # LE, global var defined in exec - +[0-9a-f]+: 58 40 d0 10 l %r4,16\(%r13\) -diff --git a/opcodes/s390-dis.c b/opcodes/s390-dis.c -index 282565a..74a7216 100644 ---- a/opcodes/s390-dis.c -+++ b/opcodes/s390-dis.c -@@ -107,6 +107,7 @@ s390_extract_operand (const bfd_byte *insn, - union operand_value ret; - unsigned int val; - int bits; -+ const bfd_byte *orig_insn = insn; - - /* Extract fragments of the operand byte for byte. */ - insn += operand->shift / 8; -@@ -140,6 +141,16 @@ s390_extract_operand (const bfd_byte *insn, - else if (operand->flags & S390_OPERAND_LENGTH) - /* Length x in an instruction has real length x + 1. */ - ret.u = val + 1; -+ -+ else if (operand->flags & S390_OPERAND_VR) -+ { -+ /* Extract the extra bits for a vector register operand stored -+ in the RXB field. */ -+ unsigned vr = operand->shift == 32 ? 3 -+ : (unsigned) operand->shift / 4 - 2; -+ -+ ret.u = val | ((orig_insn[4] & (1 << (3 - vr))) << (vr + 1)); -+ } - else - ret.u = val; - -@@ -178,22 +189,45 @@ s390_print_insn_with_opcode (bfd_vma memaddr, - continue; - } - -- info->fprintf_func (info->stream, "%c", separator); -+ /* For instructions with a last optional operand don't print it -+ if zero. */ -+ if ((opcode->flags & S390_INSTR_FLAG_OPTPARM) -+ && val.u == 0 -+ && opindex[1] == 0) -+ break; - - if (flags & S390_OPERAND_GPR) -- info->fprintf_func (info->stream, "%%r%u", val.u); -+ info->fprintf_func (info->stream, "%c%%r%u", separator, val.u); - else if (flags & S390_OPERAND_FPR) -- info->fprintf_func (info->stream, "%%f%u", val.u); -+ info->fprintf_func (info->stream, "%c%%f%u", separator, val.u); -+ else if (flags & S390_OPERAND_VR) -+ info->fprintf_func (info->stream, "%c%%v%i", separator, val.u); - else if (flags & S390_OPERAND_AR) -- info->fprintf_func (info->stream, "%%a%u", val.u); -+ info->fprintf_func (info->stream, "%c%%a%u", separator, val.u); - else if (flags & S390_OPERAND_CR) -- info->fprintf_func (info->stream, "%%c%u", val.u); -+ info->fprintf_func (info->stream, "%c%%c%u", separator, val.u); - else if (flags & S390_OPERAND_PCREL) -- info->print_address_func (memaddr + val.i + val.i, info); -+ { -+ info->fprintf_func (info->stream, "%c", separator); -+ info->print_address_func (memaddr + val.i + val.i, info); -+ } - else if (flags & S390_OPERAND_SIGNED) -- info->fprintf_func (info->stream, "%i", val.i); -+ info->fprintf_func (info->stream, "%c%i", separator, val.i); - else -- info->fprintf_func (info->stream, "%u", val.u); -+ { -+ if (flags & S390_OPERAND_OR1) -+ val.u &= ~1; -+ if (flags & S390_OPERAND_OR2) -+ val.u &= ~2; -+ if (flags & S390_OPERAND_OR8) -+ val.u &= ~8; -+ -+ if ((opcode->flags & S390_INSTR_FLAG_OPTPARM) -+ && val.u == 0 -+ && opindex[1] == 0) -+ break; -+ info->fprintf_func (info->stream, "%c%u", separator, val.u); -+ } - - if (flags & S390_OPERAND_DISP) - separator = '('; -diff --git a/opcodes/s390-mkopc.c b/opcodes/s390-mkopc.c -index bf30f5b..1fb2d24 100644 ---- a/opcodes/s390-mkopc.c -+++ b/opcodes/s390-mkopc.c -@@ -22,26 +22,7 @@ - #include - #include - #include -- --/* Taken from opcodes/s390.h */ --enum s390_opcode_mode_val -- { -- S390_OPCODE_ESA = 0, -- S390_OPCODE_ZARCH -- }; -- --enum s390_opcode_cpu_val -- { -- S390_OPCODE_G5 = 0, -- S390_OPCODE_G6, -- S390_OPCODE_Z900, -- S390_OPCODE_Z990, -- S390_OPCODE_Z9_109, -- S390_OPCODE_Z9_EC, -- S390_OPCODE_Z10, -- S390_OPCODE_Z196, -- S390_OPCODE_ZEC12 -- }; -+#include "opcode/s390.h" - - struct op_struct - { -@@ -50,6 +31,7 @@ struct op_struct - char format[16]; - int mode_bits; - int min_cpu; -+ int flags; - - unsigned long long sort_value; - int no_nibbles; -@@ -71,7 +53,7 @@ createTable (void) - - static void - insertOpcode (char *opcode, char *mnemonic, char *format, -- int min_cpu, int mode_bits) -+ int min_cpu, int mode_bits, int flags) - { - char *str; - unsigned long long sort_value; -@@ -115,6 +97,7 @@ insertOpcode (char *opcode, char *mnemonic, char *format, - op_array[ix].no_nibbles = no_nibbles; - op_array[ix].min_cpu = min_cpu; - op_array[ix].mode_bits = mode_bits; -+ op_array[ix].flags = flags; - no_ops++; - } - -@@ -176,7 +159,7 @@ const struct s390_cond_ext_format s390_crb_extensions[NUM_CRB_EXTENSIONS] = - - static void - insertExpandedMnemonic (char *opcode, char *mnemonic, char *format, -- int min_cpu, int mode_bits) -+ int min_cpu, int mode_bits, int flags) - { - char *tag; - char prefix[15]; -@@ -189,7 +172,7 @@ insertExpandedMnemonic (char *opcode, char *mnemonic, char *format, - - if (!(tag = strpbrk (mnemonic, "*$"))) - { -- insertOpcode (opcode, mnemonic, format, min_cpu, mode_bits); -+ insertOpcode (opcode, mnemonic, format, min_cpu, mode_bits, flags); - return; - } - -@@ -268,7 +251,7 @@ insertExpandedMnemonic (char *opcode, char *mnemonic, char *format, - opcode[mask_start] = ext_table[i].nibble; - strcat (new_mnemonic, ext_table[i].extension); - strcat (new_mnemonic, suffix); -- insertOpcode (opcode, new_mnemonic, format, min_cpu, mode_bits); -+ insertOpcode (opcode, new_mnemonic, format, min_cpu, mode_bits, flags); - } - return; - -@@ -286,7 +269,10 @@ static const char file_header[] = - " which bits in the actual opcode must match OPCODE.\n" - " OPERANDS is the list of operands.\n\n" - " The disassembler reads the table in order and prints the first\n" -- " instruction which matches. */\n\n" -+ " instruction which matches.\n" -+ " MODE_BITS - zarch or esa\n" -+ " MIN_CPU - number of the min cpu level required\n" -+ " FLAGS - instruction flags. */\n\n" - "const struct s390_opcode s390_opcodes[] =\n {\n"; - - /* `dumpTable': write opcode table. */ -@@ -311,7 +297,8 @@ dumpTable (void) - printf ("MASK_%s, INSTR_%s, ", - op_array[ix].format, op_array[ix].format); - printf ("%i, ", op_array[ix].mode_bits); -- printf ("%i}", op_array[ix].min_cpu); -+ printf ("%i, ", op_array[ix].min_cpu); -+ printf ("%i}", op_array[ix].flags); - if (ix < no_ops-1) - printf (",\n"); - else -@@ -339,67 +326,91 @@ main (void) - char description[80]; - char cpu_string[16]; - char modes_string[16]; -+ char flags_string[80]; - int min_cpu; - int mode_bits; -+ int flag_bits; -+ int num_matched; - char *str; - - if (currentLine[0] == '#' || currentLine[0] == '\n') - continue; - memset (opcode, 0, 8); -- if (sscanf (currentLine, "%15s %15s %15s \"%79[^\"]\" %15s %15s", -- opcode, mnemonic, format, description, -- cpu_string, modes_string) == 6) -+ num_matched = -+ sscanf (currentLine, "%15s %15s %15s \"%79[^\"]\" %15s %15s %79[^\n]", -+ opcode, mnemonic, format, description, -+ cpu_string, modes_string, flags_string); -+ if (num_matched != 6 && num_matched != 7) - { -- if (strcmp (cpu_string, "g5") == 0) -- min_cpu = S390_OPCODE_G5; -- else if (strcmp (cpu_string, "g6") == 0) -- min_cpu = S390_OPCODE_G6; -- else if (strcmp (cpu_string, "z900") == 0) -- min_cpu = S390_OPCODE_Z900; -- else if (strcmp (cpu_string, "z990") == 0) -- min_cpu = S390_OPCODE_Z990; -- else if (strcmp (cpu_string, "z9-109") == 0) -- min_cpu = S390_OPCODE_Z9_109; -- else if (strcmp (cpu_string, "z9-ec") == 0) -- min_cpu = S390_OPCODE_Z9_EC; -- else if (strcmp (cpu_string, "z10") == 0) -- min_cpu = S390_OPCODE_Z10; -- else if (strcmp (cpu_string, "z196") == 0) -- min_cpu = S390_OPCODE_Z196; -- else if (strcmp (cpu_string, "zEC12") == 0) -- min_cpu = S390_OPCODE_ZEC12; -- else { -- fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string); -- exit (1); -- } -+ fprintf (stderr, "Couldn't scan line %s\n", currentLine); -+ exit (1); -+ } - -- str = modes_string; -- mode_bits = 0; -+ if (strcmp (cpu_string, "g5") == 0) -+ min_cpu = S390_OPCODE_G5; -+ else if (strcmp (cpu_string, "g6") == 0) -+ min_cpu = S390_OPCODE_G6; -+ else if (strcmp (cpu_string, "z900") == 0) -+ min_cpu = S390_OPCODE_Z900; -+ else if (strcmp (cpu_string, "z990") == 0) -+ min_cpu = S390_OPCODE_Z990; -+ else if (strcmp (cpu_string, "z9-109") == 0) -+ min_cpu = S390_OPCODE_Z9_109; -+ else if (strcmp (cpu_string, "z9-ec") == 0) -+ min_cpu = S390_OPCODE_Z9_EC; -+ else if (strcmp (cpu_string, "z10") == 0) -+ min_cpu = S390_OPCODE_Z10; -+ else if (strcmp (cpu_string, "z196") == 0) -+ min_cpu = S390_OPCODE_Z196; -+ else if (strcmp (cpu_string, "zEC12") == 0) -+ min_cpu = S390_OPCODE_ZEC12; -+ else if (strcmp (cpu_string, "z13") == 0) -+ min_cpu = S390_OPCODE_Z13; -+ else { -+ fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string); -+ exit (1); -+ } -+ -+ str = modes_string; -+ mode_bits = 0; -+ do { -+ if (strncmp (str, "esa", 3) == 0 -+ && (str[3] == 0 || str[3] == ',')) { -+ mode_bits |= 1 << S390_OPCODE_ESA; -+ str += 3; -+ } else if (strncmp (str, "zarch", 5) == 0 -+ && (str[5] == 0 || str[5] == ',')) { -+ mode_bits |= 1 << S390_OPCODE_ZARCH; -+ str += 5; -+ } else { -+ fprintf (stderr, "Couldn't parse modes string %s\n", -+ modes_string); -+ exit (1); -+ } -+ if (*str == ',') -+ str++; -+ } while (*str != 0); -+ -+ flag_bits = 0; -+ -+ if (num_matched == 7) -+ { -+ str = flags_string; - do { -- if (strncmp (str, "esa", 3) == 0 -- && (str[3] == 0 || str[3] == ',')) { -- mode_bits |= 1 << S390_OPCODE_ESA; -- str += 3; -- } else if (strncmp (str, "zarch", 5) == 0 -- && (str[5] == 0 || str[5] == ',')) { -- mode_bits |= 1 << S390_OPCODE_ZARCH; -- str += 5; -+ if (strncmp (str, "optparm", 7) == 0 -+ && (str[7] == 0 || str[7] == ',')) { -+ flag_bits |= S390_INSTR_FLAG_OPTPARM; -+ str += 7; - } else { -- fprintf (stderr, "Couldn't parse modes string %s\n", -- modes_string); -+ fprintf (stderr, "Couldn't parse flags string %s\n", -+ flags_string); - exit (1); - } - if (*str == ',') - str++; - } while (*str != 0); -- -- insertExpandedMnemonic (opcode, mnemonic, format, min_cpu, mode_bits); -- } -- else -- { -- fprintf (stderr, "Couldn't scan line %s\n", currentLine); -- exit (1); - } -+ insertExpandedMnemonic (opcode, mnemonic, format, min_cpu, mode_bits, flag_bits); - } - - dumpTable (); -diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c -index a99eeb2..ca82ce5 100644 ---- a/opcodes/s390-opc.c -+++ b/opcodes/s390-opc.c -@@ -44,197 +44,210 @@ const struct s390_operand s390_operands[] = - - /* General purpose register operands. */ - --#define R_8 1 /* GPR starting at position 8 */ -+#define R_8 1 /* GPR starting at position 8 */ - { 4, 8, S390_OPERAND_GPR }, --#define R_12 2 /* GPR starting at position 12 */ -+#define R_12 2 /* GPR starting at position 12 */ - { 4, 12, S390_OPERAND_GPR }, --#define RO_12 3 /* optional GPR starting at position 12 */ -- { 4, 12, S390_OPERAND_GPR | S390_OPERAND_OPTIONAL }, --#define R_16 4 /* GPR starting at position 16 */ -+#define R_16 3 /* GPR starting at position 16 */ - { 4, 16, S390_OPERAND_GPR }, --#define R_20 5 /* GPR starting at position 20 */ -+#define R_20 4 /* GPR starting at position 20 */ - { 4, 20, S390_OPERAND_GPR }, --#define R_24 6 /* GPR starting at position 24 */ -+#define R_24 5 /* GPR starting at position 24 */ - { 4, 24, S390_OPERAND_GPR }, --#define R_28 7 /* GPR starting at position 28 */ -+#define R_28 6 /* GPR starting at position 28 */ - { 4, 28, S390_OPERAND_GPR }, --#define RO_28 8 /* optional GPR starting at position 28 */ -- { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) }, --#define R_32 9 /* GPR starting at position 32 */ -+#define R_32 7 /* GPR starting at position 32 */ - { 4, 32, S390_OPERAND_GPR }, - - /* General purpose register pair operands. */ - --#define RE_8 10 /* GPR starting at position 8 */ -+#define RE_8 8 /* GPR starting at position 8 */ - { 4, 8, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, --#define RE_12 11 /* GPR starting at position 12 */ -+#define RE_12 9 /* GPR starting at position 12 */ - { 4, 12, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, --#define RE_16 12 /* GPR starting at position 16 */ -+#define RE_16 10 /* GPR starting at position 16 */ - { 4, 16, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, --#define RE_20 13 /* GPR starting at position 20 */ -+#define RE_20 11 /* GPR starting at position 20 */ - { 4, 20, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, --#define RE_24 14 /* GPR starting at position 24 */ -+#define RE_24 12 /* GPR starting at position 24 */ - { 4, 24, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, --#define RE_28 15 /* GPR starting at position 28 */ -+#define RE_28 13 /* GPR starting at position 28 */ - { 4, 28, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, --#define RE_32 16 /* GPR starting at position 32 */ -+#define RE_32 14 /* GPR starting at position 32 */ - { 4, 32, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, - -- - /* Floating point register operands. */ - --#define F_8 17 /* FPR starting at position 8 */ -+#define F_8 15 /* FPR starting at position 8 */ - { 4, 8, S390_OPERAND_FPR }, --#define F_12 18 /* FPR starting at position 12 */ -+#define F_12 16 /* FPR starting at position 12 */ - { 4, 12, S390_OPERAND_FPR }, --#define F_16 19 /* FPR starting at position 16 */ -+#define F_16 17 /* FPR starting at position 16 */ - { 4, 16, S390_OPERAND_FPR }, --#define F_20 20 /* FPR starting at position 16 */ -+#define F_20 18 /* FPR starting at position 16 */ - { 4, 16, S390_OPERAND_FPR }, --#define F_24 21 /* FPR starting at position 24 */ -+#define F_24 19 /* FPR starting at position 24 */ - { 4, 24, S390_OPERAND_FPR }, --#define F_28 22 /* FPR starting at position 28 */ -+#define F_28 20 /* FPR starting at position 28 */ - { 4, 28, S390_OPERAND_FPR }, --#define F_32 23 /* FPR starting at position 32 */ -+#define F_32 21 /* FPR starting at position 32 */ - { 4, 32, S390_OPERAND_FPR }, - - /* Floating point register pair operands. */ - --#define FE_8 24 /* FPR starting at position 8 */ -+#define FE_8 22 /* FPR starting at position 8 */ - { 4, 8, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, --#define FE_12 25 /* FPR starting at position 12 */ -+#define FE_12 23 /* FPR starting at position 12 */ - { 4, 12, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, --#define FE_16 26 /* FPR starting at position 16 */ -+#define FE_16 24 /* FPR starting at position 16 */ - { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, --#define FE_20 27 /* FPR starting at position 16 */ -+#define FE_20 25 /* FPR starting at position 16 */ - { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, --#define FE_24 28 /* FPR starting at position 24 */ -+#define FE_24 26 /* FPR starting at position 24 */ - { 4, 24, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, --#define FE_28 29 /* FPR starting at position 28 */ -+#define FE_28 27 /* FPR starting at position 28 */ - { 4, 28, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, --#define FE_32 30 /* FPR starting at position 32 */ -+#define FE_32 28 /* FPR starting at position 32 */ - { 4, 32, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, - -+/* Vector register operands. */ -+ -+/* For each of these operands and additional bit in the RXB operand is -+ needed. */ -+ -+#define V_8 29 /* Vector reg. starting at position 8 */ -+ { 4, 8, S390_OPERAND_VR }, -+#define V_12 30 /* Vector reg. starting at position 12 */ -+ { 4, 12, S390_OPERAND_VR }, -+#define V_CP16_12 31 /* Vector reg. starting at position 12 */ -+ { 4, 12, S390_OPERAND_VR | S390_OPERAND_CP16 }, /* with a copy at pos 16 */ -+#define V_16 32 /* Vector reg. starting at position 16 */ -+ { 4, 16, S390_OPERAND_VR }, -+#define V_32 33 /* Vector reg. starting at position 32 */ -+ { 4, 32, S390_OPERAND_VR }, - - /* Access register operands. */ - --#define A_8 31 /* Access reg. starting at position 8 */ -+#define A_8 34 /* Access reg. starting at position 8 */ - { 4, 8, S390_OPERAND_AR }, --#define A_12 32 /* Access reg. starting at position 12 */ -+#define A_12 35 /* Access reg. starting at position 12 */ - { 4, 12, S390_OPERAND_AR }, --#define A_24 33 /* Access reg. starting at position 24 */ -+#define A_24 36 /* Access reg. starting at position 24 */ - { 4, 24, S390_OPERAND_AR }, --#define A_28 34 /* Access reg. starting at position 28 */ -+#define A_28 37 /* Access reg. starting at position 28 */ - { 4, 28, S390_OPERAND_AR }, - - /* Control register operands. */ - --#define C_8 35 /* Control reg. starting at position 8 */ -+#define C_8 38 /* Control reg. starting at position 8 */ - { 4, 8, S390_OPERAND_CR }, --#define C_12 36 /* Control reg. starting at position 12 */ -+#define C_12 39 /* Control reg. starting at position 12 */ - { 4, 12, S390_OPERAND_CR }, - - /* Base register operands. */ - --#define B_16 37 /* Base register starting at position 16 */ -+#define B_16 40 /* Base register starting at position 16 */ - { 4, 16, S390_OPERAND_BASE | S390_OPERAND_GPR }, --#define B_32 38 /* Base register starting at position 32 */ -+#define B_32 41 /* Base register starting at position 32 */ - { 4, 32, S390_OPERAND_BASE | S390_OPERAND_GPR }, - --#define X_12 39 /* Index register starting at position 12 */ -+#define X_12 42 /* Index register starting at position 12 */ - { 4, 12, S390_OPERAND_INDEX | S390_OPERAND_GPR }, - -+#define VX_12 43 /* Vector index register starting at position 12 */ -+ { 4, 12, S390_OPERAND_INDEX | S390_OPERAND_VR }, -+ - /* Address displacement operands. */ - --#define D_20 40 /* Displacement starting at position 20 */ -+#define D_20 44 /* Displacement starting at position 20 */ - { 12, 20, S390_OPERAND_DISP }, --#define DO_20 41 /* optional Displ. starting at position 20 */ -- { 12, 20, S390_OPERAND_DISP | S390_OPERAND_OPTIONAL }, --#define D_36 42 /* Displacement starting at position 36 */ -+#define D_36 45 /* Displacement starting at position 36 */ - { 12, 36, S390_OPERAND_DISP }, --#define D20_20 43 /* 20 bit displacement starting at 20 */ -+#define D20_20 46 /* 20 bit displacement starting at 20 */ - { 20, 20, S390_OPERAND_DISP | S390_OPERAND_SIGNED }, - - /* Length operands. */ - --#define L4_8 44 /* 4 bit length starting at position 8 */ -+#define L4_8 47 /* 4 bit length starting at position 8 */ - { 4, 8, S390_OPERAND_LENGTH }, --#define L4_12 45 /* 4 bit length starting at position 12 */ -+#define L4_12 48 /* 4 bit length starting at position 12 */ - { 4, 12, S390_OPERAND_LENGTH }, --#define L8_8 46 /* 8 bit length starting at position 8 */ -+#define L8_8 49 /* 8 bit length starting at position 8 */ - { 8, 8, S390_OPERAND_LENGTH }, - - /* Signed immediate operands. */ - --#define I8_8 47 /* 8 bit signed value starting at 8 */ -+#define I8_8 50 /* 8 bit signed value starting at 8 */ - { 8, 8, S390_OPERAND_SIGNED }, --#define I8_32 48 /* 8 bit signed value starting at 32 */ -+#define I8_32 51 /* 8 bit signed value starting at 32 */ - { 8, 32, S390_OPERAND_SIGNED }, --#define I12_12 49 /* 12 bit signed value starting at 12 */ -+#define I12_12 52 /* 12 bit signed value starting at 12 */ - { 12, 12, S390_OPERAND_SIGNED }, --#define I16_16 50 /* 16 bit signed value starting at 16 */ -+#define I16_16 53 /* 16 bit signed value starting at 16 */ - { 16, 16, S390_OPERAND_SIGNED }, --#define I16_32 51 /* 16 bit signed value starting at 32 */ -+#define I16_32 54 /* 16 bit signed value starting at 32 */ - { 16, 32, S390_OPERAND_SIGNED }, --#define I24_24 52 /* 24 bit signed value starting at 24 */ -+#define I24_24 55 /* 24 bit signed value starting at 24 */ - { 24, 24, S390_OPERAND_SIGNED }, --#define I32_16 53 /* 32 bit signed value starting at 16 */ -+#define I32_16 56 /* 32 bit signed value starting at 16 */ - { 32, 16, S390_OPERAND_SIGNED }, - - /* Unsigned immediate operands. */ - --#define U4_8 54 /* 4 bit unsigned value starting at 8 */ -+#define U4_8 57 /* 4 bit unsigned value starting at 8 */ - { 4, 8, 0 }, --#define U4_12 55 /* 4 bit unsigned value starting at 12 */ -+#define U4_12 58 /* 4 bit unsigned value starting at 12 */ - { 4, 12, 0 }, --#define U4_16 56 /* 4 bit unsigned value starting at 16 */ -+#define U4_16 59 /* 4 bit unsigned value starting at 16 */ - { 4, 16, 0 }, --#define U4_20 57 /* 4 bit unsigned value starting at 20 */ -+#define U4_20 60 /* 4 bit unsigned value starting at 20 */ - { 4, 20, 0 }, --#define U4_24 58 /* 4 bit unsigned value starting at 24 */ -+#define U4_24 61 /* 4 bit unsigned value starting at 24 */ - { 4, 24, 0 }, --#define U4_28 59 /* 4 bit unsigned value starting at 28 */ -+#define U4_OR1_24 62 /* 4 bit unsigned value starting at 24 */ -+ { 4, 24, S390_OPERAND_OR1 }, -+#define U4_OR2_24 63 /* 4 bit unsigned value starting at 24 */ -+ { 4, 24, S390_OPERAND_OR2 }, -+#define U4_OR3_24 64 /* 4 bit unsigned value starting at 24 */ -+ { 4, 24, S390_OPERAND_OR1 | S390_OPERAND_OR2 }, -+#define U4_28 65 /* 4 bit unsigned value starting at 28 */ - { 4, 28, 0 }, --#define U4_32 60 /* 4 bit unsigned value starting at 32 */ -+#define U4_OR8_28 66 -+ { 4, 28, S390_OPERAND_OR8 }, -+#define U4_32 67 /* 4 bit unsigned value starting at 32 */ - { 4, 32, 0 }, --#define U4_36 61 /* 4 bit unsigned value starting at 36 */ -+#define U4_36 68 /* 4 bit unsigned value starting at 36 */ - { 4, 36, 0 }, --#define U8_8 62 /* 8 bit unsigned value starting at 8 */ -+#define U8_8 69 /* 8 bit unsigned value starting at 8 */ - { 8, 8, 0 }, --#define U8_16 63 /* 8 bit unsigned value starting at 16 */ -+#define U8_16 70 /* 8 bit unsigned value starting at 16 */ - { 8, 16, 0 }, --#define U8_24 64 /* 8 bit unsigned value starting at 24 */ -+#define U8_24 71 /* 8 bit unsigned value starting at 24 */ - { 8, 24, 0 }, --#define U8_32 65 /* 8 bit unsigned value starting at 32 */ -+#define U8_32 72 /* 8 bit unsigned value starting at 32 */ - { 8, 32, 0 }, --#define U16_16 66 /* 16 bit unsigned value starting at 16 */ -+#define U12_16 73 /* 12 bit unsigned value starting at 16 */ -+ { 12, 16, 0 }, -+#define U16_16 74 /* 16 bit unsigned value starting at 16 */ - { 16, 16, 0 }, --#define U16_32 67 /* 16 bit unsigned value starting at 32 */ -+#define U16_32 75 /* 16 bit unsigned value starting at 32 */ - { 16, 32, 0 }, --#define U32_16 68 /* 32 bit unsigned value starting at 16 */ -+#define U32_16 76 /* 32 bit unsigned value starting at 16 */ - { 32, 16, 0 }, - - /* PC-relative address operands. */ - --#define J12_12 69 /* 12 bit PC relative offset at 12 */ -+#define J12_12 77 /* 12 bit PC relative offset at 12 */ - { 12, 12, S390_OPERAND_PCREL }, --#define J16_16 70 /* 16 bit PC relative offset at 16 */ -+#define J16_16 78 /* 16 bit PC relative offset at 16 */ - { 16, 16, S390_OPERAND_PCREL }, --#define J16_32 71 /* 16 bit PC relative offset at 32 */ -+#define J16_32 79 /* 24 bit PC relative offset at 24 */ - { 16, 32, S390_OPERAND_PCREL }, --#define J24_24 72 /* 24 bit PC relative offset at 24 */ -+#define J24_24 80 /* 24 bit PC relative offset at 24 */ - { 24, 24, S390_OPERAND_PCREL }, --#define J32_16 73 /* 32 bit PC relative offset at 16 */ -+#define J32_16 81 /* 32 bit PC relative offset at 16 */ - { 32, 16, S390_OPERAND_PCREL }, - -- --/* Conditional mask operands. */ -- --#define M_16OPT 74 /* 4 bit optional mask starting at 16 */ -- { 4, 16, S390_OPERAND_OPTIONAL }, --#define M_20OPT 75 /* 4 bit optional mask starting at 20 */ -- { 4, 20, S390_OPERAND_OPTIONAL }, -- - }; - - -@@ -244,7 +257,7 @@ const struct s390_operand s390_operands[] = - #define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 } - #define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 } - #define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \ -- (x >> 16) & 255, (x >> 8) & 255, x & 255} -+ (x >> 16) & 255, (x >> 8) & 255, x & 255} - - /* The new format of the INSTR_x_y and MASK_x_y defines is based - on the following rules: -@@ -263,7 +276,6 @@ const struct s390_operand s390_operands[] = - l - length, 4 or 8 bit - p - pc relative - r - general purpose register -- ro - optional register operand - re - gpr extended operand, a valid general purpose register pair - u - unsigned integer, 4, 8, 16 or 32 bit - m - mode field, 4 bit -@@ -274,7 +286,7 @@ const struct s390_operand s390_operands[] = - quite close. - - For example the instruction "mvo" is defined in the PoP as follows: -- -+ - MVO D1(L1,B1),D2(L2,B2) [SS] - - -------------------------------------- -@@ -284,358 +296,443 @@ const struct s390_operand s390_operands[] = - - The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */ - --#define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ --#define INSTR_IE_UU 4, { U4_24,U4_28,0,0,0,0 } /* e.g. niai */ --#define INSTR_MII_UPP 6, { U4_8,J12_12,J24_24 } /* e.g. bprp */ --#define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ --#define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */ --#define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. crjne */ --#define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */ --#define INSTR_RIE_RUPI 6, { R_8,I8_32,U4_12,J16_16,0,0 } /* e.g. cij */ --#define INSTR_RIE_R0PI 6, { R_8,I8_32,J16_16,0,0,0 } /* e.g. cijne */ --#define INSTR_RIE_RUPU 6, { R_8,U8_32,U4_12,J16_16,0,0 } /* e.g. clij */ --#define INSTR_RIE_R0PU 6, { R_8,U8_32,J16_16,0,0,0 } /* e.g. clijne */ --#define INSTR_RIE_R0IU 6, { R_8,I16_16,U4_32,0,0,0 } /* e.g. cit */ --#define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */ --#define INSTR_RIE_R0UU 6, { R_8,U16_16,U4_32,0,0,0 } /* e.g. clfit */ --#define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */ --#define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */ --#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ --#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ --#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ --#define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */ --#define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */ --#define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */ --#define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */ --#define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ --#define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ --#define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ --#define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */ --#define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */ --#define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */ --#define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/ --#define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ --#define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ --#define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ --#define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */ --#define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */ --#define INSTR_RRE_FE0 4, { FE_24,0,0,0,0,0 } /* e.g. lzxr */ --#define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */ --#define INSTR_RRE_FEF 4, { FE_24,F_28,0,0,0,0 } /* e.g. lxdbr */ --#define INSTR_RRE_FFE 4, { F_24,FE_28,0,0,0,0 } /* e.g. lexr */ --#define INSTR_RRE_FEFE 4, { FE_24,FE_28,0,0,0,0 } /* e.g. dxr */ --#define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */ --#define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ --#define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */ --#define INSTR_RRE_RFE 4, { R_24,FE_28,0,0,0,0 } /* e.g. csxtr */ --#define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ --#define INSTR_RRE_RER 4, { RE_24,R_28,0,0,0,0 } /* e.g. tre */ --#define INSTR_RRE_RERE 4, { RE_24,RE_28,0,0,0,0 } /* e.g. cuse */ --#define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */ --#define INSTR_RRE_FER 4, { FE_24,R_28,0,0,0,0 } /* e.g. cxfbr */ --/* Actually efpc and sfpc do not take an optional operand. -- This is just a workaround for existing code e.g. glibc. */ --#define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 } /* efpc, sfpc */ --#define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ --#define INSTR_RRF_FE0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. myr */ --#define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */ --#define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */ --#define INSTR_RRF_FE0FER 4, { FE_24,FE_16,R_28,0,0,0 } /* e.g. iextr */ --#define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ --#define INSTR_RRF_FEUFEFE 4, { FE_24,FE_16,FE_28,U4_20,0,0 } /* e.g. qaxtr */ --#define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } /* e.g. adtra */ --#define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } /* e.g. axtra */ --#define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ --#define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. lptea */ --#define INSTR_RRF_R0RR 4, { R_24,R_16,R_28,0,0,0 } /* e.g. idte */ --#define INSTR_RRF_R0RR2 4, { R_24,R_28,R_16,0,0,0 } /* e.g. ark */ --#define INSTR_RRF_RMRR 4, { R_24,R_16,R_28,M_20OPT,0,0 } /* e.g. crdte */ --#define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */ --#define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */ --#define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ --#define INSTR_RRF_U0RFE 4, { R_24,U4_16,FE_28,0,0,0 } /* e.g. cfxbr */ --#define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ --#define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */ --#define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */ --#define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ --#define INSTR_RRF_0UFEF 4, { FE_24,F_28,U4_20,0,0,0 } /* e.g. lxdtr */ --#define INSTR_RRF_FFRU 4, { F_24,F_16,R_28,U4_20,0,0 } /* e.g. rrdtr */ --#define INSTR_RRF_FEFERU 4, { FE_24,FE_16,R_28,U4_20,0,0 } /* e.g. rrxtr */ --#define INSTR_RRF_M0RR 4, { R_24,R_28,M_16OPT,0,0,0 } /* e.g. sske */ --#define INSTR_RRF_M0RER 4, { RE_24,R_28,M_16OPT,0,0,0 } /* e.g. trte */ --#define INSTR_RRF_M0RERE 4, { RE_24,RE_28,M_16OPT,0,0,0 } /* e.g. troo */ --#define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. clrt */ --#define INSTR_RRF_00RR 4, { R_24,R_28,0,0,0,0 } /* e.g. clrtne */ --#define INSTR_RRF_UUFR 4, { F_24,U4_16,R_28,U4_20,0,0 } /* e.g. cdgtra */ --#define INSTR_RRF_UUFER 4, { FE_24,U4_16,R_28,U4_20,0,0 } /* e.g. cxfbra */ --#define INSTR_RRF_UURF 4, { R_24,U4_16,F_28,U4_20,0,0 } /* e.g. cgdtra */ --#define INSTR_RRF_UURFE 4, { R_24,U4_16,FE_28,U4_20,0,0 } /* e.g. cfxbra */ --#define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ --#define INSTR_RR_0R_OPT 2, { RO_12, 0,0,0,0,0 } /* e.g. nopr */ --#define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ --#define INSTR_RR_FEF 2, { FE_8,F_12,0,0,0,0 } /* e.g. mxdr */ --#define INSTR_RR_FFE 2, { F_8,FE_12,0,0,0,0 } /* e.g. ldxr */ --#define INSTR_RR_FEFE 2, { FE_8,FE_12,0,0,0,0 } /* e.g. axr */ --#define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ --#define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ --#define INSTR_RR_RER 2, { RE_8,R_12,0,0,0,0 } /* e.g. dr */ --#define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ --#define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ --#define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */ --#define INSTR_RRR_FE0FEFE 4, { FE_24,FE_28,FE_16,0,0,0 } /* e.g. axtr */ --#define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */ --#define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */ --#define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ --#define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu */ --#define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ --#define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ --#define INSTR_RSL_R0RD 6, { D_20,L4_8,B_16,0,0,0 } /* e.g. tp */ --#define INSTR_RSL_LRDFU 6, { F_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cdzt */ --#define INSTR_RSL_LRDFEU 6, { FE_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cxzt */ --#define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ --#define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ --#define INSTR_RSY_RERERD 6, { RE_8,RE_12,D20_20,B_16,0,0 } /* e.g. cdsy */ --#define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ --#define INSTR_RSY_RURD2 6, { R_8,D20_20,B_16,U4_12,0,0 } /* e.g. loc */ --#define INSTR_RSY_R0RD 6, { R_8,D20_20,B_16,0,0,0 } /* e.g. locgt */ --#define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ --#define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. stctg */ --#define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ --#define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ --#define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ --#define INSTR_RS_RE0RD 4, { RE_8,D_20,B_16,0,0,0 } /* e.g. slda */ --#define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */ --#define INSTR_RS_RERERD 4, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. cds */ --#define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */ --#define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */ --#define INSTR_RXE_FERRD 6, { FE_8,D_20,X_12,B_16,0,0 } /* e.g. lxdb */ --#define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ --#define INSTR_RXE_RERRD 6, { RE_8,D_20,X_12,B_16,0,0 } /* e.g. dsg */ --#define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ --#define INSTR_RXF_FRRDFE 6, { FE_32,F_8,D_20,X_12,B_16,0 } /* e.g. my */ --#define INSTR_RXF_FERRDFE 6, { FE_32,FE_8,D_20,X_12,B_16,0 } /* e.g. slxt */ --#define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ --#define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */ --#define INSTR_RXY_RERRD 6, { RE_8,D20_20,X_12,B_16,0,0 } /* e.g. dsg */ --#define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ --#define INSTR_RXY_URRD 6, { U4_8,D20_20,X_12,B_16,0,0 } /* e.g. pfd */ --#define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ --#define INSTR_RX_0RRD_OPT 4, { DO_20,X_12,B_16,0,0,0 } /* e.g. nop */ --#define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ --#define INSTR_RX_FERRD 4, { FE_8,D_20,X_12,B_16,0,0 } /* e.g. mxd */ --#define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ --#define INSTR_RX_RERRD 4, { RE_8,D_20,X_12,B_16,0,0 } /* e.g. d */ --#define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ --#define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ --#define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ --#define INSTR_SIY_IRD 6, { D20_20,B_16,I8_8,0,0,0 } /* e.g. asi */ --#define INSTR_SIL_RDI 6, { D_20,B_16,I16_32,0,0,0 } /* e.g. chhsi */ --#define INSTR_SIL_RDU 6, { D_20,B_16,U16_32,0,0,0 } /* e.g. clfhsi */ --#define INSTR_SMI_U0RDP 6, { U4_8,J16_32,D_20,B_16,0,0 } /* e.g. bpp */ --#define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */ --#define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ --#define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */ --#define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ --#define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ --#define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ --#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ --#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ --#define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */ --#define INSTR_SSF_RRDRD2 6, { R_8,D_20,B_16,D_36,B_32,0 } --#define INSTR_SSF_RERDRD2 6, { RE_8,D_20,B_16,D_36,B_32,0 } /* e.g. lpd */ --#define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ --#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ -- --#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_IE_UU { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } --#define MASK_MII_UPP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } --#define MASK_RIE_RRPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } --#define MASK_RIE_RRP0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } --#define MASK_RIE_RRI0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } --#define MASK_RIE_RUPI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } --#define MASK_RIE_R0PI { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } --#define MASK_RIE_RUPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } --#define MASK_RIE_R0PU { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } --#define MASK_RIE_R0IU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } --#define MASK_RIE_R0I0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } --#define MASK_RIE_R0UU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } --#define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } --#define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } --#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RIS_RURDI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } --#define MASK_RIS_R0RDI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } --#define MASK_RIS_RURDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } --#define MASK_RIS_R0RDU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } --#define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } --#define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } --#define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } --#define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } --#define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } --#define MASK_RRE_FE0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } --#define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } --#define MASK_RRE_FEF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } --#define MASK_RRE_FFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } --#define MASK_RRE_FEFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } --#define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } --#define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } --#define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } --#define MASK_RRE_RFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } --#define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } --#define MASK_RRE_RER { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } --#define MASK_RRE_RERE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } --#define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } --#define MASK_RRE_FER { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } --#define MASK_RRE_RR_OPT { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } --#define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } --#define MASK_RRF_FE0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } --#define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } --#define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } --#define MASK_RRF_FE0FER { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } --#define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RRF_FEUFEFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RRF_FUFF2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ -+#define INSTR_IE_UU 4, { U4_24,U4_28,0,0,0,0 } /* e.g. niai */ -+#define INSTR_MII_UPP 6, { U4_8,J12_12,J24_24 } /* e.g. bprp */ -+#define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ -+#define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */ -+#define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. cgrjne */ -+#define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */ -+#define INSTR_RIE_RUPI 6, { R_8,I8_32,U4_12,J16_16,0,0 } /* e.g. cij */ -+#define INSTR_RIE_R0PI 6, { R_8,I8_32,J16_16,0,0,0 } /* e.g. cijne */ -+#define INSTR_RIE_RUPU 6, { R_8,U8_32,U4_12,J16_16,0,0 } /* e.g. clij */ -+#define INSTR_RIE_R0PU 6, { R_8,U8_32,J16_16,0,0,0 } /* e.g. clijne */ -+#define INSTR_RIE_R0IU 6, { R_8,I16_16,U4_32,0,0,0 } /* e.g. cit */ -+#define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */ -+#define INSTR_RIE_R0UU 6, { R_8,U16_16,U4_32,0,0,0 } /* e.g. clfit */ -+#define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */ -+#define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */ -+#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ -+#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ -+#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ -+#define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */ -+#define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */ -+#define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */ -+#define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */ -+#define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ -+#define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ -+#define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ -+#define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */ -+#define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */ -+#define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */ -+#define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/ -+#define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ -+#define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ -+#define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ -+#define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */ -+#define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. lzer */ -+#define INSTR_RRE_FE0 4, { FE_24,0,0,0,0,0 } /* e.g. lzxr */ -+#define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */ -+#define INSTR_RRE_FEF 4, { FE_24,F_28,0,0,0,0 } /* e.g. lxdbr */ -+#define INSTR_RRE_FFE 4, { F_24,FE_28,0,0,0,0 } /* e.g. lexr */ -+#define INSTR_RRE_FEFE 4, { FE_24,FE_28,0,0,0,0 } /* e.g. dxr */ -+#define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */ -+#define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ -+#define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. lgdr */ -+#define INSTR_RRE_RFE 4, { R_24,FE_28,0,0,0,0 } /* e.g. csxtr */ -+#define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ -+#define INSTR_RRE_RER 4, { RE_24,R_28,0,0,0,0 } /* e.g. tre */ -+#define INSTR_RRE_RERE 4, { RE_24,RE_28,0,0,0,0 } /* e.g. cuse */ -+#define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */ -+#define INSTR_RRE_FER 4, { FE_24,R_28,0,0,0,0 } /* e.g. cxfbr */ -+#define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ -+#define INSTR_RRF_FE0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. myr */ -+#define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */ -+#define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */ -+#define INSTR_RRF_FE0FER 4, { FE_24,FE_16,R_28,0,0,0 } /* e.g. iextr */ -+#define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ -+#define INSTR_RRF_FEUFEFE 4, { FE_24,FE_16,FE_28,U4_20,0,0 } /* e.g. qaxtr */ -+#define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } /* e.g. adtra */ -+#define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } /* e.g. axtra */ -+#define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ -+#define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. lptea */ -+#define INSTR_RRF_R0RR 4, { R_24,R_16,R_28,0,0,0 } /* e.g. idte */ -+#define INSTR_RRF_R0RR2 4, { R_24,R_28,R_16,0,0,0 } /* e.g. ark */ -+#define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fidbr */ -+#define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */ -+#define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ -+#define INSTR_RRF_U0RFE 4, { R_24,U4_16,FE_28,0,0,0 } /* e.g. cfxbr */ -+#define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ -+#define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */ -+#define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */ -+#define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ -+#define INSTR_RRF_0UFEF 4, { FE_24,F_28,U4_20,0,0,0 } /* e.g. lxdtr */ -+#define INSTR_RRF_FFRU 4, { F_24,F_16,R_28,U4_20,0,0 } /* e.g. rrdtr */ -+#define INSTR_RRF_FEFERU 4, { FE_24,FE_16,R_28,U4_20,0,0 } /* e.g. rrxtr */ -+#define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. sske */ -+#define INSTR_RRF_U0RER 4, { RE_24,R_28,U4_16,0,0,0 } /* e.g. trte */ -+#define INSTR_RRF_U0RERE 4, { RE_24,RE_28,U4_16,0,0,0 } /* e.g. troo */ -+#define INSTR_RRF_00RR 4, { R_24,R_28,0,0,0,0 } /* e.g. clrtne */ -+#define INSTR_RRF_UUFR 4, { F_24,U4_16,R_28,U4_20,0,0 } /* e.g. cdgtra */ -+#define INSTR_RRF_UUFER 4, { FE_24,U4_16,R_28,U4_20,0,0 } /* e.g. cxfbra */ -+#define INSTR_RRF_UURF 4, { R_24,U4_16,F_28,U4_20,0,0 } /* e.g. cgdtra */ -+#define INSTR_RRF_UURFE 4, { R_24,U4_16,FE_28,U4_20,0,0 } /* e.g. cfxbra */ -+#define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ -+#define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ -+#define INSTR_RR_FEF 2, { FE_8,F_12,0,0,0,0 } /* e.g. mxdr */ -+#define INSTR_RR_FFE 2, { F_8,FE_12,0,0,0,0 } /* e.g. ldxr */ -+#define INSTR_RR_FEFE 2, { FE_8,FE_12,0,0,0,0 } /* e.g. axr */ -+#define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ -+#define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ -+#define INSTR_RR_RER 2, { RE_8,R_12,0,0,0,0 } /* e.g. dr */ -+#define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ -+#define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ -+#define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */ -+#define INSTR_RRR_FE0FEFE 4, { FE_24,FE_28,FE_16,0,0,0 } /* e.g. axtr */ -+#define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */ -+#define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */ -+#define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ -+#define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu */ -+#define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. stctg */ -+#define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ -+#define INSTR_RSL_R0RD 6, { D_20,L4_8,B_16,0,0,0 } /* e.g. tp */ -+#define INSTR_RSL_LRDFU 6, { F_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cdzt */ -+#define INSTR_RSL_LRDFEU 6, { FE_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cxzt */ -+#define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ -+#define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ -+#define INSTR_RSY_RERERD 6, { RE_8,RE_12,D20_20,B_16,0,0 } /* e.g. cdsy */ -+#define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ -+#define INSTR_RSY_RURD2 6, { R_8,D20_20,B_16,U4_12,0,0 } /* e.g. loc */ -+#define INSTR_RSY_R0RD 6, { R_8,D20_20,B_16,0,0,0 } /* e.g. locne */ -+#define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ -+#define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. stctg */ -+#define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ -+#define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ -+#define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ -+#define INSTR_RS_RE0RD 4, { RE_8,D_20,B_16,0,0,0 } /* e.g. slda */ -+#define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */ -+#define INSTR_RS_RERERD 4, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. cds */ -+#define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */ -+#define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. adb */ -+#define INSTR_RXE_FERRD 6, { FE_8,D_20,X_12,B_16,0,0 } /* e.g. lxdb */ -+#define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ -+#define INSTR_RXE_RRRDU 6, { R_8,D_20,X_12,B_16,U4_32,0 } /* e.g. lcbb */ -+#define INSTR_RXE_RERRD 6, { RE_8,D_20,X_12,B_16,0,0 } /* e.g. dsg */ -+#define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ -+#define INSTR_RXF_FRRDFE 6, { FE_32,F_8,D_20,X_12,B_16,0 } /* e.g. my */ -+#define INSTR_RXF_FERRDFE 6, { FE_32,FE_8,D_20,X_12,B_16,0 } /* e.g. slxt */ -+#define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ -+#define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */ -+#define INSTR_RXY_RERRD 6, { RE_8,D20_20,X_12,B_16,0,0 } /* e.g. dsg */ -+#define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ -+#define INSTR_RXY_URRD 6, { U4_8,D20_20,X_12,B_16,0,0 } /* e.g. pfd */ -+#define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ -+#define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ -+#define INSTR_RX_FERRD 4, { FE_8,D_20,X_12,B_16,0,0 } /* e.g. mxd */ -+#define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ -+#define INSTR_RX_RERRD 4, { RE_8,D_20,X_12,B_16,0,0 } /* e.g. d */ -+#define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ -+#define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ -+#define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ -+#define INSTR_SIY_IRD 6, { D20_20,B_16,I8_8,0,0,0 } /* e.g. asi */ -+#define INSTR_SIL_RDI 6, { D_20,B_16,I16_32,0,0,0 } /* e.g. chhsi */ -+#define INSTR_SIL_RDU 6, { D_20,B_16,U16_32,0,0,0 } /* e.g. clfhsi */ -+#define INSTR_SMI_U0RDP 6, { U4_8,J16_32,D_20,B_16,0,0 } /* e.g. bpp */ -+#define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvcdk */ -+#define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ -+#define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */ -+#define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ -+#define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ -+#define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ -+#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ -+#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ -+#define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */ -+#define INSTR_SSF_RERDRD2 6, { RE_8,D_20,B_16,D_36,B_32,0 } /* e.g. lpd */ -+#define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ -+#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ -+#define INSTR_VRV_VVXRDU 6, { V_8,D_20,VX_12,B_16,U4_32,0 } /* e.g. vgef */ -+#define INSTR_VRI_V0U 6, { V_8,U16_16,0,0,0,0 } /* e.g. vgbm */ -+#define INSTR_VRI_V 6, { V_8,0,0,0,0,0 } /* e.g. vzero */ -+#define INSTR_VRI_V0UUU 6, { V_8,U8_16,U8_24,U4_32,0,0 } /* e.g. vgm */ -+#define INSTR_VRI_V0UU 6, { V_8,U8_16,U8_24,0,0,0 } /* e.g. vgmb */ -+#define INSTR_VRI_VVUU 6, { V_8,V_12,U16_16,U4_32,0,0 } /* e.g. vrep */ -+#define INSTR_VRI_VVU 6, { V_8,V_12,U16_16,0,0,0 } /* e.g. vrepb */ -+#define INSTR_VRI_VVU2 6, { V_8,V_12,U12_16,0,0,0 } /* e.g. vftcidb */ -+#define INSTR_VRI_V0IU 6, { V_8,I16_16,U4_32,0,0,0 } /* e.g. vrepi */ -+#define INSTR_VRI_V0I 6, { V_8,I16_16,0,0,0,0 } /* e.g. vrepib */ -+#define INSTR_VRI_VVV0UU 6, { V_8,V_12,V_16,U8_24,U4_32,0 } /* e.g. verim */ -+#define INSTR_VRI_VVV0U 6, { V_8,V_12,V_16,U8_24,0,0 } /* e.g. verimb*/ -+#define INSTR_VRI_VVUUU 6, { V_8,V_12,U12_16,U4_32,U4_28,0 } /* e.g. vftci */ -+#define INSTR_VRX_VRRD 6, { V_8,D_20,X_12,B_16,0,0 } /* e.g. vl */ -+#define INSTR_VRX_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vlr */ -+#define INSTR_VRX_VRRDU 6, { V_8,D_20,X_12,B_16,U4_32,0 } /* e.g. vlrp */ -+#define INSTR_VRS_RVRDU 6, { R_8,V_12,D_20,B_16,U4_32,0 } /* e.g. vlgv */ -+#define INSTR_VRS_RVRD 6, { R_8,V_12,D_20,B_16,0,0 } /* e.g. vlgvb */ -+#define INSTR_VRS_VVRDU 6, { V_8,V_12,D_20,B_16,U4_32,0 } /* e.g. verll */ -+#define INSTR_VRS_VVRD 6, { V_8,V_12,D_20,B_16,0,0 } /* e.g. vlm */ -+#define INSTR_VRS_VRRDU 6, { V_8,R_12,D_20,B_16,U4_32,0 } /* e.g. vlvg */ -+#define INSTR_VRS_VRRD 6, { V_8,R_12,D_20,B_16,0,0 } /* e.g. vlvgb */ -+#define INSTR_VRR_VRR 6, { V_8,R_12,R_16,0,0,0 } /* e.g. vlvgp */ -+#define INSTR_VRR_VVV0U 6, { V_8,V_12,V_16,U4_32,0,0 } /* e.g. vmrh */ -+#define INSTR_VRR_VVV0U0 6, { V_8,V_12,V_16,U4_24,0,0 } /* e.g. vfaeb */ -+#define INSTR_VRR_VVV0U1 6, { V_8,V_12,V_16,U4_OR1_24,0,0 } /* e.g. vfaebs*/ -+#define INSTR_VRR_VVV0U2 6, { V_8,V_12,V_16,U4_OR2_24,0,0 } /* e.g. vfaezb*/ -+#define INSTR_VRR_VVV0U3 6, { V_8,V_12,V_16,U4_OR3_24,0,0 } /* e.g. vfaezbs*/ -+#define INSTR_VRR_VVV 6, { V_8,V_12,V_16,0,0,0 } /* e.g. vmrhb */ -+#define INSTR_VRR_VVV2 6, { V_8,V_CP16_12,0,0,0,0 } /* e.g. vnot */ -+#define INSTR_VRR_VV0U 6, { V_8,V_12,U4_32,0,0,0 } /* e.g. vseg */ -+#define INSTR_VRR_VV0U2 6, { V_8,V_12,U4_24,0,0,0 } /* e.g. vistrb*/ -+#define INSTR_VRR_VV0UU 6, { V_8,V_12,U4_28,U4_24,0,0 } /* e.g. vcdgb */ -+#define INSTR_VRR_VV0UU8 6, { V_8,V_12,U4_OR8_28,U4_24,0,0 } /* e.g. wcdgb */ -+#define INSTR_VRR_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vsegb */ -+#define INSTR_VRR_VVVUU0V 6, { V_8,V_12,V_16,V_32,U4_20,U4_24 } /* e.g. vstrc */ -+#define INSTR_VRR_VVVU0V 6, { V_8,V_12,V_16,V_32,U4_20,0 } /* e.g. vac */ -+#define INSTR_VRR_VVVU0VB 6, { V_8,V_12,V_16,V_32,U4_24,0 } /* e.g. vstrcb*/ -+#define INSTR_VRR_VVVU0VB1 6, { V_8,V_12,V_16,V_32,U4_OR1_24,0 } /* e.g. vstrcbs*/ -+#define INSTR_VRR_VVVU0VB2 6, { V_8,V_12,V_16,V_32,U4_OR2_24,0 } /* e.g. vstrczb*/ -+#define INSTR_VRR_VVVU0VB3 6, { V_8,V_12,V_16,V_32,U4_OR3_24,0 } /* e.g. vstrczbs*/ -+#define INSTR_VRR_VVV0V 6, { V_8,V_12,V_16,V_32,0,0 } /* e.g. vacq */ -+#define INSTR_VRR_VVV0U0U 6, { V_8,V_12,V_16,U4_32,U4_24,0 } /* e.g. vfae */ -+#define INSTR_VRR_VVVV 6, { V_8,V_12,V_16,V_32,0,0 } /* e.g. vfmadb*/ -+#define INSTR_VRR_VVV0UUU 6, { V_8,V_12,V_16,U4_32,U4_28,U4_24 }/* e.g. vfch */ -+#define INSTR_VRR_VVV0UU 6, { V_8,V_12,V_16,U4_32,U4_28,0 } /* e.g. vfa */ -+#define INSTR_VRR_VV0UUU 6, { V_8,V_12,U4_32,U4_28,U4_24,0 } /* e.g. vcdg */ -+#define INSTR_VRR_VVVU0UV 6, { V_8,V_12,V_16,V_32,U4_28,U4_20 } /* e.g. vfma */ -+#define INSTR_VRR_VV0U0U 6, { V_8,V_12,U4_32,U4_24,0,0 } /* e.g. vistr */ -+ -+#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_IE_UU { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -+#define MASK_MII_UPP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_RIE_RRPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_RIE_RRP0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } -+#define MASK_RIE_RRI0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } -+#define MASK_RIE_RUPI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_RIE_R0PI { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } -+#define MASK_RIE_RUPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_RIE_R0PU { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } -+#define MASK_RIE_R0IU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } -+#define MASK_RIE_R0I0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } -+#define MASK_RIE_R0UU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } -+#define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } -+#define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RIS_RURDI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_RIS_R0RDI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } -+#define MASK_RIS_RURDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_RIS_R0RDU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } -+#define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } -+#define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } -+#define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -+#define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -+#define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } -+#define MASK_RRE_FE0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } -+#define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -+#define MASK_RRE_FEF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -+#define MASK_RRE_FFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -+#define MASK_RRE_FEFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -+#define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } -+#define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -+#define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -+#define MASK_RRE_RFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -+#define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -+#define MASK_RRE_RER { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -+#define MASK_RRE_RERE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -+#define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -+#define MASK_RRE_FER { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -+#define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } -+#define MASK_RRF_FE0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } -+#define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } -+#define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } -+#define MASK_RRF_FE0FER { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } -+#define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RRF_FEUFEFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RRF_FUFF2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } - #define MASK_RRF_FEUFEFE2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RRF_RURR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RRF_R0RR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RRF_RMRR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } --#define MASK_RRF_U0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } --#define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } --#define MASK_RRF_U0RFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } --#define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RRF_UUFFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RRF_UUFEFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } --#define MASK_RRF_0UFEF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } --#define MASK_RRF_FFRU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RRF_FEFERU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } --#define MASK_RRF_M0RER { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } --#define MASK_RRF_M0RERE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } --#define MASK_RRF_U0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } --#define MASK_RRF_00RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } --#define MASK_RRF_UUFR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RRF_UUFER { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RRF_UURF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RRF_UURFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RR_0R_OPT { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RR_FEF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RR_FFE { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RR_FEFE { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RR_RER { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } --#define MASK_RRR_FE0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } --#define MASK_RRS_RRRDU { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } --#define MASK_RRS_RRRD0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } --#define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } --#define MASK_RSE_RERERD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } --#define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } --#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } --#define MASK_RSL_R0RD { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } --#define MASK_RSL_LRDFU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } --#define MASK_RSL_LRDFEU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } --#define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RS_RE0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RS_RERERD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } --#define MASK_RSY_RERERD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } --#define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } --#define MASK_RSY_RURD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } --#define MASK_RSY_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } --#define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } --#define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } --#define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } --#define MASK_RXE_FERRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } --#define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } --#define MASK_RXE_RERRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } --#define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } --#define MASK_RXF_FRRDFE { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } --#define MASK_RXF_FERRDFE { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } --#define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } --#define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } --#define MASK_RXY_RERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } --#define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } --#define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } --#define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RX_0RRD_OPT { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RX_FERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RX_RERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } --#define MASK_SIY_IRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } --#define MASK_SIL_RDI { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_SIL_RDU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_SMI_U0RDP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } --#define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } --#define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } --#define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } --#define MASK_SSF_RRDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } --#define MASK_SSF_RERDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } --#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } --#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -- -+#define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RRF_RURR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RRF_R0RR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } -+#define MASK_RRF_U0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } -+#define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } -+#define MASK_RRF_U0RFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } -+#define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RRF_UUFFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RRF_UUFEFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } -+#define MASK_RRF_0UFEF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } -+#define MASK_RRF_FFRU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RRF_FEFERU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RRF_U0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } -+#define MASK_RRF_U0RER { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } -+#define MASK_RRF_U0RERE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } -+#define MASK_RRF_00RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -+#define MASK_RRF_UUFR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RRF_UUFER { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RRF_UURF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RRF_UURFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RR_FEF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RR_FFE { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RR_FEFE { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RR_RER { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } -+#define MASK_RRR_FE0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } -+#define MASK_RRS_RRRDU { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } -+#define MASK_RRS_RRRD0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } -+#define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } -+#define MASK_RSE_RERERD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } -+#define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } -+#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } -+#define MASK_RSL_R0RD { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } -+#define MASK_RSL_LRDFU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_RSL_LRDFEU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RS_RE0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RS_RERERD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_RSY_RERERD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_RSY_RURD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_RSY_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } -+#define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } -+#define MASK_RXE_FERRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } -+#define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } -+#define MASK_RXE_RRRDU { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } -+#define MASK_RXE_RERRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } -+#define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } -+#define MASK_RXF_FRRDFE { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } -+#define MASK_RXF_FERRDFE { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } -+#define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } -+#define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_RXY_RERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RX_FERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RX_RERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_SIY_IRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_SIL_RDI { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_SIL_RDU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_SMI_U0RDP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_SSF_RERDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } -+#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -+#define MASK_VRV_VVXRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_VRI_V0U { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff } -+#define MASK_VRI_V { 0xff, 0x0f, 0xff, 0xff, 0xf0, 0xff } -+#define MASK_VRI_V0UUU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } -+#define MASK_VRI_V0UU { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff } -+#define MASK_VRI_VVUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_VRI_VVU { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } -+#define MASK_VRI_VVU2 { 0xff, 0x00, 0x00, 0x0f, 0xf0, 0xff } -+#define MASK_VRI_V0IU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } -+#define MASK_VRI_V0I { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff } -+#define MASK_VRI_VVV0UU { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } -+#define MASK_VRI_VVV0U { 0xff, 0x00, 0x0f, 0x00, 0xf0, 0xff } -+#define MASK_VRI_VVUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_VRX_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } -+#define MASK_VRX_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff } -+#define MASK_VRX_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_VRS_RVRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_VRS_RVRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } -+#define MASK_VRS_VVRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_VRS_VVRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } -+#define MASK_VRS_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -+#define MASK_VRS_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } -+#define MASK_VRR_VRR { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff } -+#define MASK_VRR_VVV0U { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff } -+#define MASK_VRR_VVV0U0 { 0xff, 0x00, 0x0f, 0x0f, 0xf0, 0xff } -+#define MASK_VRR_VVV0U1 { 0xff, 0x00, 0x0f, 0x1f, 0xf0, 0xff } -+#define MASK_VRR_VVV0U2 { 0xff, 0x00, 0x0f, 0x2f, 0xf0, 0xff } -+#define MASK_VRR_VVV0U3 { 0xff, 0x00, 0x0f, 0x3f, 0xf0, 0xff } -+#define MASK_VRR_VVV { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff } -+#define MASK_VRR_VVV2 { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff } -+#define MASK_VRR_VVV0V { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff } -+#define MASK_VRR_VV0U { 0xff, 0x00, 0xff, 0xff, 0x00, 0xff } -+#define MASK_VRR_VV0U2 { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff } -+#define MASK_VRR_VV0UU { 0xff, 0x00, 0xff, 0x00, 0xf0, 0xff } -+#define MASK_VRR_VV0UU8 { 0xff, 0x00, 0xff, 0x08, 0xf0, 0xff } -+#define MASK_VRR_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff } -+#define MASK_VRR_VVVUU0V { 0xff, 0x00, 0x00, 0x0f, 0x00, 0xff } -+#define MASK_VRR_VVVU0V { 0xff, 0x00, 0x00, 0xff, 0x00, 0xff } -+#define MASK_VRR_VVVU0VB { 0xff, 0x00, 0x0f, 0x0f, 0x00, 0xff } -+#define MASK_VRR_VVVU0VB1 { 0xff, 0x00, 0x0f, 0x1f, 0x00, 0xff } -+#define MASK_VRR_VVVU0VB2 { 0xff, 0x00, 0x0f, 0x2f, 0x00, 0xff } -+#define MASK_VRR_VVVU0VB3 { 0xff, 0x00, 0x0f, 0x3f, 0x00, 0xff } -+#define MASK_VRR_VVV0U0U { 0xff, 0x00, 0x0f, 0x0f, 0x00, 0xff } -+#define MASK_VRR_VVVV { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff } -+#define MASK_VRR_VVV0UUU { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } -+#define MASK_VRR_VVV0UU { 0xff, 0x00, 0x0f, 0xf0, 0x00, 0xff } -+#define MASK_VRR_VV0UUU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff } -+#define MASK_VRR_VVVU0UV { 0xff, 0x00, 0x00, 0xf0, 0x00, 0xff } -+#define MASK_VRR_VV0U0U { 0xff, 0x00, 0xff, 0x0f, 0x00, 0xff } - - /* The opcode formats table (blueprints for .insn pseudo mnemonic). */ - - const struct s390_opcode s390_opformats[] = - { -- { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 }, -- { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 }, -- { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 }, -- { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 }, -- { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 }, -- { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI,3, 6 }, -- { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 }, -- { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 }, -- { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 }, -- { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU,3, 6 }, -- { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 }, -- { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 }, -- { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 }, -- { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 }, -- { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 }, -- { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 }, -- { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 }, -- { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 }, -- { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 }, -- { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 }, -- { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 }, -- { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6 }, -- { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 }, -- { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 }, -- { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 }, -+ { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 ,0 }, -+ { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 ,0 }, -+ { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 ,0 }, -+ { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 ,0 }, -+ { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 ,0 }, -+ { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI,3, 6 ,0 }, -+ { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 ,0 }, -+ { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 ,0 }, -+ { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 ,0 }, -+ { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU,3, 6 ,0 }, -+ { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 ,0 }, -+ { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 ,0 }, -+ { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 ,0 }, -+ { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 ,0 }, -+ { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 ,0 }, -+ { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 ,0 }, -+ { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 ,0 }, -+ { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 ,0 }, -+ { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 ,0 }, -+ { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 ,0 }, -+ { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 ,0 }, -+ { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6 ,0 }, -+ { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 ,0 }, -+ { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 ,0 }, -+ { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 ,0 }, - }; - - const int s390_num_opformats = -diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt -index 5db1703..2a5e1dd 100644 ---- a/opcodes/s390-opc.txt -+++ b/opcodes/s390-opc.txt -@@ -262,10 +262,10 @@ a700 tmlh RI_RU "test under mask low high" g5 esa,zarch - a700 tmh RI_RU "test under mask high" g5 esa,zarch - a701 tmll RI_RU "test under mask low low" g5 esa,zarch - a701 tml RI_RU "test under mask low" g5 esa,zarch --0700 nopr RR_0R_OPT "no operation" g5 esa,zarch -+0700 nopr RR_0R "no operation" g5 esa,zarch optparm - 0700 b*8r RR_0R "conditional branch" g5 esa,zarch - 07f0 br RR_0R "unconditional branch" g5 esa,zarch --4700 nop RX_0RRD_OPT "no operation" g5 esa,zarch -+4700 nop RX_0RRD "no operation" g5 esa,zarch optparm - 4700 b*8 RX_0RRD "conditional branch" g5 esa,zarch - 47f0 b RX_0RRD "unconditional branch" g5 esa,zarch - a704 j*8 RI_0P "conditional jump" g5 esa,zarch -@@ -298,7 +298,7 @@ b30d debr RRE_FF "divide short bfp" g5 esa,zarch - ed000000000d deb RXE_FRRD "divide short bfp" g5 esa,zarch - b35b didbr RRF_FUFF "divide to integer long bfp" g5 esa,zarch - b353 diebr RRF_FUFF "divide to integer short bfp" g5 esa,zarch --b38c efpc RRE_RR_OPT "extract fpc" g5 esa,zarch -+b38c efpc RRE_RR "extract fpc" g5 esa,zarch optparm - b342 ltxbr RRE_FEFE "load and test extended bfp" g5 esa,zarch - b312 ltdbr RRE_FF "load and test long bfp" g5 esa,zarch - b302 ltebr RRE_FF "load and test short bfp" g5 esa,zarch -@@ -341,7 +341,7 @@ b31f msdbr RRF_F0FF "multiply and subtract long bfp" g5 esa,zarch - ed000000001f msdb RXF_FRRDF "multiply and subtract long bfp" g5 esa,zarch - b30f msebr RRF_F0FF "multiply and subtract short bfp" g5 esa,zarch - ed000000000f mseb RXF_FRRDF "multiply and subtract short bfp" g5 esa,zarch --b384 sfpc RRE_RR_OPT "set fpc" g5 esa,zarch -+b384 sfpc RRE_RR "set fpc" g5 esa,zarch optparm - b299 srnm S_RD "set rounding mode" g5 esa,zarch - b316 sqxbr RRE_FEFE "square root extended bfp" g5 esa,zarch - b315 sqdbr RRE_FF "square root long bfp" g5 esa,zarch -@@ -765,21 +765,21 @@ c800 mvcos SSF_RRDRD "move with optional specifications" z9-109 zarch - # z9-109 load page-table-entry address instruction - b9aa lptea RRF_RURR2 "load page-table-entry address" z9-109 zarch - # z9-109 conditional sske facility, sske instruction entered twice --b22b sske RRF_M0RR "set storage key extended" z9-109 zarch -+b22b sske RRF_U0RR "set storage key extended" z9-109 zarch optparm - # z9-109 etf2-enhancement facility, instructions entered twice --b993 troo RRF_M0RERE "translate one to one" z9-109 esa,zarch --b992 trot RRF_M0RERE "translate one to two" z9-109 esa,zarch --b991 trto RRF_M0RERE "translate two to one" z9-109 esa,zarch --b990 trtt RRF_M0RERE "translate two to two" z9-109 esa,zarch -+b993 troo RRF_U0RERE "translate one to one" z9-109 esa,zarch optparm -+b992 trot RRF_U0RERE "translate one to two" z9-109 esa,zarch optparm -+b991 trto RRF_U0RERE "translate two to one" z9-109 esa,zarch optparm -+b990 trtt RRF_U0RERE "translate two to two" z9-109 esa,zarch optparm - # z9-109 etf3-enhancement facility, some instructions entered twice --b9b1 cu24 RRF_M0RERE "convert utf-16 to utf-32" z9-109 zarch --b2a6 cu21 RRF_M0RERE "convert utf-16 to utf-8" z9-109 zarch --b2a6 cuutf RRF_M0RERE "convert unicode to utf-8" z9-109 zarch -+b9b1 cu24 RRF_U0RERE "convert utf-16 to utf-32" z9-109 zarch optparm -+b2a6 cu21 RRF_U0RERE "convert utf-16 to utf-8" z9-109 zarch optparm -+b2a6 cuutf RRF_U0RERE "convert unicode to utf-8" z9-109 zarch optparm - b9b3 cu42 RRE_RERE "convert utf-32 to utf-16" z9-109 zarch - b9b2 cu41 RRE_RERE "convert utf-32 to utf-8" z9-109 zarch --b2a7 cu12 RRF_M0RERE "convert utf-8 to utf-16" z9-109 zarch --b2a7 cutfu RRF_M0RERE "convert utf-8 to unicode" z9-109 zarch --b9b0 cu14 RRF_M0RERE "convert utf-8 to utf-32" z9-109 zarch -+b2a7 cu12 RRF_U0RERE "convert utf-8 to utf-16" z9-109 zarch optparm -+b2a7 cutfu RRF_U0RERE "convert utf-8 to unicode" z9-109 zarch optparm -+b9b0 cu14 RRF_U0RERE "convert utf-8 to utf-32" z9-109 zarch optparm - b9be srstu RRE_RR "search string unicode" z9-109 zarch - d0 trtr SS_L0RDRD "tranlate and test reverse" z9-109 zarch - # z9-109 unnormalized hfp multiply & multiply and add -@@ -963,8 +963,8 @@ c600 exrl RIL_RP "execute relative long" z10 zarch - af00 mc SI_URD "monitor call" z10 zarch - b9a2 ptf RRE_R0 "perform topology function" z10 zarch - b9af pfmf RRE_RR "perform frame management function" z10 zarch --b9bf trte RRF_M0RER "translate and test extended" z10 zarch --b9bd trtre RRF_M0RER "translate and test reverse extended" z10 zarch -+b9bf trte RRF_U0RER "translate and test extended" z10 zarch optparm -+b9bd trtre RRF_U0RER "translate and test reverse extended" z10 zarch optparm - b2ed ecpga RRE_RR "extract coprocessor-group address" z10 zarch - b2e4 ecctr RRE_RR "extract cpu counter" z10 zarch - b2e5 epctr RRE_RR "extract peripheral counter" z10 zarch -@@ -1128,7 +1128,7 @@ c7 bpp SMI_U0RDP "branch prediction preload" zEC12 zarch - c5 bprp MII_UPP "branch prediction relative preload" zEC12 zarch - b2e8 ppa RRF_U0RR "perform processor assist" zEC12 zarch - b2fa niai IE_UU "next instruction access intent" zEC12 zarch --b98f crdte RRF_RMRR "compare and replace DAT table entry" zEC12 zarch -+b98f crdte RRF_RURR2 "compare and replace DAT table entry" zEC12 zarch optparm - e3000000009f lat RXY_RRRD "load and trap 32 bit" zEC12 zarch - e30000000085 lgat RXY_RRRD "load and trap 64 bit" zEC12 zarch - e300000000c8 lfhat RXY_RRRD "load high and trap" zEC12 zarch -@@ -1143,3 +1143,516 @@ ed00000000aa cdzt RSL_LRDFU "convert from zoned long" zEC12 zarch - ed00000000ab cxzt RSL_LRDFEU "convert from zoned extended" zEC12 zarch - ed00000000a8 czdt RSL_LRDFU "convert to zoned long" zEC12 zarch - ed00000000a9 czxt RSL_LRDFEU "convert to zoned extended" zEC12 zarch -+ -+# The new instructions of IBM z13 -+ -+e70000000027 lcbb RXE_RRRDU "load count to block boundary" z13 zarch -+ -+# Chapter 21 -+e70000000013 vgef VRV_VVXRDU "vector gather element 4 byte elements" z13 zarch -+e70000000012 vgeg VRV_VVXRDU "vector gather element 8 byte elements" z13 zarch -+e70000000044 vgbm VRI_V0U "vector generate byte mask" z13 zarch -+e70000000044 vzero VRI_V "vector set to zero" z13 zarch -+e700ffff0044 vone VRI_V "vector set to ones" z13 zarch -+e70000000046 vgm VRI_V0UUU "vector generate mask" z13 zarch -+e70000000046 vgmb VRI_V0UU "vector generate mask byte" z13 zarch -+e70000001046 vgmh VRI_V0UU "vector generate mask halfword" z13 zarch -+e70000002046 vgmf VRI_V0UU "vector generate mask word" z13 zarch -+e70000003046 vgmg VRI_V0UU "vector generate mask double word" z13 zarch -+e70000000006 vl VRX_VRRD "vector memory load" z13 zarch -+e70000000056 vlr VRX_VV "vector register load" z13 zarch -+e70000000005 vlrep VRX_VRRDU "vector load and replicate" z13 zarch -+e70000000005 vlrepb VRX_VRRD "vector load and replicate byte elements" z13 zarch -+e70000001005 vlreph VRX_VRRD "vector load and replicate halfword elements" z13 zarch -+e70000002005 vlrepf VRX_VRRD "vector load and replicate word elements" z13 zarch -+e70000003005 vlrepg VRX_VRRD "vector load and replicate double word elements" z13 zarch -+e70000000000 vleb VRX_VRRDU "vector load byte element" z13 zarch -+e70000000001 vleh VRX_VRRDU "vector load halfword element" z13 zarch -+e70000000003 vlef VRX_VRRDU "vector load word element" z13 zarch -+e70000000002 vleg VRX_VRRDU "vector load double word element" z13 zarch -+e70000000040 vleib VRI_V0IU "vector load byte element immediate" z13 zarch -+e70000000041 vleih VRI_V0IU "vector load halfword element immediate" z13 zarch -+e70000000043 vleif VRI_V0IU "vector load word element immediate" z13 zarch -+e70000000042 vleig VRI_V0IU "vector load double word element immediate" z13 zarch -+e70000000021 vlgv VRS_RVRDU "vector load gr from vr element" z13 zarch -+e70000000021 vlgvb VRS_RVRD "vector load gr from vr byte element" z13 zarch -+e70000001021 vlgvh VRS_RVRD "vector load gr from vr halfword element" z13 zarch -+e70000002021 vlgvf VRS_RVRD "vector load gr from vr word element" z13 zarch -+e70000003021 vlgvg VRS_RVRD "vector load gr from vr double word element" z13 zarch -+e70000000004 vllez VRX_VRRDU "vector load logical element and zero" z13 zarch -+e70000000004 vllezb VRX_VRRD "vector load logical byte element and zero" z13 zarch -+e70000001004 vllezh VRX_VRRD "vector load logical halfword element and zero" z13 zarch -+e70000002004 vllezf VRX_VRRD "vector load logical word element and zero" z13 zarch -+e70000003004 vllezg VRX_VRRD "vector load logical double word element and zero" z13 zarch -+e70000000036 vlm VRS_VVRD "vector load multiple" z13 zarch -+e70000000007 vlbb VRX_VRRDU "vector load to block boundary" z13 zarch -+e70000000022 vlvg VRS_VRRDU "vector load VR element from GR" z13 zarch -+e70000000022 vlvgb VRS_VRRD "vector load VR byte element from GR" z13 zarch -+e70000001022 vlvgh VRS_VRRD "vector load VR halfword element from GR" z13 zarch -+e70000002022 vlvgf VRS_VRRD "vector load VR word element from GR" z13 zarch -+e70000003022 vlvgg VRS_VRRD "vector load VR double word element from GR" z13 zarch -+e70000000062 vlvgp VRR_VRR "vector load VR from GRs disjoint" z13 zarch -+e70000000037 vll VRS_VRRD "vector load with length" z13 zarch -+e70000000061 vmrh VRR_VVV0U "vector merge high" z13 zarch -+e70000000061 vmrhb VRR_VVV "vector merge high byte" z13 zarch -+e70000001061 vmrhh VRR_VVV "vector merge high halfword" z13 zarch -+e70000002061 vmrhf VRR_VVV "vector merge high word" z13 zarch -+e70000003061 vmrhg VRR_VVV "vector merge high double word" z13 zarch -+e70000000060 vmrl VRR_VVV0U "vector merge low" z13 zarch -+e70000000060 vmrlb VRR_VVV "vector merge low byte" z13 zarch -+e70000001060 vmrlh VRR_VVV "vector merge low halfword" z13 zarch -+e70000002060 vmrlf VRR_VVV "vector merge low word" z13 zarch -+e70000003060 vmrlg VRR_VVV "vector merge low double word" z13 zarch -+e70000000094 vpk VRR_VVV0U "vector pack" z13 zarch -+e70000001094 vpkh VRR_VVV "vector pack halfword" z13 zarch -+e70000002094 vpkf VRR_VVV "vector pack word" z13 zarch -+e70000003094 vpkg VRR_VVV "vector pack double word" z13 zarch -+e70000000097 vpks VRR_VVV0U0U "vector pack saturate" z13 zarch -+e70000001097 vpksh VRR_VVV "vector pack saturate halfword" z13 zarch -+e70000002097 vpksf VRR_VVV "vector pack saturate word" z13 zarch -+e70000003097 vpksg VRR_VVV "vector pack saturate double word" z13 zarch -+e70000101097 vpkshs VRR_VVV "vector pack saturate halfword" z13 zarch -+e70000102097 vpksfs VRR_VVV "vector pack saturate word" z13 zarch -+e70000103097 vpksgs VRR_VVV "vector pack saturate double word" z13 zarch -+e70000000095 vpkls VRR_VVV0U0U "vector pack logical saturate" z13 zarch -+e70000001095 vpklsh VRR_VVV "vector pack logical saturate halfword" z13 zarch -+e70000002095 vpklsf VRR_VVV "vector pack logical saturate word" z13 zarch -+e70000003095 vpklsg VRR_VVV "vector pack logical saturate double word" z13 zarch -+e70000101095 vpklshs VRR_VVV "vector pack logical saturate halfword" z13 zarch -+e70000102095 vpklsfs VRR_VVV "vector pack logical saturate word" z13 zarch -+e70000103095 vpklsgs VRR_VVV "vector pack logical saturate double word" z13 zarch -+e7000000008c vperm VRR_VVV0V "vector permute" z13 zarch -+e70000000084 vpdi VRR_VVV0U "vector permute double word immediate" z13 zarch -+e7000000004d vrep VRI_VVUU "vector replicate" z13 zarch -+e7000000004d vrepb VRI_VVU "vector replicate byte" z13 zarch -+e7000000104d vreph VRI_VVU "vector replicate halfword" z13 zarch -+e7000000204d vrepf VRI_VVU "vector replicate word" z13 zarch -+e7000000304d vrepg VRI_VVU "vector replicate double word" z13 zarch -+e70000000045 vrepi VRI_V0IU "vector replicate immediate" z13 zarch -+e70000000045 vrepib VRI_V0I "vector replicate immediate byte" z13 zarch -+e70000001045 vrepih VRI_V0I "vector replicate immediate halfword" z13 zarch -+e70000002045 vrepif VRI_V0I "vector replicate immediate word" z13 zarch -+e70000003045 vrepig VRI_V0I "vector replicate immediate double word" z13 zarch -+e7000000001b vscef VRV_VVXRDU "vector scatter element 4 byte" z13 zarch -+e7000000001a vsceg VRV_VVXRDU "vector scatter element 8 byte" z13 zarch -+e7000000008d vsel VRR_VVV0V "vector select" z13 zarch -+e7000000005f vseg VRR_VV0U "vector sign extend to double word" z13 zarch -+e7000000005f vsegb VRR_VV "vector sign extend byte to double word" z13 zarch -+e7000000105f vsegh VRR_VV "vector sign extend halfword to double word" z13 zarch -+e7000000205f vsegf VRR_VV "vector sign extend word to double word" z13 zarch -+e7000000000e vst VRX_VRRD "vector store" z13 zarch -+e70000000008 vsteb VRX_VRRDU "vector store byte element" z13 zarch -+e70000000009 vsteh VRX_VRRDU "vector store halfword element" z13 zarch -+e7000000000b vstef VRX_VRRDU "vector store word element" z13 zarch -+e7000000000a vsteg VRX_VRRDU "vector store double word element" z13 zarch -+e7000000003e vstm VRS_VVRD "vector store multiple" z13 zarch -+e7000000003f vstl VRS_VRRD "vector store with length" z13 zarch -+e700000000d7 vuph VRR_VV0U "vector unpack high" z13 zarch -+e700000000d7 vuphb VRR_VV "vector unpack high byte" z13 zarch -+e700000010d7 vuphh VRR_VV "vector unpack high halfword" z13 zarch -+e700000020d7 vuphf VRR_VV "vector unpack high word" z13 zarch -+e700000000d5 vuplh VRR_VV0U "vector unpack logical high" z13 zarch -+e700000000d5 vuplhb VRR_VV "vector unpack logical high byte" z13 zarch -+e700000010d5 vuplhh VRR_VV "vector unpack logical high halfword" z13 zarch -+e700000020d5 vuplhf VRR_VV "vector unpack logical high word" z13 zarch -+e700000000d6 vupl VRR_VV0U "vector unpack low" z13 zarch -+e700000000d6 vuplb VRR_VV "vector unpack low byte" z13 zarch -+e700000010d6 vuplhw VRR_VV "vector unpack low halfword" z13 zarch -+e700000020d6 vuplf VRR_VV "vector unpack low word" z13 zarch -+e700000000d4 vupll VRR_VV0U "vector unpack logical low" z13 zarch -+e700000000d4 vupllb VRR_VV "vector unpack logical low byte" z13 zarch -+e700000010d4 vupllh VRR_VV "vector unpack logical low halfword" z13 zarch -+e700000020d4 vupllf VRR_VV "vector unpack logical low word" z13 zarch -+ -+# Chapter 22 -+e700000000f3 va VRR_VVV0U "vector add" z13 zarch -+e700000000f3 vab VRR_VVV "vector add byte" z13 zarch -+e700000010f3 vah VRR_VVV "vector add halfword" z13 zarch -+e700000020f3 vaf VRR_VVV "vector add word" z13 zarch -+e700000030f3 vag VRR_VVV "vector add double word" z13 zarch -+e700000040f3 vaq VRR_VVV "vector add quad word" z13 zarch -+e700000000f1 vacc VRR_VVV0U "vector add compute carry" z13 zarch -+e700000000f1 vaccb VRR_VVV "vector add compute carry byte" z13 zarch -+e700000010f1 vacch VRR_VVV "vector add compute carry halfword" z13 zarch -+e700000020f1 vaccf VRR_VVV "vector add compute carry word" z13 zarch -+e700000030f1 vaccg VRR_VVV "vector add compute carry doubleword" z13 zarch -+e700000040f1 vaccq VRR_VVV "vector add compute carry quadword" z13 zarch -+e700000000bb vac VRR_VVVU0V "vector add with carry" z13 zarch -+e700040000bb vacq VRR_VVV0V "vector add with carry quadword" z13 zarch -+e700000000b9 vaccc VRR_VVVU0V "vector add with carry compute carry" z13 zarch -+e700040000b9 vacccq VRR_VVV0V "vector add with carry compute carry quadword" z13 zarch -+e70000000068 vn VRR_VVV "vector and" z13 zarch -+e70000000069 vnc VRR_VVV "vector and with complement" z13 zarch -+e700000000f2 vavg VRR_VVV0U "vector average" z13 zarch -+e700000000f2 vavgb VRR_VVV "vector average byte" z13 zarch -+e700000010f2 vavgh VRR_VVV "vector average half word" z13 zarch -+e700000020f2 vavgf VRR_VVV "vector average word" z13 zarch -+e700000030f2 vavgg VRR_VVV "vector average double word" z13 zarch -+e700000000f0 vavgl VRR_VVV0U "vector average logical" z13 zarch -+e700000000f0 vavglb VRR_VVV "vector average logical byte" z13 zarch -+e700000010f0 vavglh VRR_VVV "vector average logical half word" z13 zarch -+e700000020f0 vavglf VRR_VVV "vector average logical word" z13 zarch -+e700000030f0 vavglg VRR_VVV "vector average logical double word" z13 zarch -+e70000000066 vcksm VRR_VVV "vector checksum" z13 zarch -+e700000000db vec VRR_VV0U "vector element compare" z13 zarch -+e700000000db vecb VRR_VV "vector element compare byte" z13 zarch -+e700000010db vech VRR_VV "vector element compare half word" z13 zarch -+e700000020db vecf VRR_VV "vector element compare word" z13 zarch -+e700000030db vecg VRR_VV "vector element compare double word" z13 zarch -+e700000000d9 vecl VRR_VV0U "vector element compare logical" z13 zarch -+e700000000d9 veclb VRR_VV "vector element compare logical byte" z13 zarch -+e700000010d9 veclh VRR_VV "vector element compare logical half word" z13 zarch -+e700000020d9 veclf VRR_VV "vector element compare logical word" z13 zarch -+e700000030d9 veclg VRR_VV "vector element compare logical double word" z13 zarch -+e700000000f8 vceq VRR_VVV0U0U "vector compare equal" z13 zarch -+e700000000f8 vceqb VRR_VVV "vector compare equal byte" z13 zarch -+e700000010f8 vceqh VRR_VVV "vector compare equal half word" z13 zarch -+e700000020f8 vceqf VRR_VVV "vector compare equal word" z13 zarch -+e700000030f8 vceqg VRR_VVV "vector compare equal double word" z13 zarch -+e700001000f8 vceqbs VRR_VVV "vector compare equal byte" z13 zarch -+e700001010f8 vceqhs VRR_VVV "vector compare equal half word" z13 zarch -+e700001020f8 vceqfs VRR_VVV "vector compare equal word" z13 zarch -+e700001030f8 vceqgs VRR_VVV "vector compare equal double word" z13 zarch -+e700000000fb vch VRR_VVV0U0U "vector compare high" z13 zarch -+e700000000fb vchb VRR_VVV "vector compare high byte" z13 zarch -+e700000010fb vchh VRR_VVV "vector compare high half word" z13 zarch -+e700000020fb vchf VRR_VVV "vector compare high word" z13 zarch -+e700000030fb vchg VRR_VVV "vector compare high double word" z13 zarch -+e700001000fb vchbs VRR_VVV "vector compare high byte" z13 zarch -+e700001010fb vchhs VRR_VVV "vector compare high half word" z13 zarch -+e700001020fb vchfs VRR_VVV "vector compare high word" z13 zarch -+e700001030fb vchgs VRR_VVV "vector compare high double word" z13 zarch -+e700000000f9 vchl VRR_VVV0U0U "vector compare high logical" z13 zarch -+e700000000f9 vchlb VRR_VVV "vector compare high logical byte" z13 zarch -+e700000010f9 vchlh VRR_VVV "vector compare high logical half word" z13 zarch -+e700000020f9 vchlf VRR_VVV "vector compare high logical word" z13 zarch -+e700000030f9 vchlg VRR_VVV "vector compare high logical double word" z13 zarch -+e700001000f9 vchlbs VRR_VVV "vector compare high logical byte" z13 zarch -+e700001010f9 vchlhs VRR_VVV "vector compare high logical half word" z13 zarch -+e700001020f9 vchlfs VRR_VVV "vector compare high logical word" z13 zarch -+e700001030f9 vchlgs VRR_VVV "vector compare high logical double word" z13 zarch -+e70000000053 vclz VRR_VV0U "vector count leading zeros" z13 zarch -+e70000000053 vclzb VRR_VV "vector count leading zeros byte" z13 zarch -+e70000001053 vclzh VRR_VV "vector count leading zeros halfword" z13 zarch -+e70000002053 vclzf VRR_VV "vector count leading zeros word" z13 zarch -+e70000003053 vclzg VRR_VV "vector count leading zeros doubleword" z13 zarch -+e70000000052 vctz VRR_VV0U "vector count trailing zeros" z13 zarch -+e70000000052 vctzb VRR_VV "vector count trailing zeros byte" z13 zarch -+e70000001052 vctzh VRR_VV "vector count trailing zeros halfword" z13 zarch -+e70000002052 vctzf VRR_VV "vector count trailing zeros word" z13 zarch -+e70000003052 vctzg VRR_VV "vector count trailing zeros doubleword" z13 zarch -+e7000000006d vx VRR_VVV "vector exclusive or" z13 zarch -+e700000000b4 vgfm VRR_VVV0U "vector galois field multiply sum" z13 zarch -+e700000000b4 vgfmb VRR_VVV "vector galois field multiply sum byte" z13 zarch -+e700000010b4 vgfmh VRR_VVV "vector galois field multiply sum halfword" z13 zarch -+e700000020b4 vgfmf VRR_VVV "vector galois field multiply sum word" z13 zarch -+e700000030b4 vgfmg VRR_VVV "vector galois field multiply sum doubleword" z13 zarch -+e700000000bc vgfma VRR_VVVU0V "vector galois field multiply sum and accumulate" z13 zarch -+e700000000bc vgfmab VRR_VVV0V "vector galois field multiply sum and accumulate byte" z13 zarch -+e700010000bc vgfmah VRR_VVV0V "vector galois field multiply sum and accumulate halfword" z13 zarch -+e700020000bc vgfmaf VRR_VVV0V "vector galois field multiply sum and accumulate word" z13 zarch -+e700030000bc vgfmag VRR_VVV0V "vector galois field multiply sum and accumulate doubleword" z13 zarch -+e700000000de vlc VRR_VV0U "vector load complement" z13 zarch -+e700000000de vlcb VRR_VV "vector load complement byte" z13 zarch -+e700000010de vlch VRR_VV "vector load complement halfword" z13 zarch -+e700000020de vlcf VRR_VV "vector load complement word" z13 zarch -+e700000030de vlcg VRR_VV "vector load complement doubleword" z13 zarch -+e700000000df vlp VRR_VV0U "vector load positive" z13 zarch -+e700000000df vlpb VRR_VV "vector load positive byte" z13 zarch -+e700000010df vlph VRR_VV "vector load positive halfword" z13 zarch -+e700000020df vlpf VRR_VV "vector load positive word" z13 zarch -+e700000030df vlpg VRR_VV "vector load positive doubleword" z13 zarch -+e700000000ff vmx VRR_VVV0U "vector maximum" z13 zarch -+e700000000ff vmxb VRR_VVV "vector maximum byte" z13 zarch -+e700000010ff vmxh VRR_VVV "vector maximum halfword" z13 zarch -+e700000020ff vmxf VRR_VVV "vector maximum word" z13 zarch -+e700000030ff vmxg VRR_VVV "vector maximum doubleword" z13 zarch -+e700000000fd vmxl VRR_VVV0U "vector maximum logical" z13 zarch -+e700000000fd vmxlb VRR_VVV "vector maximum logical byte" z13 zarch -+e700000010fd vmxlh VRR_VVV "vector maximum logical halfword" z13 zarch -+e700000020fd vmxlf VRR_VVV "vector maximum logical word" z13 zarch -+e700000030fd vmxlg VRR_VVV "vector maximum logical doubleword" z13 zarch -+e700000000fe vmn VRR_VVV0U "vector minimum" z13 zarch -+e700000000fe vmnb VRR_VVV "vector minimum byte" z13 zarch -+e700000010fe vmnh VRR_VVV "vector minimum halfword" z13 zarch -+e700000020fe vmnf VRR_VVV "vector minimum word" z13 zarch -+e700000030fe vmng VRR_VVV "vector minimum doubleword" z13 zarch -+e700000000fc vmnl VRR_VVV0U "vector minimum logical" z13 zarch -+e700000000fc vmnlb VRR_VVV "vector minimum logical byte" z13 zarch -+e700000010fc vmnlh VRR_VVV "vector minimum logical halfword" z13 zarch -+e700000020fc vmnlf VRR_VVV "vector minimum logical word" z13 zarch -+e700000030fc vmnlg VRR_VVV "vector minimum logical doubleword" z13 zarch -+e700000000aa vmal VRR_VVVU0V "vector multiply and add low" z13 zarch -+e700000000aa vmalb VRR_VVV0V "vector multiply and add low byte" z13 zarch -+e700010000aa vmalhw VRR_VVV0V "vector multiply and add low halfword" z13 zarch -+e700020000aa vmalf VRR_VVV0V "vector multiply and add low word" z13 zarch -+e700000000ab vmah VRR_VVVU0V "vector multiply and add high" z13 zarch -+e700000000ab vmahb VRR_VVV0V "vector multiply and add high byte" z13 zarch -+e700010000ab vmahh VRR_VVV0V "vector multiply and add high halfword" z13 zarch -+e700020000ab vmahf VRR_VVV0V "vector multiply and add high word" z13 zarch -+e700000000a9 vmalh VRR_VVVU0V "vector multiply and add logical high" z13 zarch -+e700000000a9 vmalhb VRR_VVV0V "vector multiply and add logical high byte" z13 zarch -+e700010000a9 vmalhh VRR_VVV0V "vector multiply and add logical high halfword" z13 zarch -+e700020000a9 vmalhf VRR_VVV0V "vector multiply and add logical high word" z13 zarch -+e700000000ae vmae VRR_VVVU0V "vector multiply and add even" z13 zarch -+e700000000ae vmaeb VRR_VVV0V "vector multiply and add even byte" z13 zarch -+e700010000ae vmaeh VRR_VVV0V "vector multiply and add even halfword" z13 zarch -+e700020000ae vmaef VRR_VVV0V "vector multiply and add even word" z13 zarch -+e700000000ac vmale VRR_VVVU0V "vector multiply and add logical even" z13 zarch -+e700000000ac vmaleb VRR_VVV0V "vector multiply and add logical even byte" z13 zarch -+e700010000ac vmaleh VRR_VVV0V "vector multiply and add logical even halfword" z13 zarch -+e700020000ac vmalef VRR_VVV0V "vector multiply and add logical even word" z13 zarch -+e700000000af vmao VRR_VVVU0V "vector multiply and add odd" z13 zarch -+e700000000af vmaob VRR_VVV0V "vector multiply and add odd byte" z13 zarch -+e700010000af vmaoh VRR_VVV0V "vector multiply and add odd halfword" z13 zarch -+e700020000af vmaof VRR_VVV0V "vector multiply and add odd word" z13 zarch -+e700000000ad vmalo VRR_VVVU0V "vector multiply and add logical odd" z13 zarch -+e700000000ad vmalob VRR_VVV0V "vector multiply and add logical odd byte" z13 zarch -+e700010000ad vmaloh VRR_VVV0V "vector multiply and add logical odd halfword" z13 zarch -+e700020000ad vmalof VRR_VVV0V "vector multiply and add logical odd word" z13 zarch -+e700000000a3 vmh VRR_VVV0U "vector multiply high" z13 zarch -+e700000000a3 vmhb VRR_VVV "vector multiply high byte" z13 zarch -+e700000010a3 vmhh VRR_VVV "vector multiply high halfword" z13 zarch -+e700000020a3 vmhf VRR_VVV "vector multiply high word" z13 zarch -+e700000000a1 vmlh VRR_VVV0U "vector multiply logical high" z13 zarch -+e700000000a1 vmlhb VRR_VVV "vector multiply logical high byte" z13 zarch -+e700000010a1 vmlhh VRR_VVV "vector multiply logical high halfword" z13 zarch -+e700000020a1 vmlhf VRR_VVV "vector multiply logical high word" z13 zarch -+e700000000a2 vml VRR_VVV0U "vector multiply low" z13 zarch -+e700000000a2 vmlb VRR_VVV "vector multiply low byte" z13 zarch -+e700000010a2 vmlhw VRR_VVV "vector multiply low halfword" z13 zarch -+e700000020a2 vmlf VRR_VVV "vector multiply low word" z13 zarch -+e700000000a6 vme VRR_VVV0U "vector multiply even" z13 zarch -+e700000000a6 vmeb VRR_VVV "vector multiply even byte" z13 zarch -+e700000010a6 vmeh VRR_VVV "vector multiply even halfword" z13 zarch -+e700000020a6 vmef VRR_VVV "vector multiply even word" z13 zarch -+e700000000a4 vmle VRR_VVV0U "vector multiply logical even" z13 zarch -+e700000000a4 vmleb VRR_VVV "vector multiply logical even byte" z13 zarch -+e700000010a4 vmleh VRR_VVV "vector multiply logical even halfword" z13 zarch -+e700000020a4 vmlef VRR_VVV "vector multiply logical even word" z13 zarch -+e700000000a7 vmo VRR_VVV0U "vector multiply odd" z13 zarch -+e700000000a7 vmob VRR_VVV "vector multiply odd byte" z13 zarch -+e700000010a7 vmoh VRR_VVV "vector multiply odd halfword" z13 zarch -+e700000020a7 vmof VRR_VVV "vector multiply odd word" z13 zarch -+e700000000a5 vmlo VRR_VVV0U "vector multiply logical odd" z13 zarch -+e700000000a5 vmlob VRR_VVV "vector multiply logical odd byte" z13 zarch -+e700000010a5 vmloh VRR_VVV "vector multiply logical odd halfword" z13 zarch -+e700000020a5 vmlof VRR_VVV "vector multiply logical odd word" z13 zarch -+e7000000006b vno VRR_VVV "vector nor" z13 zarch -+e7000000006b vnot VRR_VVV2 "vector not" z13 zarch -+e7000000006a vo VRR_VVV "vector or" z13 zarch -+e70000000050 vpopct VRR_VV0U "vector population count" z13 zarch -+e70000000073 verllv VRR_VVV0U "vector element rotate left logical reg" z13 zarch -+e70000000073 verllvb VRR_VVV "vector element rotate left logical reg byte" z13 zarch -+e70000001073 verllvh VRR_VVV "vector element rotate left logical reg halfword" z13 zarch -+e70000002073 verllvf VRR_VVV "vector element rotate left logical reg word" z13 zarch -+e70000003073 verllvg VRR_VVV "vector element rotate left logical reg doubleword" z13 zarch -+e70000000033 verll VRS_VVRDU "vector element rotate left logical mem" z13 zarch -+e70000000033 verllb VRS_VVRD "vector element rotate left logical mem byte" z13 zarch -+e70000001033 verllh VRS_VVRD "vector element rotate left logical mem halfword" z13 zarch -+e70000002033 verllf VRS_VVRD "vector element rotate left logical mem word" z13 zarch -+e70000003033 verllg VRS_VVRD "vector element rotate left logical mem doubleword" z13 zarch -+e70000000072 verim VRI_VVV0UU "vector element rotate and insert under mask" z13 zarch -+e70000000072 verimb VRI_VVV0U "vector element rotate and insert under mask byte" z13 zarch -+e70000001072 verimh VRI_VVV0U "vector element rotate and insert under mask halfword" z13 zarch -+e70000002072 verimf VRI_VVV0U "vector element rotate and insert under mask word" z13 zarch -+e70000003072 verimg VRI_VVV0U "vector element rotate and insert under mask doubleword" z13 zarch -+e70000000070 veslv VRR_VVV0U "vector element shift left reg" z13 zarch -+e70000000070 veslvb VRR_VVV "vector element shift left reg byte" z13 zarch -+e70000001070 veslvh VRR_VVV "vector element shift left reg halfword" z13 zarch -+e70000002070 veslvf VRR_VVV "vector element shift left reg word" z13 zarch -+e70000003070 veslvg VRR_VVV "vector element shift left reg doubleword" z13 zarch -+e70000000030 vesl VRS_VVRDU "vector element shift left mem" z13 zarch -+e70000000030 veslb VRS_VVRD "vector element shift left mem byte" z13 zarch -+e70000001030 veslh VRS_VVRD "vector element shift left mem halfword" z13 zarch -+e70000002030 veslf VRS_VVRD "vector element shift left mem word" z13 zarch -+e70000003030 veslg VRS_VVRD "vector element shift left mem doubleword" z13 zarch -+e7000000007a vesrav VRR_VVV0U "vector element shift right arithmetic reg" z13 zarch -+e7000000007a vesravb VRR_VVV "vector element shift right arithmetic reg byte" z13 zarch -+e7000000107a vesravh VRR_VVV "vector element shift right arithmetic reg halfword" z13 zarch -+e7000000207a vesravf VRR_VVV "vector element shift right arithmetic reg word" z13 zarch -+e7000000307a vesravg VRR_VVV "vector element shift right arithmetic reg doubleword" z13 zarch -+e7000000003a vesra VRS_VVRDU "vector element shift right arithmetic mem" z13 zarch -+e7000000003a vesrab VRS_VVRD "vector element shift right arithmetic mem byte" z13 zarch -+e7000000103a vesrah VRS_VVRD "vector element shift right arithmetic mem halfword" z13 zarch -+e7000000203a vesraf VRS_VVRD "vector element shift right arithmetic mem word" z13 zarch -+e7000000303a vesrag VRS_VVRD "vector element shift right arithmetic mem doubleword" z13 zarch -+e70000000078 vesrlv VRR_VVV0U "vector element shift right logical reg" z13 zarch -+e70000000078 vesrlvb VRR_VVV "vector element shift right logical reg byte" z13 zarch -+e70000001078 vesrlvh VRR_VVV "vector element shift right logical reg halfword" z13 zarch -+e70000002078 vesrlvf VRR_VVV "vector element shift right logical reg word" z13 zarch -+e70000003078 vesrlvg VRR_VVV "vector element shift right logical reg doubleword" z13 zarch -+e70000000038 vesrl VRS_VVRDU "vector element shift right logical mem" z13 zarch -+e70000000038 vesrlb VRS_VVRD "vector element shift right logical mem byte" z13 zarch -+e70000001038 vesrlh VRS_VVRD "vector element shift right logical mem halfword" z13 zarch -+e70000002038 vesrlf VRS_VVRD "vector element shift right logical mem word" z13 zarch -+e70000003038 vesrlg VRS_VVRD "vector element shift right logical mem doubleword" z13 zarch -+e70000000074 vsl VRR_VVV "vector shift left" z13 zarch -+e70000000075 vslb VRR_VVV "vector shift left by byte" z13 zarch -+e70000000077 vsldb VRI_VVV0U "vector shift left double by byte" z13 zarch -+e7000000007e vsra VRR_VVV "vector shift right arithmetic" z13 zarch -+e7000000007f vsrab VRR_VVV "vector shift right arithmetic by byte" z13 zarch -+e7000000007c vsrl VRR_VVV "vector shift right logical" z13 zarch -+e7000000007d vsrlb VRR_VVV "vector shift right logical by byte" z13 zarch -+e700000000f7 vs VRR_VVV0U "vector subtract" z13 zarch -+e700000000f7 vsb VRR_VVV "vector subtract byte" z13 zarch -+e700000010f7 vsh VRR_VVV "vector subtract halfword" z13 zarch -+e700000020f7 vsf VRR_VVV "vector subtract word" z13 zarch -+e700000030f7 vsg VRR_VVV "vector subtract doubleword" z13 zarch -+e700000040f7 vsq VRR_VVV "vector subtract quadword" z13 zarch -+e700000000f5 vscbi VRR_VVV0U "vector subtract compute borrow indication" z13 zarch -+e700000000f5 vscbib VRR_VVV "vector subtract compute borrow indication byte" z13 zarch -+e700000010f5 vscbih VRR_VVV "vector subtract compute borrow indication halfword" z13 zarch -+e700000020f5 vscbif VRR_VVV "vector subtract compute borrow indication word" z13 zarch -+e700000030f5 vscbig VRR_VVV "vector subtract compute borrow indication doubleword" z13 zarch -+e700000040f5 vscbiq VRR_VVV "vector subtract compute borrow indication quadword" z13 zarch -+e700000000bf vsbi VRR_VVVU0V "vector subtract with borrow indication" z13 zarch -+e700040000bf vsbiq VRR_VVV0V "vector subtract with borrow indication quadword" z13 zarch -+e700000000bd vsbcbi VRR_VVVU0V "vector subtract with borrow compute borrow indication" z13 zarch -+e700040000bd vsbcbiq VRR_VVV0V "vector subtract with borrow compute borrow indication quadword" z13 zarch -+e70000000065 vsumg VRR_VVV0U "vector sum across doubleword" z13 zarch -+e70000001065 vsumgh VRR_VVV "vector sum across doubleword - halfword" z13 zarch -+e70000002065 vsumgf VRR_VVV "vector sum across doubleword - word" z13 zarch -+e70000000067 vsumq VRR_VVV0U "vector sum across quadword" z13 zarch -+e70000002067 vsumqf VRR_VVV "vector sum across quadword - word elements" z13 zarch -+e70000003067 vsumqg VRR_VVV "vector sum across quadword - doubleword elements" z13 zarch -+e70000000064 vsum VRR_VVV0U "vector sum across word" z13 zarch -+e70000000064 vsumb VRR_VVV "vector sum across word - byte elements" z13 zarch -+e70000001064 vsumh VRR_VVV "vector sum across word - halfword elements" z13 zarch -+e700000000d8 vtm VRR_VV "vector test under mask" z13 zarch -+ -+# Chapter 23 - Vector String Instructions -+e70000000082 vfae VRR_VVV0U0U "vector find any element equal" z13 zarch optparm -+e70000000082 vfaeb VRR_VVV0U0 "vector find any element equal byte" z13 zarch optparm -+e70000001082 vfaeh VRR_VVV0U0 "vector find any element equal halfword" z13 zarch optparm -+e70000002082 vfaef VRR_VVV0U0 "vector find any element equal word" z13 zarch optparm -+e70000100082 vfaebs VRR_VVV0U1 "vector find any element equal" z13 zarch optparm -+e70000101082 vfaehs VRR_VVV0U1 "vector find any element equal" z13 zarch optparm -+e70000102082 vfaefs VRR_VVV0U1 "vector find any element equal" z13 zarch optparm -+e70000200082 vfaezb VRR_VVV0U2 "vector find any element equal" z13 zarch optparm -+e70000201082 vfaezh VRR_VVV0U2 "vector find any element equal" z13 zarch optparm -+e70000202082 vfaezf VRR_VVV0U2 "vector find any element equal" z13 zarch optparm -+e70000300082 vfaezbs VRR_VVV0U3 "vector find any element equal" z13 zarch optparm -+e70000301082 vfaezhs VRR_VVV0U3 "vector find any element equal" z13 zarch optparm -+e70000302082 vfaezfs VRR_VVV0U3 "vector find any element equal" z13 zarch optparm -+e70000000080 vfee VRR_VVV0U0U "vector find element equal" z13 zarch optparm -+e70000000080 vfeeb VRR_VVV0U0 "vector find element equal byte" z13 zarch optparm -+e70000001080 vfeeh VRR_VVV0U0 "vector find element equal halfword" z13 zarch optparm -+e70000002080 vfeef VRR_VVV0U0 "vector find element equal word" z13 zarch optparm -+e70000100080 vfeebs VRR_VVV "vector find element equal byte" z13 zarch -+e70000101080 vfeehs VRR_VVV "vector find element equal halfword" z13 zarch -+e70000102080 vfeefs VRR_VVV "vector find element equal word" z13 zarch -+e70000200080 vfeezb VRR_VVV "vector find element equal byte" z13 zarch -+e70000201080 vfeezh VRR_VVV "vector find element equal halfword" z13 zarch -+e70000202080 vfeezf VRR_VVV "vector find element equal word" z13 zarch -+e70000300080 vfeezbs VRR_VVV "vector find element equal byte" z13 zarch -+e70000301080 vfeezhs VRR_VVV "vector find element equal halfword" z13 zarch -+e70000302080 vfeezfs VRR_VVV "vector find element equal word" z13 zarch -+e70000000081 vfene VRR_VVV0U0U "vector find element not equal" z13 zarch optparm -+e70000000081 vfeneb VRR_VVV0U0 "vector find element not equal byte" z13 zarch optparm -+e70000001081 vfeneh VRR_VVV0U0 "vector find element not equal halfword" z13 zarch optparm -+e70000002081 vfenef VRR_VVV0U0 "vector find element not equal word" z13 zarch optparm -+e70000100081 vfenebs VRR_VVV "vector find element not equal byte" z13 zarch -+e70000101081 vfenehs VRR_VVV "vector find element not equal halfword" z13 zarch -+e70000102081 vfenefs VRR_VVV "vector find element not equal word" z13 zarch -+e70000200081 vfenezb VRR_VVV "vector find element not equal byte" z13 zarch -+e70000201081 vfenezh VRR_VVV "vector find element not equal halfword" z13 zarch -+e70000202081 vfenezf VRR_VVV "vector find element not equal word" z13 zarch -+e70000300081 vfenezbs VRR_VVV "vector find element not equal byte" z13 zarch -+e70000301081 vfenezhs VRR_VVV "vector find element not equal halfword" z13 zarch -+e70000302081 vfenezfs VRR_VVV "vector find element not equal word" z13 zarch -+e7000000005c vistr VRR_VV0U0U "vector isolate string" z13 zarch optparm -+e7000000005c vistrb VRR_VV0U2 "vector isolate string byte" z13 zarch optparm -+e7000000105c vistrh VRR_VV0U2 "vector isolate string halfword" z13 zarch optparm -+e7000000205c vistrf VRR_VV0U2 "vector isolate string word" z13 zarch optparm -+e7000010005c vistrbs VRR_VV "vector isolate string byte" z13 zarch -+e7000010105c vistrhs VRR_VV "vector isolate string halfword" z13 zarch -+e7000010205c vistrfs VRR_VV "vector isolate string word" z13 zarch -+e7000000008a vstrc VRR_VVVUU0V "vector string range compare" z13 zarch optparm -+e7000000008a vstrcb VRR_VVVU0VB "vector string range compare byte" z13 zarch optparm -+e7000100008a vstrch VRR_VVVU0VB "vector string range compare halfword" z13 zarch optparm -+e7000200008a vstrcf VRR_VVVU0VB "vector string range compare word" z13 zarch optparm -+e7000010008a vstrcbs VRR_VVVU0VB1 "vector string range compare byte" z13 zarch optparm -+e7000110008a vstrchs VRR_VVVU0VB1 "vector string range compare halfword" z13 zarch optparm -+e7000210008a vstrcfs VRR_VVVU0VB1 "vector string range compare word" z13 zarch optparm -+e7000020008a vstrczb VRR_VVVU0VB2 "vector string range compare byte" z13 zarch optparm -+e7000120008a vstrczh VRR_VVVU0VB2 "vector string range compare halfword" z13 zarch optparm -+e7000220008a vstrczf VRR_VVVU0VB2 "vector string range compare word" z13 zarch optparm -+e7000030008a vstrczbs VRR_VVVU0VB3 "vector string range compare byte" z13 zarch optparm -+e7000130008a vstrczhs VRR_VVVU0VB3 "vector string range compare halfword" z13 zarch optparm -+e7000230008a vstrczfs VRR_VVVU0VB3 "vector string range compare word" z13 zarch optparm -+ -+# Chapter 24 -+e700000000e3 vfa VRR_VVV0UU "vector fp add" z13 zarch -+e700000030e3 vfadb VRR_VVV "vector fp add" z13 zarch -+e700000830e3 wfadb VRR_VVV "vector fp add" z13 zarch -+e700000000cb wfc VRR_VV0UU "vector fp compare scalar" z13 zarch -+e700000030cb wfcdb VRR_VV "vector fp compare scalar" z13 zarch -+e700000000ca wfk VRR_VV0UU "vector fp compare and signal scalar" z13 zarch -+e700000030ca wfkdb VRR_VV "vector fp compare and signal scalar" z13 zarch -+e700000000e8 vfce VRR_VVV "vector fp compare equal" z13 zarch -+e700000030e8 vfcedb VRR_VVV "vector fp compare equal" z13 zarch -+e700001030e8 vfcedbs VRR_VVV "vector fp compare equal" z13 zarch -+e700000830e8 wfcedb VRR_VVV "vector fp compare equal" z13 zarch -+e700001830e8 wfcedbs VRR_VVV "vector fp compare equal" z13 zarch -+e700000000eb vfch VRR_VVV0UUU "vector fp compare high" z13 zarch -+e700000030eb vfchdb VRR_VVV "vector fp compare high" z13 zarch -+e700001030eb vfchdbs VRR_VVV "vector fp compare high" z13 zarch -+e700000830eb wfchdb VRR_VVV "vector fp compare high" z13 zarch -+e700001830eb wfchdbs VRR_VVV "vector fp compare high" z13 zarch -+e700000000ea vfche VRR_VVV0UUU "vector fp compare high or equal" z13 zarch -+e700000030ea vfchedb VRR_VVV "vector fp compare high or equal" z13 zarch -+e700001030ea vfchedbs VRR_VVV "vector fp compare high or equal" z13 zarch -+e700000830ea wfchedb VRR_VVV "vector fp compare high or equal" z13 zarch -+e700001830ea wfchedbs VRR_VVV "vector fp compare high or equal" z13 zarch -+e700000000c3 vcdg VRR_VV0UUU "vector fp convert from fixed 64 bit" z13 zarch -+e700000030c3 vcdgb VRR_VV0UU "vector fp convert from fixed 64 bit" z13 zarch -+e700000830c3 wcdgb VRR_VV0UU8 "vector fp convert from fixed 64 bit" z13 zarch -+e700000000c1 vcdlg VRR_VV0UUU "vector fp convert from logical 64 bit" z13 zarch -+e700000030c1 vcdlgb VRR_VV0UU "vector fp convert from logical 64 bit" z13 zarch -+e700000830c1 wcdlgb VRR_VV0UU8 "vector fp convert from logical 64 bit" z13 zarch -+e700000000c2 vcgd VRR_VV0UUU "vector fp convert to fixed 64 bit" z13 zarch -+e700000030c2 vcgdb VRR_VV0UU "vector fp convert to fixed 64 bit" z13 zarch -+e700000830c2 wcgdb VRR_VV0UU8 "vector fp convert to fixed 64 bit" z13 zarch -+e700000000c0 vclgd VRR_VV0UUU "vector fp convert to logical 64 bit" z13 zarch -+e700000030c0 vclgdb VRR_VV0UU "vector fp convert to logical 64 bit" z13 zarch -+e700000830c0 wclgdb VRR_VV0UU8 "vector fp convert to logical 64 bit" z13 zarch -+e700000000e5 vfd VRR_VVV0UU "vector fp divide" z13 zarch -+e700000030e5 vfddb VRR_VVV "vector fp divide" z13 zarch -+e700000830e5 wfddb VRR_VVV "vector fp divide" z13 zarch -+e700000000c7 vfi VRR_VV0UUU "vector load fp integer" z13 zarch -+e700000030c7 vfidb VRR_VV0UU "vector load fp integer" z13 zarch -+e700000830c7 wfidb VRR_VV0UU8 "vector load fp integer" z13 zarch -+e700000000c4 vlde VRR_VV0UU "vector fp load lengthened" z13 zarch -+e700000020c4 vldeb VRR_VV "vector fp load lengthened" z13 zarch -+e700000820c4 wldeb VRR_VV "vector fp load lengthened" z13 zarch -+e700000000c5 vled VRR_VV0UUU "vector fp load rounded" z13 zarch -+e700000030c5 vledb VRR_VV0UU "vector fp load rounded" z13 zarch -+e700000830c5 wledb VRR_VV0UU8 "vector fp load rounded" z13 zarch -+e700000000e7 vfm VRR_VVV0UU "vector fp multiply" z13 zarch -+e700000030e7 vfmdb VRR_VVV "vector fp multiply" z13 zarch -+e700000830e7 wfmdb VRR_VVV "vector fp multiply" z13 zarch -+e7000000008f vfma VRR_VVVU0UV "vector fp multiply and add" z13 zarch -+e7000300008f vfmadb VRR_VVVV "vector fp multiply and add" z13 zarch -+e7000308008f wfmadb VRR_VVVV "vector fp multiply and add" z13 zarch -+e7000000008e vfms VRR_VVVU0UV "vector fp multiply and subtract" z13 zarch -+e7000300008e vfmsdb VRR_VVVV "vector fp multiply and subtract" z13 zarch -+e7000308008e wfmsdb VRR_VVVV "vector fp multiply and subtract" z13 zarch -+e700000000cc vfpso VRR_VV0UUU "vector fp perform sign operation" z13 zarch -+e700000030cc vfpsodb VRR_VV0U2 "vector fp perform sign operation" z13 zarch -+e700000830cc wfpsodb VRR_VV0U2 "vector fp perform sign operation" z13 zarch -+e700000030cc vflcdb VRR_VV "vector fp perform sign operation" z13 zarch -+e700000830cc wflcdb VRR_VV "vector fp perform sign operation" z13 zarch -+e700001030cc vflndb VRR_VV "vector fp perform sign operation" z13 zarch -+e700001830cc wflndb VRR_VV "vector fp perform sign operation" z13 zarch -+e700002030cc vflpdb VRR_VV "vector fp perform sign operation" z13 zarch -+e700002830cc wflpdb VRR_VV "vector fp perform sign operation" z13 zarch -+e700000000ce vfsq VRR_VV0UU "vector fp square root" z13 zarch -+e700000030ce vfsqdb VRR_VV "vector fp square root" z13 zarch -+e700000830ce wfsqdb VRR_VV "vector fp square root" z13 zarch -+e700000000e2 vfs VRR_VVV0UU "vector fp subtract" z13 zarch -+e700000030e2 vfsdb VRR_VVV "vector fp subtract" z13 zarch -+e700000830e2 wfsdb VRR_VVV "vector fp subtract" z13 zarch -+e7000000004a vftci VRI_VVUUU "vector fp test data class immediate" z13 zarch -+e7000000304a vftcidb VRI_VVU2 "vector fp test data class immediate" z13 zarch -+e7000008304a wftcidb VRI_VVU2 "vector fp test data class immediate" z13 zarch --- -2.3.0 - diff --git a/0002-S-390-Add-check-for-length-field-operand.patch b/0002-S-390-Add-check-for-length-field-operand.patch deleted file mode 100644 index 2811564..0000000 --- a/0002-S-390-Add-check-for-length-field-operand.patch +++ /dev/null @@ -1,34 +0,0 @@ -From ae2046d38892cc42febb799141b2457f4e519fd0 Mon Sep 17 00:00:00 2001 -From: Andreas Krebbel -Date: Tue, 10 Mar 2015 12:41:57 +0100 -Subject: [PATCH 2/5] S/390: Add check for length field operand - -gas/ -2015-03-10 Andreas Krebbel - - * gas/config/tc-s390.c (md_gather_operands): Check for valid - length field operands. - -# Conflicts: -# gas/ChangeLog ---- - gas/config/tc-s390.c | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c -index 052baf1..a8394c5 100644 ---- a/gas/config/tc-s390.c -+++ b/gas/config/tc-s390.c -@@ -1216,6 +1216,9 @@ md_gather_operands (char *str, - } - else - { -+ if ((operand->flags & S390_OPERAND_LENGTH) -+ && ex.X_op != O_constant) -+ as_fatal (_("invalid length field specified")); - if ((operand->flags & S390_OPERAND_INDEX) - && ex.X_add_number == 0 - && warn_areg_zero) --- -2.3.0 - diff --git a/0003-S-390-Add-more-IBM-z13-instructions.patch b/0003-S-390-Add-more-IBM-z13-instructions.patch deleted file mode 100644 index a046038..0000000 --- a/0003-S-390-Add-more-IBM-z13-instructions.patch +++ /dev/null @@ -1,365 +0,0 @@ -From ac7c37a5eec4299bfae164839a04b03eae27b962 Mon Sep 17 00:00:00 2001 -From: Andreas Krebbel -Date: Tue, 10 Mar 2015 12:44:54 +0100 -Subject: [PATCH 3/5] S/390: Add more IBM z13 instructions - -opcodes/ -2015-03-10 Andreas Krebbel - - * s390-opc.c: Add new IBM z13 instructions. - * s390-opc.txt: Likewise. - -gas/testsuite/ -2015-03-10 Andreas Krebbel - - * gas/s390/zarch-z13.d: Add more z13 instructions. - * gas/s390/zarch-z13.s: Likewise. - -# Conflicts: -# gas/testsuite/ChangeLog -# opcodes/ChangeLog ---- - gas/testsuite/gas/s390/zarch-z13.d | 134 +++++++++++++++++++++++++++++++++++++ - gas/testsuite/gas/s390/zarch-z13.s | 134 +++++++++++++++++++++++++++++++++++++ - opcodes/s390-opc.c | 2 + - opcodes/s390-opc.txt | 23 +++++++ - 4 files changed, 293 insertions(+) - -diff --git a/gas/testsuite/gas/s390/zarch-z13.d b/gas/testsuite/gas/s390/zarch-z13.d -index f74b9f8..b2e010d 100644 ---- a/gas/testsuite/gas/s390/zarch-z13.d -+++ b/gas/testsuite/gas/s390/zarch-z13.d -@@ -546,3 +546,137 @@ Disassembly of section .text: - .*: e7 f1 ff db c4 4a [ ]*vftci %v15,%v17,4093,12,11 - .*: e7 f1 ff d0 34 4a [ ]*vftcidb %v15,%v17,4093 - .*: e7 f1 ff d8 34 4a [ ]*wftcidb %v15,%v17,4093 -+.*: ed fa 6f a0 3c ae [ ]*cdpt %f3,4000\(251,%r6\),12 -+.*: ed fa 6f a0 1c af [ ]*cxpt %f1,4000\(251,%r6\),12 -+.*: ed fa 6f a0 3c ac [ ]*cpdt %f3,4000\(251,%r6\),12 -+.*: ed fa 6f a0 1c ad [ ]*cpxt %f1,4000\(251,%r6\),12 -+.*: b9 e0 d0 69 [ ]*locfhrnh %r6,%r9 -+.*: b9 e0 10 69 [ ]*locfhro %r6,%r9 -+.*: b9 e0 20 69 [ ]*locfhrh %r6,%r9 -+.*: b9 e0 20 69 [ ]*locfhrh %r6,%r9 -+.*: b9 e0 30 69 [ ]*locfhrnle %r6,%r9 -+.*: b9 e0 40 69 [ ]*locfhrl %r6,%r9 -+.*: b9 e0 40 69 [ ]*locfhrl %r6,%r9 -+.*: b9 e0 50 69 [ ]*locfhrnhe %r6,%r9 -+.*: b9 e0 60 69 [ ]*locfhrlh %r6,%r9 -+.*: b9 e0 70 69 [ ]*locfhrne %r6,%r9 -+.*: b9 e0 70 69 [ ]*locfhrne %r6,%r9 -+.*: b9 e0 80 69 [ ]*locfhre %r6,%r9 -+.*: b9 e0 80 69 [ ]*locfhre %r6,%r9 -+.*: b9 e0 90 69 [ ]*locfhrnlh %r6,%r9 -+.*: b9 e0 a0 69 [ ]*locfhrhe %r6,%r9 -+.*: b9 e0 b0 69 [ ]*locfhrnl %r6,%r9 -+.*: b9 e0 b0 69 [ ]*locfhrnl %r6,%r9 -+.*: b9 e0 c0 69 [ ]*locfhrle %r6,%r9 -+.*: b9 e0 d0 69 [ ]*locfhrnh %r6,%r9 -+.*: b9 e0 d0 69 [ ]*locfhrnh %r6,%r9 -+.*: b9 e0 e0 69 [ ]*locfhrno %r6,%r9 -+.*: eb 6d 98 f0 fd e0 [ ]*locfhnh %r6,-10000\(%r9\) -+.*: eb 61 98 f0 fd e0 [ ]*locfho %r6,-10000\(%r9\) -+.*: eb 62 98 f0 fd e0 [ ]*locfhh %r6,-10000\(%r9\) -+.*: eb 62 98 f0 fd e0 [ ]*locfhh %r6,-10000\(%r9\) -+.*: eb 63 98 f0 fd e0 [ ]*locfhnle %r6,-10000\(%r9\) -+.*: eb 64 98 f0 fd e0 [ ]*locfhl %r6,-10000\(%r9\) -+.*: eb 64 98 f0 fd e0 [ ]*locfhl %r6,-10000\(%r9\) -+.*: eb 65 98 f0 fd e0 [ ]*locfhnhe %r6,-10000\(%r9\) -+.*: eb 66 98 f0 fd e0 [ ]*locfhlh %r6,-10000\(%r9\) -+.*: eb 67 98 f0 fd e0 [ ]*locfhne %r6,-10000\(%r9\) -+.*: eb 67 98 f0 fd e0 [ ]*locfhne %r6,-10000\(%r9\) -+.*: eb 68 98 f0 fd e0 [ ]*locfhe %r6,-10000\(%r9\) -+.*: eb 68 98 f0 fd e0 [ ]*locfhe %r6,-10000\(%r9\) -+.*: eb 69 98 f0 fd e0 [ ]*locfhnlh %r6,-10000\(%r9\) -+.*: eb 6a 98 f0 fd e0 [ ]*locfhhe %r6,-10000\(%r9\) -+.*: eb 6b 98 f0 fd e0 [ ]*locfhnl %r6,-10000\(%r9\) -+.*: eb 6b 98 f0 fd e0 [ ]*locfhnl %r6,-10000\(%r9\) -+.*: eb 6c 98 f0 fd e0 [ ]*locfhle %r6,-10000\(%r9\) -+.*: eb 6d 98 f0 fd e0 [ ]*locfhnh %r6,-10000\(%r9\) -+.*: eb 6d 98 f0 fd e0 [ ]*locfhnh %r6,-10000\(%r9\) -+.*: eb 6e 98 f0 fd e0 [ ]*locfhno %r6,-10000\(%r9\) -+.*: ec 6c 80 03 00 42 [ ]*lochile %r6,-32765 -+.*: ec 61 80 03 00 42 [ ]*lochio %r6,-32765 -+.*: ec 62 80 03 00 42 [ ]*lochih %r6,-32765 -+.*: ec 62 80 03 00 42 [ ]*lochih %r6,-32765 -+.*: ec 63 80 03 00 42 [ ]*lochinle %r6,-32765 -+.*: ec 64 80 03 00 42 [ ]*lochil %r6,-32765 -+.*: ec 64 80 03 00 42 [ ]*lochil %r6,-32765 -+.*: ec 65 80 03 00 42 [ ]*lochinhe %r6,-32765 -+.*: ec 66 80 03 00 42 [ ]*lochilh %r6,-32765 -+.*: ec 67 80 03 00 42 [ ]*lochine %r6,-32765 -+.*: ec 67 80 03 00 42 [ ]*lochine %r6,-32765 -+.*: ec 68 80 03 00 42 [ ]*lochie %r6,-32765 -+.*: ec 68 80 03 00 42 [ ]*lochie %r6,-32765 -+.*: ec 69 80 03 00 42 [ ]*lochinlh %r6,-32765 -+.*: ec 6a 80 03 00 42 [ ]*lochihe %r6,-32765 -+.*: ec 6b 80 03 00 42 [ ]*lochinl %r6,-32765 -+.*: ec 6b 80 03 00 42 [ ]*lochinl %r6,-32765 -+.*: ec 6c 80 03 00 42 [ ]*lochile %r6,-32765 -+.*: ec 6d 80 03 00 42 [ ]*lochinh %r6,-32765 -+.*: ec 6d 80 03 00 42 [ ]*lochinh %r6,-32765 -+.*: ec 6e 80 03 00 42 [ ]*lochino %r6,-32765 -+.*: ec 6c 80 03 00 46 [ ]*locghile %r6,-32765 -+.*: ec 61 80 03 00 46 [ ]*locghio %r6,-32765 -+.*: ec 62 80 03 00 46 [ ]*locghih %r6,-32765 -+.*: ec 62 80 03 00 46 [ ]*locghih %r6,-32765 -+.*: ec 63 80 03 00 46 [ ]*locghinle %r6,-32765 -+.*: ec 64 80 03 00 46 [ ]*locghil %r6,-32765 -+.*: ec 64 80 03 00 46 [ ]*locghil %r6,-32765 -+.*: ec 65 80 03 00 46 [ ]*locghinhe %r6,-32765 -+.*: ec 66 80 03 00 46 [ ]*locghilh %r6,-32765 -+.*: ec 67 80 03 00 46 [ ]*locghine %r6,-32765 -+.*: ec 67 80 03 00 46 [ ]*locghine %r6,-32765 -+.*: ec 68 80 03 00 46 [ ]*locghie %r6,-32765 -+.*: ec 68 80 03 00 46 [ ]*locghie %r6,-32765 -+.*: ec 69 80 03 00 46 [ ]*locghinlh %r6,-32765 -+.*: ec 6a 80 03 00 46 [ ]*locghihe %r6,-32765 -+.*: ec 6b 80 03 00 46 [ ]*locghinl %r6,-32765 -+.*: ec 6b 80 03 00 46 [ ]*locghinl %r6,-32765 -+.*: ec 6c 80 03 00 46 [ ]*locghile %r6,-32765 -+.*: ec 6d 80 03 00 46 [ ]*locghinh %r6,-32765 -+.*: ec 6d 80 03 00 46 [ ]*locghinh %r6,-32765 -+.*: ec 6e 80 03 00 46 [ ]*locghino %r6,-32765 -+.*: ec 6c 80 03 00 4e [ ]*lochhile %r6,-32765 -+.*: ec 61 80 03 00 4e [ ]*lochhio %r6,-32765 -+.*: ec 62 80 03 00 4e [ ]*lochhih %r6,-32765 -+.*: ec 62 80 03 00 4e [ ]*lochhih %r6,-32765 -+.*: ec 63 80 03 00 4e [ ]*lochhinle %r6,-32765 -+.*: ec 64 80 03 00 4e [ ]*lochhil %r6,-32765 -+.*: ec 64 80 03 00 4e [ ]*lochhil %r6,-32765 -+.*: ec 65 80 03 00 4e [ ]*lochhinhe %r6,-32765 -+.*: ec 66 80 03 00 4e [ ]*lochhilh %r6,-32765 -+.*: ec 67 80 03 00 4e [ ]*lochhine %r6,-32765 -+.*: ec 67 80 03 00 4e [ ]*lochhine %r6,-32765 -+.*: ec 68 80 03 00 4e [ ]*lochhie %r6,-32765 -+.*: ec 68 80 03 00 4e [ ]*lochhie %r6,-32765 -+.*: ec 69 80 03 00 4e [ ]*lochhinlh %r6,-32765 -+.*: ec 6a 80 03 00 4e [ ]*lochhihe %r6,-32765 -+.*: ec 6b 80 03 00 4e [ ]*lochhinl %r6,-32765 -+.*: ec 6b 80 03 00 4e [ ]*lochhinl %r6,-32765 -+.*: ec 6c 80 03 00 4e [ ]*lochhile %r6,-32765 -+.*: ec 6d 80 03 00 4e [ ]*lochhinh %r6,-32765 -+.*: ec 6d 80 03 00 4e [ ]*lochhinh %r6,-32765 -+.*: ec 6e 80 03 00 4e [ ]*lochhino %r6,-32765 -+.*: eb 6d 98 f0 fd e1 [ ]*stocfhnh %r6,-10000\(%r9\) -+.*: eb 61 98 f0 fd e1 [ ]*stocfho %r6,-10000\(%r9\) -+.*: eb 62 98 f0 fd e1 [ ]*stocfhh %r6,-10000\(%r9\) -+.*: eb 62 98 f0 fd e1 [ ]*stocfhh %r6,-10000\(%r9\) -+.*: eb 63 98 f0 fd e1 [ ]*stocfhnle %r6,-10000\(%r9\) -+.*: eb 64 98 f0 fd e1 [ ]*stocfhl %r6,-10000\(%r9\) -+.*: eb 64 98 f0 fd e1 [ ]*stocfhl %r6,-10000\(%r9\) -+.*: eb 65 98 f0 fd e1 [ ]*stocfhnhe %r6,-10000\(%r9\) -+.*: eb 66 98 f0 fd e1 [ ]*stocfhlh %r6,-10000\(%r9\) -+.*: eb 67 98 f0 fd e1 [ ]*stocfhne %r6,-10000\(%r9\) -+.*: eb 67 98 f0 fd e1 [ ]*stocfhne %r6,-10000\(%r9\) -+.*: eb 68 98 f0 fd e1 [ ]*stocfhe %r6,-10000\(%r9\) -+.*: eb 68 98 f0 fd e1 [ ]*stocfhe %r6,-10000\(%r9\) -+.*: eb 69 98 f0 fd e1 [ ]*stocfhnlh %r6,-10000\(%r9\) -+.*: eb 6a 98 f0 fd e1 [ ]*stocfhhe %r6,-10000\(%r9\) -+.*: eb 6b 98 f0 fd e1 [ ]*stocfhnl %r6,-10000\(%r9\) -+.*: eb 6b 98 f0 fd e1 [ ]*stocfhnl %r6,-10000\(%r9\) -+.*: eb 6c 98 f0 fd e1 [ ]*stocfhle %r6,-10000\(%r9\) -+.*: eb 6d 98 f0 fd e1 [ ]*stocfhnh %r6,-10000\(%r9\) -+.*: eb 6d 98 f0 fd e1 [ ]*stocfhnh %r6,-10000\(%r9\) -+.*: eb 6e 98 f0 fd e1 [ ]*stocfhno %r6,-10000\(%r9\) -+.*: e3 69 b8 f0 fd 3a [ ]*llzrgf %r6,-10000\(%r9,%r11\) -+.*: e3 69 b8 f0 fd 3b [ ]*lzrf %r6,-10000\(%r9,%r11\) -+.*: e3 69 b8 f0 fd 2a [ ]*lzrg %r6,-10000\(%r9,%r11\) -+.*: b9 ec 00 69 [ ]*ppno %r6,%r9 -diff --git a/gas/testsuite/gas/s390/zarch-z13.s b/gas/testsuite/gas/s390/zarch-z13.s -index 812e3e8..688020d 100644 ---- a/gas/testsuite/gas/s390/zarch-z13.s -+++ b/gas/testsuite/gas/s390/zarch-z13.s -@@ -540,3 +540,137 @@ foo: - vftci %v15,%v17,4093,12,11 - vftcidb %v15,%v17,4093 - wftcidb %v15,%v17,4093 -+ cdpt %f3,4000(251,%r6),12 -+ cxpt %f1,4000(251,%r6),12 -+ cpdt %f3,4000(251,%r6),12 -+ cpxt %f1,4000(251,%r6),12 -+ locfhr %r6,%r9,13 -+ locfhro %r6,%r9 -+ locfhrh %r6,%r9 -+ locfhrp %r6,%r9 -+ locfhrnle %r6,%r9 -+ locfhrl %r6,%r9 -+ locfhrm %r6,%r9 -+ locfhrnhe %r6,%r9 -+ locfhrlh %r6,%r9 -+ locfhrne %r6,%r9 -+ locfhrnz %r6,%r9 -+ locfhre %r6,%r9 -+ locfhrz %r6,%r9 -+ locfhrnlh %r6,%r9 -+ locfhrhe %r6,%r9 -+ locfhrnl %r6,%r9 -+ locfhrnm %r6,%r9 -+ locfhrle %r6,%r9 -+ locfhrnh %r6,%r9 -+ locfhrnp %r6,%r9 -+ locfhrno %r6,%r9 -+ locfh %r6,-10000(%r9),13 -+ locfho %r6,-10000(%r9) -+ locfhh %r6,-10000(%r9) -+ locfhp %r6,-10000(%r9) -+ locfhnle %r6,-10000(%r9) -+ locfhl %r6,-10000(%r9) -+ locfhm %r6,-10000(%r9) -+ locfhnhe %r6,-10000(%r9) -+ locfhlh %r6,-10000(%r9) -+ locfhne %r6,-10000(%r9) -+ locfhnz %r6,-10000(%r9) -+ locfhe %r6,-10000(%r9) -+ locfhz %r6,-10000(%r9) -+ locfhnlh %r6,-10000(%r9) -+ locfhhe %r6,-10000(%r9) -+ locfhnl %r6,-10000(%r9) -+ locfhnm %r6,-10000(%r9) -+ locfhle %r6,-10000(%r9) -+ locfhnh %r6,-10000(%r9) -+ locfhnp %r6,-10000(%r9) -+ locfhno %r6,-10000(%r9) -+ lochi %r6,-32765,12 -+ lochio %r6,-32765 -+ lochih %r6,-32765 -+ lochip %r6,-32765 -+ lochinle %r6,-32765 -+ lochil %r6,-32765 -+ lochim %r6,-32765 -+ lochinhe %r6,-32765 -+ lochilh %r6,-32765 -+ lochine %r6,-32765 -+ lochinz %r6,-32765 -+ lochie %r6,-32765 -+ lochiz %r6,-32765 -+ lochinlh %r6,-32765 -+ lochihe %r6,-32765 -+ lochinl %r6,-32765 -+ lochinm %r6,-32765 -+ lochile %r6,-32765 -+ lochinh %r6,-32765 -+ lochinp %r6,-32765 -+ lochino %r6,-32765 -+ locghi %r6,-32765,12 -+ locghio %r6,-32765 -+ locghih %r6,-32765 -+ locghip %r6,-32765 -+ locghinle %r6,-32765 -+ locghil %r6,-32765 -+ locghim %r6,-32765 -+ locghinhe %r6,-32765 -+ locghilh %r6,-32765 -+ locghine %r6,-32765 -+ locghinz %r6,-32765 -+ locghie %r6,-32765 -+ locghiz %r6,-32765 -+ locghinlh %r6,-32765 -+ locghihe %r6,-32765 -+ locghinl %r6,-32765 -+ locghinm %r6,-32765 -+ locghile %r6,-32765 -+ locghinh %r6,-32765 -+ locghinp %r6,-32765 -+ locghino %r6,-32765 -+ lochhi %r6,-32765,12 -+ lochhio %r6,-32765 -+ lochhih %r6,-32765 -+ lochhip %r6,-32765 -+ lochhinle %r6,-32765 -+ lochhil %r6,-32765 -+ lochhim %r6,-32765 -+ lochhinhe %r6,-32765 -+ lochhilh %r6,-32765 -+ lochhine %r6,-32765 -+ lochhinz %r6,-32765 -+ lochhie %r6,-32765 -+ lochhiz %r6,-32765 -+ lochhinlh %r6,-32765 -+ lochhihe %r6,-32765 -+ lochhinl %r6,-32765 -+ lochhinm %r6,-32765 -+ lochhile %r6,-32765 -+ lochhinh %r6,-32765 -+ lochhinp %r6,-32765 -+ lochhino %r6,-32765 -+ stocfh %r6,-10000(%r9),13 -+ stocfho %r6,-10000(%r9) -+ stocfhh %r6,-10000(%r9) -+ stocfhp %r6,-10000(%r9) -+ stocfhnle %r6,-10000(%r9) -+ stocfhl %r6,-10000(%r9) -+ stocfhm %r6,-10000(%r9) -+ stocfhnhe %r6,-10000(%r9) -+ stocfhlh %r6,-10000(%r9) -+ stocfhne %r6,-10000(%r9) -+ stocfhnz %r6,-10000(%r9) -+ stocfhe %r6,-10000(%r9) -+ stocfhz %r6,-10000(%r9) -+ stocfhnlh %r6,-10000(%r9) -+ stocfhhe %r6,-10000(%r9) -+ stocfhnl %r6,-10000(%r9) -+ stocfhnm %r6,-10000(%r9) -+ stocfhle %r6,-10000(%r9) -+ stocfhnh %r6,-10000(%r9) -+ stocfhnp %r6,-10000(%r9) -+ stocfhno %r6,-10000(%r9) -+ llzrgf %r6,-10000(%r9,%r11) -+ lzrf %r6,-10000(%r9,%r11) -+ lzrg %r6,-10000(%r9,%r11) -+ ppno %r6,%r9 -diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c -index ca82ce5..6f66fd8 100644 ---- a/opcodes/s390-opc.c -+++ b/opcodes/s390-opc.c -@@ -311,6 +311,7 @@ const struct s390_operand s390_operands[] = - #define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */ - #define INSTR_RIE_R0UU 6, { R_8,U16_16,U4_32,0,0,0 } /* e.g. clfit */ - #define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */ -+#define INSTR_RIE_RUI0 6, { R_8,I16_16,U4_12,0,0,0 } /* e.g. lochi */ - #define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */ - #define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ - #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ -@@ -515,6 +516,7 @@ const struct s390_operand s390_operands[] = - #define MASK_RIE_R0I0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } - #define MASK_RIE_R0UU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } - #define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } -+#define MASK_RIE_RUI0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } - #define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } - #define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } - #define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt -index 2a5e1dd..3429494 100644 ---- a/opcodes/s390-opc.txt -+++ b/opcodes/s390-opc.txt -@@ -1656,3 +1656,26 @@ e700000830e2 wfsdb VRR_VVV "vector fp subtract" z13 zarch - e7000000004a vftci VRI_VVUUU "vector fp test data class immediate" z13 zarch - e7000000304a vftcidb VRI_VVU2 "vector fp test data class immediate" z13 zarch - e7000008304a wftcidb VRI_VVU2 "vector fp test data class immediate" z13 zarch -+ -+ed00000000ae cdpt RSL_LRDFU "convert from packed to long dfp" z13 zarch -+ed00000000af cxpt RSL_LRDFEU "convert from packed to extended dfp" z13 zarch -+ed00000000ac cpdt RSL_LRDFU "convert from long dfp to packed" z13 zarch -+ed00000000ad cpxt RSL_LRDFEU "convert from extended dfp to packed" z13 zarch -+ -+b9e0 locfhr RRF_U0RR "load high on condition from gpr" z13 zarch -+b9e000000000 locfhr*16 RRF_00RR "load high on condition from gpr" z13 zarch -+eb00000000e0 locfh RSY_RURD2 "load high on condition from memory" z13 zarch -+eb00000000e0 locfh*12 RSY_R0RD "load high on condition from memory" z13 zarch -+ec0000000042 lochi RIE_RUI0 "load halfword immediate on condition into 32 bit gpr" z13 zarch -+ec0000000042 lochi*12 RIE_R0I0 "load halfword immediate on condition into 32 bit gpr" z13 zarch -+ec0000000046 locghi RIE_RUI0 "load halfword immediate on condition into 64 bit gpr" z13 zarch -+ec0000000046 locghi*12 RIE_R0I0 "load halfword immediate on condition into 64 bit gpr" z13 zarch -+ec000000004e lochhi RIE_RUI0 "load halfword high immediate on condition" z13 zarch -+ec000000004e lochhi*12 RIE_R0I0 "load halfword high immediate on condition" z13 zarch -+eb00000000e1 stocfh RSY_RURD2 "store high on condition" z13 zarch -+eb00000000e1 stocfh*12 RSY_R0RD "store high on condition" z13 zarch -+ -+e3000000003a llzrgf RXY_RRRD "load logical and zero rightmost bytes 32->64" z13 zarch -+e3000000003b lzrf RXY_RRRD "load and zero rightmost byte 32->32" z13 zarch -+e3000000002a lzrg RXY_RRRD "load and zero rightmost byte 64->64" z13 zarch -+b9ec ppno RRE_RR "perform pseudorandom number operation" z13 zarch --- -2.3.0 - diff --git a/0004-S-390-Fixes-for-z13-instructions.patch b/0004-S-390-Fixes-for-z13-instructions.patch deleted file mode 100644 index 5d54962..0000000 --- a/0004-S-390-Fixes-for-z13-instructions.patch +++ /dev/null @@ -1,135 +0,0 @@ -From 29983261245edabe68ab379d8e8f7691de467a57 Mon Sep 17 00:00:00 2001 -From: Andreas Krebbel -Date: Mon, 27 Apr 2015 10:29:16 +0200 -Subject: [PATCH 4/5] S/390: Fixes for z13 instructions. - -opcodes/ - * s390-opc.c: New instruction type VV0UU2. - * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK, - and WFC. - -gas/testsuite/ - * gas/s390/zarch-z13.d: Fix tests for VFCE, VLDE, VFSQ, WFK, and - WFC. - * gas/s390/zarch-z13.s: Likewise. - -# Conflicts: -# gas/testsuite/ChangeLog -# opcodes/ChangeLog ---- - gas/testsuite/gas/s390/zarch-z13.d | 10 +++++----- - gas/testsuite/gas/s390/zarch-z13.s | 2 +- - opcodes/s390-opc.c | 2 ++ - opcodes/s390-opc.txt | 10 +++++----- - 4 files changed, 13 insertions(+), 11 deletions(-) - -diff --git a/gas/testsuite/gas/s390/zarch-z13.d b/gas/testsuite/gas/s390/zarch-z13.d -index b2e010d..66808d6 100644 ---- a/gas/testsuite/gas/s390/zarch-z13.d -+++ b/gas/testsuite/gas/s390/zarch-z13.d -@@ -476,11 +476,11 @@ Disassembly of section .text: - .*: e7 f1 40 0c d6 e3 [ ]*vfa %v15,%v17,%v20,13,12 - .*: e7 f1 40 00 36 e3 [ ]*vfadb %v15,%v17,%v20 - .*: e7 f1 40 08 36 e3 [ ]*wfadb %v15,%v17,%v20 --.*: e7 f1 00 cd 04 cb [ ]*wfc %v15,%v17,13,12 -+.*: e7 f1 00 0c d4 cb [ ]*wfc %v15,%v17,13,12 - .*: e7 f1 00 00 34 cb [ ]*wfcdb %v15,%v17 --.*: e7 f1 00 cd 04 ca [ ]*wfk %v15,%v17,13,12 -+.*: e7 f1 00 0c d4 ca [ ]*wfk %v15,%v17,13,12 - .*: e7 f1 00 00 34 ca [ ]*wfkdb %v15,%v17 --.*: e7 f1 40 00 06 e8 [ ]*vfce %v15,%v17,%v20 -+.*: e7 f1 40 bc d6 e8 [ ]*vfce %v15,%v17,%v20,13,12,11 - .*: e7 f1 40 00 36 e8 [ ]*vfcedb %v15,%v17,%v20 - .*: e7 f1 40 10 36 e8 [ ]*vfcedbs %v15,%v17,%v20 - .*: e7 f1 40 08 36 e8 [ ]*wfcedb %v15,%v17,%v20 -@@ -513,7 +513,7 @@ Disassembly of section .text: - .*: e7 f1 00 bc d4 c7 [ ]*vfi %v15,%v17,13,12,11 - .*: e7 f1 00 cd 34 c7 [ ]*wfidb %v15,%v17,5,12 - .*: e7 f1 00 cd 34 c7 [ ]*wfidb %v15,%v17,5,12 --.*: e7 f1 00 cd 04 c4 [ ]*vlde %v15,%v17,13,12 -+.*: e7 f1 00 0c d4 c4 [ ]*vlde %v15,%v17,13,12 - .*: e7 f1 00 00 24 c4 [ ]*vldeb %v15,%v17 - .*: e7 f1 00 08 24 c4 [ ]*wldeb %v15,%v17 - .*: e7 f1 00 bc d4 c5 [ ]*vled %v15,%v17,13,12,11 -@@ -537,7 +537,7 @@ Disassembly of section .text: - .*: e7 f1 00 18 34 cc [ ]*wflndb %v15,%v17 - .*: e7 f1 00 20 34 cc [ ]*vflpdb %v15,%v17 - .*: e7 f1 00 28 34 cc [ ]*wflpdb %v15,%v17 --.*: e7 f1 00 cd 04 ce [ ]*vfsq %v15,%v17,13,12 -+.*: e7 f1 00 0c d4 ce [ ]*vfsq %v15,%v17,13,12 - .*: e7 f1 00 00 34 ce [ ]*vfsqdb %v15,%v17 - .*: e7 f1 00 08 34 ce [ ]*wfsqdb %v15,%v17 - .*: e7 f1 40 0c d6 e2 [ ]*vfs %v15,%v17,%v20,13,12 -diff --git a/gas/testsuite/gas/s390/zarch-z13.s b/gas/testsuite/gas/s390/zarch-z13.s -index 688020d..c2964d8 100644 ---- a/gas/testsuite/gas/s390/zarch-z13.s -+++ b/gas/testsuite/gas/s390/zarch-z13.s -@@ -474,7 +474,7 @@ foo: - wfcdb %v15,%v17 - wfk %v15,%v17,13,12 - wfkdb %v15,%v17 -- vfce %v15,%v17,%v20 -+ vfce %v15,%v17,%v20,13,12,11 - vfcedb %v15,%v17,%v20 - vfcedbs %v15,%v17,%v20 - wfcedb %v15,%v17,%v20 -diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c -index 6f66fd8..9c557fa 100644 ---- a/opcodes/s390-opc.c -+++ b/opcodes/s390-opc.c -@@ -484,6 +484,7 @@ const struct s390_operand s390_operands[] = - #define INSTR_VRR_VV0U 6, { V_8,V_12,U4_32,0,0,0 } /* e.g. vseg */ - #define INSTR_VRR_VV0U2 6, { V_8,V_12,U4_24,0,0,0 } /* e.g. vistrb*/ - #define INSTR_VRR_VV0UU 6, { V_8,V_12,U4_28,U4_24,0,0 } /* e.g. vcdgb */ -+#define INSTR_VRR_VV0UU2 6, { V_8,V_12,U4_32,U4_28,0,0 } /* e.g. wfc */ - #define INSTR_VRR_VV0UU8 6, { V_8,V_12,U4_OR8_28,U4_24,0,0 } /* e.g. wcdgb */ - #define INSTR_VRR_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vsegb */ - #define INSTR_VRR_VVVUU0V 6, { V_8,V_12,V_16,V_32,U4_20,U4_24 } /* e.g. vstrc */ -@@ -690,6 +691,7 @@ const struct s390_operand s390_operands[] = - #define MASK_VRR_VV0U { 0xff, 0x00, 0xff, 0xff, 0x00, 0xff } - #define MASK_VRR_VV0U2 { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff } - #define MASK_VRR_VV0UU { 0xff, 0x00, 0xff, 0x00, 0xf0, 0xff } -+#define MASK_VRR_VV0UU2 { 0xff, 0x00, 0xff, 0xf0, 0x00, 0xff } - #define MASK_VRR_VV0UU8 { 0xff, 0x00, 0xff, 0x08, 0xf0, 0xff } - #define MASK_VRR_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff } - #define MASK_VRR_VVVUU0V { 0xff, 0x00, 0x00, 0x0f, 0x00, 0xff } -diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt -index 3429494..b86da96 100644 ---- a/opcodes/s390-opc.txt -+++ b/opcodes/s390-opc.txt -@@ -1586,11 +1586,11 @@ e7000230008a vstrczfs VRR_VVVU0VB3 "vector string range compare word" z13 zarch - e700000000e3 vfa VRR_VVV0UU "vector fp add" z13 zarch - e700000030e3 vfadb VRR_VVV "vector fp add" z13 zarch - e700000830e3 wfadb VRR_VVV "vector fp add" z13 zarch --e700000000cb wfc VRR_VV0UU "vector fp compare scalar" z13 zarch -+e700000000cb wfc VRR_VV0UU2 "vector fp compare scalar" z13 zarch - e700000030cb wfcdb VRR_VV "vector fp compare scalar" z13 zarch --e700000000ca wfk VRR_VV0UU "vector fp compare and signal scalar" z13 zarch -+e700000000ca wfk VRR_VV0UU2 "vector fp compare and signal scalar" z13 zarch - e700000030ca wfkdb VRR_VV "vector fp compare and signal scalar" z13 zarch --e700000000e8 vfce VRR_VVV "vector fp compare equal" z13 zarch -+e700000000e8 vfce VRR_VVV0UUU "vector fp compare equal" z13 zarch - e700000030e8 vfcedb VRR_VVV "vector fp compare equal" z13 zarch - e700001030e8 vfcedbs VRR_VVV "vector fp compare equal" z13 zarch - e700000830e8 wfcedb VRR_VVV "vector fp compare equal" z13 zarch -@@ -1623,7 +1623,7 @@ e700000830e5 wfddb VRR_VVV "vector fp divide" z13 zarch - e700000000c7 vfi VRR_VV0UUU "vector load fp integer" z13 zarch - e700000030c7 vfidb VRR_VV0UU "vector load fp integer" z13 zarch - e700000830c7 wfidb VRR_VV0UU8 "vector load fp integer" z13 zarch --e700000000c4 vlde VRR_VV0UU "vector fp load lengthened" z13 zarch -+e700000000c4 vlde VRR_VV0UU2 "vector fp load lengthened" z13 zarch - e700000020c4 vldeb VRR_VV "vector fp load lengthened" z13 zarch - e700000820c4 wldeb VRR_VV "vector fp load lengthened" z13 zarch - e700000000c5 vled VRR_VV0UUU "vector fp load rounded" z13 zarch -@@ -1647,7 +1647,7 @@ e700001030cc vflndb VRR_VV "vector fp perform sign operation" z13 zarch - e700001830cc wflndb VRR_VV "vector fp perform sign operation" z13 zarch - e700002030cc vflpdb VRR_VV "vector fp perform sign operation" z13 zarch - e700002830cc wflpdb VRR_VV "vector fp perform sign operation" z13 zarch --e700000000ce vfsq VRR_VV0UU "vector fp square root" z13 zarch -+e700000000ce vfsq VRR_VV0UU2 "vector fp square root" z13 zarch - e700000030ce vfsqdb VRR_VV "vector fp square root" z13 zarch - e700000830ce wfsqdb VRR_VV "vector fp square root" z13 zarch - e700000000e2 vfs VRR_VVV0UU "vector fp subtract" z13 zarch --- -2.3.0 - diff --git a/0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch b/0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch deleted file mode 100644 index 38ed1a8..0000000 --- a/0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch +++ /dev/null @@ -1,285 +0,0 @@ -From d77ae458893b48e4e4ad5aa74a94023dff4ec4e1 Mon Sep 17 00:00:00 2001 -From: Andreas Krebbel -Date: Mon, 27 Apr 2015 10:32:23 +0200 -Subject: [PATCH 5/5] S/390: z13 use GNU attribute to indicate vector ABI - -bfd/ - * elf-s390-common.c (elf_s390_merge_obj_attributes): New function. - * elf32-s390.c (elf32_s390_merge_private_bfd_data): Call - elf_s390_merge_obj_attributes. - * elf64-s390.c (elf64_s390_merge_private_bfd_data): New function. - -binutils/ - * readelf.c (display_s390_gnu_attribute): New function. - (process_s390_specific): New function. - (process_arch_specific): Call process_s390_specific. - -gas/ - * doc/as.texinfo: Document Tag_GNU_S390_ABI_Vector. - -include/elf/ - * s390.h: Define Tag_GNU_S390_ABI_Vector. - -# Conflicts: -# bfd/ChangeLog -# binutils/ChangeLog -# gas/testsuite/ChangeLog -# include/elf/ChangeLog - -# Conflicts: -# bfd/elf-s390-common.c ---- - bfd/elf-s390-common.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++++++ - bfd/elf32-s390.c | 9 ++++++++ - bfd/elf64-s390.c | 18 +++++++++++++++- - binutils/readelf.c | 46 ++++++++++++++++++++++++++++++++++++++++ - gas/doc/as.texinfo | 16 ++++++++++++++ - include/elf/s390.h | 15 +++++++++++-- - 6 files changed, 159 insertions(+), 3 deletions(-) - -Index: binutils-2.25.0/bfd/elf-s390-common.c -=================================================================== ---- binutils-2.25.0.orig/bfd/elf-s390-common.c 2015-07-09 16:44:50.000000000 +0200 -+++ binutils-2.25.0/bfd/elf-s390-common.c 2015-07-09 16:44:51.000000000 +0200 -@@ -254,3 +254,61 @@ elf_s390_elf_sort_relocs_p (asection *se - { - return (sec->flags & SEC_CODE) == 0; - } -+ -+/* Merge object attributes from IBFD into OBFD. Raise an error if -+ there are conflicting attributes. */ -+static bfd_boolean -+elf_s390_merge_obj_attributes (bfd *ibfd, bfd *obfd) -+{ -+ obj_attribute *in_attr, *in_attrs; -+ obj_attribute *out_attr, *out_attrs; -+ -+ if (!elf_known_obj_attributes_proc (obfd)[0].i) -+ { -+ /* This is the first object. Copy the attributes. */ -+ _bfd_elf_copy_obj_attributes (ibfd, obfd); -+ -+ /* Use the Tag_null value to indicate the attributes have been -+ initialized. */ -+ elf_known_obj_attributes_proc (obfd)[0].i = 1; -+ -+ return TRUE; -+ } -+ -+ in_attrs = elf_known_obj_attributes (ibfd)[OBJ_ATTR_GNU]; -+ out_attrs = elf_known_obj_attributes (obfd)[OBJ_ATTR_GNU]; -+ -+ /* Check for conflicting Tag_GNU_S390_ABI_Vector attributes and -+ merge non-conflicting ones. */ -+ in_attr = &in_attrs[Tag_GNU_S390_ABI_Vector]; -+ out_attr = &out_attrs[Tag_GNU_S390_ABI_Vector]; -+ -+ if (in_attr->i > 2) -+ _bfd_error_handler -+ (_("Warning: %B uses unknown vector ABI %d"), ibfd, -+ in_attr->i); -+ else if (out_attr->i > 2) -+ _bfd_error_handler -+ (_("Warning: %B uses unknown vector ABI %d"), obfd, -+ out_attr->i); -+ else if (in_attr->i != out_attr->i) -+ { -+ out_attr->type = ATTR_TYPE_FLAG_INT_VAL; -+ -+ if (in_attr->i && out_attr->i) -+ { -+ const char abi_str[3][9] = { "none", "software", "hardware" }; -+ -+ _bfd_error_handler -+ (_("Warning: %B uses vector %s ABI, %B uses %s ABI"), -+ ibfd, obfd, abi_str[in_attr->i], abi_str[out_attr->i]); -+ } -+ if (in_attr->i > out_attr->i) -+ out_attr->i = in_attr->i; -+ } -+ -+ /* Merge Tag_compatibility attributes and any common GNU ones. */ -+ _bfd_elf_merge_object_attributes (ibfd, obfd); -+ -+ return TRUE; -+} -Index: binutils-2.25.0/bfd/elf32-s390.c -=================================================================== ---- binutils-2.25.0.orig/bfd/elf32-s390.c 2015-07-09 16:44:50.000000000 +0200 -+++ binutils-2.25.0/bfd/elf32-s390.c 2015-07-09 16:44:51.000000000 +0200 -@@ -4001,9 +4001,18 @@ elf_s390_plt_sym_val (bfd_vma i, const a - return plt->vma + PLT_FIRST_ENTRY_SIZE + i * PLT_ENTRY_SIZE; - } - -+/* Merge backend specific data from an object file to the output -+ object file when linking. */ -+ - static bfd_boolean - elf32_s390_merge_private_bfd_data (bfd *ibfd, bfd *obfd) - { -+ if (!is_s390_elf (ibfd) || !is_s390_elf (obfd)) -+ return TRUE; -+ -+ if (!elf_s390_merge_obj_attributes (ibfd, obfd)) -+ return FALSE; -+ - elf_elfheader (obfd)->e_flags |= elf_elfheader (ibfd)->e_flags; - return TRUE; - } -Index: binutils-2.25.0/bfd/elf64-s390.c -=================================================================== ---- binutils-2.25.0.orig/bfd/elf64-s390.c 2015-07-09 16:44:50.000000000 +0200 -+++ binutils-2.25.0/bfd/elf64-s390.c 2015-07-09 16:44:51.000000000 +0200 -@@ -3766,6 +3766,21 @@ elf_s390_plt_sym_val (bfd_vma i, const a - return plt->vma + PLT_FIRST_ENTRY_SIZE + i * PLT_ENTRY_SIZE; - } - -+/* Merge backend specific data from an object file to the output -+ object file when linking. */ -+ -+static bfd_boolean -+elf64_s390_merge_private_bfd_data (bfd *ibfd, bfd *obfd) -+{ -+ if (!is_s390_elf (ibfd) || !is_s390_elf (obfd)) -+ return TRUE; -+ -+ if (!elf_s390_merge_obj_attributes (ibfd, obfd)) -+ return FALSE; -+ -+ return TRUE; -+} -+ - /* Why was the hash table entry size definition changed from - ARCH_SIZE/8 to 4? This breaks the 64 bit dynamic linker and - this is the only reason for the s390_elf64_size_info structure. */ -@@ -3824,7 +3839,8 @@ const struct elf_size_info s390_elf64_si - #define bfd_elf64_bfd_is_local_label_name elf_s390_is_local_label_name - #define bfd_elf64_bfd_link_hash_table_create elf_s390_link_hash_table_create - #define bfd_elf64_bfd_reloc_type_lookup elf_s390_reloc_type_lookup --#define bfd_elf64_bfd_reloc_name_lookup elf_s390_reloc_name_lookup -+#define bfd_elf64_bfd_reloc_name_lookup elf_s390_reloc_name_lookup -+#define bfd_elf64_bfd_merge_private_bfd_data elf64_s390_merge_private_bfd_data - - #define elf_backend_adjust_dynamic_symbol elf_s390_adjust_dynamic_symbol - #define elf_backend_check_relocs elf_s390_check_relocs -Index: binutils-2.25.0/binutils/readelf.c -=================================================================== ---- binutils-2.25.0.orig/binutils/readelf.c 2015-07-09 16:44:50.000000000 +0200 -+++ binutils-2.25.0/binutils/readelf.c 2015-07-09 16:44:51.000000000 +0200 -@@ -12462,6 +12462,41 @@ display_power_gnu_attribute (unsigned ch - return display_tag_value (tag & 1, p, end); - } - -+static unsigned char * -+display_s390_gnu_attribute (unsigned char * p, -+ int tag, -+ const unsigned char * const end) -+{ -+ unsigned int len; -+ int val; -+ -+ if (tag == Tag_GNU_S390_ABI_Vector) -+ { -+ val = read_uleb128 (p, &len, end); -+ p += len; -+ printf (" Tag_GNU_S390_ABI_Vector: "); -+ -+ switch (val) -+ { -+ case 0: -+ printf (_("any\n")); -+ break; -+ case 1: -+ printf (_("software\n")); -+ break; -+ case 2: -+ printf (_("hardware\n")); -+ break; -+ default: -+ printf ("??? (%d)\n", val); -+ break; -+ } -+ return p; -+ } -+ -+ return display_tag_value (tag & 1, p, end); -+} -+ - static void - display_sparc_hwcaps (int mask) - { -@@ -13233,6 +13268,13 @@ process_power_specific (FILE * file) - } - - static int -+process_s390_specific (FILE * file) -+{ -+ return process_attributes (file, NULL, SHT_GNU_ATTRIBUTES, NULL, -+ display_s390_gnu_attribute); -+} -+ -+static int - process_sparc_specific (FILE * file) - { - return process_attributes (file, NULL, SHT_GNU_ATTRIBUTES, NULL, -@@ -15046,6 +15088,10 @@ process_arch_specific (FILE * file) - case EM_PPC: - return process_power_specific (file); - break; -+ case EM_S390: -+ case EM_S390_OLD: -+ return process_s390_specific (file); -+ break; - case EM_SPARC: - case EM_SPARC32PLUS: - case EM_SPARCV9: -Index: binutils-2.25.0/gas/doc/as.texinfo -=================================================================== ---- binutils-2.25.0.orig/gas/doc/as.texinfo 2015-07-09 16:44:51.000000000 +0200 -+++ binutils-2.25.0/gas/doc/as.texinfo 2015-07-09 16:44:51.000000000 +0200 -@@ -7086,6 +7086,22 @@ The vector ABI used by this object file. - @end itemize - @end table - -+@subsection IBM z Systems Attributes -+ -+@table @r -+@item Tag_GNU_S390_ABI_Vector (8) -+The vector ABI used by this object file. The value will be: -+ -+@itemize @bullet -+@item -+0 for files not affected by the vector ABI. -+@item -+1 for files using software vector ABI. -+@item -+2 for files using hardware vector ABI. -+@end itemize -+@end table -+ - @node Defining New Object Attributes - @section Defining New Object Attributes - -Index: binutils-2.25.0/include/elf/s390.h -=================================================================== ---- binutils-2.25.0.orig/include/elf/s390.h 2015-01-15 09:57:57.000000000 +0100 -+++ binutils-2.25.0/include/elf/s390.h 2015-07-09 16:44:51.000000000 +0200 -@@ -129,6 +129,17 @@ START_RELOC_NUMBERS (elf_s390_reloc_type - RELOC_NUMBER (R_390_GNU_VTENTRY, 251) - END_RELOC_NUMBERS (R_390_max) - --#endif /* _ELF_390_H */ -+/* Object attribute tags. */ -+enum -+{ -+ /* 0-3 are generic. */ -+ /* 4 is reserved for the FP ABI. */ - -+ /* Vector ABI: -+ 0 = not affected by the vector ABI, or not tagged. -+ 1 = software vector ABI being used -+ 2 = hardware vector ABI being used. */ -+ Tag_GNU_S390_ABI_Vector = 8, -+}; - -+#endif /* _ELF_390_H */ diff --git a/binutils-2.25-branch.diff.gz b/binutils-2.25-branch.diff.gz deleted file mode 100644 index 273baf7..0000000 --- a/binutils-2.25-branch.diff.gz +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:673b157e24075bd7bcd25f1c010413989808e9ceb689050d64cb63f516af011c -size 204790 diff --git a/binutils-2.25.0.tar.bz2 b/binutils-2.25.0.tar.bz2 deleted file mode 100644 index 8f0d3e8..0000000 --- a/binutils-2.25.0.tar.bz2 +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:a74c4dc2762c971df8ae09cdc4bcceba2167eb1c522d15532ba36292bf91b867 -size 25662100 diff --git a/binutils-2.26-branch.diff b/binutils-2.26-branch.diff new file mode 100644 index 0000000..a598523 --- /dev/null +++ b/binutils-2.26-branch.diff @@ -0,0 +1,5146 @@ +diff --git a/bfd/ChangeLog b/bfd/ChangeLog +index e860c3e..4dbc32f 100644 +--- a/bfd/ChangeLog ++++ b/bfd/ChangeLog +@@ -1,3 +1,81 @@ ++2016-02-26 H.J. Lu ++ ++ Backport from master ++ 2016-02-24 H.J. Lu ++ ++ PR ld/19698 ++ * elflink.c (bfd_elf_record_link_assignment): Set versioned if ++ symbol version is unknown. ++ ++2016-02-26 H.J. Lu ++ ++ Backport from master ++ 2016-02-01 H.J. Lu ++ ++ PR ld/19553 ++ * elflink.c (elf_link_add_object_symbols): Don't add DT_NEEDED ++ if a symbol from a library loaded via DT_NEEDED doesn't match ++ the symbol referenced by regular object. ++ ++2016-02-26 H.J. Lu ++ ++ Backport from master ++ 2016-02-24 H.J. Lu ++ ++ * elf32-i386.c (elf_i386_allocate_dynrelocs): Set plt_got.offset ++ to (bfd_vma) -1 when setting needs_plt to 0. ++ * elf64-x86-64.c (elf_x86_64_allocate_dynrelocs): Likewise. ++ ++2016-02-26 Alan Modra ++ ++ * elf64-ppc.c (create_linkage_sections): Create sfpr when ++ save_restore_funcs, rest of sections when not relocatable. ++ (ppc64_elf_init_stub_bfd): Always call create_linkage_sections. ++ (sfpr_define): Define all symbols on emitted code. ++ (ppc64_elf_func_desc_adjust): Adjust for sfpr now being created ++ when relocatable. Move sfpr_define loop earlier. ++ ++2016-02-25 Jiong Wang ++ ++ Backport from master ++ 2016-01-21 Jiong Wang ++ ++ * elfnn-aarch64.c (aarch64_type_of_stub): Allow insert long branch ++ veneer for sym_sec != input_sec. ++ (elfNN_aarch64_size_stub): Support STT_SECTION symbol. ++ (elfNN_aarch64_final_link_relocate): Take rela addend into account when ++ calculation destination. ++ ++2016-02-10 H.J. Lu ++ ++ Backport from master ++ 2016-02-10 H.J. Lu ++ ++ PR ld/19601 ++ * elf32-i386.c (elf_i386_relocate_section): Mask off the least ++ significant bit in GOT offset for R_386_GOT32X. ++ ++2016-02-02 H.J. Lu ++ ++ Backport from master ++ 2016-02-02 H.J. Lu ++ ++ PR ld/19542 ++ * elf64-x86-64.c (elf_x86_64_convert_load): Store the estimated ++ distances in the compressed_size field of the output section. ++ ++2016-02-01 John David Anglin ++ ++ PR ld/19526 ++ * elf32-hppa.c (elf32_hppa_final_link): Don't sort non-regular output ++ files. ++ * elf64-hppa.c (elf32_hppa_final_link): Likewise. Remove retval. ++ ++2016-01-25 Tristan Gingold ++ ++ * version.m4: Bump version to 2.26.0 ++ * configure: Regenerate. ++ + 2016-01-25 Tristan Gingold + + * version.m4: Bump version to 2.26 +@@ -119,7 +197,7 @@ + * configure: Regenerate. + + 2015-11-11 Alan Modra +- Peter Bergner ++ Peter Bergner + + * elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_REL16DX_HA. + (ppc_elf_reloc_type_lookup): Handle R_PPC_REL16DX_HA. +@@ -179,8 +257,8 @@ + + 2015-10-29 Catherine Moore + +- * elfxx-mips.c (mips_elf_check_mips16_stubs): Set a stub's output +- section to bfd_abs_section_ptr if the stub is discarded. ++ * elfxx-mips.c (mips_elf_check_mips16_stubs): Set a stub's output ++ section to bfd_abs_section_ptr if the stub is discarded. + + 2015-10-29 Ed Schouten + +@@ -232,7 +310,7 @@ + * bfd-in2.h: Regenerate. + + 2015-10-27 Laurent Alfonsi +- Christophe Monat ++ Christophe Monat + + * bfd-in2.h: Regenerate. + * bfd-in.h (bfd_arm_stm32l4xx_fix): New enum. Specify how +@@ -1225,115 +1303,115 @@ + + 2015-08-18 H.J. Lu + +- * bfd/aoutx.h: Replace shared, executable, relocatable and pie ++ * aoutx.h: Replace shared, executable, relocatable and pie + fields with bfd_link_executable, bfd_link_dll, + bfd_link_relocatable, bfd_link_pic and bfd_link_pie. +- * bfd/bout.c: Likewise. +- * bfd/coff-alpha.c: Likewise. +- * bfd/coff-arm.c: Likewise. +- * bfd/coff-i386.c: Likewise. +- * bfd/coff-i960.c: Likewise. +- * bfd/coff-m68k.c: Likewise. +- * bfd/coff-mcore.c: Likewise. +- * bfd/coff-mips.c: Likewise. +- * bfd/coff-ppc.c: Likewise. +- * bfd/coff-rs6000.c: Likewise. +- * bfd/coff-sh.c: Likewise. +- * bfd/coff-tic80.c: Likewise. +- * bfd/coff-x86_64.c: Likewise. +- * bfd/coff64-rs6000.c: Likewise. +- * bfd/coffgen.c: Likewise. +- * bfd/cofflink.c: Likewise. +- * bfd/ecoff.c: Likewise. +- * bfd/ecofflink.c: Likewise. +- * bfd/elf-bfd.h: Likewise. +- * bfd/elf-eh-frame.c: Likewise. +- * bfd/elf-ifunc.c: Likewise. +- * bfd/elf-m10200.c: Likewise. +- * bfd/elf-m10300.c: Likewise. +- * bfd/elf-s390-common.c: Likewise. +- * bfd/elf-vxworks.c: Likewise. +- * bfd/elf.c: Likewise. +- * bfd/elf32-arm.c: Likewise. +- * bfd/elf32-avr.c: Likewise. +- * bfd/elf32-bfin.c: Likewise. +- * bfd/elf32-cr16.c: Likewise. +- * bfd/elf32-cr16c.c: Likewise. +- * bfd/elf32-cris.c: Likewise. +- * bfd/elf32-crx.c: Likewise. +- * bfd/elf32-d10v.c: Likewise. +- * bfd/elf32-dlx.c: Likewise. +- * bfd/elf32-epiphany.c: Likewise. +- * bfd/elf32-fr30.c: Likewise. +- * bfd/elf32-frv.c: Likewise. +- * bfd/elf32-ft32.c: Likewise. +- * bfd/elf32-h8300.c: Likewise. +- * bfd/elf32-hppa.c: Likewise. +- * bfd/elf32-i370.c: Likewise. +- * bfd/elf32-i386.c: Likewise. +- * bfd/elf32-i860.c: Likewise. +- * bfd/elf32-ip2k.c: Likewise. +- * bfd/elf32-iq2000.c: Likewise. +- * bfd/elf32-lm32.c: Likewise. +- * bfd/elf32-m32c.c: Likewise. +- * bfd/elf32-m32r.c: Likewise. +- * bfd/elf32-m68hc11.c: Likewise. +- * bfd/elf32-m68hc1x.c: Likewise. +- * bfd/elf32-m68k.c: Likewise. +- * bfd/elf32-mcore.c: Likewise. +- * bfd/elf32-mep.c: Likewise. +- * bfd/elf32-metag.c: Likewise. +- * bfd/elf32-microblaze.c: Likewise. +- * bfd/elf32-moxie.c: Likewise. +- * bfd/elf32-msp430.c: Likewise. +- * bfd/elf32-mt.c: Likewise. +- * bfd/elf32-nds32.c: Likewise. +- * bfd/elf32-nios2.c: Likewise. +- * bfd/elf32-or1k.c: Likewise. +- * bfd/elf32-ppc.c: Likewise. +- * bfd/elf32-rl78.c: Likewise. +- * bfd/elf32-rx.c: Likewise. +- * bfd/elf32-s390.c: Likewise. +- * bfd/elf32-score.c: Likewise. +- * bfd/elf32-score7.c: Likewise. +- * bfd/elf32-sh-symbian.c: Likewise. +- * bfd/elf32-sh.c: Likewise. +- * bfd/elf32-sh64.c: Likewise. +- * bfd/elf32-spu.c: Likewise. +- * bfd/elf32-tic6x.c: Likewise. +- * bfd/elf32-tilepro.c: Likewise. +- * bfd/elf32-v850.c: Likewise. +- * bfd/elf32-vax.c: Likewise. +- * bfd/elf32-visium.c: Likewise. +- * bfd/elf32-xc16x.c: Likewise. +- * bfd/elf32-xstormy16.c: Likewise. +- * bfd/elf32-xtensa.c: Likewise. +- * bfd/elf64-alpha.c: Likewise. +- * bfd/elf64-hppa.c: Likewise. +- * bfd/elf64-ia64-vms.c: Likewise. +- * bfd/elf64-mmix.c: Likewise. +- * bfd/elf64-ppc.c: Likewise. +- * bfd/elf64-s390.c: Likewise. +- * bfd/elf64-sh64.c: Likewise. +- * bfd/elf64-x86-64.c: Likewise. +- * bfd/elflink.c: Likewise. +- * bfd/elfnn-aarch64.c: Likewise. +- * bfd/elfnn-ia64.c: Likewise. +- * bfd/elfxx-mips.c: Likewise. +- * bfd/elfxx-sparc.c: Likewise. +- * bfd/elfxx-tilegx.c: Likewise. +- * bfd/i386linux.c: Likewise. +- * bfd/linker.c: Likewise. +- * bfd/m68klinux.c: Likewise. +- * bfd/pdp11.c: Likewise. +- * bfd/pe-mips.c: Likewise. +- * bfd/peXXigen.c: Likewise. +- * bfd/reloc.c: Likewise. +- * bfd/reloc16.c: Likewise. +- * bfd/sparclinux.c: Likewise. +- * bfd/sunos.c: Likewise. +- * bfd/vms-alpha.c: Likewise. +- * bfd/xcofflink.c: Likewise. ++ * bout.c: Likewise. ++ * coff-alpha.c: Likewise. ++ * coff-arm.c: Likewise. ++ * coff-i386.c: Likewise. ++ * coff-i960.c: Likewise. ++ * coff-m68k.c: Likewise. ++ * coff-mcore.c: Likewise. ++ * coff-mips.c: Likewise. ++ * coff-ppc.c: Likewise. ++ * coff-rs6000.c: Likewise. ++ * coff-sh.c: Likewise. ++ * coff-tic80.c: Likewise. ++ * coff-x86_64.c: Likewise. ++ * coff64-rs6000.c: Likewise. ++ * coffgen.c: Likewise. ++ * cofflink.c: Likewise. ++ * ecoff.c: Likewise. ++ * ecofflink.c: Likewise. ++ * elf-bfd.h: Likewise. ++ * elf-eh-frame.c: Likewise. ++ * elf-ifunc.c: Likewise. ++ * elf-m10200.c: Likewise. ++ * elf-m10300.c: Likewise. ++ * elf-s390-common.c: Likewise. ++ * elf-vxworks.c: Likewise. ++ * elf.c: Likewise. ++ * elf32-arm.c: Likewise. ++ * elf32-avr.c: Likewise. ++ * elf32-bfin.c: Likewise. ++ * elf32-cr16.c: Likewise. ++ * elf32-cr16c.c: Likewise. ++ * elf32-cris.c: Likewise. ++ * elf32-crx.c: Likewise. ++ * elf32-d10v.c: Likewise. ++ * elf32-dlx.c: Likewise. ++ * elf32-epiphany.c: Likewise. ++ * elf32-fr30.c: Likewise. ++ * elf32-frv.c: Likewise. ++ * elf32-ft32.c: Likewise. ++ * elf32-h8300.c: Likewise. ++ * elf32-hppa.c: Likewise. ++ * elf32-i370.c: Likewise. ++ * elf32-i386.c: Likewise. ++ * elf32-i860.c: Likewise. ++ * elf32-ip2k.c: Likewise. ++ * elf32-iq2000.c: Likewise. ++ * elf32-lm32.c: Likewise. ++ * elf32-m32c.c: Likewise. ++ * elf32-m32r.c: Likewise. ++ * elf32-m68hc11.c: Likewise. ++ * elf32-m68hc1x.c: Likewise. ++ * elf32-m68k.c: Likewise. ++ * elf32-mcore.c: Likewise. ++ * elf32-mep.c: Likewise. ++ * elf32-metag.c: Likewise. ++ * elf32-microblaze.c: Likewise. ++ * elf32-moxie.c: Likewise. ++ * elf32-msp430.c: Likewise. ++ * elf32-mt.c: Likewise. ++ * elf32-nds32.c: Likewise. ++ * elf32-nios2.c: Likewise. ++ * elf32-or1k.c: Likewise. ++ * elf32-ppc.c: Likewise. ++ * elf32-rl78.c: Likewise. ++ * elf32-rx.c: Likewise. ++ * elf32-s390.c: Likewise. ++ * elf32-score.c: Likewise. ++ * elf32-score7.c: Likewise. ++ * elf32-sh-symbian.c: Likewise. ++ * elf32-sh.c: Likewise. ++ * elf32-sh64.c: Likewise. ++ * elf32-spu.c: Likewise. ++ * elf32-tic6x.c: Likewise. ++ * elf32-tilepro.c: Likewise. ++ * elf32-v850.c: Likewise. ++ * elf32-vax.c: Likewise. ++ * elf32-visium.c: Likewise. ++ * elf32-xc16x.c: Likewise. ++ * elf32-xstormy16.c: Likewise. ++ * elf32-xtensa.c: Likewise. ++ * elf64-alpha.c: Likewise. ++ * elf64-hppa.c: Likewise. ++ * elf64-ia64-vms.c: Likewise. ++ * elf64-mmix.c: Likewise. ++ * elf64-ppc.c: Likewise. ++ * elf64-s390.c: Likewise. ++ * elf64-sh64.c: Likewise. ++ * elf64-x86-64.c: Likewise. ++ * elflink.c: Likewise. ++ * elfnn-aarch64.c: Likewise. ++ * elfnn-ia64.c: Likewise. ++ * elfxx-mips.c: Likewise. ++ * elfxx-sparc.c: Likewise. ++ * elfxx-tilegx.c: Likewise. ++ * i386linux.c: Likewise. ++ * linker.c: Likewise. ++ * m68klinux.c: Likewise. ++ * pdp11.c: Likewise. ++ * pe-mips.c: Likewise. ++ * peXXigen.c: Likewise. ++ * reloc.c: Likewise. ++ * reloc16.c: Likewise. ++ * sparclinux.c: Likewise. ++ * sunos.c: Likewise. ++ * vms-alpha.c: Likewise. ++ * xcofflink.c: Likewise. + + 2015-08-18 Alan Modra + +@@ -1387,7 +1465,7 @@ + + 2015-08-11 Jiong Wang + +- * bfd/elfnn-aarch64.c (aarch64_type_of_stub): New parameter "sym_sec". ++ * elfnn-aarch64.c (aarch64_type_of_stub): New parameter "sym_sec". + Loose the check for symbol from ABS section. + (elfNN_aarch64_size_stubs): Pass sym_sec. + +@@ -1688,10 +1766,10 @@ + + 2015-07-10 H.J. Lu + +- PR binutils/18656 +- * bfd.c (bfd_convert_section_size): New function. +- (bfd_convert_section_contents): Likewise. +- * bfd-in2.h: Regenerated. ++ PR binutils/18656 ++ * bfd.c (bfd_convert_section_size): New function. ++ (bfd_convert_section_contents): Likewise. ++ * bfd-in2.h: Regenerated. + + 2015-07-09 Catherine Moore + +@@ -2004,7 +2082,6 @@ + Bernd Schmidt + Paul Brook + +- bfd/ + * bfd-in2.h: Regenerated. + * elf-bfd.h (DWARF2_EH_HDR, COMPACT_EH_HDR): Define. + (COMPACT_EH_CANT_UNWIND_OPCODE): Define. +@@ -2913,7 +2990,7 @@ + 2015-03-18 H.J. Lu + + * compress.c (bfd_compress_section_contents): Make it static. +- * bfd/bfd-in2.h: Regenerated. ++ * bfd-in2.h: Regenerated. + + 2015-03-18 Eric Youngdale + +@@ -3062,8 +3139,8 @@ + + 2015-02-27 Marcus Shawcroft + +- * bfd/bfd-in2.h: Regenerate. +- * bfd/libbfd.h: Regenerate. ++ * bfd-in2.h: Regenerate. ++ * libbfd.h: Regenerate. + + 2015-02-26 Marcus Shawcroft + +@@ -3534,7 +3611,7 @@ + is weak or pointer_equality_needed is FALSE. + + * elf32-arm.c (elf32_arm_finish_dynamic_symbol): Improve +- comment discussing why we clear st_value for some symbols. ++ comment discussing why we clear st_value for some symbols. + + 2015-02-02 Kuan-Lin Chen + +diff --git a/bfd/configure b/bfd/configure +index cf3c746..7411c6d 100755 +--- a/bfd/configure ++++ b/bfd/configure +@@ -1,6 +1,6 @@ + #! /bin/sh + # Guess values for system-dependent variables and create Makefiles. +-# Generated by GNU Autoconf 2.64 for bfd 2.26. ++# Generated by GNU Autoconf 2.64 for bfd 2.26.0. + # + # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, + # 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software +@@ -556,8 +556,8 @@ MAKEFLAGS= + # Identity of this package. + PACKAGE_NAME='bfd' + PACKAGE_TARNAME='bfd' +-PACKAGE_VERSION='2.26' +-PACKAGE_STRING='bfd 2.26' ++PACKAGE_VERSION='2.26.0' ++PACKAGE_STRING='bfd 2.26.0' + PACKAGE_BUGREPORT='' + PACKAGE_URL='' + +@@ -1351,7 +1351,7 @@ if test "$ac_init_help" = "long"; then + # Omit some internal or obsolete options to make the list less imposing. + # This message is too long to be a string in the A/UX 3.1 sh. + cat <<_ACEOF +-\`configure' configures bfd 2.26 to adapt to many kinds of systems. ++\`configure' configures bfd 2.26.0 to adapt to many kinds of systems. + + Usage: $0 [OPTION]... [VAR=VALUE]... + +@@ -1422,7 +1422,7 @@ fi + + if test -n "$ac_init_help"; then + case $ac_init_help in +- short | recursive ) echo "Configuration of bfd 2.26:";; ++ short | recursive ) echo "Configuration of bfd 2.26.0:";; + esac + cat <<\_ACEOF + +@@ -1543,7 +1543,7 @@ fi + test -n "$ac_init_help" && exit $ac_status + if $ac_init_version; then + cat <<\_ACEOF +-bfd configure 2.26 ++bfd configure 2.26.0 + generated by GNU Autoconf 2.64 + + Copyright (C) 2009 Free Software Foundation, Inc. +@@ -2185,7 +2185,7 @@ cat >config.log <<_ACEOF + This file contains any messages produced by compilers while + running configure, to aid debugging if configure makes a mistake. + +-It was created by bfd $as_me 2.26, which was ++It was created by bfd $as_me 2.26.0, which was + generated by GNU Autoconf 2.64. Invocation command line was + + $ $0 $@ +@@ -3993,7 +3993,7 @@ fi + + # Define the identity of the package. + PACKAGE='bfd' +- VERSION='2.26' ++ VERSION='2.26.0' + + + cat >>confdefs.h <<_ACEOF +@@ -16533,7 +16533,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + # report actual input values of CONFIG_FILES etc. instead of their + # values after options handling. + ac_log=" +-This file was extended by bfd $as_me 2.26, which was ++This file was extended by bfd $as_me 2.26.0, which was + generated by GNU Autoconf 2.64. Invocation command line was + + CONFIG_FILES = $CONFIG_FILES +@@ -16597,7 +16597,7 @@ Report bugs to the package provider." + _ACEOF + cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 + ac_cs_version="\\ +-bfd config.status 2.26 ++bfd config.status 2.26.0 + configured by $0, generated by GNU Autoconf 2.64, + with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" + +diff --git a/bfd/elf32-hppa.c b/bfd/elf32-hppa.c +index ad40914..3fc1f57 100644 +--- a/bfd/elf32-hppa.c ++++ b/bfd/elf32-hppa.c +@@ -3245,6 +3245,8 @@ tpoff (struct bfd_link_info *info, bfd_vma address) + static bfd_boolean + elf32_hppa_final_link (bfd *abfd, struct bfd_link_info *info) + { ++ struct stat buf; ++ + /* Invoke the regular ELF linker to do all the work. */ + if (!bfd_elf_final_link (abfd, info)) + return FALSE; +@@ -3254,6 +3256,13 @@ elf32_hppa_final_link (bfd *abfd, struct bfd_link_info *info) + if (bfd_link_relocatable (info)) + return TRUE; + ++ /* Do not attempt to sort non-regular files. This is here ++ especially for configure scripts and kernel builds which run ++ tests with "ld [...] -o /dev/null". */ ++ if (stat (abfd->filename, &buf) != 0 ++ || !S_ISREG(buf.st_mode)) ++ return TRUE; ++ + return elf_hppa_sort_unwind (abfd); + } + +diff --git a/bfd/elf32-i386.c b/bfd/elf32-i386.c +index 300839b..5d07c77 100644 +--- a/bfd/elf32-i386.c ++++ b/bfd/elf32-i386.c +@@ -2490,12 +2490,14 @@ elf_i386_allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf) + } + else + { ++ eh->plt_got.offset = (bfd_vma) -1; + h->plt.offset = (bfd_vma) -1; + h->needs_plt = 0; + } + } + else + { ++ eh->plt_got.offset = (bfd_vma) -1; + h->plt.offset = (bfd_vma) -1; + h->needs_plt = 0; + } +@@ -4016,10 +4018,12 @@ elf_i386_relocate_section (bfd *output_bfd, + + /* It is relative to .got.plt section. */ + if (h->got.offset != (bfd_vma) -1) +- /* Use GOT entry. */ ++ /* Use GOT entry. Mask off the least significant bit in ++ GOT offset which may be set by R_386_GOT32 processing ++ below. */ + relocation = (htab->elf.sgot->output_section->vma + + htab->elf.sgot->output_offset +- + h->got.offset - offplt); ++ + (h->got.offset & ~1) - offplt); + else + /* Use GOTPLT entry. */ + relocation = (h->plt.offset / plt_entry_size - 1 + 3) * 4; +diff --git a/bfd/elf64-hppa.c b/bfd/elf64-hppa.c +index 3b628b4..aa9cfd2 100644 +--- a/bfd/elf64-hppa.c ++++ b/bfd/elf64-hppa.c +@@ -2945,7 +2945,7 @@ elf_hppa_record_segment_addrs (bfd *abfd, + static bfd_boolean + elf_hppa_final_link (bfd *abfd, struct bfd_link_info *info) + { +- bfd_boolean retval; ++ struct stat buf; + struct elf64_hppa_link_hash_table *hppa_info = hppa_link_hash_table (info); + + if (hppa_info == NULL) +@@ -3029,7 +3029,8 @@ elf_hppa_final_link (bfd *abfd, struct bfd_link_info *info) + info); + + /* Invoke the regular ELF backend linker to do all the work. */ +- retval = bfd_elf_final_link (abfd, info); ++ if (!bfd_elf_final_link (abfd, info)) ++ return FALSE; + + elf_link_hash_traverse (elf_hash_table (info), + elf_hppa_remark_useless_dynamic_symbols, +@@ -3037,10 +3038,17 @@ elf_hppa_final_link (bfd *abfd, struct bfd_link_info *info) + + /* If we're producing a final executable, sort the contents of the + unwind section. */ +- if (retval && !bfd_link_relocatable (info)) +- retval = elf_hppa_sort_unwind (abfd); ++ if (bfd_link_relocatable (info)) ++ return TRUE; ++ ++ /* Do not attempt to sort non-regular files. This is here ++ especially for configure scripts and kernel builds which run ++ tests with "ld [...] -o /dev/null". */ ++ if (stat (abfd->filename, &buf) != 0 ++ || !S_ISREG(buf.st_mode)) ++ return TRUE; + +- return retval; ++ return elf_hppa_sort_unwind (abfd); + } + + /* Relocate the given INSN. VALUE should be the actual value we want +diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c +index 162862c..ffe23e6 100644 +--- a/bfd/elf64-ppc.c ++++ b/bfd/elf64-ppc.c +@@ -4344,14 +4344,20 @@ create_linkage_sections (bfd *dynobj, struct bfd_link_info *info) + + htab = ppc_hash_table (info); + +- /* Create .sfpr for code to save and restore fp regs. */ + flags = (SEC_ALLOC | SEC_LOAD | SEC_CODE | SEC_READONLY + | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED); +- htab->sfpr = bfd_make_section_anyway_with_flags (dynobj, ".sfpr", +- flags); +- if (htab->sfpr == NULL +- || ! bfd_set_section_alignment (dynobj, htab->sfpr, 2)) +- return FALSE; ++ if (htab->params->save_restore_funcs) ++ { ++ /* Create .sfpr for code to save and restore fp regs. */ ++ htab->sfpr = bfd_make_section_anyway_with_flags (dynobj, ".sfpr", ++ flags); ++ if (htab->sfpr == NULL ++ || ! bfd_set_section_alignment (dynobj, htab->sfpr, 2)) ++ return FALSE; ++ } ++ ++ if (bfd_link_relocatable (info)) ++ return TRUE; + + /* Create .glink for lazy dynamic linking support. */ + htab->glink = bfd_make_section_anyway_with_flags (dynobj, ".glink", +@@ -4429,9 +4435,6 @@ ppc64_elf_init_stub_bfd (struct bfd_link_info *info, + htab->elf.dynobj = params->stub_bfd; + htab->params = params; + +- if (bfd_link_relocatable (info)) +- return TRUE; +- + return create_linkage_sections (htab->elf.dynobj, info); + } + +@@ -6665,7 +6668,7 @@ sfpr_define (struct bfd_link_info *info, + sym[len + 0] = i / 10 + '0'; + sym[len + 1] = i % 10 + '0'; + h = (struct ppc_link_hash_entry *) +- elf_link_hash_lookup (&htab->elf, sym, FALSE, FALSE, TRUE); ++ elf_link_hash_lookup (&htab->elf, sym, writing, TRUE, TRUE); + if (stub_sec != NULL) + { + if (h != NULL +@@ -6706,6 +6709,7 @@ sfpr_define (struct bfd_link_info *info, + h->elf.root.u.def.value = htab->sfpr->size; + h->elf.type = STT_FUNC; + h->elf.def_regular = 1; ++ h->elf.non_elf = 0; + _bfd_elf_link_hash_hide_symbol (info, &h->elf, TRUE); + writing = TRUE; + if (htab->sfpr->contents == NULL) +@@ -7050,14 +7054,28 @@ ppc64_elf_func_desc_adjust (bfd *obfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info) + { + struct ppc_link_hash_table *htab; +- unsigned int i; + + htab = ppc_hash_table (info); + if (htab == NULL) + return FALSE; + +- if (!bfd_link_relocatable (info) +- && htab->elf.hgot != NULL) ++ /* Provide any missing _save* and _rest* functions. */ ++ if (htab->sfpr != NULL) ++ { ++ unsigned int i; ++ ++ htab->sfpr->size = 0; ++ for (i = 0; i < ARRAY_SIZE (save_res_funcs); i++) ++ if (!sfpr_define (info, &save_res_funcs[i], NULL)) ++ return FALSE; ++ if (htab->sfpr->size == 0) ++ htab->sfpr->flags |= SEC_EXCLUDE; ++ } ++ ++ if (bfd_link_relocatable (info)) ++ return TRUE; ++ ++ if (htab->elf.hgot != NULL) + { + _bfd_elf_link_hash_hide_symbol (info, htab->elf.hgot, TRUE); + /* Make .TOC. defined so as to prevent it being made dynamic. +@@ -7076,22 +7094,8 @@ ppc64_elf_func_desc_adjust (bfd *obfd ATTRIBUTE_UNUSED, + | STV_HIDDEN); + } + +- if (htab->sfpr == NULL) +- /* We don't have any relocs. */ +- return TRUE; +- +- /* Provide any missing _save* and _rest* functions. */ +- htab->sfpr->size = 0; +- if (htab->params->save_restore_funcs) +- for (i = 0; i < ARRAY_SIZE (save_res_funcs); i++) +- if (!sfpr_define (info, &save_res_funcs[i], NULL)) +- return FALSE; +- + elf_link_hash_traverse (&htab->elf, func_desc_adjust, info); + +- if (htab->sfpr->size == 0) +- htab->sfpr->flags |= SEC_EXCLUDE; +- + return TRUE; + } + +diff --git a/bfd/elf64-x86-64.c b/bfd/elf64-x86-64.c +index 63957bb..bddcfe1 100644 +--- a/bfd/elf64-x86-64.c ++++ b/bfd/elf64-x86-64.c +@@ -2723,12 +2723,14 @@ elf_x86_64_allocate_dynrelocs (struct elf_link_hash_entry *h, void * inf) + } + else + { ++ eh->plt_got.offset = (bfd_vma) -1; + h->plt.offset = (bfd_vma) -1; + h->needs_plt = 0; + } + } + else + { ++ eh->plt_got.offset = (bfd_vma) -1; + h->plt.offset = (bfd_vma) -1; + h->needs_plt = 0; + } +@@ -3190,35 +3192,43 @@ elf_x86_64_convert_load (bfd *abfd, asection *sec, + } + else + { +- asection *asect; +- bfd_size_type size; ++ bfd_signed_vma distance; + + /* At this point, we don't know the load addresses of TSEC + section nor SEC section. We estimate the distrance between +- SEC and TSEC. */ +- size = 0; +- for (asect = sec->output_section; +- asect != NULL && asect != tsec->output_section; +- asect = asect->next) ++ SEC and TSEC. We store the estimated distances in the ++ compressed_size field of the output section, which is only ++ used to decompress the compressed input section. */ ++ if (sec->output_section->compressed_size == 0) + { +- asection *i; +- for (i = asect->output_section->map_head.s; +- i != NULL; +- i = i->map_head.s) ++ asection *asect; ++ bfd_size_type size = 0; ++ for (asect = link_info->output_bfd->sections; ++ asect != NULL; ++ asect = asect->next) + { +- size = align_power (size, i->alignment_power); +- size += i->size; ++ asection *i; ++ for (i = asect->map_head.s; ++ i != NULL; ++ i = i->map_head.s) ++ { ++ size = align_power (size, i->alignment_power); ++ size += i->size; ++ } ++ asect->compressed_size = size; + } + } + + /* Don't convert GOTPCREL relocations if TSEC isn't placed + after SEC. */ +- if (asect == NULL) ++ distance = (tsec->output_section->compressed_size ++ - sec->output_section->compressed_size); ++ if (distance < 0) + continue; + + /* Take PT_GNU_RELRO segment into account by adding + maxpagesize. */ +- if ((toff + size + maxpagesize - roff + 0x80000000) ++ if ((toff + distance + maxpagesize - roff + 0x80000000) + > 0xffffffff) + continue; + } +diff --git a/bfd/elflink.c b/bfd/elflink.c +index 3d37bb4..8fcaadd 100644 +--- a/bfd/elflink.c ++++ b/bfd/elflink.c +@@ -555,6 +555,19 @@ bfd_elf_record_link_assignment (bfd *output_bfd, + if (h == NULL) + return provide; + ++ if (h->versioned == unknown) ++ { ++ /* Set versioned if symbol version is unknown. */ ++ char *version = strrchr (name, ELF_VER_CHR); ++ if (version) ++ { ++ if (version > name && version[-1] != ELF_VER_CHR) ++ h->versioned = versioned_hidden; ++ else ++ h->versioned = versioned; ++ } ++ } ++ + switch (h->root.type) + { + case bfd_link_hash_defined: +@@ -4562,8 +4575,10 @@ error_free_dyn: + break; + } + +- /* Don't add DT_NEEDED for references from the dummy bfd. */ ++ /* Don't add DT_NEEDED for references from the dummy bfd nor ++ for unmatched symbol. */ + if (!add_needed ++ && matched + && definition + && ((dynsym + && h->ref_regular_nonweak +diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c +index 59c51cc..d83dc1b 100644 +--- a/bfd/elfnn-aarch64.c ++++ b/bfd/elfnn-aarch64.c +@@ -2655,7 +2655,7 @@ aarch64_type_of_stub (struct bfd_link_info *info, + bfd_boolean via_plt_p; + + if (st_type != STT_FUNC +- && (sym_sec != bfd_abs_section_ptr)) ++ && (sym_sec == input_sec)) + return stub_type; + + globals = elf_aarch64_hash_table (info); +@@ -4174,7 +4174,7 @@ elfNN_aarch64_size_stubs (bfd *output_bfd, + goto error_ret_free_internal; + } + +- stub_entry->target_value = sym_value; ++ stub_entry->target_value = sym_value + irela->r_addend; + stub_entry->target_section = sym_sec; + stub_entry->stub_type = stub_type; + stub_entry->h = hash; +@@ -5280,15 +5280,28 @@ elfNN_aarch64_final_link_relocate (reloc_howto_type *howto, + /* Check if a stub has to be inserted because the destination + is too far away. */ + struct elf_aarch64_stub_hash_entry *stub_entry = NULL; +- if (! aarch64_valid_branch_p (value, place)) ++ ++ /* If the branch destination is directed to plt stub, "value" will be ++ the final destination, otherwise we should plus signed_addend, it may ++ contain non-zero value, for example call to local function symbol ++ which are turned into "sec_sym + sec_off", and sec_off is kept in ++ signed_addend. */ ++ if (! aarch64_valid_branch_p (via_plt_p ? value : value + signed_addend, ++ place)) + /* The target is out of reach, so redirect the branch to + the local stub for this function. */ + stub_entry = elfNN_aarch64_get_stub_entry (input_section, sym_sec, h, + rel, globals); + if (stub_entry != NULL) +- value = (stub_entry->stub_offset +- + stub_entry->stub_sec->output_offset +- + stub_entry->stub_sec->output_section->vma); ++ { ++ value = (stub_entry->stub_offset ++ + stub_entry->stub_sec->output_offset ++ + stub_entry->stub_sec->output_section->vma); ++ ++ /* We have redirected the destination to stub entry address, ++ so ignore any addend record in the original rela entry. */ ++ signed_addend = 0; ++ } + } + value = _bfd_aarch64_elf_resolve_relocation (bfd_r_type, place, value, + signed_addend, weak_undef_p); +diff --git a/bfd/version.h b/bfd/version.h +index ed51cc9..cd412b9 100644 +--- a/bfd/version.h ++++ b/bfd/version.h +@@ -1,4 +1,4 @@ +-#define BFD_VERSION_DATE 20160125 ++#define BFD_VERSION_DATE 20160229 + #define BFD_VERSION @bfd_version@ + #define BFD_VERSION_STRING @bfd_version_package@ @bfd_version_string@ + #define REPORT_BUGS_TO @report_bugs_to@ +diff --git a/bfd/version.m4 b/bfd/version.m4 +index 9fb81c5..607d328 100644 +--- a/bfd/version.m4 ++++ b/bfd/version.m4 +@@ -1 +1 @@ +-m4_define([BFD_VERSION], [2.26]) ++m4_define([BFD_VERSION], [2.26.0]) +diff --git a/binutils/ChangeLog b/binutils/ChangeLog +index 2250b30..4648d93 100644 +--- a/binutils/ChangeLog ++++ b/binutils/ChangeLog +@@ -1,3 +1,14 @@ ++2016-02-12 H.J. Lu ++ ++ Backport from master ++ 2016-02-12 H.J. Lu ++ ++ * doc/binutils.texi: Fix a typo. ++ ++2016-01-25 Tristan Gingold ++ ++ * configure: Regenerate. ++ + 2016-01-25 Tristan Gingold + + * configure: Regenerate. +@@ -238,12 +249,12 @@ + + 2015-07-10 H.J. Lu + +- PR binutils/18656 +- * objcopy.c (setup_section): Call bfd_convert_section_size +- to get the output section size. +- (copy_section): Get the section size from the output section +- and call bfd_get_full_section_contents to convert section +- contents for output. ++ PR binutils/18656 ++ * objcopy.c (setup_section): Call bfd_convert_section_size ++ to get the output section size. ++ (copy_section): Get the section size from the output section ++ and call bfd_get_full_section_contents to convert section ++ contents for output. + + 2015-07-10 H.J. Lu + +diff --git a/binutils/configure b/binutils/configure +index 6e1f21e..d4f3e1e 100755 +--- a/binutils/configure ++++ b/binutils/configure +@@ -1,6 +1,6 @@ + #! /bin/sh + # Guess values for system-dependent variables and create Makefiles. +-# Generated by GNU Autoconf 2.64 for binutils 2.26. ++# Generated by GNU Autoconf 2.64 for binutils 2.26.0. + # + # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, + # 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software +@@ -556,8 +556,8 @@ MAKEFLAGS= + # Identity of this package. + PACKAGE_NAME='binutils' + PACKAGE_TARNAME='binutils' +-PACKAGE_VERSION='2.26' +-PACKAGE_STRING='binutils 2.26' ++PACKAGE_VERSION='2.26.0' ++PACKAGE_STRING='binutils 2.26.0' + PACKAGE_BUGREPORT='' + PACKAGE_URL='' + +@@ -1335,7 +1335,7 @@ if test "$ac_init_help" = "long"; then + # Omit some internal or obsolete options to make the list less imposing. + # This message is too long to be a string in the A/UX 3.1 sh. + cat <<_ACEOF +-\`configure' configures binutils 2.26 to adapt to many kinds of systems. ++\`configure' configures binutils 2.26.0 to adapt to many kinds of systems. + + Usage: $0 [OPTION]... [VAR=VALUE]... + +@@ -1406,7 +1406,7 @@ fi + + if test -n "$ac_init_help"; then + case $ac_init_help in +- short | recursive ) echo "Configuration of binutils 2.26:";; ++ short | recursive ) echo "Configuration of binutils 2.26.0:";; + esac + cat <<\_ACEOF + +@@ -1527,7 +1527,7 @@ fi + test -n "$ac_init_help" && exit $ac_status + if $ac_init_version; then + cat <<\_ACEOF +-binutils configure 2.26 ++binutils configure 2.26.0 + generated by GNU Autoconf 2.64 + + Copyright (C) 2009 Free Software Foundation, Inc. +@@ -2169,7 +2169,7 @@ cat >config.log <<_ACEOF + This file contains any messages produced by compilers while + running configure, to aid debugging if configure makes a mistake. + +-It was created by binutils $as_me 2.26, which was ++It was created by binutils $as_me 2.26.0, which was + generated by GNU Autoconf 2.64. Invocation command line was + + $ $0 $@ +@@ -3977,7 +3977,7 @@ fi + + # Define the identity of the package. + PACKAGE='binutils' +- VERSION='2.26' ++ VERSION='2.26.0' + + + cat >>confdefs.h <<_ACEOF +@@ -15142,7 +15142,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + # report actual input values of CONFIG_FILES etc. instead of their + # values after options handling. + ac_log=" +-This file was extended by binutils $as_me 2.26, which was ++This file was extended by binutils $as_me 2.26.0, which was + generated by GNU Autoconf 2.64. Invocation command line was + + CONFIG_FILES = $CONFIG_FILES +@@ -15206,7 +15206,7 @@ Report bugs to the package provider." + _ACEOF + cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 + ac_cs_version="\\ +-binutils config.status 2.26 ++binutils config.status 2.26.0 + configured by $0, generated by GNU Autoconf 2.64, + with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" + +diff --git a/binutils/doc/binutils.texi b/binutils/doc/binutils.texi +index 7dc09c3..2e424ef 100644 +--- a/binutils/doc/binutils.texi ++++ b/binutils/doc/binutils.texi +@@ -1872,7 +1872,7 @@ ELF ABI. Note - if compression would actually make a section + @itemx --compress-debug-sections=zlib-gabi + For ELF files, these options control how DWARF debug sections are + compressed. @option{--compress-debug-sections=none} is equivalent +-to @option{--nocompress-debug-sections}. ++to @option{--decompress-debug-sections}. + @option{--compress-debug-sections=zlib} and + @option{--compress-debug-sections=zlib-gabi} are equivalent to + @option{--compress-debug-sections}. +diff --git a/binutils/testsuite/ChangeLog b/binutils/testsuite/ChangeLog +index c579c69..52ddadc 100644 +--- a/binutils/testsuite/ChangeLog ++++ b/binutils/testsuite/ChangeLog +@@ -90,7 +90,7 @@ + + * binutils-all/localize-hidden-1.d: Allow for extra symbols in the + output. +- * binutils-all/strip-11.d: Skip for the RL78. ++ * binutils-all/strip-11.d: Skip for the RL78. + + 2015-07-14 H.J. Lu + +@@ -98,9 +98,9 @@ + + 2015-07-10 H.J. Lu + +- PR binutils/18656 +- * binutils-all/compress.exp (convert_test): New proc. +- Run conversion tests between x86-64 and x32. ++ PR binutils/18656 ++ * binutils-all/compress.exp (convert_test): New proc. ++ Run conversion tests between x86-64 and x32. + + 2015-07-10 H.J. Lu + +diff --git a/elfcpp/ChangeLog b/elfcpp/ChangeLog +index 0f54787..f95130a 100644 +--- a/elfcpp/ChangeLog ++++ b/elfcpp/ChangeLog +@@ -339,11 +339,11 @@ + + 2009-10-16 Doug Kwan + +- * elfcpp/elfcpp.h (DT_PREINIT_ARRAY): Correct enum value. ++ * elfcpp.h (DT_PREINIT_ARRAY): Correct enum value. + + 2009-10-09 Andrew Pinski + +- * elfcpp/elfcpp_file.h (Elf_file::section_name): Change shstr_size ++ * elfcpp_file.h (Elf_file::section_name): Change shstr_size + to Elf_WXword. + + 2009-10-09 Mikolaj Zalewski +diff --git a/gas/ChangeLog b/gas/ChangeLog +index 534a954..96a8822 100644 +--- a/gas/ChangeLog ++++ b/gas/ChangeLog +@@ -1,3 +1,70 @@ ++2016-02-20 H.J. Lu ++ ++ Backport from master ++ 2016-02-20 H.J. Lu ++ ++ * config/tc-i386.c (register_number): Check RegVRex. ++ * testsuite/gas/i386/x86-64-avx512f.s: Add a test for vgatherqpd ++ with %zmm19 and %zmm3. ++ * testsuite/gas/i386/x86-64-avx512f-intel.d: Updated. ++ * testsuite/gas/i386/x86-64-avx512f.d: Likewise. ++ ++2016-02-03 H.J. Lu ++ ++ Backport from master ++ 2016-02-03 H.J. Lu ++ ++ PR gas/19520 ++ * NEWS: Mention new command line option -mrelax-relocations and ++ new configure option --enable-x86-relax-relocations for x86 ++ target. ++ * config.in: Regenerated. ++ * configure.ac: Add --enable-x86-relax-relocations. ++ (ac_default_x86_relax_relocations): New. Default to 1 except ++ for x86 Solaris targets older than Solaris 12. ++ (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS): Define. ++ * configure: Likewise. ++ * config/tc-i386.c (generate_relax_relocations): New. ++ (OPTION_MRELAX_RELOCATIONS): Likewise. ++ (output_disp): Don't generate relax relocations if ++ generate_relax_relocations is 0. ++ (md_longopts): Add -mrelax-relocations. ++ (md_show_usage): Likewise. ++ (md_parse_option): Handle OPTION_MRELAX_RELOCATIONS. ++ * doc/c-i386.texi: Document -mrelax-relocations=. ++ * testsuite/gas/i386/got-no-relax.d: New file. ++ * testsuite/gas/i386/x86-64-gotpcrel-no-relax.d: Likewise. ++ * testsuite/gas/i386/got.d: Pass -mrelax-relocations=yes to as. ++ * testsuite/gas/i386/localpic.d: Likewise. ++ * testsuite/gas/i386/mixed-mode-reloc32.d: Likewise. ++ * testsuite/gas/i386/reloc32.d: Likewise. ++ * testsuite/gas/i386/x86-64-gotpcrel.d: Likewise. ++ * testsuite/gas/i386/x86-64-localpic.d: Likewise. ++ * testsuite/gas/i386/ilp32/x86-64-gotpcrel.d: Likewise. ++ * testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise. ++ * testsuite/gas/i386/i386.exp: Run got-no-relax and ++ x86-64-gotpcrel-no-relax. ++ ++2016-02-03 H.J. Lu ++ ++ Backport from master ++ 2016-02-03 H.J. Lu ++ ++ * NEWS: Remove duplicated marker for 2.26. ++ ++2016-01-29 H.J. Lu ++ ++ Backport from master ++ 2016-01-29 H.J. Lu ++ ++ PR gas/19532 ++ * configure.ac (compressed_debug_sections): Replace == with =. ++ * configure: Regenerated. ++ ++2016-01-25 Tristan Gingold ++ ++ * configure: Regenerate. ++ + 2016-01-25 Tristan Gingold + + * configure: Regenerate. +@@ -8,12 +75,8 @@ + + 2015-12-17 Ramana Radhakrishnan + +- * gas/config/tc-arm.c (aeabi_set_public_attributes): Adjust ++ * config/tc-arm.c (aeabi_set_public_attributes): Adjust + TAG_ARCH_profile for armv8-a. +- * gas/testsuite/gas/arm/armv8a-automatic-hlt.d: New test. +- * gas/testsuite/gas/arm/armv8a-automatic-hlt.s: New test. +- * gas/testsuite/gas/arm/armv8a-automatic-lda.d: New test. +- * gas/testsuite/gas/arm/armv8a-automatic-lda.s: New test. + + 2015-12-15 Nick Clifton + +@@ -320,10 +383,10 @@ + + 2015-10-07 Claudiu Zissulescu + +- * config/tc-arc.c: Revamped file for ARC support. +- * config/tc-arc.h: Likewise. +- * doc/as.texinfo: Add new ARC options. +- * doc/c-arc.texi: Likewise. ++ * config/tc-arc.c: Revamped file for ARC support. ++ * config/tc-arc.h: Likewise. ++ * doc/as.texinfo: Add new ARC options. ++ * doc/c-arc.texi: Likewise. + + 2015-10-02 Renlin Li + +@@ -572,9 +635,9 @@ + + 2015-08-17 Alan Modra + +- * gas/config/tc-arm.c (s_align): Delete. ++ * config/tc-arm.c (s_align): Delete. + (md_pseudo_table): Use s_align_ptwo for "align". +- * gas/config/tc-arm.h (TC_ALIGN_ZERO_IS_DEFAULT): Define. ++ * config/tc-arm.h (TC_ALIGN_ZERO_IS_DEFAULT): Define. + * read.c (s_align): Modify for TC_ALIGN_ZERO_IS_DEFAULT. + + 2015-08-13 Alan Modra +@@ -952,7 +1015,7 @@ + 2015-06-11 John David Anglin + + PR gas/18427 +- * gas/config/tc-hppa.c (last_label_symbol): Declare. ++ * config/tc-hppa.c (last_label_symbol): Declare. + (pa_get_label): Return last label in current space/segment or NULL. + (pa_define_label): Record last label and add to root. + (pa_undefine_label): Remove last label from root. +@@ -1028,7 +1091,6 @@ + Bernd Schmidt + Paul Brook + +- gas/ + * config/tc-alpha.c (all_cfi_sections): Declare. + (s_alpha_ent): Initialize all_cfi_sections. + (alpha_elf_md_end): Invoke cfi_set_sections. +@@ -1796,7 +1858,7 @@ + + 2015-01-12 Jan Beulich + +- * gas/dw2gencfi.c (cfi_add_label, dot_cfi_label): New. ++ * dw2gencfi.c (cfi_add_label, dot_cfi_label): New. + (cfi_pseudo_table): Add "cfi_label". + (output_cfi_insn): Handle CFI_label. + (select_cie_for_fde): Als terminate CIE when encountering +@@ -1809,7 +1871,7 @@ + + 2015-01-12 Jan Beulich + +- * gas/config/tc-arm.c (do_neon_shl_imm): Check immediate range. ++ * config/tc-arm.c (do_neon_shl_imm): Check immediate range. + (do_neon_qshl_imm): Likewise. + + 2015-01-12 Alan Modra +diff --git a/gas/NEWS b/gas/NEWS +index 2cb2fab..e20a073 100644 +--- a/gas/NEWS ++++ b/gas/NEWS +@@ -1,5 +1,12 @@ + -*- text -*- + ++* Add a configure option --enable-x86-relax-relocations to decide whether ++ x86 assembler should generate relax relocations by default. Default to ++ yes, except for x86 Solaris targets older than Solaris 12. ++ ++* New command line option -mrelax-relocations= for x86 target to control ++ whether to generate relax relocations. ++ + Changes in 2.26: + + * Add a configure option --enable-compressed-debug-sections={all,gas} to +@@ -8,8 +15,6 @@ Changes in 2.26: + * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + +-Changes in 2.26: +- + * Symbol and label names can now be enclosed in double quotes (") which allows + them to contain characters that are not part of valid symbol names in high + level languages. +diff --git a/gas/config.in b/gas/config.in +index 35c8202..8b040fc 100644 +--- a/gas/config.in ++++ b/gas/config.in +@@ -39,6 +39,9 @@ + /* Define if you want compressed debug sections by default. */ + #undef DEFAULT_FLAG_COMPRESS_DEBUG + ++/* Define to 1 if you want to generate x86 relax relocations by default. */ ++#undef DEFAULT_GENERATE_X86_RELAX_RELOCATIONS ++ + /* Supported emulations. */ + #undef EMULATIONS + +diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c +index 1573043..8676c5f 100644 +--- a/gas/config/tc-i386.c ++++ b/gas/config/tc-i386.c +@@ -552,6 +552,10 @@ static int allow_index_reg = 0; + specified explicitly. */ + static int omit_lock_prefix = 0; + ++/* 1 if the assembler should generate relax relocations. */ ++static int generate_relax_relocations ++ = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; ++ + static enum check_kind + { + check_none = 0, +@@ -1871,6 +1875,9 @@ register_number (const reg_entry *r) + if (r->reg_flags & RegRex) + nr += 8; + ++ if (r->reg_flags & RegVRex) ++ nr += 16; ++ + return nr; + } + +@@ -7241,9 +7248,14 @@ output_disp (fragS *insn_start_frag, offsetT insn_start_off) + /* Check for "call/jmp *mem", "mov mem, %reg", + "test %reg, mem" and "binop mem, %reg" where binop + is one of adc, add, and, cmp, or, sbb, sub, xor +- instructions. */ +- if ((i.rm.mode == 2 +- || (i.rm.mode == 0 && i.rm.regmem == 5)) ++ instructions. Always generate R_386_GOT32X for ++ "sym*GOT" operand in 32-bit mode. */ ++ if ((generate_relax_relocations ++ || (!object_64bit ++ && i.rm.mode == 0 ++ && i.rm.regmem == 5)) ++ && (i.rm.mode == 2 ++ || (i.rm.mode == 0 && i.rm.regmem == 5)) + && ((i.operands == 1 + && i.tm.base_opcode == 0xff + && (i.rm.reg == 2 || i.rm.reg == 4)) +@@ -9616,6 +9628,7 @@ const char *md_shortopts = "qn"; + #define OPTION_MSHARED (OPTION_MD_BASE + 21) + #define OPTION_MAMD64 (OPTION_MD_BASE + 22) + #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) ++#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 24) + + struct option md_longopts[] = + { +@@ -9647,6 +9660,7 @@ struct option md_longopts[] = + {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, + #endif + {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX}, ++ {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, + {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, + {"mamd64", no_argument, NULL, OPTION_MAMD64}, + {"mintel64", no_argument, NULL, OPTION_MINTEL64}, +@@ -9966,6 +9980,15 @@ md_parse_option (int c, char *arg) + as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); + break; + ++ case OPTION_MRELAX_RELOCATIONS: ++ if (strcasecmp (arg, "yes") == 0) ++ generate_relax_relocations = 1; ++ else if (strcasecmp (arg, "no") == 0) ++ generate_relax_relocations = 0; ++ else ++ as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); ++ break; ++ + case OPTION_MAMD64: + cpu_arch_flags.bitfield.cpuamd64 = 1; + cpu_arch_flags.bitfield.cpuintel64 = 0; +@@ -10146,6 +10169,9 @@ md_show_usage (FILE *stream) + -momit-lock-prefix=[no|yes]\n\ + strip all lock prefixes\n")); + fprintf (stream, _("\ ++ -mrelax-relocations=[no|yes]\n\ ++ generate relax relocations\n")); ++ fprintf (stream, _("\ + -mamd64 accept only AMD64 ISA\n")); + fprintf (stream, _("\ + -mintel64 accept only Intel64 ISA\n")); +diff --git a/gas/configure b/gas/configure +index f959e95..dd9c953 100755 +--- a/gas/configure ++++ b/gas/configure +@@ -1,6 +1,6 @@ + #! /bin/sh + # Guess values for system-dependent variables and create Makefiles. +-# Generated by GNU Autoconf 2.64 for gas 2.26. ++# Generated by GNU Autoconf 2.64 for gas 2.26.0. + # + # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, + # 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software +@@ -556,8 +556,8 @@ MAKEFLAGS= + # Identity of this package. + PACKAGE_NAME='gas' + PACKAGE_TARNAME='gas' +-PACKAGE_VERSION='2.26' +-PACKAGE_STRING='gas 2.26' ++PACKAGE_VERSION='2.26.0' ++PACKAGE_STRING='gas 2.26.0' + PACKAGE_BUGREPORT='' + PACKAGE_URL='' + +@@ -765,6 +765,7 @@ enable_largefile + enable_targets + enable_checking + enable_compressed_debug_sections ++enable_x86_relax_relocations + enable_werror + enable_build_warnings + enable_nls +@@ -1323,7 +1324,7 @@ if test "$ac_init_help" = "long"; then + # Omit some internal or obsolete options to make the list less imposing. + # This message is too long to be a string in the A/UX 3.1 sh. + cat <<_ACEOF +-\`configure' configures gas 2.26 to adapt to many kinds of systems. ++\`configure' configures gas 2.26.0 to adapt to many kinds of systems. + + Usage: $0 [OPTION]... [VAR=VALUE]... + +@@ -1394,7 +1395,7 @@ fi + + if test -n "$ac_init_help"; then + case $ac_init_help in +- short | recursive ) echo "Configuration of gas 2.26:";; ++ short | recursive ) echo "Configuration of gas 2.26.0:";; + esac + cat <<\_ACEOF + +@@ -1415,6 +1416,8 @@ Optional Features: + --enable-checking enable run-time checks + --enable-compressed-debug-sections={all,gas,none} + compress debug sections by default] ++ --enable-x86-relax-relocations ++ generate x86 relax relocations by default + --enable-werror treat compile warnings as errors + --enable-build-warnings enable build-time compiler warnings + --disable-nls do not use Native Language Support +@@ -1510,7 +1513,7 @@ fi + test -n "$ac_init_help" && exit $ac_status + if $ac_init_version; then + cat <<\_ACEOF +-gas configure 2.26 ++gas configure 2.26.0 + generated by GNU Autoconf 2.64 + + Copyright (C) 2009 Free Software Foundation, Inc. +@@ -1920,7 +1923,7 @@ cat >config.log <<_ACEOF + This file contains any messages produced by compilers while + running configure, to aid debugging if configure makes a mistake. + +-It was created by gas $as_me 2.26, which was ++It was created by gas $as_me 2.26.0, which was + generated by GNU Autoconf 2.64. Invocation command line was + + $ $0 $@ +@@ -3728,7 +3731,7 @@ fi + + # Define the identity of the package. + PACKAGE='gas' +- VERSION='2.26' ++ VERSION='2.26.0' + + + cat >>confdefs.h <<_ACEOF +@@ -10972,7 +10975,7 @@ else + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 10975 "configure" ++#line 10978 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -11078,7 +11081,7 @@ else + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 11081 "configure" ++#line 11084 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -11680,6 +11683,17 @@ if test "${enable_compressed_debug_sections+set}" = set; then : + esac + fi + ++# PR gas/19520 ++# Decide if x86 assembler should generate relax relocations. ++ac_default_x86_relax_relocations=unset ++# Provide a configure time option to override our default. ++# Check whether --enable-x86_relax_relocations was given. ++if test "${enable_x86_relax_relocations+set}" = set; then : ++ enableval=$enable_x86_relax_relocations; case "${enableval}" in ++ no) ac_default_x86_relax_relocations=0 ;; ++esac ++fi ++ + using_cgen=no + + +@@ -12085,6 +12099,17 @@ $as_echo "#define STRICTCOFF 1" >>confdefs.h + + ;; + ++ i386-*-solaris2 \ ++ | x86_64-*-solaris2 \ ++ | i386-*-solaris2.[0-9] \ ++ | i386-*-solaris2.1[01] \ ++ | x86_64-*-solaris2.1[01]) ++ if test ${this_target} = $target \ ++ && test ${ac_default_x86_relax_relocations} = unset; then ++ ac_default_x86_relax_relocations=0 ++ fi ++ ;; ++ + i860-*-*) + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: GAS support for ${generic_target} is preliminary and a work in progress" >&5 + $as_echo "$as_me: WARNING: GAS support for ${generic_target} is preliminary and a work in progress" >&2;} +@@ -12505,7 +12530,16 @@ _ACEOF + + done + +-if test x$ac_default_compressed_debug_sections == xyes ; then ++if test ${ac_default_x86_relax_relocations} = unset; then ++ ac_default_x86_relax_relocations=1 ++fi ++ ++cat >>confdefs.h <<_ACEOF ++#define DEFAULT_GENERATE_X86_RELAX_RELOCATIONS $ac_default_x86_relax_relocations ++_ACEOF ++ ++ ++if test x$ac_default_compressed_debug_sections = xyes ; then + + $as_echo "#define DEFAULT_FLAG_COMPRESS_DEBUG 1" >>confdefs.h + +@@ -15029,7 +15063,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + # report actual input values of CONFIG_FILES etc. instead of their + # values after options handling. + ac_log=" +-This file was extended by gas $as_me 2.26, which was ++This file was extended by gas $as_me 2.26.0, which was + generated by GNU Autoconf 2.64. Invocation command line was + + CONFIG_FILES = $CONFIG_FILES +@@ -15093,7 +15127,7 @@ Report bugs to the package provider." + _ACEOF + cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 + ac_cs_version="\\ +-gas config.status 2.26 ++gas config.status 2.26.0 + configured by $0, generated by GNU Autoconf 2.64, + with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" + +diff --git a/gas/configure.ac b/gas/configure.ac +index 07f825d..0e22593 100644 +--- a/gas/configure.ac ++++ b/gas/configure.ac +@@ -77,6 +77,17 @@ AC_ARG_ENABLE(compressed_debug_sections, + *) ac_default_compressed_debug_sections=unset ;; + esac])dnl + ++# PR gas/19520 ++# Decide if x86 assembler should generate relax relocations. ++ac_default_x86_relax_relocations=unset ++# Provide a configure time option to override our default. ++AC_ARG_ENABLE(x86_relax_relocations, ++ AS_HELP_STRING([--enable-x86-relax-relocations], ++ [generate x86 relax relocations by default]), ++[case "${enableval}" in ++ no) ac_default_x86_relax_relocations=0 ;; ++esac])dnl ++ + using_cgen=no + + AM_BINUTILS_WARNINGS +@@ -168,6 +179,17 @@ for this_target in $target $canon_targets ; do + AC_DEFINE(STRICTCOFF, 1, [Using strict COFF?]) + ;; + ++ i386-*-solaris2 \ ++ | x86_64-*-solaris2 \ ++ | i386-*-solaris2.[[0-9]] \ ++ | i386-*-solaris2.1[[01]] \ ++ | x86_64-*-solaris2.1[[01]]) ++ if test ${this_target} = $target \ ++ && test ${ac_default_x86_relax_relocations} = unset; then ++ ac_default_x86_relax_relocations=0 ++ fi ++ ;; ++ + i860-*-*) + AC_MSG_WARN(GAS support for ${generic_target} is preliminary and a work in progress) + ;; +@@ -549,7 +571,14 @@ changequote([,])dnl + + done + +-if test x$ac_default_compressed_debug_sections == xyes ; then ++if test ${ac_default_x86_relax_relocations} = unset; then ++ ac_default_x86_relax_relocations=1 ++fi ++AC_DEFINE_UNQUOTED(DEFAULT_GENERATE_X86_RELAX_RELOCATIONS, ++ $ac_default_x86_relax_relocations, ++ [Define to 1 if you want to generate x86 relax relocations by default.]) ++ ++if test x$ac_default_compressed_debug_sections = xyes ; then + AC_DEFINE(DEFAULT_FLAG_COMPRESS_DEBUG, 1, [Define if you want compressed debug sections by default.]) + fi + +diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi +index 4af05e3..7eb1fbc 100644 +--- a/gas/doc/c-i386.texi ++++ b/gas/doc/c-i386.texi +@@ -327,6 +327,18 @@ single-thread computers + @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual, + which is the default. + ++@cindex @samp{-mrelax-relocations=} option, i386 ++@cindex @samp{-mrelax-relocations=} option, x86-64 ++@item -mrelax-relocations=@var{no} ++@itemx -mrelax-relocations=@var{yes} ++These options control whether the assembler should generate relax ++relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and ++R_X86_64_REX_GOTPCRELX, in 64-bit mode. ++@option{-mrelax-relocations=@var{yes}} will generate relax relocations. ++@option{-mrelax-relocations=@var{no}} will not generate relax ++relocations. The default can be controlled by a configure option ++@option{--enable-x86-relax-relocations}. ++ + @cindex @samp{-mevexrcig=} option, i386 + @cindex @samp{-mevexrcig=} option, x86-64 + @item -mevexrcig=@var{rne} +diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog +index 4c86c8c..2c01d7b 100644 +--- a/gas/testsuite/ChangeLog ++++ b/gas/testsuite/ChangeLog +@@ -15,6 +15,13 @@ + * gas/arm/armv8-a.d: : Rename mismatched mnemonics ... + : ... to this. + ++2015-12-17 Ramana Radhakrishnan ++ ++ * gas/arm/armv8a-automatic-hlt.d: New test. ++ * gas/arm/armv8a-automatic-hlt.s: New test. ++ * gas/arm/armv8a-automatic-lda.d: New test. ++ * gas/arm/armv8a-automatic-lda.s: New test. ++ + 2015-12-15 Matthew Wahab + + * gas/aarch64/advsimd-fp16.d: Update expected output. +@@ -153,7 +160,7 @@ + Apply from master. + 2015-11-19 Alan Modra + * gas/ppc/altivec3.d: Allow for padding at end of section. +- * gas/testsuite/gas/ppc/power9.d: Likewise. ++ * gas/ppc/power9.d: Likewise. + + 2015-12-09 H.J. Lu + +@@ -207,8 +214,8 @@ + + 2015-10-28 Andre Vieira + +- * gas/arm/pinsn.s: New. +- * gas/arm/pinsn.d: Likewise. ++ * gas/arm/pinsn.s: New. ++ * gas/arm/pinsn.d: Likewise. + + 2015-10-27 Nick Clifton + +@@ -385,8 +392,8 @@ + + 2015-10-02 Renlin Li + +- * gas/aarch64/reloc-tlsgd_g0_nc.d: New. +- * gas/aarch64/reloc-tlsgd_g0_nc.s: New. ++ * gas/aarch64/reloc-tlsgd_g0_nc.d: New. ++ * gas/aarch64/reloc-tlsgd_g0_nc.s: New. + + 2015-10-02 Renlin Li + +@@ -958,9 +965,7 @@ + 2015-05-28 Catherine Moore + Bernd Schmidt + +- gas/testsuite/ + * gas/mips/mips.exp: Run new tests. +- + * gas/mips/compact-eh-1.s: New file. + * gas/mips/compact-eh-2.s: New file. + * gas/mips/compact-eh-3.s: New file. +diff --git a/gas/testsuite/gas/i386/got-no-relax.d b/gas/testsuite/gas/i386/got-no-relax.d +new file mode 100644 +index 0000000..6bf138a +--- /dev/null ++++ b/gas/testsuite/gas/i386/got-no-relax.d +@@ -0,0 +1,31 @@ ++#source: got.s ++#as: -mrelax-relocations=no ++#objdump: -dwr ++ ++.*: +file format .* ++ ++ ++Disassembly of section .text: ++ ++0+ <_start>: ++[ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax 1: R_386_GOT32 foo ++[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0,%eax 7: R_386_GOT32X foo ++[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%eax\),%eax d: R_386_GOT32 foo ++[ ]*[a-f0-9]+: 05 00 00 00 00 add \$0x0,%eax 12: R_386_GOT32 foo ++[ ]*[a-f0-9]+: 03 05 00 00 00 00 add 0x0,%eax 18: R_386_GOT32X foo ++[ ]*[a-f0-9]+: 03 80 00 00 00 00 add 0x0\(%eax\),%eax 1e: R_386_GOT32 foo ++[ ]*[a-f0-9]+: ff 15 00 00 00 00 call \*0x0 24: R_386_GOT32X foo ++[ ]*[a-f0-9]+: ff 90 00 00 00 00 call \*0x0\(%eax\) 2a: R_386_GOT32 foo ++[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0 30: R_386_GOT32X foo ++[ ]*[a-f0-9]+: ff a0 00 00 00 00 jmp \*0x0\(%eax\) 36: R_386_GOT32 foo ++[ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax 3b: R_386_GOT32 foo ++[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0,%eax 41: R_386_GOT32X foo ++[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%eax\),%eax 47: R_386_GOT32 foo ++[ ]*[a-f0-9]+: 05 00 00 00 00 add \$0x0,%eax 4c: R_386_GOT32 foo ++[ ]*[a-f0-9]+: 03 05 00 00 00 00 add 0x0,%eax 52: R_386_GOT32X foo ++[ ]*[a-f0-9]+: 03 80 00 00 00 00 add 0x0\(%eax\),%eax 58: R_386_GOT32 foo ++[ ]*[a-f0-9]+: ff 90 00 00 00 00 call \*0x0\(%eax\) 5e: R_386_GOT32 foo ++[ ]*[a-f0-9]+: ff 15 00 00 00 00 call \*0x0 64: R_386_GOT32X foo ++[ ]*[a-f0-9]+: ff a0 00 00 00 00 jmp \*0x0\(%eax\) 6a: R_386_GOT32 foo ++[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0 70: R_386_GOT32X foo ++#pass +diff --git a/gas/testsuite/gas/i386/got.d b/gas/testsuite/gas/i386/got.d +index f76ca47..7621cdf 100644 +--- a/gas/testsuite/gas/i386/got.d ++++ b/gas/testsuite/gas/i386/got.d +@@ -1,3 +1,4 @@ ++#as: -mrelax-relocations=yes + #objdump: -dwr + + .*: +file format .* +diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp +index d881cd8..9ad7a9e 100644 +--- a/gas/testsuite/gas/i386/i386.exp ++++ b/gas/testsuite/gas/i386/i386.exp +@@ -406,6 +406,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] + run_dump_test "relax-4" + + run_dump_test "got" ++ run_dump_test "got-no-relax" + + if {![istarget "*-*-nacl*"]} then { + run_dump_test "iamcu-1" +@@ -784,6 +785,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t + run_list_test "x86-64-branch-3" "-al -mintel64" + + run_dump_test "x86-64-gotpcrel" ++ run_dump_test "x86-64-gotpcrel-no-relax" + } + + set ASFLAGS "$old_ASFLAGS" +diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-gotpcrel.d b/gas/testsuite/gas/i386/ilp32/x86-64-gotpcrel.d +index e5a3b1c..1314e5b 100644 +--- a/gas/testsuite/gas/i386/ilp32/x86-64-gotpcrel.d ++++ b/gas/testsuite/gas/i386/ilp32/x86-64-gotpcrel.d +@@ -1,4 +1,5 @@ + #source: ../x86-64-gotpcrel.s ++#as: --x32 -mrelax-relocations=yes + #objdump: -dwr + #name: x86-64 (ILP32) gotpcrel + +diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-localpic.d b/gas/testsuite/gas/i386/ilp32/x86-64-localpic.d +index 0ca69c7..a9528a2 100644 +--- a/gas/testsuite/gas/i386/ilp32/x86-64-localpic.d ++++ b/gas/testsuite/gas/i386/ilp32/x86-64-localpic.d +@@ -1,4 +1,5 @@ + #source: ../x86-64-localpic.s ++#as: --x32 -mrelax-relocations=yes + #readelf: -rsW + #name: x86-64 (ILP32) local PIC + +diff --git a/gas/testsuite/gas/i386/localpic.d b/gas/testsuite/gas/i386/localpic.d +index 04fb5ce..0a5eec5 100644 +--- a/gas/testsuite/gas/i386/localpic.d ++++ b/gas/testsuite/gas/i386/localpic.d +@@ -1,3 +1,4 @@ ++#as: -mrelax-relocations=yes + #readelf: -rs + #name: i386 local PIC + +diff --git a/gas/testsuite/gas/i386/mixed-mode-reloc32.d b/gas/testsuite/gas/i386/mixed-mode-reloc32.d +index 9affc36..a2ef6a0 100644 +--- a/gas/testsuite/gas/i386/mixed-mode-reloc32.d ++++ b/gas/testsuite/gas/i386/mixed-mode-reloc32.d +@@ -1,3 +1,4 @@ ++#as: -mrelax-relocations=yes + #objdump: -r + #source: mixed-mode-reloc.s + #name: x86 mixed mode relocs (32-bit object) +diff --git a/gas/testsuite/gas/i386/reloc32.d b/gas/testsuite/gas/i386/reloc32.d +index 45c9cd2..b6e1bbd 100644 +--- a/gas/testsuite/gas/i386/reloc32.d ++++ b/gas/testsuite/gas/i386/reloc32.d +@@ -1,3 +1,4 @@ ++#as: -mrelax-relocations=yes + #objdump: -Drw + #name: i386 relocs + +diff --git a/gas/testsuite/gas/i386/x86-64-avx512f-intel.d b/gas/testsuite/gas/i386/x86-64-avx512f-intel.d +index c6bdbc5..ff2a3d1 100644 +--- a/gas/testsuite/gas/i386/x86-64-avx512f-intel.d ++++ b/gas/testsuite/gas/i386/x86-64-avx512f-intel.d +@@ -3666,6 +3666,7 @@ Disassembly of section .text: + [ ]*[a-f0-9]+: 62 02 fd 41 93 b4 fe 7b 00 00 00 vgatherqpd zmm30\{k1\},ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\] + [ ]*[a-f0-9]+: 62 02 fd 41 93 74 39 20 vgatherqpd zmm30\{k1\},ZMMWORD PTR \[r9\+zmm31\*1\+0x100\] + [ ]*[a-f0-9]+: 62 22 fd 41 93 b4 b9 00 04 00 00 vgatherqpd zmm30\{k1\},ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\] ++[ ]*[a-f0-9]+: 62 d2 fd 41 93 9c de 7b 00 00 00 vgatherqpd zmm3\{k1\},ZMMWORD PTR \[r14\+zmm19\*8\+0x7b\] + [ ]*[a-f0-9]+: 62 02 7d 41 93 b4 fe 7b 00 00 00 vgatherqps ymm30\{k1\},YMMWORD PTR \[r14\+zmm31\*8\+0x7b\] + [ ]*[a-f0-9]+: 62 02 7d 41 93 b4 fe 7b 00 00 00 vgatherqps ymm30\{k1\},YMMWORD PTR \[r14\+zmm31\*8\+0x7b\] + [ ]*[a-f0-9]+: 62 02 7d 41 93 74 39 40 vgatherqps ymm30\{k1\},YMMWORD PTR \[r9\+zmm31\*1\+0x100\] +@@ -10686,6 +10687,7 @@ Disassembly of section .text: + [ ]*[a-f0-9]+: 62 02 fd 41 93 b4 fe 85 ff ff ff vgatherqpd zmm30\{k1\},ZMMWORD PTR \[r14\+zmm31\*8-0x7b\] + [ ]*[a-f0-9]+: 62 02 fd 41 93 74 39 20 vgatherqpd zmm30\{k1\},ZMMWORD PTR \[r9\+zmm31\*1\+0x100\] + [ ]*[a-f0-9]+: 62 22 fd 41 93 b4 b9 00 04 00 00 vgatherqpd zmm30\{k1\},ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\] ++[ ]*[a-f0-9]+: 62 d2 fd 41 93 9c de 7b 00 00 00 vgatherqpd zmm3\{k1\},ZMMWORD PTR \[r14\+zmm19\*8\+0x7b\] + [ ]*[a-f0-9]+: 62 02 7d 41 93 b4 fe 85 ff ff ff vgatherqps ymm30\{k1\},YMMWORD PTR \[r14\+zmm31\*8-0x7b\] + [ ]*[a-f0-9]+: 62 02 7d 41 93 b4 fe 85 ff ff ff vgatherqps ymm30\{k1\},YMMWORD PTR \[r14\+zmm31\*8-0x7b\] + [ ]*[a-f0-9]+: 62 02 7d 41 93 74 39 40 vgatherqps ymm30\{k1\},YMMWORD PTR \[r9\+zmm31\*1\+0x100\] +diff --git a/gas/testsuite/gas/i386/x86-64-avx512f.d b/gas/testsuite/gas/i386/x86-64-avx512f.d +index d672fa5..2db0b3e 100644 +--- a/gas/testsuite/gas/i386/x86-64-avx512f.d ++++ b/gas/testsuite/gas/i386/x86-64-avx512f.d +@@ -3665,6 +3665,7 @@ Disassembly of section .text: + [ ]*[a-f0-9]+: 62 02 fd 41 93 b4 fe 7b 00 00 00 vgatherqpd 0x7b\(%r14,%zmm31,8\),%zmm30\{%k1\} + [ ]*[a-f0-9]+: 62 02 fd 41 93 74 39 20 vgatherqpd 0x100\(%r9,%zmm31,1\),%zmm30\{%k1\} + [ ]*[a-f0-9]+: 62 22 fd 41 93 b4 b9 00 04 00 00 vgatherqpd 0x400\(%rcx,%zmm31,4\),%zmm30\{%k1\} ++[ ]*[a-f0-9]+: 62 d2 fd 41 93 9c de 7b 00 00 00 vgatherqpd 0x7b\(%r14,%zmm19,8\),%zmm3\{%k1\} + [ ]*[a-f0-9]+: 62 02 7d 41 93 b4 fe 7b 00 00 00 vgatherqps 0x7b\(%r14,%zmm31,8\),%ymm30\{%k1\} + [ ]*[a-f0-9]+: 62 02 7d 41 93 b4 fe 7b 00 00 00 vgatherqps 0x7b\(%r14,%zmm31,8\),%ymm30\{%k1\} + [ ]*[a-f0-9]+: 62 02 7d 41 93 74 39 40 vgatherqps 0x100\(%r9,%zmm31,1\),%ymm30\{%k1\} +@@ -10685,6 +10686,7 @@ Disassembly of section .text: + [ ]*[a-f0-9]+: 62 02 fd 41 93 b4 fe 85 ff ff ff vgatherqpd -0x7b\(%r14,%zmm31,8\),%zmm30\{%k1\} + [ ]*[a-f0-9]+: 62 02 fd 41 93 74 39 20 vgatherqpd 0x100\(%r9,%zmm31,1\),%zmm30\{%k1\} + [ ]*[a-f0-9]+: 62 22 fd 41 93 b4 b9 00 04 00 00 vgatherqpd 0x400\(%rcx,%zmm31,4\),%zmm30\{%k1\} ++[ ]*[a-f0-9]+: 62 d2 fd 41 93 9c de 7b 00 00 00 vgatherqpd 0x7b\(%r14,%zmm19,8\),%zmm3\{%k1\} + [ ]*[a-f0-9]+: 62 02 7d 41 93 b4 fe 85 ff ff ff vgatherqps -0x7b\(%r14,%zmm31,8\),%ymm30\{%k1\} + [ ]*[a-f0-9]+: 62 02 7d 41 93 b4 fe 85 ff ff ff vgatherqps -0x7b\(%r14,%zmm31,8\),%ymm30\{%k1\} + [ ]*[a-f0-9]+: 62 02 7d 41 93 74 39 40 vgatherqps 0x100\(%r9,%zmm31,1\),%ymm30\{%k1\} +diff --git a/gas/testsuite/gas/i386/x86-64-avx512f.s b/gas/testsuite/gas/i386/x86-64-avx512f.s +index fa42326..e2cbb12 100644 +--- a/gas/testsuite/gas/i386/x86-64-avx512f.s ++++ b/gas/testsuite/gas/i386/x86-64-avx512f.s +@@ -3973,6 +3973,7 @@ _start: + vgatherqpd 123(%r14,%zmm31,8), %zmm30{%k1} # AVX512F + vgatherqpd 256(%r9,%zmm31), %zmm30{%k1} # AVX512F + vgatherqpd 1024(%rcx,%zmm31,4), %zmm30{%k1} # AVX512F ++ vgatherqpd 123(%r14,%zmm19,8), %zmm3{%k1} # AVX512F + + vgatherqps 123(%r14,%zmm31,8), %ymm30{%k1} # AVX512F + vgatherqps 123(%r14,%zmm31,8), %ymm30{%k1} # AVX512F +@@ -11630,6 +11631,7 @@ _start: + vgatherqpd zmm30{k1}, ZMMWORD PTR [r14+zmm31*8-123] # AVX512F + vgatherqpd zmm30{k1}, ZMMWORD PTR [r9+zmm31+256] # AVX512F + vgatherqpd zmm30{k1}, ZMMWORD PTR [rcx+zmm31*4+1024] # AVX512F ++ vgatherqpd zmm3{k1}, ZMMWORD PTR [r14+zmm19*8+123] # AVX512F + + vgatherqps ymm30{k1}, YMMWORD PTR [r14+zmm31*8-123] # AVX512F + vgatherqps ymm30{k1}, YMMWORD PTR [r14+zmm31*8-123] # AVX512F +diff --git a/gas/testsuite/gas/i386/x86-64-gotpcrel-no-relax.d b/gas/testsuite/gas/i386/x86-64-gotpcrel-no-relax.d +new file mode 100644 +index 0000000..a3f8943 +--- /dev/null ++++ b/gas/testsuite/gas/i386/x86-64-gotpcrel-no-relax.d +@@ -0,0 +1,27 @@ ++#source: x86-64-gotpcrel.s ++#as: -mrelax-relocations=no ++#objdump: -dwr ++ ++.*: +file format .* ++ ++ ++Disassembly of section .text: ++ ++0+ <_start>: ++[ ]*[a-f0-9]+: 48 c7 c0 00 00 00 00 mov \$0x0,%rax 3: R_X86_64_GOTPCREL foo ++[ ]*[a-f0-9]+: 48 8b 04 25 00 00 00 00 mov 0x0,%rax b: R_X86_64_GOTPCREL foo ++[ ]*[a-f0-9]+: 48 8b 05 00 00 00 00 mov 0x0\(%rip\),%rax # 16 <_start\+0x16> 12: R_X86_64_GOTPCREL foo-0x4 ++[ ]*[a-f0-9]+: 48 8b 81 00 00 00 00 mov 0x0\(%rcx\),%rax 19: R_X86_64_GOTPCREL foo ++[ ]*[a-f0-9]+: ff 15 00 00 00 00 callq \*0x0\(%rip\) # 23 <_start\+0x23> 1f: R_X86_64_GOTPCREL foo-0x4 ++[ ]*[a-f0-9]+: ff 90 00 00 00 00 callq \*0x0\(%rax\) 25: R_X86_64_GOTPCREL foo ++[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmpq \*0x0\(%rip\) # 2f <_start\+0x2f> 2b: R_X86_64_GOTPCREL foo-0x4 ++[ ]*[a-f0-9]+: ff a1 00 00 00 00 jmpq \*0x0\(%rcx\) 31: R_X86_64_GOTPCREL foo ++[ ]*[a-f0-9]+: 48 c7 c0 00 00 00 00 mov \$0x0,%rax 38: R_X86_64_GOTPCREL foo ++[ ]*[a-f0-9]+: 48 8b 04 25 00 00 00 00 mov 0x0,%rax 40: R_X86_64_GOTPCREL foo ++[ ]*[a-f0-9]+: 48 8b 05 00 00 00 00 mov 0x0\(%rip\),%rax # 4b <_start\+0x4b> 47: R_X86_64_GOTPCREL foo-0x4 ++[ ]*[a-f0-9]+: 48 8b 81 00 00 00 00 mov 0x0\(%rcx\),%rax 4e: R_X86_64_GOTPCREL foo ++[ ]*[a-f0-9]+: ff 15 00 00 00 00 callq \*0x0\(%rip\) # 58 <_start\+0x58> 54: R_X86_64_GOTPCREL foo-0x4 ++[ ]*[a-f0-9]+: ff 90 00 00 00 00 callq \*0x0\(%rax\) 5a: R_X86_64_GOTPCREL foo ++[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmpq \*0x0\(%rip\) # 64 <_start\+0x64> 60: R_X86_64_GOTPCREL foo-0x4 ++[ ]*[a-f0-9]+: ff a1 00 00 00 00 jmpq \*0x0\(%rcx\) 66: R_X86_64_GOTPCREL foo ++#pass +diff --git a/gas/testsuite/gas/i386/x86-64-gotpcrel.d b/gas/testsuite/gas/i386/x86-64-gotpcrel.d +index 6ca3fc7..fbe5e47 100644 +--- a/gas/testsuite/gas/i386/x86-64-gotpcrel.d ++++ b/gas/testsuite/gas/i386/x86-64-gotpcrel.d +@@ -1,3 +1,4 @@ ++#as: -mrelax-relocations=yes + #objdump: -dwr + + .*: +file format .* +diff --git a/gas/testsuite/gas/i386/x86-64-localpic.d b/gas/testsuite/gas/i386/x86-64-localpic.d +index 0a07149..bafaa9c 100644 +--- a/gas/testsuite/gas/i386/x86-64-localpic.d ++++ b/gas/testsuite/gas/i386/x86-64-localpic.d +@@ -1,3 +1,4 @@ ++#as: -mrelax-relocations=yes + #readelf: -rsW + #name: x86-64 local PIC + +diff --git a/gold/ChangeLog b/gold/ChangeLog +index b283a88..92b26ba 100644 +--- a/gold/ChangeLog ++++ b/gold/ChangeLog +@@ -33,7 +33,7 @@ + 2015-11-11 Alan Modra + Peter Bergner + +- * gold/powerpc.cc (Powerpc_relocate_functions::addr16_dq): New function. ++ * powerpc.cc (Powerpc_relocate_functions::addr16_dq): New function. + (Powerpc_relocate_functions::addr16dx_ha): Likewise. + (Target_powerpc::Scan::local): Handle R_POWERPC_REL16DX_HA. + (Target_powerpc::Scan::global): Likewise. +@@ -339,7 +339,7 @@ + 2015-07-26 Doug Kwan + + * testsuite/arm_unaligned_reloc.{s,sh}: Make test less sensitive to +- disassembler output format. ++ disassembler output format. + + 2015-07-23 Ian Coolidge + Plumb --pic-veneer option for gold. +@@ -566,7 +566,7 @@ + 2015-06-29 Doug Kwan + + * testsuite/arm_bl_out_of_range.s: Align stub table so that it appears +- at address expected by test. ++ at address expected by test. + * testsuite/arm_cortex_a8_b.s: Ditto. + * testsuite/arm_cortex_a8_b_cond.s: Ditto. + * testsuite/arm_cortex_a8_bl.s: Ditto. +@@ -940,7 +940,6 @@ + 2015-04-07 HC Yen + + Add AArch32 support for gold linker. +- gold/ + * arm.cc: Add V8 arch combine table. + + 2015-04-06 Rafael Ávila de Espíndola +@@ -1455,7 +1454,6 @@ + (Output_data_plt_arm::entry_count): Modified. + (Output_data_plt_arm::address_for_global): New method. + (Output_data_plt_arm::address_for_local): New method. +-gold/ + (Output_data_plt_arm::set_final_data_size): Add irelative_count_. + (Output_data_plt_arm::insert_irelative_data): New method. + (Output_data_plt_arm::irelative_rel_): New member. +@@ -2490,7 +2488,7 @@ gold/ + + Add .gdb_index version 7 support. + +- * gold/dwarf_reader.cc: include (for make_pair). ++ * dwarf_reader.cc: include (for make_pair). + (Dwarf_abbrev_table::do_read_abbrevs): Check for compressed + debug sections. + (Dwarf_ranges_table::read_ranges_table): Likewise. +@@ -2501,21 +2499,21 @@ gold/ + for end of list by offset, not by offset == 0. + (Dwarf_info_reader::do_read_string_table): Check for compressed + debug sections. +- * gold/dwarf_reader.h (Dwarf_pubnames_table::Dwarf_pubnames_table): ++ * dwarf_reader.h (Dwarf_pubnames_table::Dwarf_pubnames_table): + Initialize new data members. + (Dwarf_pubnames_table::next_name): return flag_byte. + (Dwarf_pubnames_table::end_of_table_): New data member. + (Dwarf_pubnames_table::is_gnu_style_): New data member. +- * gold/gdb-index.cc (gdb_index_version): Update to version 7. ++ * gdb-index.cc (gdb_index_version): Update to version 7. + (Gdb_index_info_reader::read_pubtable): Read flag_byte. + (Gdb_index_info_reader::read_pubnames_and_pubtypes): Don't + read skeleton type unit DIEs. + (Gdb_index::add_symbol): Add flag_byte; adjust all callers. + (Gdb_index::do_write): Write flag_byte. +- * gold/gdb-index.h (Gdb_index::add_symbol): Add flags parameter. ++ * gdb-index.h (Gdb_index::add_symbol): Add flags parameter. + (Gdb_index::Cu_vector): Store flags along with cu indexes. +- * gold/testsuite/gdb_index_test_3.sh: Allow versions 4-7. +- * gold/testsuite/gdb_index_test_comm.sh: Likewise. ++ * testsuite/gdb_index_test_3.sh: Allow versions 4-7. ++ * testsuite/gdb_index_test_comm.sh: Likewise. + + 2014-01-08 H.J. Lu + +@@ -5554,15 +5552,15 @@ gold/ + + 2012-01-03 Cary Coutant + +- * gold/incremental.cc (Sized_incremental_binary::do_process_got_plt): ++ * incremental.cc (Sized_incremental_binary::do_process_got_plt): + Use abstract base class for GOT. +- * gold/output.h (class Output_data_got_base): New abstract base class. ++ * output.h (class Output_data_got_base): New abstract base class. + (class Output_data_got): Derive from new base class, adjust ctors. + (Output_data_got::reserve_slot): Make virtual; rename to + do_reserve_slot; Adjust callers. +- * gold/target.h (Sized_target::init_got_plt_for_update): Return ++ * target.h (Sized_target::init_got_plt_for_update): Return + pointer to abstract base class. +- * gold/x86_64.cc (Target_x86_64::init_got_plt_for_update): Likewise. ++ * x86_64.cc (Target_x86_64::init_got_plt_for_update): Likewise. + + 2011-12-18 Ian Lance Taylor + +@@ -6073,10 +6071,10 @@ gold/ + + 2011-08-01 Cary Coutant + +- * gold/testsuite/Makefile.am (justsyms_exec): New testcase. +- * gold/testsuite/Makefile.in: Regenerate. +- * gold/testsuite/justsyms_exec.c: New source file. +- * gold/testsuite/justsyms_lib.c: New source file. ++ * testsuite/Makefile.am (justsyms_exec): New testcase. ++ * testsuite/Makefile.in: Regenerate. ++ * testsuite/justsyms_exec.c: New source file. ++ * testsuite/justsyms_lib.c: New source file. + + 2011-08-01 Cary Coutant + +@@ -6402,7 +6400,7 @@ gold/ + + 2011-07-06 Cary Coutant + +- * gold/incremental.cc ++ * incremental.cc + (Output_section_incremental_inputs::write_info_blocks): Check for + hidden and internal symbols. + +@@ -6943,9 +6941,9 @@ gold/ + 2011-06-09 Cary Coutant + + PR gold/12804 +- * gold/gold.cc (queue_initial_tasks): Warn if --incremental is ++ * gold.cc (queue_initial_tasks): Warn if --incremental is + used with --compress-debug-sections. +- * gold/object.cc (Sized_relobj_file::do_layout): Report ++ * object.cc (Sized_relobj_file::do_layout): Report + uncompressed size of compressed input sections. + + 2011-06-08 Cary Coutant +@@ -7073,10 +7071,10 @@ gold/ + 2011-06-02 Cary Coutant + + PR gold/12163 +- * gold/archive.cc (Archive::Archive): Initialize new data member. ++ * archive.cc (Archive::Archive): Initialize new data member. + (Archive::include_all_members): Return if archive has already been + included. +- * gold/archive.h (Archive::include_all_members_): New data member. ++ * archive.h (Archive::include_all_members_): New data member. + + 2011-06-02 Nick Clifton + +@@ -7593,9 +7591,9 @@ gold/ + + 2011-04-14 Cary Coutant + +- * gold/layout.cc (Layout::symtab_section_offset): New function. +- * gold/layout.h (Layout::symtab_section_offset): New function. +- * gold/reloc.cc (Sized_relobj::do_relocate): Call it. ++ * layout.cc (Layout::symtab_section_offset): New function. ++ * layout.h (Layout::symtab_section_offset): New function. ++ * reloc.cc (Sized_relobj::do_relocate): Call it. + + 2011-04-12 Ian Lance Taylor + +@@ -8706,7 +8704,7 @@ gold/ + + 2010-10-17 Doug Kwan + +- * gold/arm.cc (Target_arm::got_section): Use correct order and set ++ * arm.cc (Target_arm::got_section): Use correct order and set + GOT output section to be writable. + + 2010-10-14 Cary Coutant +@@ -8858,7 +8856,7 @@ gold/ + + 2010-09-30 Doug Kwan + +- * gold/testsuite/arm_branch_out_of_range.sh: Fix broken tests. ++ * testsuite/arm_branch_out_of_range.sh: Fix broken tests. + + 2010-09-28 Sriraman Tallam + +@@ -8902,13 +8900,13 @@ gold/ + + 2010-09-15 Doug Kwan + +- * gold/testsuite/script_test_3.t: Add ARM special sections. +- * gold/testsuite/script_test_4.t: Same. +- * gold/testsuite/script_test_5.t: Same. +- * gold/testsuite/script_test_6.t: Same. +- * gold/testsuite/script_test_7.t: Same. +- * gold/testsuite/script_test_7.t: Same. +- * gold/testsuite/thumb_blx_out_of_range.s: Fix instruction alignment. ++ * testsuite/script_test_3.t: Add ARM special sections. ++ * testsuite/script_test_4.t: Same. ++ * testsuite/script_test_5.t: Same. ++ * testsuite/script_test_6.t: Same. ++ * testsuite/script_test_7.t: Same. ++ * testsuite/script_test_7.t: Same. ++ * testsuite/thumb_blx_out_of_range.s: Fix instruction alignment. + + 2010-09-14 Cary Coutant + +@@ -9041,7 +9039,7 @@ gold/ + + 2010-08-27 Doug Kwan + +- * gold/resolve.cc (Symbol_table::should_override): Let a weak ++ * resolve.cc (Symbol_table::should_override): Let a weak + reference override an existing dynamic weak reference. + * testsuite/Makefile.am: Add new test dyn_weak_ref. + * testsuite/Makefile.in: Regenerate. +@@ -9133,11 +9131,11 @@ gold/ + 2010-08-19 Neil Vachharajani + Cary Coutant + +- * gold/archive.h (Add_lib_group_symbols): Add readsyms_blocker_, adjust ++ * archive.h (Add_lib_group_symbols): Add readsyms_blocker_, adjust + constructor, and set_blocker. +- * gold/archive.cc (Add_lib_group_symbols::is_runnable): Also check ++ * archive.cc (Add_lib_group_symbols::is_runnable): Also check + readsyms_blocker_. +- * gold/readsyms.cc (Read_symbols::do_lib_group): Also pass ++ * readsyms.cc (Read_symbols::do_lib_group): Also pass + this->this_blocker_ to Add_lib_group_symbols::set_blocker. + * testsuite/Makefile.am (start_lib_test): New test case. + * testsuite/Makefile.in: Regenerate. +@@ -9740,9 +9738,9 @@ gold/ + 2010-07-27 Jeffrey Yasskin + + * testsuite/debug_msg.sh: Test mixed weak/strong symbol behavior. +- * gold/testsuite/debug_msg.cc: Likewise. +- * gold/testsuite/odr_violation1.cc +- * gold/testsuite/odr_violation2.cc ++ * testsuite/debug_msg.cc: Likewise. ++ * testsuite/odr_violation1.cc ++ * testsuite/odr_violation2.cc + + 2010-07-21 Cary Coutant + +@@ -10087,13 +10085,13 @@ gold/ + 2010-05-26 Rafael Espindola + + PR 11604 +- * gold/object.cc(Sized_relobj::do_layout_deferred_sections): Avoid ++ * object.cc(Sized_relobj::do_layout_deferred_sections): Avoid + adding sections the garbage collector removed. +- * gold/testsuite/Makefile.am: Add test. +- * gold/testsuite/Makefile.in: Regenerate. +- * gold/testsuite/plugin_test_7.sh: New. +- * gold/testsuite/plugin_test_7_1.c: New. +- * gold/testsuite/plugin_test_7_2.c: New. ++ * testsuite/Makefile.am: Add test. ++ * testsuite/Makefile.in: Regenerate. ++ * testsuite/plugin_test_7.sh: New. ++ * testsuite/plugin_test_7_1.c: New. ++ * testsuite/plugin_test_7_2.c: New. + + 2010-05-26 Rafael Espindola + +@@ -10577,7 +10575,7 @@ gold/ + + 2010-03-25 Doug Kwan + +- * gold/arm.cc (Arm_exidx_fixup::update_offset_map): Rearrange code ++ * arm.cc (Arm_exidx_fixup::update_offset_map): Rearrange code + to avoid a conversion warning on a 32-bit host. + + 2010-03-24 Ian Lance Taylor +@@ -10781,7 +10779,7 @@ gold/ + + 2010-03-08 Doug Kwan + +- * gold/arm.cc (Arm_exidx_fixup::update_offset_map): Fix build breakage ++ * arm.cc (Arm_exidx_fixup::update_offset_map): Fix build breakage + due to a conversion warning. + (Arm_relobj::update_output_local_symbol_count): Check for local + symbol with unset output index. +@@ -11403,7 +11401,7 @@ gold/ + + 2010-01-29 Viktor Kutuzov + +- * gold/arm.cc: Added support for the ARM relocations: R_ARM_THM_PC8, ++ * arm.cc: Added support for the ARM relocations: R_ARM_THM_PC8, + R_ARM_THM_PC12, R_ARM_THM_ALU_PREL_11_0. + (Arm_relocate_functions::thm_alu11): New Method. + (Arm_relocate_functions::thm_pc8): New Method. +@@ -11553,12 +11551,12 @@ gold/ + + 2010-01-22 Viktor Kutuzov + +- * gold/arm.cc (Target_arm): Updated fix_v4bx method and usage of ++ * arm.cc (Target_arm): Updated fix_v4bx method and usage of + Fix_v4bx enum values . +- * gold/options.h (General_options): New option definitions. ++ * options.h (General_options): New option definitions. + (General_options::fix_v4bx): New method. + (General_options::Fix_v4bx): New enum. +- * gold/options.cc (General_options::parse_fix_v4bx): New method. ++ * options.cc (General_options::parse_fix_v4bx): New method. + (General_options::parse_fix_v4bx_interworking): New method. + + 2010-01-22 Doug Kwan +@@ -11618,7 +11616,7 @@ gold/ + + 2010-01-20 Viktor Kutuzov + +- * gold/arm.cc: Added support for R_ARM_V4BX relocation ++ * arm.cc: Added support for R_ARM_V4BX relocation + (class Arm_v4bx_stub): New class. + (DEF_STUBS): Updated definition to support v4_veneer_bx. + (Stub_factory::make_arm_v4bx_stub): New method. +@@ -12675,7 +12673,7 @@ gold/ + attributes_section and attributes_vendor. + * i386.cc (Target_i386::i386_info): Same. + * object.cc (Sized_relobj::do_layout): Skip attribute section. +- * gold/powerpc.cc (Target_powerpc::powerpc_info): Initialize new ++ * powerpc.cc (Target_powerpc::powerpc_info): Initialize new + fields attributes_section and attributes_vendor. + * sparc.cc (Target_sparc::sparc_info): Same. + * target.h (Target::attributes_section, Target::attributes_vendor, +@@ -13322,7 +13320,7 @@ gold/ + (Segment_start_expression::value): New method definition. + (script_exp_function_segment_start): Return a new + Segment_start_expression. +- * gold/script-c.h (script_saw_segment_start_expression): New function ++ * script-c.h (script_saw_segment_start_expression): New function + prototype. + * script-sections.cc (Script_sections::Script_sections): Initialize + SAW_SEGMENT_START_EXPRESSION_ to false. +@@ -14113,9 +14111,9 @@ gold/ + (Script_sections::attach_sections_using_phdrs_clause): Do not modify + segment list. + (Script_sections::release_segments): New method definition. +- * gold/script-sections.h (Script_sections::release_segments): New ++ * script-sections.h (Script_sections::release_segments): New + method declaration. +- * gold/target.h (Target::may_relax, Target::relax, ++ * target.h (Target::may_relax, Target::relax, + Target::do_may_relax, Target::do_relax): New method definitions. + + 2009-09-17 Viktor Kutuzov +@@ -14689,7 +14687,7 @@ gold/ + + 2009-06-03 Doug Kwan + +- * gold/arm.cc (namespace utils): New. ++ * arm.cc (namespace utils): New. + (Target_arm::reloc_is_non_pic): Define new method. + (class Arm_relocate_functions): New. + (Target_arm::Relocate::relocate): Handle relocation types used by +@@ -14701,7 +14699,7 @@ gold/ + + 2009-06-02 Doug Kwan + +- * gold/arm.cc (Target_arm::Scan::Scan): Initialize ++ * arm.cc (Target_arm::Scan::Scan): Initialize + issued_non_pic_error_. + (class Target_arm::Scan): Declare new method check_non_pic. + Define new method symbol_needs_plt_entry. +@@ -14722,7 +14720,7 @@ gold/ + + 2009-05-29 Doug Kwan + +- * gold/arm.cc (Output_data_plt_arm): Forward declaration for new ++ * arm.cc (Output_data_plt_arm): Forward declaration for new + template class. + (class Target_arm): Update comment. + (Target_arm::Target_arm): Initialize new data members GOT_, +diff --git a/gprof/ChangeLog b/gprof/ChangeLog +index 9fa2109..cb3b0c3 100644 +--- a/gprof/ChangeLog ++++ b/gprof/ChangeLog +@@ -2,6 +2,10 @@ + + * configure: Regenerate. + ++2016-01-25 Tristan Gingold ++ ++ * configure: Regenerate. ++ + 2015-11-13 Tristan Gingold + + * configure: Regenerate. +diff --git a/gprof/configure b/gprof/configure +index 8ea2c70..693b927 100755 +--- a/gprof/configure ++++ b/gprof/configure +@@ -1,6 +1,6 @@ + #! /bin/sh + # Guess values for system-dependent variables and create Makefiles. +-# Generated by GNU Autoconf 2.64 for gprof 2.26. ++# Generated by GNU Autoconf 2.64 for gprof 2.26.0. + # + # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, + # 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software +@@ -556,8 +556,8 @@ MAKEFLAGS= + # Identity of this package. + PACKAGE_NAME='gprof' + PACKAGE_TARNAME='gprof' +-PACKAGE_VERSION='2.26' +-PACKAGE_STRING='gprof 2.26' ++PACKAGE_VERSION='2.26.0' ++PACKAGE_STRING='gprof 2.26.0' + PACKAGE_BUGREPORT='' + PACKAGE_URL='' + +@@ -1299,7 +1299,7 @@ if test "$ac_init_help" = "long"; then + # Omit some internal or obsolete options to make the list less imposing. + # This message is too long to be a string in the A/UX 3.1 sh. + cat <<_ACEOF +-\`configure' configures gprof 2.26 to adapt to many kinds of systems. ++\`configure' configures gprof 2.26.0 to adapt to many kinds of systems. + + Usage: $0 [OPTION]... [VAR=VALUE]... + +@@ -1370,7 +1370,7 @@ fi + + if test -n "$ac_init_help"; then + case $ac_init_help in +- short | recursive ) echo "Configuration of gprof 2.26:";; ++ short | recursive ) echo "Configuration of gprof 2.26.0:";; + esac + cat <<\_ACEOF + +@@ -1476,7 +1476,7 @@ fi + test -n "$ac_init_help" && exit $ac_status + if $ac_init_version; then + cat <<\_ACEOF +-gprof configure 2.26 ++gprof configure 2.26.0 + generated by GNU Autoconf 2.64 + + Copyright (C) 2009 Free Software Foundation, Inc. +@@ -1841,7 +1841,7 @@ cat >config.log <<_ACEOF + This file contains any messages produced by compilers while + running configure, to aid debugging if configure makes a mistake. + +-It was created by gprof $as_me 2.26, which was ++It was created by gprof $as_me 2.26.0, which was + generated by GNU Autoconf 2.64. Invocation command line was + + $ $0 $@ +@@ -3649,7 +3649,7 @@ fi + + # Define the identity of the package. + PACKAGE='gprof' +- VERSION='2.26' ++ VERSION='2.26.0' + + + cat >>confdefs.h <<_ACEOF +@@ -12706,7 +12706,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + # report actual input values of CONFIG_FILES etc. instead of their + # values after options handling. + ac_log=" +-This file was extended by gprof $as_me 2.26, which was ++This file was extended by gprof $as_me 2.26.0, which was + generated by GNU Autoconf 2.64. Invocation command line was + + CONFIG_FILES = $CONFIG_FILES +@@ -12770,7 +12770,7 @@ Report bugs to the package provider." + _ACEOF + cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 + ac_cs_version="\\ +-gprof config.status 2.26 ++gprof config.status 2.26.0 + configured by $0, generated by GNU Autoconf 2.64, + with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" + +diff --git a/include/ChangeLog b/include/ChangeLog +index 01a25de..0ceba89 100644 +--- a/include/ChangeLog ++++ b/include/ChangeLog +@@ -30,10 +30,6 @@ + * dwarf2.def (DW_AT_GNU_numerator, DW_AT_GNU_denominator): New + attributes. + +-2015-09-26 James Bowman +- +- * opcode/ft32.h: Add instruction macros FT32_*() +- + 2015-09-20 Rich Felker + + * bfdlink.h (struct bfd_link_info): Add "nointerp" field. +@@ -55,7 +51,7 @@ + + 2015-08-18 H.J. Lu + +- * include/bfdlink.h (output_type): New enum. ++ * bfdlink.h (output_type): New enum. + (bfd_link_executable): New macro. + (bfd_link_dll): Likewise. + (bfd_link_relocatable): Likewise. +@@ -71,10 +67,6 @@ + + * ansidecl.h (GCC_FINAL): New macro. + +-2015-07-16 Jiong Wang +- +- * elf/aarch64.h (R_AARCH64_P32_TLSLD_ADR_PREL21): New enumeration. +- + 2015-07-14 H.J. Lu + + Sync with GCC +@@ -97,25 +89,12 @@ + PR target/65261 + * ansidecl.h (ATTRIBUTE_NO_SANITIZE_UNDEFINED): New macro. + +-2015-07-09 Catherine Moore +- +- * elf/mips/mips.h (Val_GNU_MIPS_ABI_FP_NAN2008): New. +- +-2015-07-08 Pitchumani Sivanupandi +- +- * elf/avr.h: Add new 32 bit PC relative relocation. +- +-2015-06-26 Matthew Fortune +- +- * elf/mips.h (DT_MIPS_RLD_MAP_REL): New macro. +- + 2015-06-22 Nick Clifton + + * dis-asm.h (struct disassemble_info): Add stop_vma field. + + 2015-05-28 Catherine Moore + +- include/ + * bfdlink.h: Rename eh_frame_hdr to eh_frame_hdr_type. + + 2015-05-22 Yunlian Jiang +@@ -123,10 +102,6 @@ + * libiberty.h (asprintf): Don't declare if HAVE_DECL_ASPRINTF is + not defined. + +-2015-05-12 Jiong Wang +- +- * elf/aarch64.h (R_AARCH64_P32_LD32_GOTPAGE_LO14): New enumeration. +- + 2015-05-01 H.J. Lu + + Merge with gcc: +@@ -160,11 +135,6 @@ + PR ld/pr17709 + * bfdlink.h (bfd_link_info): Add extern_protected_data. + +-2015-03-10 Matthew Wahab +- +- PR ld/16572 +- * elf/arm.h (EF_ARM_HASENTRY): Remove. +- + 2015-02-19 Pedro Alves + + * floatformat.h [__cplusplus]: Wrap in extern "C". +@@ -247,31 +217,14 @@ + PR debug/63239 + * dwarf2.def (DW_AT_GNU_deleted): New attribute. + +-2014-11-21 Terry Guo +- +- * opcode/arm.h (FPU_VFP_EXT_ARMV8xD): New macro. +- (FPU_VFP_V5D16): Likewise. +- (FPU_VFP_V5_SP_D16): Likewise. +- (FPU_ARCH_VFP_V5D16): Likewise. +- (FPU_ARCH_VFP_V5_SP_D16): Likewise. +- + 2014-11-18 Igor Zamyatin + + * bfdlink.h (struct bfd_link_info): Add bndplt. + +-2014-10-30 Andrew Pinski +- +- * elf/mips.h (AFL_EXT_OCTEON3): Define. +- INSN_OCTEON3, CPU_OCTEON3): Define. +- + 2014-10-28 Yury Gribov + + * libiberty.h (strtol, strtoul, strtoll, strtoull): New prototypes. + +-2014-10-22 Matthew Fortune +- +- * elf/mips.h (AFL_ASE_MASK): Define. +- + 2014-10-15 David Malcolm + + * libiberty.h (choose_tmpdir): New prototype. +@@ -303,28 +256,6 @@ + + * bfdlink.h (struct bfd_link_info): Add lto_plugin_active. + +-2014-07-29 Matthew Fortune +- +- * elf/mips.h (PT_MIPS_ABIFLAGS, SHT_MIPS_ABIFLAGS): Define. +- (Val_GNU_MIPS_ABI_FP_OLD_64): Rename from Val_GNU_MIPS_ABI_FP_64. +- (Val_GNU_MIPS_ABI_FP_64): Redefine. +- (Val_GNU_MIPS_ABI_FP_XX): Define. +- (Elf_External_ABIFlags_v0, Elf_Internal_ABIFlags_v0): New structures. +- (AFL_REG_NONE, AFL_REG_32, AFL_REG_64, AFL_REG_128): Define. +- (AFL_ASE_DSP, AFL_ASE_DSPR2, AFL_ASE_EVA, AFL_ASE_MCU): Likewise. +- (AFL_ASE_MDMX, AFL_ASE_MIPS3D, AFL_ASE_MT, AFL_ASE_SMARTMIPS): Likewise. +- (AFL_ASE_VIRT, AFL_ASE_MSA, AFL_ASE_MIPS16): Likewise. +- (AFL_ASE_MICROMIPS, AFL_ASE_XPA): Likewise. +- (AFL_EXT_XLR, AFL_EXT_OCTEON2, AFL_EXT_OCTEONP): Likewise. +- (AFL_EXT_LOONGSON_3A, AFL_EXT_OCTEON, AFL_EXT_5900): Likewise. +- (AFL_EXT_4650, AFL_EXT_4010, AFL_EXT_4100, AFL_EXT_3900): Likewise. +- (AFL_EXT_10000, AFL_EXT_SB1, AFL_EXT_4111, AFL_EXT_4120): Likewise. +- (AFL_EXT_5400, AFL_EXT_5500, AFL_EXT_LOONGSON_2E): Likewise. +- (AFL_EXT_LOONGSON_2F): Likewise. +- (bfd_mips_elf_swap_abiflags_v0_in): Prototype. +- (bfd_mips_elf_swap_abiflags_v0_out): Likewise. +- (bfd_mips_isa_ext): Likewise. +- + 2014-06-13 Alan Modra + + * bfdlink.h (struct bfd_link_hash_table): Add hash_table_free field. +@@ -340,20 +271,12 @@ + + 2014-05-01 Steve Ellcey + +- * include/longlong.h: Import latest version from GCC tree. +- +-2014-04-23 Andrew Bennett +- +- * opcode/mips.h (ASE_XPA): New define. ++ * longlong.h: Import latest version from GCC tree. + + 2014-04-22 Christian Svensson + + * dis-asm.h: Remove openrisc and or32 support. Add support for or1k. + +-2014-04-10 Senthil Kumar Selvaraj +- +- * elf/avr.h: Add new DIFF relocs. +- + 2014-03-05 Alan Modra + + Update copyright years. +@@ -386,11 +309,6 @@ + + * longlong.h: New file. + +-2013-11-11 Catherine Moore +- +- * opcode/mips.h (INSN_LOAD_MEMORY_DELAY): Rename to... +- (INSN_LOAD_MEMORY): ...this. +- + 2013-10-29 Marc Glisse + + PR tree-optimization/58689 +@@ -401,10 +319,6 @@ + xmalloc, xrealloc, xcalloc, xstrdup, xstrndup, xmemdup, pex_init): + Mark with attribute returns_nonnull. + +-2013-10-22 Sterling Augustine +- +- * gdb/gdb-index.h: Merge from gdb tree. +- + 2013-10-10 Sean Keys + + * xgate.h : Cleanup after opcode +@@ -424,31 +338,6 @@ + + * vtv-change-permission.h: New file. + +-2013-08-05 Eric Botcazou +- Konrad Eisele +- +- * opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_LEON. +- +-2013-06-08 Catherine Moore +- +- * opcode/mips.h (mips_opcode): Add ase field. +- (INSN_ASE_MASK): Delete. +- (INSN_DSP): Rename to ASE_DSP. Provide new value. +- (INSN_DSPR2): Rename to ASE_DSPR2. Provide new value. +- (INSN_MCU): Rename to ASE_MCU. Provide new value. +- (INSN_MDMX): Rename to ASE_MDMX. Provide new value. +- (INSN_MIPS3d): Rename to ASE_MIPS3D. Provide new value. +- (INSN_MT): Rename to ASE_MT. Provide new value. +- (INSN_SMARTMIPS): Rename to ASE_SMARTMIPS. Provide new value. +- (INSN_VIRT): Rename to ASE_VIRT. Provide new value. +- (INSN_VIRT64): Rename to ASE_VIRT64. Provide new value. +- (opcode_is_member): Add ase argument. Check ase. +- +-2013-05-06 Paul Brook +- +- include/elf/ +- * mips.h (R_MIPS_PC32): Update comment. +- + 2013-04-03 Jason Merrill + + Demangle C++11 ref-qualifier. +@@ -456,20 +345,6 @@ + DEMANGLE_COMPONENT_REFERENCE_THIS, + DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS. + +-2013-03-12 Sebastian Huber +- +- * opcode/nios2.h: Edit comment. +- +-2013-03-11 Sebastian Huber +- +- * opcode/nios2.h (OPX_WRPRS): New define. +- (OP_MATCH_WRPRS): Likewise. +- +-2013-03-11 Sebastian Huber +- +- * opcode/nios2.h (OP_RDPRS): New define. +- (OP_MATCH_RDPRS): Likewise. +- + 2013-03-01 Cary Coutant + + * dwarf2.h (enum dwarf_sect): New enum type. +@@ -516,12 +391,6 @@ + * fopen-bin.h: Likewise. + * fopen-same.h: Likewise. + * fopen-vms.h: Likewise. +- * aout/hppa.h: Likewise. +- * opcode/tahoe.h: Likewise. +- +-2012-12-11 Edgar E. Iglesias +- +- * elf/microblaze.h: Add TLS relocs to START_RELOC_NUMBERS + + 2012-11-09 Jason Merrill + +@@ -570,14 +439,6 @@ + PR other/54411 + * objalloc.h (objalloc_alloc): Do not use fast path on wraparound. + +-2012-09-27 Anthony Green +- +- * opcode/moxie.h (MOXIE_BAD): New define. +- +-2012-09-12 Chris Schlumberger-Socha +- +- * elf/aarch64.h (R_AARCH64_GOT_LD_PREL19): New reloc. +- + 2012-09-06 Cary Coutant + + * dwarf2.def: Edit comment. +@@ -592,30 +453,6 @@ + (tv_allow_unique_segment_for_sections): New member. + (tv_unique_segment_for_sections): New member. + +-2012-08-24 Matthew Gretton-Dann +- +- * opcode/arm.h (ARM_CPU_IS_ANY): New define. +- +-2012-08-24 Matthew Gretton-Dann +- +- * elf/arm.h (TAG_CPU_ARCH_V8): New define. +- (MAX_TAG_CPU_ARCH): Update. +- * opcode/arm.h (ARM_EXT_V8): New define. +- (FPU_VFP_EXT_ARMV8): Likewise. +- (FPU_NEON_EXT_ARMV8): Likewise. +- (FPU_CRYPTO_EXT_ARMV8): Likewise. +- (ARM_AEXT_V8A): Likewise. +- (FPU_VFP_ARMV8): Likwise. +- (FPU_NEON_ARMV8): Likewise. +- (FPU_CRYPTO_ARMV8): Likewise. +- (FPU_ARCH_VFP_ARMV8): Likewise. +- (FPU_ARCH_NEON_VFP_ARMV8): Likewise. +- (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8): Likewise. +- (ARM_ARCH_V8A): Likwise. +- (ARM_ARCH_V8A_FP): Likewise. +- (ARM_ARCH_V8A_SIMD): Likewise. +- (ARM_ARCH_V8A_CRYPTO): Likewise. +- + 2012-08-13 Ian Bolton + Laurent Desnogues + Jim MacArthur +@@ -631,10 +468,6 @@ + (print_aarch64_disassembler_options): New declaration. + (aarch64_symbol_is_valid): New declaration. + +-2012-08-02 Sean Keys +- +- * elf/m68hc11.h: #define E_M68HC11_NO_BANK_WARNING 0x000000200 +- + 2012-07-24 Stephan McCamant + Dr David Alan Gilbert + +@@ -646,15 +479,6 @@ + * filenames.h: #include "hashtab.h". + (filename_hash, filename_eq): Declare. + +-2012-07-13 Andreas Krebbel +- +- * elf/s390.h (START_RELOC_NUMBERS): Define R_390_IRELATIVE reloc. +- +-2012-07-05 Sean Keys +- +- * opcode/xgate.h: Changed the format string for mode +- XGATE_OP_DYA_MON. +- + 2012-06-18 Doug Evans + + * dwarf2.def (DW_OP): Add DW_OP_GNU_const_index. +@@ -724,11 +548,6 @@ + (get_DW_OP_name, get_DW_ATE_name): Declare. + * dwarf2.def: New file, from dwarf2.h. + +-2012-04-12 David S. Miller +- +- * elf/sparc.h (R_SPARC_WDISP10): New reloc. +- * opcode/sparc.h: Define '=' as generating R_SPARC_WDISP10. +- + 2012-04-10 Tristan Gingold + + * splay-tree.h: Conditionnaly includes stdint.h and inttypes.h +@@ -746,7 +565,7 @@ + + Add DWARF attribute value for the "Borland fastcall" calling + convention. +- * elf/dwarf2.h: Add DW_CC_GNU_borland_fastcall_i386 constant. ++ * dwarf2.h: Add DW_CC_GNU_borland_fastcall_i386 constant. + + 2012-01-31 H.J. Lu + +@@ -1049,14 +868,6 @@ + + * libiberty.h (setproctitle): Add prototype. + +-2010-09-29 Bernd Schmidt +- +- * opcode/tic6x-control-registers.h (tscl): Now read_write. +- +-2010-09-27 Andreas Krebbel +- +- * opcode/s390.h: Add S390_OPCODE_Z196 to enum s390_opcode_cpu_val. +- + 2010-09-23 Matthew Gretton-Dann + + * arm.h (ARM_EXT_V6Z): Remove. +@@ -1259,7 +1070,7 @@ + + 2009-10-15 Jakub Jelinek + +- * include/dwarf2.h (DW_LANG_Python): Add comment that it is ++ * dwarf2.h (DW_LANG_Python): Add comment that it is + a DWARF 4 addition. + + 2009-10-14 Alan Modra +@@ -1348,16 +1159,6 @@ + * bfdlink.h (struct bfd_link_hash_common_entry): Move to top + level. + +-2009-09-04 Jie Zhang +- +- * opcode/bfin.h (PseudoDbg_Assert): Add bits_grp and mask_grp. +- (PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask): Define. +- (PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, +- PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask): +- Adjust accordingly. +- (init_PseudoDbg_Assert): Add PseudoDbg_Assert_grp_bits and +- PseudoDbg_Assert_grp_mask. +- + 2009-08-06 Michael Eager + + * dis-asm.h: Decl print_insn_microblaze(). +@@ -1518,10 +1319,6 @@ + * demangle.h (enum demangle_component_type): Add + DEMANGLE_COMPONENT_PACK_EXPANSION. + +-2008-09-24 Richard Henderson +- +- * elf/dwarf2.h (DW_OP_GNU_encoded_addr): New. +- + 2008-09-22 Rafael Espindola + + * plugin-api.h (ld_plugin_status): Remove comma from the last item. +@@ -1550,32 +1347,17 @@ + + * bfdlink.h (bfd_generic_link_read_symbols): Declare. + +-2008-08-08 Anatoly Sokolov +- +- * elf/avr.h (E_AVR_MACH_AVR25, E_AVR_MACH_AVR31, +- E_AVR_MACH_AVR35, E_AVR_MACH_AVR51): Define. +- (EF_AVR_MACH): Redefine to 0x7F. +- * opcode/avr.h (AVR_ISA_TINY3, AVR_ISA_ALL, AVR_ISA_USB162): Remove. +- (AVR_ISA_AVR3): Redefine. +- (AVR_ISA_AVR1, AVR_ISA_AVR2, AVR_ISA_AVR31, AVR_ISA_AVR35, +- AVR_ISA_AVR3_ALL, AVR_ISA_AVR4, AVR_ISA_AVR5, AVR_ISA_AVR51, +- AVR_ISA_AVR6): Define. +- + 2008-07-12 Jie Zhang + + Revert + 2008-07-12 Jie Zhang + * bfdlink.h (struct bfd_link_info): Add sep_code member + variable. +- * elf/bfin.h (EF_BFIN_CODE_IN_L1): Define. +- (EF_BFIN_DATA_IN_L1): Define. + + 2008-07-12 Jie Zhang + + * bfdlink.h (struct bfd_link_info): Add sep_code member + variable. +- * elf/bfin.h (EF_BFIN_CODE_IN_L1): Define. +- (EF_BFIN_DATA_IN_L1): Define. + + 2008-07-07 Stan Shebs + +@@ -1938,10 +1720,6 @@ + + * libiberty.h (strverscmp): Prototype. + +-2005-06-17 Jakub Jelinek +- +- * elf/external.h (GRP_ENTRY_SIZE): Define. +- + 2005-06-08 Zack Weinberg + + * dis-asm.h (get_arm_regnames): Update prototype. +diff --git a/include/aout/ChangeLog b/include/aout/ChangeLog +index 790763b..7caa35b 100644 +--- a/include/aout/ChangeLog ++++ b/include/aout/ChangeLog +@@ -6,6 +6,10 @@ + + Update copyright years. + ++2012-12-17 Nick Clifton ++ ++ * hppa.h: Add copyright notice. ++ + 2010-04-15 Nick Clifton + + * adobe.h: Update copyright notice to use GPLv3. +diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog +index 3c6eddc..c10e95e 100644 +--- a/include/elf/ChangeLog ++++ b/include/elf/ChangeLog +@@ -58,6 +58,18 @@ + + * aarch64.h (R_AARCH64_P32_TLSLD_ADR_PAGE21): Define. + ++2015-07-16 Jiong Wang ++ ++ * aarch64.h (R_AARCH64_P32_TLSLD_ADR_PREL21): New enumeration. ++ ++2015-07-09 Catherine Moore ++ ++ * mips.h (Val_GNU_MIPS_ABI_FP_NAN2008): New. ++ ++2015-07-08 Pitchumani Sivanupandi ++ ++ * avr.h: Add new 32 bit PC relative relocation. ++ + 2015-07-01 Sandra Loosemore + Cesar Philippidis + +@@ -81,11 +93,19 @@ + + * nios2.h (EF_NIOS2_ARCH_R1, EF_NIOS2_ARCH_R2): Define. + ++2015-06-26 Matthew Fortune ++ ++ * mips.h (DT_MIPS_RLD_MAP_REL): New macro. ++ + 2015-05-29 Roland McGrath + + * common.h (GNU_ABI_TAG_SYLLABLE): New macro. + (GNU_ABI_TAG_NACL): New macro. + ++2015-05-12 Jiong Wang ++ ++ * aarch64.h (R_AARCH64_P32_LD32_GOTPAGE_LO14): New enumeration. ++ + 2015-05-11 H.J. Lu + + * common.h (EM_486): Renamed to ... +@@ -133,6 +153,11 @@ + (E_FLAG_RL78_CPU_MASK, E_FLAG_RL78_ANY_CPU, E_FLAG_RL78_G13 + E_FLAG_RL78_G14): New flags. + ++2015-03-10 Matthew Wahab ++ ++ PR ld/16572 ++ * arm.h (EF_ARM_HASENTRY): Remove. ++ + 2015-02-19 Marcus Shawcroft + + * aarch64.h (R_AARCH64_P32_TLSGD_ADR_PREL21): Add. +@@ -188,6 +213,15 @@ + + * x86-64.h (R_X86_64_GOTPLT64): Mark it obsolete. + ++2014-10-30 Andrew Pinski ++ ++ * mips.h (AFL_EXT_OCTEON3): Define. ++ (INSN_OCTEON3, CPU_OCTEON3): Define. ++ ++2014-10-22 Matthew Fortune ++ ++ * mips.h (AFL_ASE_MASK): Define. ++ + 2014-10-17 Jose E. Marchesi + + * sparc.h (ELF_SPARC_HWCAP2_VIS3B): Documentation improved. +@@ -227,6 +261,28 @@ + + * rl78.h (RL78_RELAXA_MASK): New. Relax types are enums, not bits + ++2014-07-29 Matthew Fortune ++ ++ * mips.h (PT_MIPS_ABIFLAGS, SHT_MIPS_ABIFLAGS): Define. ++ (Val_GNU_MIPS_ABI_FP_OLD_64): Rename from Val_GNU_MIPS_ABI_FP_64. ++ (Val_GNU_MIPS_ABI_FP_64): Redefine. ++ (Val_GNU_MIPS_ABI_FP_XX): Define. ++ (Elf_External_ABIFlags_v0, Elf_Internal_ABIFlags_v0): New structures. ++ (AFL_REG_NONE, AFL_REG_32, AFL_REG_64, AFL_REG_128): Define. ++ (AFL_ASE_DSP, AFL_ASE_DSPR2, AFL_ASE_EVA, AFL_ASE_MCU): Likewise. ++ (AFL_ASE_MDMX, AFL_ASE_MIPS3D, AFL_ASE_MT, AFL_ASE_SMARTMIPS): Likewise. ++ (AFL_ASE_VIRT, AFL_ASE_MSA, AFL_ASE_MIPS16): Likewise. ++ (AFL_ASE_MICROMIPS, AFL_ASE_XPA): Likewise. ++ (AFL_EXT_XLR, AFL_EXT_OCTEON2, AFL_EXT_OCTEONP): Likewise. ++ (AFL_EXT_LOONGSON_3A, AFL_EXT_OCTEON, AFL_EXT_5900): Likewise. ++ (AFL_EXT_4650, AFL_EXT_4010, AFL_EXT_4100, AFL_EXT_3900): Likewise. ++ (AFL_EXT_10000, AFL_EXT_SB1, AFL_EXT_4111, AFL_EXT_4120): Likewise. ++ (AFL_EXT_5400, AFL_EXT_5500, AFL_EXT_LOONGSON_2E): Likewise. ++ (AFL_EXT_LOONGSON_2F): Likewise. ++ (bfd_mips_elf_swap_abiflags_v0_in): Prototype. ++ (bfd_mips_elf_swap_abiflags_v0_out): Likewise. ++ (bfd_mips_isa_ext): Likewise. ++ + 2014-07-07 Barney Stratford + + * avr.h: Add R_AVR_PORT5 and R_AVR_PORT6. +@@ -252,6 +308,10 @@ + * openrisc.h: Delete. + * or32.h: Delete. + ++2014-04-10 Senthil Kumar Selvaraj ++ ++ * avr.h: Add new DIFF relocs. ++ + 2014-03-05 Alan Modra + + Update copyright years. +@@ -395,6 +455,10 @@ + (EM_INTEL208): Likewise. + (EM_INTEL209): Likewise. + ++2013-05-06 Paul Brook ++ ++ * mips.h (R_MIPS_PC32): Update comment. ++ + 2013-05-02 Nick Clifton + + * msp430.h: Add MSP430X relocs. +@@ -443,6 +507,10 @@ + * mips.h: Add MIPS machine variant number for r5900 which is + compatible with old Playstation 2 software. + ++2012-12-11 Edgar E. Iglesias ++ ++ * microblaze.h: Add TLS relocs to START_RELOC_NUMBERS ++ + 2012-11-16 H.J. Lu + + * common.h (DF_1_CONLFAT): Renamed to ... +@@ -477,13 +545,17 @@ + + 2012-10-30 Steve McIntyre + +- * elf/arm.h (EF_ARM_ABI_FLOAT_SOFT): New define. ++ * arm.h (EF_ARM_ABI_FLOAT_SOFT): New define. + (EF_ARM_ABI_FLOAT_HARD): Likewise. + + 2012-10-23 Tom Tromey + + * common.h (NT_SIGINFO, NT_FILE): New defines. + ++2012-09-12 Chris Schlumberger-Socha ++ ++ * aarch64.h (R_AARCH64_GOT_LD_PREL19): New reloc. ++ + 2012-08-27 Walter Lee + + * tilegx.h (R_TILEGX_IMM16_X0_HW0_PLT_PCREL): New relocation. +@@ -501,6 +573,11 @@ + (R_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL ): Ditto. + (R_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL): Ditto. + ++2012-08-24 Matthew Gretton-Dann ++ ++ * arm.h (TAG_CPU_ARCH_V8): New define. ++ (MAX_TAG_CPU_ARCH): Update. ++ + 2012-08-13 Ian Bolton + Laurent Desnogues + Jim MacArthur +@@ -516,6 +593,14 @@ + * common.h (EM_res183): Rename to EM_AARCH64. + (EM_res184): Rename to EM_ARM184. + ++2012-08-02 Sean Keys ++ ++ * m68hc11.h: #define E_M68HC11_NO_BANK_WARNING 0x000000200 ++ ++2012-07-13 Andreas Krebbel ++ ++ * s390.h (START_RELOC_NUMBERS): Define R_390_IRELATIVE reloc. ++ + 2012-06-28 Iain Sandoe + + * common.h (AT_L1I_CACHESHAPE, AT_L1D_CACHESHAPE, +@@ -565,7 +650,7 @@ + 2012-05-11 Georg-Johann Lay +@@ -577,6 +662,10 @@ + * sparc.h: Add new ELF_SPARC_HWCAP_* defines for crypto, + pause, and compare-and-branch instructions. + ++2012-04-12 David S. Miller ++ ++ * sparc.h (R_SPARC_WDISP10): New reloc. ++ + 2012-03-07 Nick Clifton + + * mn10300.h (elf_mn10300_reloc_type): Add R_MN10300_TLS_GD, +@@ -1096,13 +1185,13 @@ + + 2009-08-09 Michael Eager + +- * elf/common.h: Define EM_resnnn reserved values. Add EM_AVR32, ++ * common.h: Define EM_resnnn reserved values. Add EM_AVR32, + EM_STM8, EM_TILE64, EM_TILEPRO. Change EM_MICROBLAZE. + + 2009-08-06 Michael Eager + +- * elf/common.h: Define EM_MICROBLAZE & EM_MICROBLAZE_OLD. +- * elf/microblaze.h: New reloc definitions. ++ * common.h: Define EM_MICROBLAZE & EM_MICROBLAZE_OLD. ++ * microblaze.h: New reloc definitions. + + 2009-07-30 Alan Modra + +@@ -1171,7 +1260,7 @@ + + 2009-04-24 Cary Coutant + +- * dwarf2.h (DW_LNE_set_discriminator): New enum value. ++ * dwarf2.h (DW_LNE_set_discriminator): New enum value. + + 2009-04-15 Anthony Green + +@@ -1303,12 +1392,22 @@ + (R_CRIS_32_GOT_TPREL, R_CRIS_16_GOT_TPREL, R_CRIS_32_TPREL) + (R_CRIS_16_TPREL): New relocations. + ++2008-09-24 Richard Henderson ++ ++ * dwarf2.h (DW_OP_GNU_encoded_addr): New. ++ + 2008-08-20 Bob Wilson + + * xtensa.h (R_XTENSA_TLSDESC_FN, R_XTENSA_TLSDESC_ARG) + (R_XTENSA_TLS_DTPOFF, R_XTENSA_TLS_TPOFF, R_XTENSA_TLS_FUNC) + (R_XTENSA_TLS_ARG, R_XTENSA_TLS_CALL): New. + ++2008-08-08 Anatoly Sokolov ++ ++ * avr.h (E_AVR_MACH_AVR25, E_AVR_MACH_AVR31, ++ E_AVR_MACH_AVR35, E_AVR_MACH_AVR51): Define. ++ (EF_AVR_MACH): Redefine to 0x7F. ++ + 2008-08-08 Richard Sandiford + Daniel Jacobowitz + Catherine Moore +@@ -1329,6 +1428,18 @@ + + * common.h: Define NT_PPC_VSX. + ++2008-07-12 Jie Zhang ++ ++ Revert ++ 2008-07-12 Jie Zhang ++ * bfin.h (EF_BFIN_CODE_IN_L1): Define. ++ (EF_BFIN_DATA_IN_L1): Define. ++ ++2008-07-12 Jie Zhang ++ ++ * bfin.h (EF_BFIN_CODE_IN_L1): Define. ++ (EF_BFIN_DATA_IN_L1): Define. ++ + 2008-07-10 Richard Sandiford + + * mips.h (ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): New macros. +@@ -1366,7 +1477,7 @@ + + 2008-04-16 David S. Miller + +- * elf/sparc.h (R_SPARC_GOTDATA_HIX22, ++ * sparc.h (R_SPARC_GOTDATA_HIX22, + R_SPARC_GOTDATA_LOX10, R_SPARC_GOTDATA_OP_HIX22, + R_SPARC_GOTDATA_OP_LOX10, R_SPARC_GOTDATA_OP, + R_SPARC_H34, R_SPARC_SIZE32, R_SPARC_SIZE64): New relocs. +@@ -1689,6 +1800,7 @@ + + 2006-05-24 Carlos O'Donell + Randolph Chung ++ + * hppa.h (R_PARISC_TLS_GD21L, R_PARISC_TLS_GD14R, R_PARISC_TLS_GDCALL, + R_PARISC_TLS_LDM21L, R_PARISC_TLS_LDM14R, R_PARISC_TLS_LDMCALL, + R_PARISC_TLS_LDO21L, R_PARISC_TLS_LDO14R, R_PARISC_TLS_DTPMOD32, +diff --git a/include/gdb/ChangeLog b/include/gdb/ChangeLog +index 57a83ce..5a3ecee 100644 +--- a/include/gdb/ChangeLog ++++ b/include/gdb/ChangeLog +@@ -51,9 +51,13 @@ + + * section-scripts.h: New file. + ++2013-10-22 Sterling Augustine ++ ++ * gdb-index.h: Merge from gdb tree. ++ + 2013-03-15 Steve Ellcey + +- * gdb/remote-sim.h (sim_command_completer): Make char arguments const. ++ * remote-sim.h (sim_command_completer): Make char arguments const. + + 2013-01-01 Joel Brobecker + +@@ -218,7 +222,7 @@ + + 2003-06-10 Corinna Vinschen + +- * gdb/fileio.h: New file. ++ * fileio.h: New file. + + 2003-05-07 Andrew Cagney + +@@ -256,7 +260,7 @@ + 2002-07-29 Andrey Volkov + + * sim-h8300.h: Rename all enums from H8300_ to SIM_H8300_ +- prefix. ++ prefix. + + 2002-07-23 Andrey Volkov + +diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog +index 0aee194..87d4653 100644 +--- a/include/opcode/ChangeLog ++++ b/include/opcode/ChangeLog +@@ -95,10 +95,10 @@ + * aarch64.h [__cplusplus]: Wrap in extern "C". + + 2015-10-07 Claudiu Zissulescu +- Cupertino Miranda ++ Cupertino Miranda + +- * arc-func.h: New file. +- * arc.h: Likewise. ++ * arc-func.h: New file. ++ * arc.h: Likewise. + + 2015-10-02 Yao Qi + +@@ -115,6 +115,10 @@ + (S390_INSTR_FLAG_VX): New flag. + (S390_INSTR_FLAG_FACILITY_MASK): New flag mask. + ++2015-09-26 James Bowman ++ ++ * ft32.h: Add instruction macros FT32_*() ++ + 2015-09-23 Nick Clifton + + * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left +@@ -258,6 +262,14 @@ + (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete. + (NIOS2_INSN_OPTARG): Renumber. + ++2014-11-21 Terry Guo ++ ++ * arm.h (FPU_VFP_EXT_ARMV8xD): New macro. ++ (FPU_VFP_V5D16): Likewise. ++ (FPU_VFP_V5_SP_D16): Likewise. ++ (FPU_ARCH_VFP_V5D16): Likewise. ++ (FPU_ARCH_VFP_V5_SP_D16): Likewise. ++ + 2014-11-06 Sandra Loosemore + + * nios2.h (nios2_find_opcode_hash): Add mach parameter to +@@ -347,7 +359,7 @@ + * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT, + OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6 + instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B, +- +I, +O, +R, +:, +\, +", +; ++ +I, +O, +R, +:, +\, +", +; + (mips_check_prev_operand): New struct. + (INSN2_FORBIDDEN_SLOT): New define. + (INSN_ISA32R6): New define. +@@ -425,6 +437,10 @@ + + * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values. + ++2014-04-23 Andrew Bennett ++ ++ * mips.h (ASE_XPA): New define. ++ + 2014-04-22 Christian Svensson + + * or32.h: Delete. +@@ -472,6 +488,11 @@ + * aarch64.h (aarch64_sys_reg_readonly_p): New declaration. + (aarch64_sys_reg_writeonly_p): Ditto. + ++2013-11-11 Catherine Moore ++ ++ * mips.h (INSN_LOAD_MEMORY_DELAY): Rename to... ++ (INSN_LOAD_MEMORY): ...this. ++ + 2013-11-05 Yufeng Zhang + + * aarch64.h (aarch64_sys_reg): New typedef. +@@ -514,6 +535,11 @@ + * mips.h (OP_OPTIONAL_REG): New mips_operand_type. + (mips_optional_operand_p): New function. + ++2013-08-05 Eric Botcazou ++ Konrad Eisele ++ ++ * sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_LEON. ++ + 2013-08-04 Jürgen Urban + Richard Sandiford + +@@ -677,6 +703,21 @@ + + * nios2.h (OP_MATCH_ERET): Correct eret encoding. + ++2013-06-08 Catherine Moore ++ ++ * mips.h (mips_opcode): Add ase field. ++ (INSN_ASE_MASK): Delete. ++ (INSN_DSP): Rename to ASE_DSP. Provide new value. ++ (INSN_DSPR2): Rename to ASE_DSPR2. Provide new value. ++ (INSN_MCU): Rename to ASE_MCU. Provide new value. ++ (INSN_MDMX): Rename to ASE_MDMX. Provide new value. ++ (INSN_MIPS3d): Rename to ASE_MIPS3D. Provide new value. ++ (INSN_MT): Rename to ASE_MT. Provide new value. ++ (INSN_SMARTMIPS): Rename to ASE_SMARTMIPS. Provide new value. ++ (INSN_VIRT): Rename to ASE_VIRT. Provide new value. ++ (INSN_VIRT64): Rename to ASE_VIRT64. Provide new value. ++ (opcode_is_member): Add ase argument. Check ase. ++ + 2013-05-22 Jürgen Urban + + * mips.h (M_LQC2_AB, M_SQC2_AB): New macros. +@@ -741,6 +782,20 @@ + * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp + and rsqrdp opcodes to use the new field coding types. + ++2013-03-12 Sebastian Huber ++ ++ * nios2.h: Edit comment. ++ ++2013-03-11 Sebastian Huber ++ ++ * nios2.h (OPX_WRPRS): New define. ++ (OP_MATCH_WRPRS): Likewise. ++ ++2013-03-11 Sebastian Huber ++ ++ * nios2.h (OP_RDPRS): New define. ++ (OP_MATCH_RDPRS): Likewise. ++ + 2013-03-11 Kyrylo Tkachov + + * arm.h (CRC_EXT_ARMV8): New constant. +@@ -798,6 +853,10 @@ + (make_instruction,match_opcode): Added function prototypes. + (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern. + ++2012-12-17 Nick Clifton ++ ++ * tahoe.h: Add copyright notice. ++ + 2012-11-23 Alan Modra + + * ppc.h (ppc_parse_cpu): Update prototype. +@@ -811,10 +870,36 @@ + + * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12. + ++2012-09-27 Anthony Green ++ ++ * moxie.h (MOXIE_BAD): New define. ++ + 2012-09-04 Sergey A. Guriev + + * ia64.h (ia64_opnd): Add new operand types. + ++2012-08-24 Matthew Gretton-Dann ++ ++ * arm.h (ARM_CPU_IS_ANY): New define. ++ ++2012-08-24 Matthew Gretton-Dann ++ ++ * arm.h (ARM_EXT_V8): New define. ++ (FPU_VFP_EXT_ARMV8): Likewise. ++ (FPU_NEON_EXT_ARMV8): Likewise. ++ (FPU_CRYPTO_EXT_ARMV8): Likewise. ++ (ARM_AEXT_V8A): Likewise. ++ (FPU_VFP_ARMV8): Likwise. ++ (FPU_NEON_ARMV8): Likewise. ++ (FPU_CRYPTO_ARMV8): Likewise. ++ (FPU_ARCH_VFP_ARMV8): Likewise. ++ (FPU_ARCH_NEON_VFP_ARMV8): Likewise. ++ (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8): Likewise. ++ (ARM_ARCH_V8A): Likwise. ++ (ARM_ARCH_V8A_FP): Likewise. ++ (ARM_ARCH_V8A_SIMD): Likewise. ++ (ARM_ARCH_V8A_CRYPTO): Likewise. ++ + 2012-08-21 David S. Miller + + * sparc.h (F3F4): New macro. +@@ -859,6 +944,10 @@ + + * mips.h: Fix a typo in description. + ++2012-07-05 Sean Keys ++ ++ * xgate.h: Changed the format string for mode XGATE_OP_DYA_MON. ++ + 2012-06-07 Georg-Johann Lay + + * avr.h: (AVR_ISA_XCH): New define. +@@ -906,6 +995,10 @@ + HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE, + HWCAP_CBCOND, HWCAP_CRC32): New defines. + ++2012-04-12 David S. Miller ++ ++ * sparc.h: Define '=' as generating R_SPARC_WDISP10. ++ + 2012-03-10 Edmar Wienskoski + + * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR. +@@ -1275,6 +1368,14 @@ + * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_. + (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise. + ++2010-09-29 Bernd Schmidt ++ ++ * tic6x-control-registers.h (tscl): Now read_write. ++ ++2010-09-27 Andreas Krebbel ++ ++ * s390.h: Add S390_OPCODE_Z196 to enum s390_opcode_cpu_val. ++ + 2010-09-23 Matthew Gretton-Dann + + * arm.h (ARM_EXT_VIRT): New define. +@@ -1306,6 +1407,16 @@ + + * bfin.h: Strip trailing whitespace. + ++2009-09-04 Jie Zhang ++ ++ * bfin.h (PseudoDbg_Assert): Add bits_grp and mask_grp. ++ (PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask): Define. ++ (PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, ++ PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask): ++ Adjust accordingly. ++ (init_PseudoDbg_Assert): Add PseudoDbg_Assert_grp_bits and ++ PseudoDbg_Assert_grp_mask. ++ + 2010-07-29 DJ Delorie + + * rx.h (RX_Operand_Type): Add TwoReg. +@@ -1358,7 +1469,7 @@ + + 2010-05-26 Catherine Moore + +- * opcode/mips.h (INSN_MIPS16): Remove. ++ * mips.h (INSN_MIPS16): Remove. + + 2010-04-21 Joseph Myers + +@@ -1428,7 +1539,7 @@ + + 2010-02-08 Philipp Tomsich + +- * opcode/ppc.h (PPC_OPCODE_TITAN): Define. ++ * ppc.h (PPC_OPCODE_TITAN): Define. + + 2010-01-14 H.J. Lu + +@@ -1552,7 +1663,7 @@ + + 2009-01-28 Doug Evans + +- * opcode/i386.h: Add multiple inclusion protection. ++ * i386.h: Add multiple inclusion protection. + (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM) + (EDI_REG_NUM): New macros. + (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros. +@@ -1583,6 +1694,14 @@ + * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update + IA64_RS_CR. + ++2008-08-08 Anatoly Sokolov ++ ++ * avr.h (AVR_ISA_TINY3, AVR_ISA_ALL, AVR_ISA_USB162): Remove. ++ (AVR_ISA_AVR3): Redefine. ++ (AVR_ISA_AVR1, AVR_ISA_AVR2, AVR_ISA_AVR31, AVR_ISA_AVR35, ++ AVR_ISA_AVR3_ALL, AVR_ISA_AVR4, AVR_ISA_AVR5, AVR_ISA_AVR51, ++ AVR_ISA_AVR6): Define. ++ + 2008-08-01 Peter Bergner + + * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New. +@@ -2039,7 +2158,7 @@ + 2005-07-28 John David Anglin + + PR gas/336 +- * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb ++ * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb + and pitlb. + + 2005-07-27 Jan Beulich +diff --git a/ld/ChangeLog b/ld/ChangeLog +index 75fd708..4f6abb9 100644 +--- a/ld/ChangeLog ++++ b/ld/ChangeLog +@@ -1,3 +1,128 @@ ++2016-02-26 H.J. Lu ++ ++ Backport from master ++ 2016-02-24 H.J. Lu ++ ++ PR ld/19698 ++ * testsuite/ld-elf/pr19698.d: New file. ++ * testsuite/ld-elf/pr19698.s: Likewise. ++ * testsuite/ld-elf/pr19698.t: Likewise. ++ ++2016-02-26 H.J. Lu ++ ++ Backport from master ++ 2016-02-01 H.J. Lu ++ ++ PR ld/19553 ++ * testsuite/ld-elf/indirect.exp: Run tests for PR ld/19553. ++ * testsuite/ld-elf/pr19553.map: New file. ++ * testsuite/ld-elf/pr19553.map: Likewise. ++ * testsuite/ld-elf/pr19553a.c: Likewise. ++ * testsuite/ld-elf/pr19553b.c: Likewise. ++ * testsuite/ld-elf/pr19553b.out: Likewise. ++ * testsuite/ld-elf/pr19553c.c: Likewise. ++ * testsuite/ld-elf/pr19553c.out: Likewise. ++ * testsuite/ld-elf/pr19553d.c: Likewise. ++ * testsuite/ld-elf/pr19553d.out: Likewise. ++ ++2016-02-25 Jiong Wang ++ ++ Backport from master ++ 2016-01-20 Jiong Wang ++ ++ * testsuite/ld-aarch64/farcall-section.d: Delete. ++ * testsuite/ld-aarch64/farcall-section.s: Delete. ++ * testsuite/ld-aarch64/farcall-b-section.d: New expectation file. ++ * testsuite/ld-aarch64/farcall-bl-section.d: Likewise. ++ * testsuite/ld-aarch64/farcall-b-section.s: New testcase. ++ * testsuite/ld-aarch64/farcall-bl-section.s: Likewise. ++ * testsuite/ld-aarch64/aarch64-elf.exp: Likewise. ++ ++2016-02-11 H.J. Lu ++ ++ Backport from master ++ 2016-02-11 H.J. Lu ++ ++ PR ld/19615 ++ * ld.texinfo: Document -Bsymbolic and -Bsymbolic-functions for ++ PIE. ++ * lexsup.c (parse_args): Enable -Bsymbolic and ++ -Bsymbolic-functions for PIE. ++ * testsuite/ld-i386/i386.exp: Run pr19615. ++ * testsuite/ld-i386/pr19615.d: New file. ++ * testsuite/ld-i386/pr19615.s: Likewise. ++ * testsuite/ld-x86-64/pr19615.d: Likewise. ++ * testsuite/ld-x86-64/pr19615.s: Likewise. ++ ++2016-02-03 H.J. Lu ++ ++ Backport from master ++ 2016-02-03 H.J. Lu ++ ++ PR gas/19520 ++ * testsuite/ld-i386/branch1.d: Pass -mrelax-relocations=yes to as. ++ * testsuite/ld-i386/call1.d: Likewise. ++ * testsuite/ld-i386/call2.d: Likewise. ++ * testsuite/ld-i386/call3a.d: Likewise. ++ * testsuite/ld-i386/call3b.d: Likewise. ++ * testsuite/ld-i386/call3c.d: Likewise. ++ * testsuite/ld-i386/call3d.d: Likewise. ++ * testsuite/ld-i386/call3e.d: Likewise. ++ * testsuite/ld-i386/call3f.d: Likewise. ++ * testsuite/ld-i386/call3g.d: Likewise. ++ * testsuite/ld-i386/call3h.d: Likewise. ++ * testsuite/ld-i386/jmp1.d: Likewise. ++ * testsuite/ld-i386/jmp2.d: Likewise. ++ * testsuite/ld-i386/lea1c.d: Likewise. ++ * testsuite/ld-i386/load1.d: Likewise. ++ * testsuite/ld-i386/load2.d: Likewise. ++ * testsuite/ld-i386/load3.d: Likewise. ++ * testsuite/ld-i386/load4a.d: Likewise. ++ * testsuite/ld-i386/load5a.d: Likewise. ++ * testsuite/ld-i386/mov2b.d: Likewise. ++ * testsuite/ld-i386/mov3.d: Likewise. ++ * testsuite/ld-ifunc/ifunc-21-x86-64.d: Likewise. ++ * testsuite/ld-ifunc/ifunc-22-x86-64.d: Likewise. ++ * testsuite/ld-ifunc/ifunc-5r-local-x86-64.d: Likewise. ++ * testsuite/ld-x86-64/call1a.d: Likewise. ++ * testsuite/ld-x86-64/call1b.d: Likewise. ++ * testsuite/ld-x86-64/call1c.d: Likewise. ++ * testsuite/ld-x86-64/call1d.d: Likewise. ++ * testsuite/ld-x86-64/call1e.d: Likewise. ++ * testsuite/ld-x86-64/call1f.d: Likewise. ++ * testsuite/ld-x86-64/call1h.d: Likewise. ++ * testsuite/ld-x86-64/call1i.d: Likewise. ++ * testsuite/ld-x86-64/load1a.d: Likewise. ++ * testsuite/ld-x86-64/load1b.d: Likewise. ++ * testsuite/ld-i386/got1a.S: Load GOT into %ecx and use it. ++ * testsuite/ld-i386/got1.dd: Updated. ++ * testsuite/ld-i386/got1d.S (1): Removed. ++ * testsuite/ld-i386/i386.exp: Add -Wa,-mrelax-relocations=yes. ++ * testsuite/ld-x86-64/x86-64.exp: Likewise. ++ ++2016-02-02 H.J. Lu ++ ++ Backport from master ++ 2016-02-02 H.J. Lu ++ ++ PR ld/18591 ++ * testsuite/ld-x86-64/pr18591.d: New file. ++ * testsuite/ld-x86-64/pr18591.s: Likewise. ++ * testsuite/ld-x86-64/x86-64.exp: Run pr18591. ++ ++2016-01-29 H.J. Lu ++ ++ Backport from master ++ 2016-01-29 H.J. Lu ++ ++ PR ld/19533 ++ * configure.ac (compressed_debug_sections): Replace == with =. ++ * configure: Regenerated. ++ ++2016-01-25 Tristan Gingold ++ ++ * configure: Regenerate. ++ + 2016-01-25 Tristan Gingold + + * configure: Regenerate. +@@ -89,7 +214,7 @@ + decide placement. + + 2015-10-27 Laurent Alfonsi +- Christophe Monat ++ Christophe Monat + + * ld.texinfo: Add description of the STM32L4xx erratum + workaround. +@@ -129,7 +254,7 @@ + + 2015-10-22 H.J. Lu + +- * ld/ld.texinfo: Document "-z call-nop=PADDING" option. ++ * ld.texinfo: Document "-z call-nop=PADDING" option. + * emulparams/call_nop.sh: New file. + * emulparams/elf_i386_be.sh: Source + ${srcdir}/emulparams/call_nop.sh. +@@ -165,7 +290,7 @@ + + 2015-10-15 Simon Dardis + +- * ld/ldexp.c: (try_copy_symbol_flags): New. Factored out from... ++ * ldexp.c: (try_copy_symbol_flags): New. Factored out from... + (exp_fold_tree_1): Here. Cope with ternary operator in + assignments. Use new helper. + +@@ -308,7 +433,7 @@ + 2015-09-09 James Bowman + + * scripttempl/ft32.sc: default linker script RAM and +- FLASH size symbols ++ FLASH size symbols + + 2015-09-09 Nick Clifton + +@@ -359,58 +484,58 @@ + + 2015-08-18 H.J. Lu + +- * ld/ldctor.c: Replace shared, executable, relocatable and pie ++ * ldctor.c: Replace shared, executable, relocatable and pie + fields with bfd_link_executable, bfd_link_dll, + bfd_link_relocatable, bfd_link_pic and bfd_link_pie. +- * ld/ldemul.c: Likewise. +- * ld/ldfile.c: Likewise. +- * ld/ldlang.c: Likewise. +- * ld/ldmain.c: Likewise. +- * ld/ldwrite.c: Likewise. +- * ld/lexsup.c: Likewise. +- * ld/pe-dll.c: Likewise. +- * ld/plugin.c: Likewise. +- * ld/emultempl/aarch64elf.em: Likewise. +- * ld/emultempl/aix.em: Likewise. +- * ld/emultempl/alphaelf.em: Likewise. +- * ld/emultempl/armcoff.em: Likewise. +- * ld/emultempl/armelf.em: Likewise. +- * ld/emultempl/avrelf.em: Likewise. +- * ld/emultempl/beos.em: Likewise. +- * ld/emultempl/cr16elf.em: Likewise. +- * ld/emultempl/elf-generic.em: Likewise. +- * ld/emultempl/elf32.em: Likewise. +- * ld/emultempl/genelf.em: Likewise. +- * ld/emultempl/generic.em: Likewise. +- * ld/emultempl/gld960.em: Likewise. +- * ld/emultempl/gld960c.em: Likewise. +- * ld/emultempl/hppaelf.em: Likewise. +- * ld/emultempl/irix.em: Likewise. +- * ld/emultempl/linux.em: Likewise. +- * ld/emultempl/lnk960.em: Likewise. +- * ld/emultempl/m68hc1xelf.em: Likewise. +- * ld/emultempl/m68kcoff.em: Likewise. +- * ld/emultempl/m68kelf.em: Likewise. +- * ld/emultempl/metagelf.em: Likewise. +- * ld/emultempl/mipself.em: Likewise. +- * ld/emultempl/mmo.em: Likewise. +- * ld/emultempl/msp430.em: Likewise. +- * ld/emultempl/nds32elf.em: Likewise. +- * ld/emultempl/needrelax.em: Likewise. +- * ld/emultempl/nios2elf.em: Likewise. +- * ld/emultempl/pe.em: Likewise. +- * ld/emultempl/pep.em: Likewise. +- * ld/emultempl/ppc32elf.em: Likewise. +- * ld/emultempl/ppc64elf.em: Likewise. +- * ld/emultempl/sh64elf.em: Likewise. +- * ld/emultempl/solaris2.em: Likewise. +- * ld/emultempl/spuelf.em: Likewise. +- * ld/emultempl/sunos.em: Likewise. +- * ld/emultempl/tic6xdsbt.em: Likewise. +- * ld/emultempl/ticoff.em: Likewise. +- * ld/emultempl/v850elf.em: Likewise. +- * ld/emultempl/vms.em: Likewise. +- * ld/emultempl/vxworks.em: Likewise. ++ * ldemul.c: Likewise. ++ * ldfile.c: Likewise. ++ * ldlang.c: Likewise. ++ * ldmain.c: Likewise. ++ * ldwrite.c: Likewise. ++ * lexsup.c: Likewise. ++ * pe-dll.c: Likewise. ++ * plugin.c: Likewise. ++ * emultempl/aarch64elf.em: Likewise. ++ * emultempl/aix.em: Likewise. ++ * emultempl/alphaelf.em: Likewise. ++ * emultempl/armcoff.em: Likewise. ++ * emultempl/armelf.em: Likewise. ++ * emultempl/avrelf.em: Likewise. ++ * emultempl/beos.em: Likewise. ++ * emultempl/cr16elf.em: Likewise. ++ * emultempl/elf-generic.em: Likewise. ++ * emultempl/elf32.em: Likewise. ++ * emultempl/genelf.em: Likewise. ++ * emultempl/generic.em: Likewise. ++ * emultempl/gld960.em: Likewise. ++ * emultempl/gld960c.em: Likewise. ++ * emultempl/hppaelf.em: Likewise. ++ * emultempl/irix.em: Likewise. ++ * emultempl/linux.em: Likewise. ++ * emultempl/lnk960.em: Likewise. ++ * emultempl/m68hc1xelf.em: Likewise. ++ * emultempl/m68kcoff.em: Likewise. ++ * emultempl/m68kelf.em: Likewise. ++ * emultempl/metagelf.em: Likewise. ++ * emultempl/mipself.em: Likewise. ++ * emultempl/mmo.em: Likewise. ++ * emultempl/msp430.em: Likewise. ++ * emultempl/nds32elf.em: Likewise. ++ * emultempl/needrelax.em: Likewise. ++ * emultempl/nios2elf.em: Likewise. ++ * emultempl/pe.em: Likewise. ++ * emultempl/pep.em: Likewise. ++ * emultempl/ppc32elf.em: Likewise. ++ * emultempl/ppc64elf.em: Likewise. ++ * emultempl/sh64elf.em: Likewise. ++ * emultempl/solaris2.em: Likewise. ++ * emultempl/spuelf.em: Likewise. ++ * emultempl/sunos.em: Likewise. ++ * emultempl/tic6xdsbt.em: Likewise. ++ * emultempl/ticoff.em: Likewise. ++ * emultempl/v850elf.em: Likewise. ++ * emultempl/vms.em: Likewise. ++ * emultempl/vxworks.em: Likewise. + + 2015-08-18 Alan Modra + +diff --git a/ld/configure b/ld/configure +index a446283..8095b71 100755 +--- a/ld/configure ++++ b/ld/configure +@@ -1,6 +1,6 @@ + #! /bin/sh + # Guess values for system-dependent variables and create Makefiles. +-# Generated by GNU Autoconf 2.64 for ld 2.26. ++# Generated by GNU Autoconf 2.64 for ld 2.26.0. + # + # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, + # 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software +@@ -556,8 +556,8 @@ MAKEFLAGS= + # Identity of this package. + PACKAGE_NAME='ld' + PACKAGE_TARNAME='ld' +-PACKAGE_VERSION='2.26' +-PACKAGE_STRING='ld 2.26' ++PACKAGE_VERSION='2.26.0' ++PACKAGE_STRING='ld 2.26.0' + PACKAGE_BUGREPORT='' + PACKAGE_URL='' + +@@ -1350,7 +1350,7 @@ if test "$ac_init_help" = "long"; then + # Omit some internal or obsolete options to make the list less imposing. + # This message is too long to be a string in the A/UX 3.1 sh. + cat <<_ACEOF +-\`configure' configures ld 2.26 to adapt to many kinds of systems. ++\`configure' configures ld 2.26.0 to adapt to many kinds of systems. + + Usage: $0 [OPTION]... [VAR=VALUE]... + +@@ -1421,7 +1421,7 @@ fi + + if test -n "$ac_init_help"; then + case $ac_init_help in +- short | recursive ) echo "Configuration of ld 2.26:";; ++ short | recursive ) echo "Configuration of ld 2.26.0:";; + esac + cat <<\_ACEOF + +@@ -1545,7 +1545,7 @@ fi + test -n "$ac_init_help" && exit $ac_status + if $ac_init_version; then + cat <<\_ACEOF +-ld configure 2.26 ++ld configure 2.26.0 + generated by GNU Autoconf 2.64 + + Copyright (C) 2009 Free Software Foundation, Inc. +@@ -2254,7 +2254,7 @@ cat >config.log <<_ACEOF + This file contains any messages produced by compilers while + running configure, to aid debugging if configure makes a mistake. + +-It was created by ld $as_me 2.26, which was ++It was created by ld $as_me 2.26.0, which was + generated by GNU Autoconf 2.64. Invocation command line was + + $ $0 $@ +@@ -4063,7 +4063,7 @@ fi + + # Define the identity of the package. + PACKAGE='ld' +- VERSION='2.26' ++ VERSION='2.26.0' + + + cat >>confdefs.h <<_ACEOF +@@ -17134,7 +17134,7 @@ do + fi + done + +-if test x$ac_default_compressed_debug_sections == xyes ; then ++if test x$ac_default_compressed_debug_sections = xyes ; then + + $as_echo "#define DEFAULT_FLAG_COMPRESS_DEBUG 1" >>confdefs.h + +@@ -17740,7 +17740,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + # report actual input values of CONFIG_FILES etc. instead of their + # values after options handling. + ac_log=" +-This file was extended by ld $as_me 2.26, which was ++This file was extended by ld $as_me 2.26.0, which was + generated by GNU Autoconf 2.64. Invocation command line was + + CONFIG_FILES = $CONFIG_FILES +@@ -17804,7 +17804,7 @@ Report bugs to the package provider." + _ACEOF + cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 + ac_cs_version="\\ +-ld config.status 2.26 ++ld config.status 2.26.0 + configured by $0, generated by GNU Autoconf 2.64, + with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" + +diff --git a/ld/configure.ac b/ld/configure.ac +index 188172d..e28f38e 100644 +--- a/ld/configure.ac ++++ b/ld/configure.ac +@@ -384,7 +384,7 @@ do + fi + done + +-if test x$ac_default_compressed_debug_sections == xyes ; then ++if test x$ac_default_compressed_debug_sections = xyes ; then + AC_DEFINE(DEFAULT_FLAG_COMPRESS_DEBUG, 1, [Define if you want compressed debug sections by default.]) + fi + +diff --git a/ld/ld.texinfo b/ld/ld.texinfo +index 1dd7492..2389661 100644 +--- a/ld/ld.texinfo ++++ b/ld/ld.texinfo +@@ -1325,15 +1325,21 @@ libraries. + When creating a shared library, bind references to global symbols to the + definition within the shared library, if any. Normally, it is possible + for a program linked against a shared library to override the definition +-within the shared library. This option is only meaningful on ELF +-platforms which support shared libraries. ++within the shared library. This option can also be used with the ++@option{--export-dynamic} option, when creating a position independent ++executable, to bind references to global symbols to the definition within ++the executable. This option is only meaningful on ELF platforms which ++support shared libraries and position independent executables. + + @kindex -Bsymbolic-functions + @item -Bsymbolic-functions + When creating a shared library, bind references to global function + symbols to the definition within the shared library, if any. ++This option can also be used with the @option{--export-dynamic} option, ++when creating a position independent executable, to bind references ++to global function symbols to the definition within the executable. + This option is only meaningful on ELF platforms which support shared +-libraries. ++libraries and position independent executables. + + @kindex --dynamic-list=@var{dynamic-list-file} + @item --dynamic-list=@var{dynamic-list-file} +diff --git a/ld/lexsup.c b/ld/lexsup.c +index 4cad209..e2fb212 100644 +--- a/ld/lexsup.c ++++ b/ld/lexsup.c +@@ -1586,15 +1586,14 @@ parse_args (unsigned argc, char **argv) + /* We may have -Bsymbolic, -Bsymbolic-functions, --dynamic-list-data, + --dynamic-list-cpp-new, --dynamic-list-cpp-typeinfo and + --dynamic-list FILE. -Bsymbolic and -Bsymbolic-functions are +- for shared libraries. -Bsymbolic overrides all others and vice +- versa. */ ++ for PIC outputs. -Bsymbolic overrides all others and vice versa. */ + switch (command_line.symbolic) + { + case symbolic_unset: + break; + case symbolic: +- /* -Bsymbolic is for shared library only. */ +- if (bfd_link_dll (&link_info)) ++ /* -Bsymbolic is for PIC output only. */ ++ if (bfd_link_pic (&link_info)) + { + link_info.symbolic = TRUE; + /* Should we free the unused memory? */ +@@ -1603,8 +1602,8 @@ parse_args (unsigned argc, char **argv) + } + break; + case symbolic_functions: +- /* -Bsymbolic-functions is for shared library only. */ +- if (bfd_link_dll (&link_info)) ++ /* -Bsymbolic-functions is for PIC output only. */ ++ if (bfd_link_pic (&link_info)) + command_line.dynamic_list = dynamic_list_data; + break; + } +diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog +index cb51928..d09a332 100644 +--- a/ld/testsuite/ChangeLog ++++ b/ld/testsuite/ChangeLog +@@ -117,12 +117,12 @@ + * ld-x86-64/plt-main3.rd: Also check GOTPCRELX. + + 2015-10-29 Catherine Moore +- +- * ld-mips-elf/mips16-fp-stub-1.s: New. +- * ld-mips-elf/mips16-fp-stub-2.s: New. +- * ld-mips-elf/mips16-fp-stub.d: New. +- * ld-mips-elf/mips-elf.exp: Run new tests. +- * ld-mips-elf/mips16-intermix.d: Update expected output. ++ ++ * ld-mips-elf/mips16-fp-stub-1.s: New. ++ * ld-mips-elf/mips16-fp-stub-2.s: New. ++ * ld-mips-elf/mips16-fp-stub.d: New. ++ * ld-mips-elf/mips-elf.exp: Run new tests. ++ * ld-mips-elf/mips16-intermix.d: Update expected output. + + 2015-10-28 H.J. Lu + +@@ -133,7 +133,7 @@ + * ld-x86-64/pr19162b.s: Likewise. + + 2015-10-27 Laurent Alfonsi +- Christophe Monat ++ Christophe Monat + + * ld-arm/arm-elf.exp (armelftests_common): Add STM32L4XX + tests. +@@ -1069,7 +1069,6 @@ + + 2015-05-28 Catherine Moore + +- ld/testsuite/ + * ld-mips-elf/compact-eh.ld: New linker script. + * ld-mips-elf/compact-eh1.d: New. + * ld-mips-elf/compact-eh1.s: New. +diff --git a/ld/testsuite/ld-aarch64/aarch64-elf.exp b/ld/testsuite/ld-aarch64/aarch64-elf.exp +index 0e5b31e..576cc65 100644 +--- a/ld/testsuite/ld-aarch64/aarch64-elf.exp ++++ b/ld/testsuite/ld-aarch64/aarch64-elf.exp +@@ -170,7 +170,6 @@ run_dump_test "pcrel_pic_defined_local" + + run_dump_test "limit-b" + run_dump_test "limit-bl" +-run_dump_test "farcall-section" + run_dump_test "farcall-back" + run_dump_test "farcall-b-defsym" + run_dump_test "farcall-bl-defsym" +@@ -181,6 +180,8 @@ run_dump_test "farcall-bl" + run_dump_test "farcall-b" + run_dump_test "farcall-b-none-function" + run_dump_test "farcall-bl-none-function" ++run_dump_test "farcall-b-section" ++run_dump_test "farcall-bl-section" + + run_dump_test "tls-relax-all" + run_dump_test "tls-relax-gd-le" +diff --git a/ld/testsuite/ld-aarch64/farcall-b-none-function.d b/ld/testsuite/ld-aarch64/farcall-b-none-function.d +index 34a6568..ba2981f 100644 +--- a/ld/testsuite/ld-aarch64/farcall-b-none-function.d ++++ b/ld/testsuite/ld-aarch64/farcall-b-none-function.d +@@ -2,4 +2,23 @@ + #source: farcall-b-none-function.s + #as: + #ld: -Ttext 0x1000 --section-start .foo=0x8001000 +-#error: .*\(.text\+0x0\): relocation truncated to fit: R_AARCH64_JUMP26 against symbol `bar'.* ++#objdump: -dr ++#... ++ ++Disassembly of section .text: ++ ++.* <_start>: ++ 1000: 14000003 b 100c <__bar_veneer> ++ 1004: d65f03c0 ret ++ 1008: 14000007 b 1024 <__bar_veneer\+0x18> ++ ++.* <__bar_veneer>: ++ 100c: 90040010 adrp x16, 8001000 ++ 1010: 91000210 add x16, x16, #0x0 ++ 1014: d61f0200 br x16 ++ ... ++ ++Disassembly of section .foo: ++ ++.* : ++ 8001000: d65f03c0 ret +diff --git a/ld/testsuite/ld-aarch64/farcall-b-section.d b/ld/testsuite/ld-aarch64/farcall-b-section.d +new file mode 100644 +index 0000000..4745c0f +--- /dev/null ++++ b/ld/testsuite/ld-aarch64/farcall-b-section.d +@@ -0,0 +1,34 @@ ++#name: aarch64-farcall-b-section ++#source: farcall-b-section.s ++#as: ++#ld: -Ttext 0x1000 --section-start .foo=0x8001000 ++#objdump: -dr ++#... ++ ++Disassembly of section .text: ++ ++.* <_start>: ++ 1000: 14000008 b 1020 <___veneer> ++ 1004: 14000003 b 1010 <___veneer> ++ 1008: d65f03c0 ret ++ 100c: 1400000d b 1040 <___veneer\+0x20> ++ ++.* <___veneer>: ++ 1010: 90040010 adrp x16, 8001000 ++ 1014: 91001210 add x16, x16, #0x4 ++ 1018: d61f0200 br x16 ++ 101c: 00000000 .inst 0x00000000 ; undefined ++ ++.* <___veneer>: ++ 1020: 90040010 adrp x16, 8001000 ++ 1024: 91000210 add x16, x16, #0x0 ++ 1028: d61f0200 br x16 ++ ... ++ ++Disassembly of section .foo: ++ ++.* : ++ 8001000: d65f03c0 ret ++ ++.* : ++ 8001004: d65f03c0 ret +diff --git a/ld/testsuite/ld-aarch64/farcall-b-section.s b/ld/testsuite/ld-aarch64/farcall-b-section.s +new file mode 100644 +index 0000000..1a135ef +--- /dev/null ++++ b/ld/testsuite/ld-aarch64/farcall-b-section.s +@@ -0,0 +1,20 @@ ++.global _start ++ ++# We will place the section .text at 0x1000. ++ ++ .text ++ ++_start: ++ b bar ++ b bar2 ++ ret ++ ++# We will place the section .foo at 0x8001000. ++ ++ .section .foo, "xa" ++ .type bar, @function ++bar: ++ ret ++ .type bar2, @function ++bar2: ++ ret +diff --git a/ld/testsuite/ld-aarch64/farcall-bl-none-function.d b/ld/testsuite/ld-aarch64/farcall-bl-none-function.d +index 6ce9ca4..b6a4dda 100644 +--- a/ld/testsuite/ld-aarch64/farcall-bl-none-function.d ++++ b/ld/testsuite/ld-aarch64/farcall-bl-none-function.d +@@ -2,4 +2,23 @@ + #source: farcall-bl-none-function.s + #as: + #ld: -Ttext 0x1000 --section-start .foo=0x8001000 +-#error: .*\(.text\+0x0\): relocation truncated to fit: R_AARCH64_CALL26 against symbol `bar'.* ++#objdump: -dr ++#... ++ ++Disassembly of section .text: ++ ++.* <_start>: ++ 1000: 94000003 bl 100c <__bar_veneer> ++ 1004: d65f03c0 ret ++ 1008: 14000007 b 1024 <__bar_veneer\+0x18> ++ ++.* <__bar_veneer>: ++ 100c: 90040010 adrp x16, 8001000 ++ 1010: 91000210 add x16, x16, #0x0 ++ 1014: d61f0200 br x16 ++ ... ++ ++Disassembly of section .foo: ++ ++.* : ++ 8001000: d65f03c0 ret +diff --git a/ld/testsuite/ld-aarch64/farcall-bl-section.d b/ld/testsuite/ld-aarch64/farcall-bl-section.d +new file mode 100644 +index 0000000..2bd4f85 +--- /dev/null ++++ b/ld/testsuite/ld-aarch64/farcall-bl-section.d +@@ -0,0 +1,34 @@ ++#name: aarch64-farcall-bl-section ++#source: farcall-bl-section.s ++#as: ++#ld: -Ttext 0x1000 --section-start .foo=0x8001000 ++#objdump: -dr ++#... ++ ++Disassembly of section .text: ++ ++.* <_start>: ++ 1000: 94000008 bl 1020 <___veneer> ++ 1004: 94000003 bl 1010 <___veneer> ++ 1008: d65f03c0 ret ++ 100c: 1400000d b 1040 <___veneer\+0x20> ++ ++.* <___veneer>: ++ 1010: 90040010 adrp x16, 8001000 ++ 1014: 91001210 add x16, x16, #0x4 ++ 1018: d61f0200 br x16 ++ 101c: 00000000 .inst 0x00000000 ; undefined ++ ++.* <___veneer>: ++ 1020: 90040010 adrp x16, 8001000 ++ 1024: 91000210 add x16, x16, #0x0 ++ 1028: d61f0200 br x16 ++ ... ++ ++Disassembly of section .foo: ++ ++.* : ++ 8001000: d65f03c0 ret ++ ++.* : ++ 8001004: d65f03c0 ret +diff --git a/ld/testsuite/ld-aarch64/farcall-bl-section.s b/ld/testsuite/ld-aarch64/farcall-bl-section.s +new file mode 100644 +index 0000000..4469d4d +--- /dev/null ++++ b/ld/testsuite/ld-aarch64/farcall-bl-section.s +@@ -0,0 +1,20 @@ ++ .global _start ++ ++# We will place the section .text at 0x1000. ++ ++ .text ++ ++_start: ++ bl bar ++ bl bar2 ++ ret ++ ++# We will place the section .foo at 0x8001000. ++ ++ .section .foo, "xa" ++ .type bar, @function ++bar: ++ ret ++ .type bar2, @function ++bar2: ++ ret +diff --git a/ld/testsuite/ld-aarch64/farcall-section.d b/ld/testsuite/ld-aarch64/farcall-section.d +deleted file mode 100644 +index 85775e1..0000000 +--- a/ld/testsuite/ld-aarch64/farcall-section.d ++++ /dev/null +@@ -1,5 +0,0 @@ +-#name: Aarch64 farcall to symbol of type STT_SECTION +-#source: farcall-section.s +-#as: +-#ld: -Ttext 0x1000 --section-start .foo=0x8001014 +-#error: .*\(.text\+0x0\): relocation truncated to fit: R_AARCH64_CALL26 against `.foo' +diff --git a/ld/testsuite/ld-aarch64/farcall-section.s b/ld/testsuite/ld-aarch64/farcall-section.s +deleted file mode 100644 +index 86a070c..0000000 +--- a/ld/testsuite/ld-aarch64/farcall-section.s ++++ /dev/null +@@ -1,19 +0,0 @@ +-# Test to ensure that an Aarch64 call exceeding 128MB generates an error +-# if the destination is of type STT_SECTION (eg non-global symbol) +- +- .global _start +- +-# We will place the section .text at 0x1000. +- +- .text +- +-_start: +- bl bar +- +-# We will place the section .foo at 0x8001020. +- +- .section .foo, "xa" +- +-bar: +- ret +- +diff --git a/ld/testsuite/ld-elf/indirect.exp b/ld/testsuite/ld-elf/indirect.exp +index e8ac1ae..25845a0 100644 +--- a/ld/testsuite/ld-elf/indirect.exp ++++ b/ld/testsuite/ld-elf/indirect.exp +@@ -66,7 +66,11 @@ if { ![ld_compile $CC $srcdir/$subdir/indirect1a.c tmpdir/indirect1a.o] + || ![ld_compile $CC $srcdir/$subdir/indirect4a.c tmpdir/indirect4a.o] + || ![ld_compile $CC $srcdir/$subdir/indirect4b.c tmpdir/indirect4b.o] + || ![ld_compile "$CC -O2 -fPIC -I../bfd" $srcdir/$subdir/pr18720a.c tmpdir/pr18720a.o] +- || ![ld_compile $CC $srcdir/$subdir/pr18720b.c tmpdir/pr18720b.o] } { ++ || ![ld_compile $CC $srcdir/$subdir/pr18720b.c tmpdir/pr18720b.o] ++ || ![ld_compile "$CC -fPIC" $srcdir/$subdir/pr19553d.c tmpdir/pr19553d.o] ++ || ![ld_compile "$CC -fPIC" $srcdir/$subdir/pr19553c.c tmpdir/pr19553c.o] ++ || ![ld_compile "$CC -fPIC" $srcdir/$subdir/pr19553b.c tmpdir/pr19553b.o] ++ || ![ld_compile $CC $srcdir/$subdir/pr19553a.c tmpdir/pr19553a.o] } { + unresolved "Indirect symbol tests" + return + } +@@ -87,6 +91,15 @@ set build_tests { + {"Build pr18720b1.o" + "-r -nostdlib tmpdir/pr18720b.o" "" + {dummy.c} {} "pr18720b1.o"} ++ {"Build libpr19553b.so" ++ "-shared -Wl,--version-script=pr19553.map" "-fPIC" ++ {pr19553b.c} {} "libpr19553b.so"} ++ {"Build libpr19553c.so" ++ "-shared -Wl,--version-script=pr19553.map" "-fPIC" ++ {pr19553c.c} {} "libpr19553c.so"} ++ {"Build libpr19553d.so" ++ "-shared tmpdir/libpr19553c.so" "-fPIC" ++ {pr19553d.c} {} "libpr19553d.so"} + } + + run_cc_link_tests $build_tests +@@ -155,6 +168,15 @@ set run_tests { + {"Run with libpr18720c.so 5" + "tmpdir/libpr18720c.so tmpdir/pr18720b1.o tmpdir/pr18720a.o" "" + {check-ptr-eq.c} "pr18720d" "pr18720.out"} ++ {"Run with libpr19553b.so" ++ "tmpdir/libpr19553b.so tmpdir/libpr19553d.so -rpath-link ." "" ++ {pr19553a.c} "pr19553b" "pr19553b.out"} ++ {"Run with libpr19553c.so" ++ "tmpdir/libpr19553c.so tmpdir/libpr19553b.so tmpdir/libpr19553d.so" "" ++ {pr19553a.c} "pr19553c" "pr19553c.out"} ++ {"Run with libpr19553d.so" ++ "tmpdir/libpr19553d.so tmpdir/libpr19553b.so -rpath-link ." "" ++ {pr19553a.c} "pr19553d" "pr19553d.out"} + } + + run_ld_link_exec_tests [] $run_tests +diff --git a/ld/testsuite/ld-elf/pr19553.map b/ld/testsuite/ld-elf/pr19553.map +new file mode 100644 +index 0000000..f2c03ac +--- /dev/null ++++ b/ld/testsuite/ld-elf/pr19553.map +@@ -0,0 +1,5 @@ ++FOO ++{ ++global: ++ foo; ++}; +diff --git a/ld/testsuite/ld-elf/pr19553a.c b/ld/testsuite/ld-elf/pr19553a.c +new file mode 100644 +index 0000000..f1cb6b4 +--- /dev/null ++++ b/ld/testsuite/ld-elf/pr19553a.c +@@ -0,0 +1,8 @@ ++extern void foo (void); ++ ++int ++main (void) ++{ ++ foo (); ++ return 0; ++} +diff --git a/ld/testsuite/ld-elf/pr19553b.c b/ld/testsuite/ld-elf/pr19553b.c +new file mode 100644 +index 0000000..0c438a2 +--- /dev/null ++++ b/ld/testsuite/ld-elf/pr19553b.c +@@ -0,0 +1,8 @@ ++#include ++ ++__attribute__ ((weak)) ++void ++foo (void) ++{ ++ printf ("pr19553b\n"); ++} +diff --git a/ld/testsuite/ld-elf/pr19553b.out b/ld/testsuite/ld-elf/pr19553b.out +new file mode 100644 +index 0000000..a5575d9 +--- /dev/null ++++ b/ld/testsuite/ld-elf/pr19553b.out +@@ -0,0 +1 @@ ++pr19553b +diff --git a/ld/testsuite/ld-elf/pr19553c.c b/ld/testsuite/ld-elf/pr19553c.c +new file mode 100644 +index 0000000..d80dfc9 +--- /dev/null ++++ b/ld/testsuite/ld-elf/pr19553c.c +@@ -0,0 +1,9 @@ ++#include ++ ++void ++foo (void) ++{ ++ printf ("pr19553c\n"); ++} ++ ++asm (".symver foo,foo@FOO"); +diff --git a/ld/testsuite/ld-elf/pr19553c.out b/ld/testsuite/ld-elf/pr19553c.out +new file mode 100644 +index 0000000..9d23215 +--- /dev/null ++++ b/ld/testsuite/ld-elf/pr19553c.out +@@ -0,0 +1 @@ ++pr19553c +diff --git a/ld/testsuite/ld-elf/pr19553d.c b/ld/testsuite/ld-elf/pr19553d.c +new file mode 100644 +index 0000000..d48f8f3 +--- /dev/null ++++ b/ld/testsuite/ld-elf/pr19553d.c +@@ -0,0 +1,8 @@ ++#include ++ ++__attribute__ ((weak)) ++void ++foo (void) ++{ ++ printf ("pr19553d\n"); ++} +diff --git a/ld/testsuite/ld-elf/pr19553d.out b/ld/testsuite/ld-elf/pr19553d.out +new file mode 100644 +index 0000000..2b4cf0b +--- /dev/null ++++ b/ld/testsuite/ld-elf/pr19553d.out +@@ -0,0 +1 @@ ++pr19553d +diff --git a/ld/testsuite/ld-elf/pr19698.d b/ld/testsuite/ld-elf/pr19698.d +new file mode 100644 +index 0000000..a39f67a +--- /dev/null ++++ b/ld/testsuite/ld-elf/pr19698.d +@@ -0,0 +1,10 @@ ++#ld: -shared $srcdir/$subdir/pr19698.t ++#readelf : --dyn-syms --wide ++#target: *-*-linux* *-*-gnu* *-*-solaris* ++ ++Symbol table '\.dynsym' contains [0-9]+ entries: ++#... ++ +[0-9]+: +[0-9a-f]+ +[0-9a-f]+ +FUNC +GLOBAL +DEFAULT +[0-9]+ +foo@VERS.1 ++#... ++ +[0-9]+: +[0-9a-f]+ +[0-9a-f]+ +FUNC +GLOBAL +DEFAULT +[0-9]+ +foo@@VERS.2 ++#pass +diff --git a/ld/testsuite/ld-elf/pr19698.s b/ld/testsuite/ld-elf/pr19698.s +new file mode 100644 +index 0000000..875dca4 +--- /dev/null ++++ b/ld/testsuite/ld-elf/pr19698.s +@@ -0,0 +1,5 @@ ++ .text ++ .globl foo ++ .type foo, %function ++foo: ++ .byte 0 +diff --git a/ld/testsuite/ld-elf/pr19698.t b/ld/testsuite/ld-elf/pr19698.t +new file mode 100644 +index 0000000..09d9125 +--- /dev/null ++++ b/ld/testsuite/ld-elf/pr19698.t +@@ -0,0 +1,11 @@ ++"foo@VERS.1" = foo; ++ ++VERSION { ++VERS.2 { ++ global: ++ foo; ++}; ++ ++VERS.1 { ++}; ++} +diff --git a/ld/testsuite/ld-i386/branch1.d b/ld/testsuite/ld-i386/branch1.d +index a078f1d..81b069e 100644 +--- a/ld/testsuite/ld-i386/branch1.d ++++ b/ld/testsuite/ld-i386/branch1.d +@@ -1,4 +1,4 @@ +-#as: --32 ++#as: --32 -mrelax-relocations=yes + #ld: -melf_i386 + #objdump: -dw + +diff --git a/ld/testsuite/ld-i386/call1.d b/ld/testsuite/ld-i386/call1.d +index 69383b2..e3ebedc 100644 +--- a/ld/testsuite/ld-i386/call1.d ++++ b/ld/testsuite/ld-i386/call1.d +@@ -1,3 +1,3 @@ +-#as: --32 ++#as: --32 -mrelax-relocations=yes + #ld: -shared -melf_i386 + #error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object +diff --git a/ld/testsuite/ld-i386/call2.d b/ld/testsuite/ld-i386/call2.d +index 69383b2..e3ebedc 100644 +--- a/ld/testsuite/ld-i386/call2.d ++++ b/ld/testsuite/ld-i386/call2.d +@@ -1,3 +1,3 @@ +-#as: --32 ++#as: --32 -mrelax-relocations=yes + #ld: -shared -melf_i386 + #error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object +diff --git a/ld/testsuite/ld-i386/call3a.d b/ld/testsuite/ld-i386/call3a.d +index a8ff27f..5a1e1df 100644 +--- a/ld/testsuite/ld-i386/call3a.d ++++ b/ld/testsuite/ld-i386/call3a.d +@@ -1,5 +1,5 @@ + #source: call3.s +-#as: --32 ++#as: --32 -mrelax-relocations=yes + #ld: -melf_i386 + #objdump: -dw + +diff --git a/ld/testsuite/ld-i386/call3b.d b/ld/testsuite/ld-i386/call3b.d +index 06af6f5..de98ce4 100644 +--- a/ld/testsuite/ld-i386/call3b.d ++++ b/ld/testsuite/ld-i386/call3b.d +@@ -1,5 +1,5 @@ + #source: call3.s +-#as: --32 ++#as: --32 -mrelax-relocations=yes + #ld: -melf_i386 -z call-nop=prefix-addr + #objdump: -dw + +diff --git a/ld/testsuite/ld-i386/call3c.d b/ld/testsuite/ld-i386/call3c.d +index 64e8372..0fdbee4 100644 +--- a/ld/testsuite/ld-i386/call3c.d ++++ b/ld/testsuite/ld-i386/call3c.d +@@ -1,5 +1,5 @@ + #source: call3.s +-#as: --32 ++#as: --32 -mrelax-relocations=yes + #ld: -melf_i386 -z call-nop=prefix-nop + #objdump: -dw + +diff --git a/ld/testsuite/ld-i386/call3d.d b/ld/testsuite/ld-i386/call3d.d +index a9274c8..4d965b3 100644 +--- a/ld/testsuite/ld-i386/call3d.d ++++ b/ld/testsuite/ld-i386/call3d.d +@@ -1,5 +1,5 @@ + #source: call3.s +-#as: --32 ++#as: --32 -mrelax-relocations=yes + #ld: -melf_i386 -z call-nop=suffix-nop + #objdump: -dw + +diff --git a/ld/testsuite/ld-i386/call3e.d b/ld/testsuite/ld-i386/call3e.d +index 2876b49..608682c 100644 +--- a/ld/testsuite/ld-i386/call3e.d ++++ b/ld/testsuite/ld-i386/call3e.d +@@ -1,5 +1,5 @@ + #source: call3.s +-#as: --32 ++#as: --32 -mrelax-relocations=yes + #ld: -melf_i386 -z call-nop=prefix-0x67 + #objdump: -dw + +diff --git a/ld/testsuite/ld-i386/call3f.d b/ld/testsuite/ld-i386/call3f.d +index 5ab0cf1..f3a4869 100644 +--- a/ld/testsuite/ld-i386/call3f.d ++++ b/ld/testsuite/ld-i386/call3f.d +@@ -1,5 +1,5 @@ + #source: call3.s +-#as: --32 ++#as: --32 -mrelax-relocations=yes + #ld: -melf_i386 -z call-nop=prefix-0x90 + #objdump: -dw + +diff --git a/ld/testsuite/ld-i386/call3g.d b/ld/testsuite/ld-i386/call3g.d +index 8287770..f3e3f36 100644 +--- a/ld/testsuite/ld-i386/call3g.d ++++ b/ld/testsuite/ld-i386/call3g.d +@@ -1,5 +1,5 @@ + #source: call3.s +-#as: --32 ++#as: --32 -mrelax-relocations=yes + #ld: -melf_i386 -z call-nop=suffix-0x90 + #objdump: -dw + +diff --git a/ld/testsuite/ld-i386/call3h.d b/ld/testsuite/ld-i386/call3h.d +index 83f371a..afd1ce8 100644 +--- a/ld/testsuite/ld-i386/call3h.d ++++ b/ld/testsuite/ld-i386/call3h.d +@@ -1,5 +1,5 @@ + #source: call3.s +-#as: --32 ++#as: --32 -mrelax-relocations=yes + #ld: -melf_i386 -z call-nop=suffix-144 + #objdump: -dw + +diff --git a/ld/testsuite/ld-i386/got1.dd b/ld/testsuite/ld-i386/got1.dd +index e46153d..e6e82de 100644 +--- a/ld/testsuite/ld-i386/got1.dd ++++ b/ld/testsuite/ld-i386/got1.dd +@@ -10,6 +10,8 @@ + [ ]*[a-f0-9]+: ff d0 call \*%eax + [ ]*[a-f0-9]+: [ a-f0-9]+ mov *0x[a-f0-9]+,%eax + [ ]*[a-f0-9]+: ff d0 call \*%eax ++[ ]*[a-f0-9]+: [ a-f0-9]+ call [a-f0-9]+ <__x86.get_pc_thunk.cx> ++[ ]*[a-f0-9]+: [ a-f0-9]+ add \$0x[a-f0-9]+,%ecx + [ ]*[a-f0-9]+: [ a-f0-9]+ lea *0x[a-f0-9]+,%ecx + [ ]*[a-f0-9]+: ff d1 call \*%ecx + [ ]*[a-f0-9]+: 83 ec 0c sub \$0xc,%esp +diff --git a/ld/testsuite/ld-i386/got1a.S b/ld/testsuite/ld-i386/got1a.S +index f3d5330..7a3f7b5 100644 +--- a/ld/testsuite/ld-i386/got1a.S ++++ b/ld/testsuite/ld-i386/got1a.S +@@ -12,10 +12,19 @@ main: + call *%eax + movl plt@GOT, %eax + call *%eax +- movl foo@GOT(%ebx), %ecx ++ call __x86.get_pc_thunk.cx ++ addl $_GLOBAL_OFFSET_TABLE_, %ecx ++ movl foo@GOT(%ecx), %ecx + call *%ecx + subl $12, %esp + pushl $0 + pushl $0 # Push a dummy return address onto stack. + jmp *myexit@GOT + .size main, .-main ++ .section .text.__x86.get_pc_thunk.cx,"axG",@progbits,__x86.get_pc_thunk.cx,comdat ++ .globl __x86.get_pc_thunk.cx ++ .hidden __x86.get_pc_thunk.cx ++ .type __x86.get_pc_thunk.cx, @function ++__x86.get_pc_thunk.cx: ++ movl (%esp), %ecx ++ ret +diff --git a/ld/testsuite/ld-i386/got1d.S b/ld/testsuite/ld-i386/got1d.S +index a6d51c6..7e4c9b1 100644 +--- a/ld/testsuite/ld-i386/got1d.S ++++ b/ld/testsuite/ld-i386/got1d.S +@@ -19,7 +19,6 @@ plt: + pushl %esi + pushl %ebx + call __x86.get_pc_thunk.bx +-1: + addl $_GLOBAL_OFFSET_TABLE_, %ebx + subl $20, %esp + leal __FUNCTION__.1866@GOTOFF(%ebx), %esi +diff --git a/ld/testsuite/ld-i386/i386.exp b/ld/testsuite/ld-i386/i386.exp +index fb1d3ea..0cc9645 100644 +--- a/ld/testsuite/ld-i386/i386.exp ++++ b/ld/testsuite/ld-i386/i386.exp +@@ -319,6 +319,7 @@ run_dump_test "load5a" + run_dump_test "load5b" + run_dump_test "load6" + run_dump_test "pr19175" ++run_dump_test "pr19615" + + if { !([istarget "i?86-*-linux*"] + || [istarget "i?86-*-gnu*"] +@@ -357,7 +358,7 @@ if { [isnative] + [list \ + "Build libplt-main1.a" \ + "" \ +- "-fPIC" \ ++ "-fPIC -Wa,-mrelax-relocations=yes" \ + { plt-main1.c } \ + {{readelf {-Wr} plt-main1.rd}} \ + "libplt-main1.a" \ +@@ -365,7 +366,7 @@ if { [isnative] + [list \ + "Build libplt-main2.a" \ + "" \ +- "-fPIC" \ ++ "-fPIC -Wa,-mrelax-relocations=yes" \ + { plt-main2.c } \ + {{readelf {-Wr} plt-main2.rd}} \ + "libplt-main2.a" \ +@@ -373,7 +374,7 @@ if { [isnative] + [list \ + "Build libplt-main3.a" \ + "" \ +- "-fPIC $PLT_CFLAGS" \ ++ "-fPIC -Wa,-mrelax-relocations=yes $PLT_CFLAGS" \ + { plt-main3.c } \ + {{readelf {-Wr} plt-main3.rd}} \ + "libplt-main3.a" \ +@@ -381,7 +382,7 @@ if { [isnative] + [list \ + "Build libplt-main4.a" \ + "" \ +- "-fPIC $PLT_CFLAGS" \ ++ "-fPIC -Wa,-mrelax-relocations=yes $PLT_CFLAGS" \ + { plt-main4.c } \ + {{readelf {-Wr} plt-main4.rd}} \ + "libplt-main4.a" \ +@@ -535,7 +536,7 @@ if { [isnative] + [list \ + "Build gotpc1" \ + "tmpdir/got1d.so" \ +- "" \ ++ "-Wa,-mrelax-relocations=yes" \ + { got1a.S got1b.c got1c.c } \ + {{objdump {-dw} got1.dd}} \ + "got1" \ +diff --git a/ld/testsuite/ld-i386/jmp1.d b/ld/testsuite/ld-i386/jmp1.d +index 69383b2..e3ebedc 100644 +--- a/ld/testsuite/ld-i386/jmp1.d ++++ b/ld/testsuite/ld-i386/jmp1.d +@@ -1,3 +1,3 @@ +-#as: --32 ++#as: --32 -mrelax-relocations=yes + #ld: -shared -melf_i386 + #error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object +diff --git a/ld/testsuite/ld-i386/jmp2.d b/ld/testsuite/ld-i386/jmp2.d +index 69383b2..e3ebedc 100644 +--- a/ld/testsuite/ld-i386/jmp2.d ++++ b/ld/testsuite/ld-i386/jmp2.d +@@ -1,3 +1,3 @@ +-#as: --32 ++#as: --32 -mrelax-relocations=yes + #ld: -shared -melf_i386 + #error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object +diff --git a/ld/testsuite/ld-i386/lea1c.d b/ld/testsuite/ld-i386/lea1c.d +index dd76258..0c3580d 100644 +--- a/ld/testsuite/ld-i386/lea1c.d ++++ b/ld/testsuite/ld-i386/lea1c.d +@@ -1,5 +1,5 @@ + #source: lea1.s +-#as: --32 ++#as: --32 -mrelax-relocations=yes + #ld: -melf_i386 + #objdump: -dw + +diff --git a/ld/testsuite/ld-i386/load1.d b/ld/testsuite/ld-i386/load1.d +index 062ea18..a252a15 100644 +--- a/ld/testsuite/ld-i386/load1.d ++++ b/ld/testsuite/ld-i386/load1.d +@@ -1,4 +1,4 @@ +-#as: --32 ++#as: --32 -mrelax-relocations=yes + #ld: -melf_i386 + #objdump: -dw --sym + #notarget: i?86-*-nacl* x86_64-*-nacl* +diff --git a/ld/testsuite/ld-i386/load2.d b/ld/testsuite/ld-i386/load2.d +index 87c2509..467fee0 100644 +--- a/ld/testsuite/ld-i386/load2.d ++++ b/ld/testsuite/ld-i386/load2.d +@@ -1,3 +1,3 @@ +-#as: --32 ++#as: --32 -mrelax-relocations=yes + #ld: -melf_i386 -shared + #error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object +diff --git a/ld/testsuite/ld-i386/load3.d b/ld/testsuite/ld-i386/load3.d +index 87c2509..467fee0 100644 +--- a/ld/testsuite/ld-i386/load3.d ++++ b/ld/testsuite/ld-i386/load3.d +@@ -1,3 +1,3 @@ +-#as: --32 ++#as: --32 -mrelax-relocations=yes + #ld: -melf_i386 -shared + #error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object +diff --git a/ld/testsuite/ld-i386/load4a.d b/ld/testsuite/ld-i386/load4a.d +index 3aa56bd..f3f02ea 100644 +--- a/ld/testsuite/ld-i386/load4a.d ++++ b/ld/testsuite/ld-i386/load4a.d +@@ -1,4 +1,4 @@ + #source: load4.s +-#as: --32 ++#as: --32 -mrelax-relocations=yes + #ld: -Bsymbolic -shared -melf_i386 + #error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object +diff --git a/ld/testsuite/ld-i386/load5a.d b/ld/testsuite/ld-i386/load5a.d +index 88c225a..9744316 100644 +--- a/ld/testsuite/ld-i386/load5a.d ++++ b/ld/testsuite/ld-i386/load5a.d +@@ -1,4 +1,4 @@ + #source: load5.s +-#as: --32 ++#as: --32 -mrelax-relocations=yes + #ld: -Bsymbolic -shared -melf_i386 + #error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object +diff --git a/ld/testsuite/ld-i386/mov2b.d b/ld/testsuite/ld-i386/mov2b.d +index ea5dd9b..295a7c5 100644 +--- a/ld/testsuite/ld-i386/mov2b.d ++++ b/ld/testsuite/ld-i386/mov2b.d +@@ -1,5 +1,5 @@ + #source: mov2.s +-#as: --32 ++#as: --32 -mrelax-relocations=yes + #ld: -pie -melf_i386 + #objdump: -dw + +diff --git a/ld/testsuite/ld-i386/mov3.d b/ld/testsuite/ld-i386/mov3.d +index 17da244..4ce5cd8 100644 +--- a/ld/testsuite/ld-i386/mov3.d ++++ b/ld/testsuite/ld-i386/mov3.d +@@ -1,4 +1,4 @@ +-#as: --32 ++#as: --32 -mrelax-relocations=yes + #ld: -melf_i386 + #objdump: -dw + +diff --git a/ld/testsuite/ld-i386/pr19615.d b/ld/testsuite/ld-i386/pr19615.d +new file mode 100644 +index 0000000..86aebd1 +--- /dev/null ++++ b/ld/testsuite/ld-i386/pr19615.d +@@ -0,0 +1,13 @@ ++#as: --32 ++#ld: -pie -Bsymbolic -E -melf_i386 ++#readelf: -r --wide --dyn-syms ++ ++Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 1 entries: ++ Offset Info Type Sym. Value Symbol's Name ++[0-9a-f]+ +[0-9a-f]+ +R_386_RELATIVE + ++ ++Symbol table '.dynsym' contains [0-9]+ entries: ++ Num: Value Size Type Bind Vis Ndx Name ++#... ++[ ]*[a-f0-9]+: [a-f0-9]+ 0 FUNC GLOBAL DEFAULT [a-f0-9]+ xyzzy ++#... +diff --git a/ld/testsuite/ld-i386/pr19615.s b/ld/testsuite/ld-i386/pr19615.s +new file mode 100644 +index 0000000..1d85926 +--- /dev/null ++++ b/ld/testsuite/ld-i386/pr19615.s +@@ -0,0 +1,13 @@ ++ .text ++ .globl _start ++ .type _start, @function ++_start: ++ ret ++ ++ .globl xyzzy /* This symbol should be exported */ ++ .type xyzzy, @function ++xyzzy: ++ ret ++ ++ .section ".xyzzy_ptr","aw",%progbits ++ .dc.a xyzzy +diff --git a/ld/testsuite/ld-ifunc/ifunc-21-x86-64.d b/ld/testsuite/ld-ifunc/ifunc-21-x86-64.d +index 53ccd5a..ae75487 100644 +--- a/ld/testsuite/ld-ifunc/ifunc-21-x86-64.d ++++ b/ld/testsuite/ld-ifunc/ifunc-21-x86-64.d +@@ -1,4 +1,4 @@ +-#as: --64 ++#as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 + #objdump: -dw + #target: x86_64-*-* +diff --git a/ld/testsuite/ld-ifunc/ifunc-22-x86-64.d b/ld/testsuite/ld-ifunc/ifunc-22-x86-64.d +index 53ccd5a..ae75487 100644 +--- a/ld/testsuite/ld-ifunc/ifunc-22-x86-64.d ++++ b/ld/testsuite/ld-ifunc/ifunc-22-x86-64.d +@@ -1,4 +1,4 @@ +-#as: --64 ++#as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 + #objdump: -dw + #target: x86_64-*-* +diff --git a/ld/testsuite/ld-ifunc/ifunc-5r-local-x86-64.d b/ld/testsuite/ld-ifunc/ifunc-5r-local-x86-64.d +index 18021e7..2ce53a9 100644 +--- a/ld/testsuite/ld-ifunc/ifunc-5r-local-x86-64.d ++++ b/ld/testsuite/ld-ifunc/ifunc-5r-local-x86-64.d +@@ -1,5 +1,5 @@ + #source: ifunc-5-local-x86-64.s +-#as: --64 ++#as: --64 -mrelax-relocations=yes + #ld: -r -melf_x86_64 + #readelf: -r --wide + #target: x86_64-*-* +diff --git a/ld/testsuite/ld-x86-64/call1a.d b/ld/testsuite/ld-x86-64/call1a.d +index 2a63b1c..2b131ee 100644 +--- a/ld/testsuite/ld-x86-64/call1a.d ++++ b/ld/testsuite/ld-x86-64/call1a.d +@@ -1,5 +1,5 @@ + #source: call1.s +-#as: --64 ++#as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 + #objdump: -dw + +diff --git a/ld/testsuite/ld-x86-64/call1b.d b/ld/testsuite/ld-x86-64/call1b.d +index e782fa2..e2fef07 100644 +--- a/ld/testsuite/ld-x86-64/call1b.d ++++ b/ld/testsuite/ld-x86-64/call1b.d +@@ -1,5 +1,5 @@ + #source: call1.s +-#as: --64 ++#as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 -z call-nop=prefix-addr + #objdump: -dw + +diff --git a/ld/testsuite/ld-x86-64/call1c.d b/ld/testsuite/ld-x86-64/call1c.d +index d058fc7..7fe8056 100644 +--- a/ld/testsuite/ld-x86-64/call1c.d ++++ b/ld/testsuite/ld-x86-64/call1c.d +@@ -1,5 +1,5 @@ + #source: call1.s +-#as: --64 ++#as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 -z call-nop=prefix-nop + #objdump: -dw + +diff --git a/ld/testsuite/ld-x86-64/call1d.d b/ld/testsuite/ld-x86-64/call1d.d +index 8871cc6..c93756b 100644 +--- a/ld/testsuite/ld-x86-64/call1d.d ++++ b/ld/testsuite/ld-x86-64/call1d.d +@@ -1,5 +1,5 @@ + #source: call1.s +-#as: --64 ++#as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 -z call-nop=suffix-nop + #objdump: -dw + +diff --git a/ld/testsuite/ld-x86-64/call1e.d b/ld/testsuite/ld-x86-64/call1e.d +index 7127f1a..c7c467c 100644 +--- a/ld/testsuite/ld-x86-64/call1e.d ++++ b/ld/testsuite/ld-x86-64/call1e.d +@@ -1,5 +1,5 @@ + #source: call1.s +-#as: --64 ++#as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 -z call-nop=prefix-0x67 + #objdump: -dw + +diff --git a/ld/testsuite/ld-x86-64/call1f.d b/ld/testsuite/ld-x86-64/call1f.d +index 587bade..d0c3f11 100644 +--- a/ld/testsuite/ld-x86-64/call1f.d ++++ b/ld/testsuite/ld-x86-64/call1f.d +@@ -1,5 +1,5 @@ + #source: call1.s +-#as: --64 ++#as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 -z call-nop=prefix-0x90 + #objdump: -dw + +diff --git a/ld/testsuite/ld-x86-64/call1g.d b/ld/testsuite/ld-x86-64/call1g.d +index 3bb512e..6a8d790 100644 +--- a/ld/testsuite/ld-x86-64/call1g.d ++++ b/ld/testsuite/ld-x86-64/call1g.d +@@ -1,5 +1,5 @@ + #source: call1.s +-#as: --64 ++#as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 -z call-nop=suffix-0x90 + #objdump: -dw + +diff --git a/ld/testsuite/ld-x86-64/call1h.d b/ld/testsuite/ld-x86-64/call1h.d +index c7c8dde..f8e1d07 100644 +--- a/ld/testsuite/ld-x86-64/call1h.d ++++ b/ld/testsuite/ld-x86-64/call1h.d +@@ -1,5 +1,5 @@ + #source: call1.s +-#as: --64 ++#as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 -z call-nop=suffix-144 + #objdump: -dw + +diff --git a/ld/testsuite/ld-x86-64/call1i.d b/ld/testsuite/ld-x86-64/call1i.d +index b3684ad..d5a157b 100644 +--- a/ld/testsuite/ld-x86-64/call1i.d ++++ b/ld/testsuite/ld-x86-64/call1i.d +@@ -1,5 +1,5 @@ + #source: call1.s +-#as: --x32 ++#as: --x32 -mrelax-relocations=yes + #ld: -melf32_x86_64 -z call-nop=suffix-0x90 + #objdump: -dw + +diff --git a/ld/testsuite/ld-x86-64/load1a.d b/ld/testsuite/ld-x86-64/load1a.d +index 5c9349e..0eb4880 100644 +--- a/ld/testsuite/ld-x86-64/load1a.d ++++ b/ld/testsuite/ld-x86-64/load1a.d +@@ -1,5 +1,5 @@ + #source: load1.s +-#as: --64 ++#as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 + #objdump: -dw --sym + #notarget: x86_64-*-nacl* +diff --git a/ld/testsuite/ld-x86-64/load1b.d b/ld/testsuite/ld-x86-64/load1b.d +index 70ef274..8827f38 100644 +--- a/ld/testsuite/ld-x86-64/load1b.d ++++ b/ld/testsuite/ld-x86-64/load1b.d +@@ -1,5 +1,5 @@ + #source: load1.s +-#as: --x32 ++#as: --x32 -mrelax-relocations=yes + #ld: -melf32_x86_64 + #objdump: -dw --sym + #notarget: x86_64-*-nacl* +diff --git a/ld/testsuite/ld-x86-64/pr18591.d b/ld/testsuite/ld-x86-64/pr18591.d +new file mode 100644 +index 0000000..9f60622 +--- /dev/null ++++ b/ld/testsuite/ld-x86-64/pr18591.d +@@ -0,0 +1,12 @@ ++#as: --64 ++#ld: -melf_x86_64 -shared -z max-page-size=0x200000 ++#objdump: -dw ++ ++.*: +file format .* ++ ++ ++Disassembly of section .text: ++ ++[a-f0-9]+ : ++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+> ++#pass +diff --git a/ld/testsuite/ld-x86-64/pr18591.s b/ld/testsuite/ld-x86-64/pr18591.s +new file mode 100644 +index 0000000..d726f08 +--- /dev/null ++++ b/ld/testsuite/ld-x86-64/pr18591.s +@@ -0,0 +1,8 @@ ++ .hidden foo ++ .comm pad,0x80000000,8 ++ .comm foo,8,8 ++ .text ++ .globl bar ++ .type bar, @function ++bar: ++ movq foo@GOTPCREL(%rip), %rax +diff --git a/ld/testsuite/ld-x86-64/pr19615.d b/ld/testsuite/ld-x86-64/pr19615.d +new file mode 100644 +index 0000000..f09bcf3 +--- /dev/null ++++ b/ld/testsuite/ld-x86-64/pr19615.d +@@ -0,0 +1,13 @@ ++#as: --64 ++#ld: -pie -Bsymbolic -E -melf_x86_64 ++#readelf: -r --wide --dyn-syms ++ ++Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 1 entries: ++ Offset Info Type Symbol's Value Symbol's Name \+ Addend ++[0-9a-f]+ +[0-9a-f]+ +R_X86_64_RELATIVE +[0-9]+ ++ ++Symbol table '.dynsym' contains [0-9]+ entries: ++ Num: Value Size Type Bind Vis Ndx Name ++#... ++[ ]*[a-f0-9]+: [a-f0-9]+ 0 FUNC GLOBAL DEFAULT [a-f0-9]+ xyzzy ++#... +diff --git a/ld/testsuite/ld-x86-64/pr19615.s b/ld/testsuite/ld-x86-64/pr19615.s +new file mode 100644 +index 0000000..1d85926 +--- /dev/null ++++ b/ld/testsuite/ld-x86-64/pr19615.s +@@ -0,0 +1,13 @@ ++ .text ++ .globl _start ++ .type _start, @function ++_start: ++ ret ++ ++ .globl xyzzy /* This symbol should be exported */ ++ .type xyzzy, @function ++xyzzy: ++ ret ++ ++ .section ".xyzzy_ptr","aw",%progbits ++ .dc.a xyzzy +diff --git a/ld/testsuite/ld-x86-64/x86-64.exp b/ld/testsuite/ld-x86-64/x86-64.exp +index 45b7f09..90f856c 100644 +--- a/ld/testsuite/ld-x86-64/x86-64.exp ++++ b/ld/testsuite/ld-x86-64/x86-64.exp +@@ -353,6 +353,8 @@ run_dump_test "pr19013-x32" + run_dump_test "pr19013-nacl" + run_dump_test "pr19162" + run_dump_test "pr19175" ++run_dump_test "pr18591" ++run_dump_test "pr19615" + + # Add $PLT_CFLAGS if PLT is expected. + global PLT_CFLAGS +@@ -391,7 +393,7 @@ if { [isnative] && [which $CC] != 0 } { + [list \ + "Build libplt-main1.a" \ + "" \ +- "-fPIC" \ ++ "-fPIC -Wa,-mrelax-relocations=yes" \ + { plt-main1.c } \ + {{readelf {-Wr} plt-main1.rd}} \ + "libplt-main1.a" \ +@@ -399,7 +401,7 @@ if { [isnative] && [which $CC] != 0 } { + [list \ + "Build libplt-main2.a" \ + "" \ +- "-fPIC" \ ++ "-fPIC -Wa,-mrelax-relocations=yes" \ + { plt-main2.c } \ + {{readelf {-Wr} plt-main2.rd}} \ + "libplt-main2.a" \ +@@ -407,7 +409,7 @@ if { [isnative] && [which $CC] != 0 } { + [list \ + "Build libplt-main3.a" \ + "" \ +- "-fPIC $PLT_CFLAGS" \ ++ "-fPIC -Wa,-mrelax-relocations=yes $PLT_CFLAGS" \ + { plt-main3.c } \ + {{readelf {-Wr} plt-main3.rd}} \ + "libplt-main3.a" \ +@@ -415,7 +417,7 @@ if { [isnative] && [which $CC] != 0 } { + [list \ + "Build libplt-main4.a" \ + "" \ +- "-fPIC $PLT_CFLAGS" \ ++ "-fPIC -Wa,-mrelax-relocations=yes $PLT_CFLAGS" \ + { plt-main4.c } \ + {{readelf {-Wr} plt-main4.rd}} \ + "libplt-main4.a" \ +@@ -545,7 +547,7 @@ if { [isnative] && [which $CC] != 0 } { + [list \ + "Build gotpcrel1" \ + "tmpdir/gotpcrel1d.so" \ +- "" \ ++ "-Wa,-mrelax-relocations=yes" \ + { gotpcrel1a.S gotpcrel1b.c gotpcrel1c.c } \ + {{objdump {-dw} gotpcrel1.dd}} \ + "gotpcrel1" \ +diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog +index 726335d..e7f539a 100644 +--- a/opcodes/ChangeLog ++++ b/opcodes/ChangeLog +@@ -1,3 +1,24 @@ ++2016-02-26 Alan Modra ++ ++ Apply from master. ++ 2015-12-12 Alan Modra ++ PR 19359 ++ * ppc-opc.c (insert_fxm): Remove "ignored" from error message. ++ (powerpc_opcodes): Remove single-operand mfcr. ++ ++2016-02-15 H.J. Lu ++ ++ Backport from master ++ 2016-02-15 H.J. Lu ++ ++ * i386-dis.c (print_insn): Parenthesize expression to prevent ++ truncated addresses. ++ (OP_J): Likewise. ++ ++2016-01-25 Tristan Gingold ++ ++ * configure: Regenerate. ++ + 2016-01-25 Tristan Gingold + + * configure: Regenerate. +@@ -810,7 +831,7 @@ + + 2015-05-11 H.J. Lu + +- * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit ++ * i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit + direct branch. + (jmp): Likewise. + * i386-tbl.h: Regenerated. +diff --git a/opcodes/configure b/opcodes/configure +index 3be129b..eedb184 100755 +--- a/opcodes/configure ++++ b/opcodes/configure +@@ -1,6 +1,6 @@ + #! /bin/sh + # Guess values for system-dependent variables and create Makefiles. +-# Generated by GNU Autoconf 2.64 for opcodes 2.26. ++# Generated by GNU Autoconf 2.64 for opcodes 2.26.0. + # + # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, + # 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software +@@ -556,8 +556,8 @@ MAKEFLAGS= + # Identity of this package. + PACKAGE_NAME='opcodes' + PACKAGE_TARNAME='opcodes' +-PACKAGE_VERSION='2.26' +-PACKAGE_STRING='opcodes 2.26' ++PACKAGE_VERSION='2.26.0' ++PACKAGE_STRING='opcodes 2.26.0' + PACKAGE_BUGREPORT='' + PACKAGE_URL='' + +@@ -1319,7 +1319,7 @@ if test "$ac_init_help" = "long"; then + # Omit some internal or obsolete options to make the list less imposing. + # This message is too long to be a string in the A/UX 3.1 sh. + cat <<_ACEOF +-\`configure' configures opcodes 2.26 to adapt to many kinds of systems. ++\`configure' configures opcodes 2.26.0 to adapt to many kinds of systems. + + Usage: $0 [OPTION]... [VAR=VALUE]... + +@@ -1390,7 +1390,7 @@ fi + + if test -n "$ac_init_help"; then + case $ac_init_help in +- short | recursive ) echo "Configuration of opcodes 2.26:";; ++ short | recursive ) echo "Configuration of opcodes 2.26.0:";; + esac + cat <<\_ACEOF + +@@ -1497,7 +1497,7 @@ fi + test -n "$ac_init_help" && exit $ac_status + if $ac_init_version; then + cat <<\_ACEOF +-opcodes configure 2.26 ++opcodes configure 2.26.0 + generated by GNU Autoconf 2.64 + + Copyright (C) 2009 Free Software Foundation, Inc. +@@ -1907,7 +1907,7 @@ cat >config.log <<_ACEOF + This file contains any messages produced by compilers while + running configure, to aid debugging if configure makes a mistake. + +-It was created by opcodes $as_me 2.26, which was ++It was created by opcodes $as_me 2.26.0, which was + generated by GNU Autoconf 2.64. Invocation command line was + + $ $0 $@ +@@ -3715,7 +3715,7 @@ fi + + # Define the identity of the package. + PACKAGE='opcodes' +- VERSION='2.26' ++ VERSION='2.26.0' + + + cat >>confdefs.h <<_ACEOF +@@ -13223,7 +13223,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + # report actual input values of CONFIG_FILES etc. instead of their + # values after options handling. + ac_log=" +-This file was extended by opcodes $as_me 2.26, which was ++This file was extended by opcodes $as_me 2.26.0, which was + generated by GNU Autoconf 2.64. Invocation command line was + + CONFIG_FILES = $CONFIG_FILES +@@ -13287,7 +13287,7 @@ Report bugs to the package provider." + _ACEOF + cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 + ac_cs_version="\\ +-opcodes config.status 2.26 ++opcodes config.status 2.26.0 + configured by $0, generated by GNU Autoconf 2.64, + with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" + +diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c +index 1b4c51a..3712b59 100644 +--- a/opcodes/i386-dis.c ++++ b/opcodes/i386-dis.c +@@ -13644,7 +13644,7 @@ print_insn (bfd_vma pc, disassemble_info *info) + if (op_index[i] != -1 && op_riprel[i]) + { + (*info->fprintf_func) (info->stream, " # "); +- (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep ++ (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) + + op_address[op_index[i]]), info); + break; + } +@@ -16158,7 +16158,7 @@ OP_J (int bytemode, int sizeflag) + the displacement is added! */ + mask = 0xffff; + if ((prefixes & PREFIX_DATA) == 0) +- segment = ((start_pc + codep - start_codep) ++ segment = ((start_pc + (codep - start_codep)) + & ~((bfd_vma) 0xffff)); + } + if (address_mode != mode_64bit +diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c +index e8c92f6..9b25b60 100644 +--- a/opcodes/ppc-opc.c ++++ b/opcodes/ppc-opc.c +@@ -1434,7 +1434,7 @@ insert_fxm (unsigned long insn, + /* A value of -1 means we used the one operand form of + mfcr which is valid. */ + if (value != -1) +- *errmsg = _("ignoring invalid mfcr mask"); ++ *errmsg = _("invalid mfcr mask"); + value = 0; + } + +@@ -4742,8 +4742,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { + {"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, PPCNONE, {RA0, RB}}, + {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, PPCNONE, {T, RA0, RB}}, + +-{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, PPCNONE, {RT, FXM4}}, +-{"mfcr", XFXM(31,19,0,0), XRARB_MASK, COM|PPCVLE, POWER4, {RT}}, ++{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {RT, FXM4}}, + {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {RT, FXM}}, + + {"lwarx", X(31,20), XEH_MASK, PPC|PPCVLE, PPCNONE, {RT, RA0, RB, EH}}, diff --git a/binutils-2.26.tar.bz2 b/binutils-2.26.tar.bz2 new file mode 100644 index 0000000..4ef8989 --- /dev/null +++ b/binutils-2.26.tar.bz2 @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c2ace41809542f5237afc7e3b8f32bb92bc7bc53c6232a84463c423b0714ecd9 +size 25543552 diff --git a/binutils-build-as-needed.diff b/binutils-build-as-needed.diff index 3f1401c..6567673 100644 --- a/binutils-build-as-needed.diff +++ b/binutils-build-as-needed.diff @@ -1,11 +1,11 @@ Index: ld/ldmain.c =================================================================== ---- ld/ldmain.c.orig 2012-09-14 14:10:47.347146972 +0200 -+++ ld/ldmain.c 2012-09-14 14:20:50.004126111 +0200 -@@ -290,6 +290,8 @@ main (int argc, char **argv) - link_info.pei386_auto_import = -1; - link_info.spare_dynamic_tags = 5; - link_info.path_separator = ':'; +--- ld/ldmain.c.orig 2016-01-27 13:44:14.092983985 +0100 ++++ ld/ldmain.c 2016-01-27 13:44:37.389254054 +0100 +@@ -286,6 +286,8 @@ main (int argc, char **argv) + #ifdef DEFAULT_FLAG_COMPRESS_DEBUG + link_info.compress_debug = COMPRESS_DEBUG_GABI_ZLIB; + #endif + if (getenv ("SUSE_ASNEEDED") && atoi(getenv ("SUSE_ASNEEDED")) > 0) + input_flags.add_DT_NEEDED_for_regular = TRUE; diff --git a/binutils-fix--dynamic-list.patch b/binutils-fix--dynamic-list.patch deleted file mode 100644 index e69f0eb..0000000 --- a/binutils-fix--dynamic-list.patch +++ /dev/null @@ -1,127 +0,0 @@ -From e9c1bdad269c0c3352eebcc9481ed65144001b0b Mon Sep 17 00:00:00 2001 -From: Cary Coutant -Date: Mon, 16 Feb 2015 22:15:12 -0800 -Subject: [PATCH] Fix --dynamic-list so that symbols not in the list are still - exported. - -In PR 13577, the complaint was that -Bsymbolic was overriding the binding -behavior for symbols listed in the --dynamic-list by setting the DT_SYMBOLIC -tag in the dynamic table. In reading the Gnu ld manual, I decided that ---dynamic-list should be mutually exclusive of -Bsymbolic, and modified -gold so that --dynamic-list would treat symbols listed as preemptible, -and all other symbols as internally bound. I was wrong. - -PR 16992 shows that with --dynamic-list (and not -Bsymbolic), a symbol -not listed in the dynamic list is being internally bound within the -shared library, but because it's still in the dynamic symbol table, we -expose it to a COPY relocation, and things go really bad from there. - -(I can reproduce the same failure, simply by turning on -Bsymbolic-functions -with the Gnu linker. Even though the symbol is bound internally, it's -still exported to the dynamic symbol table, and is exposed to a COPY -relocation.) - -I've backed out part of the fix for PR 13577, and -Bsymbolic (or --Bsymbolic-functions) can now be used with --dynamic-list, but if the -two are used together, we do not set DT_SYMBOLIC or DF_SYMBOLIC -(this matches Gnu ld behavior). We now treat symbols listed in the -dynamic list as premptible, but we do not automatically treat symbols -not listed there as non-premptible. - -gold/ - PR gold/13577 - PR gold/16992 - * layout.cc (Layout::finish_dynamic_section): Don't set DT_SYMBOLIC or - DF_SYMBOLIC if --dynamic-list option is used. - * options.cc (General_options::finalize): --dynamic-list is not - mutually exclusive with -Bsymbolic. - * symtab.h (Symbol::is_preemptible): Don't exclude dynamic symbols not - listed in --dynamic-list. - * testsuite/Makefile.am (dynamic_list_lib2.so): Add - -Bsymbolic-functions. - * testsuite/Makefile.in: Regenerate. ---- - gold/layout.cc | 3 ++- - gold/options.cc | 7 ------- - gold/symtab.h | 6 ++---- - gold/testsuite/Makefile.am | 2 +- - gold/testsuite/Makefile.in | 2 +- - 5 files changed, 6 insertions(+), 14 deletions(-) - -diff --git a/gold/layout.cc b/gold/layout.cc -index bcdaac8..7836640 100644 ---- a/gold/layout.cc -+++ b/gold/layout.cc -@@ -4873,7 +4873,8 @@ Layout::finish_dynamic_section(const Input_objects* input_objects, - flags |= elfcpp::DF_STATIC_TLS; - if (parameters->options().origin()) - flags |= elfcpp::DF_ORIGIN; -- if (parameters->options().Bsymbolic()) -+ if (parameters->options().Bsymbolic() -+ && !parameters->options().have_dynamic_list()) - { - flags |= elfcpp::DF_SYMBOLIC; - // Add DT_SYMBOLIC for compatibility with older loaders. -diff --git a/gold/options.cc b/gold/options.cc -index 7eb8f27..7f1f69e 100644 ---- a/gold/options.cc -+++ b/gold/options.cc -@@ -1200,13 +1200,6 @@ General_options::finalize() - // in the path, as appropriate. - this->add_sysroot(); - -- // --dynamic-list overrides -Bsymbolic and -Bsymbolic-functions. -- if (this->have_dynamic_list()) -- { -- this->set_Bsymbolic(false); -- this->set_Bsymbolic_functions(false); -- } -- - // Now that we've normalized the options, check for contradictory ones. - if (this->shared() && this->is_static()) - gold_fatal(_("-shared and -static are incompatible")); -diff --git a/gold/symtab.h b/gold/symtab.h -index aa0cb68..9413360 100644 ---- a/gold/symtab.h -+++ b/gold/symtab.h -@@ -604,10 +604,8 @@ class Symbol - if (parameters->options().in_dynamic_list(this->name())) - return true; - -- // If the user used -Bsymbolic or provided a --dynamic-list script, -- // then nothing (else) is preemptible. -- if (parameters->options().Bsymbolic() -- || parameters->options().have_dynamic_list()) -+ // If the user used -Bsymbolic, then nothing (else) is preemptible. -+ if (parameters->options().Bsymbolic()) - return false; - - // If the user used -Bsymbolic-functions, then functions are not -diff --git a/gold/testsuite/Makefile.am b/gold/testsuite/Makefile.am -index f767c21..7b73f9d 100644 ---- a/gold/testsuite/Makefile.am -+++ b/gold/testsuite/Makefile.am -@@ -1518,7 +1518,7 @@ dynamic_list_lib1.o: dynamic_list_lib1.cc - $(CXXCOMPILE) -c -fpic -o $@ $< - - dynamic_list_lib2.so: gcctestdir/ld dynamic_list_lib2.o $(srcdir)/dynamic_list_2.t -- $(CXXLINK) -Bgcctestdir/ -shared -Wl,--dynamic-list,$(srcdir)/dynamic_list_2.t dynamic_list_lib2.o -+ $(CXXLINK) -Bgcctestdir/ -shared -Wl,-Bsymbolic-functions -Wl,--dynamic-list,$(srcdir)/dynamic_list_2.t dynamic_list_lib2.o - dynamic_list_lib2.o: dynamic_list_lib2.cc - $(CXXCOMPILE) -c -fpic -o $@ $< - -diff --git a/gold/testsuite/Makefile.in b/gold/testsuite/Makefile.in -index 217e472..b4ae3fd 100644 ---- a/gold/testsuite/Makefile.in -+++ b/gold/testsuite/Makefile.in -@@ -5319,7 +5319,7 @@ uninstall-am: - @GCC_TRUE@@NATIVE_LINKER_TRUE@ $(CXXCOMPILE) -c -fpic -o $@ $< - - @GCC_TRUE@@NATIVE_LINKER_TRUE@dynamic_list_lib2.so: gcctestdir/ld dynamic_list_lib2.o $(srcdir)/dynamic_list_2.t --@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(CXXLINK) -Bgcctestdir/ -shared -Wl,--dynamic-list,$(srcdir)/dynamic_list_2.t dynamic_list_lib2.o -+@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(CXXLINK) -Bgcctestdir/ -shared -Wl,-Bsymbolic-functions -Wl,--dynamic-list,$(srcdir)/dynamic_list_2.t dynamic_list_lib2.o - @GCC_TRUE@@NATIVE_LINKER_TRUE@dynamic_list_lib2.o: dynamic_list_lib2.cc - @GCC_TRUE@@NATIVE_LINKER_TRUE@ $(CXXCOMPILE) -c -fpic -o $@ $< - --- -1.9.4 diff --git a/binutils-fix-gold-aarch64.diff b/binutils-fix-gold-aarch64.diff deleted file mode 100644 index 8b00df2..0000000 --- a/binutils-fix-gold-aarch64.diff +++ /dev/null @@ -1,12 +0,0 @@ -Index: gold/configure.tgt -=================================================================== ---- gold/configure.tgt.orig 2014-12-01 16:37:19.000000000 +0100 -+++ gold/configure.tgt 2014-12-01 17:00:55.000000000 +0100 -@@ -146,6 +146,7 @@ arm*-*-*) - ;; - aarch64*-*) - targ_obj=aarch64 -+ targ_extra_obj=aarch64-reloc-property - targ_machine=EM_AARCH64 - targ_size=64 - targ_extra_size=32 diff --git a/binutils.changes b/binutils.changes index 6a12f9b..febad5b 100644 --- a/binutils.changes +++ b/binutils.changes @@ -1,3 +1,60 @@ +------------------------------------------------------------------- +Mon Feb 29 12:49:50 UTC 2016 - rguenther@suse.com + +- Add binutils-2.26-branch.diff, updates to branch head. + * Adds -mrelax-relocations on x86 + * Fixes bso#19698 + +------------------------------------------------------------------- +Mon Feb 1 09:03:02 UTC 2016 - rguenther@suse.com + +- Refresh cross-avr-nesc-as.patch + +------------------------------------------------------------------- +Wed Jan 27 13:12:17 UTC 2016 - rguenther@suse.com + +- Update to binutils 2.26 + * Add --fix-stm32l4xx-629360 to the ARM linker to enable a link-time + workaround for a bug in the bus matrix / memory controller for some of + the STM32 Cortex-M4 based products (STM32L4xx) + * Add a configure option --enable-compressed-debug-sections={all,ld} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Experimental support for linker garbage collection (--gc-sections) + has been enabled for COFF and PE based targets. + * New command line option for ELF targets to compress DWARF debug + sections, --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. + * New command line option, --orphan-handling=[place|warn|error|discard], to + adjust how orphan sections are handled. The default is 'place' which gives + the current behaviour, 'warn' and 'error' issue a warning or error + respectively when orphan sections are found, and 'discard' will discard all + orphan sections. + * Add support for LLVM plugin. + * Add --print-memory-usage option to report memory blocks usage. + * Add --require-defined option, it's like --undefined except the new symbol + must be defined by the end of the link. + * Add a configure option --enable-compressed-debug-sections={all,gas} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + * Add option to objcopy to insert new symbols into a file: + --add-symbol =[
:][,] + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Extend objcopy --compress-debug-sections option to support + --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF + targets. + * Add --update-section option to objcopy. + * Add --output-separator option to strings. +- Includes z13 support, remove 0001-S-390-Add-support-for-IBM-z13.patch, + 0002-S-390-Add-check-for-length-field-operand.patch, + 0003-S-390-Add-more-IBM-z13-instructions.patch, + 0004-S-390-Fixes-for-z13-instructions.patch and + 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch +- Includes fixes in binutils-fix--dynamic-list.patch, + binutils-fix-gold-aarch64.diff, gold-arm64-abi-pagesize.patch + and s390-troo-insn-type.patch +- Refresh s390-pic-dso.diff and binutils-build-as-needed.diff + ------------------------------------------------------------------- Wed Jan 13 08:31:17 UTC 2016 - schwab@suse.de diff --git a/binutils.spec b/binutils.spec index df8fa8a..32e71f2 100644 --- a/binutils.spec +++ b/binutils.spec @@ -35,7 +35,7 @@ BuildRequires: zlib-devel-static %else BuildRequires: zlib-devel %endif -Version: 2.25.0 +Version: 2.26 Release: 0 # # RUN_TESTS @@ -82,7 +82,7 @@ Source: binutils-%{binutils_version}.tar.bz2 Source1: pre_checkin.sh Source2: README.First-for.SuSE.packagers Source3: baselibs.conf -Patch1: binutils-2.25-branch.diff.gz +Patch: binutils-2.26-branch.diff Patch3: binutils-skip-rpaths.patch Patch4: s390-biarch.diff Patch5: x86-64-biarch.patch @@ -96,15 +96,6 @@ Patch12: s390-pic-dso.diff Patch14: binutils-build-as-needed.diff Patch18: gold-depend-on-opcodes.diff Patch22: binutils-bfd_h.patch -Patch23: binutils-fix-gold-aarch64.diff -Patch26: binutils-fix--dynamic-list.patch -Patch27: 0001-S-390-Add-support-for-IBM-z13.patch -Patch28: 0002-S-390-Add-check-for-length-field-operand.patch -Patch29: 0003-S-390-Add-more-IBM-z13-instructions.patch -Patch30: 0004-S-390-Fixes-for-z13-instructions.patch -Patch31: 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch -Patch32: gold-arm64-abi-pagesize.patch -Patch33: s390-troo-insn-type.patch Patch34: aarch64-common-pagesize.patch Patch35: gold-relocate-tls.patch Patch90: cross-avr-nesc-as.patch @@ -162,8 +153,8 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa %setup -q -n binutils-%{binutils_version} # Patch1 is outside test_vanilla because it's supposed to be the # patch bringing the tarball to the newest upstream version -%patch1 -p1 %if !%{test_vanilla} +%patch -p1 %patch3 %patch4 %patch5 @@ -176,20 +167,11 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa # The MIPS ABI is incompatible with .gnu.hash, so don't # use it there %patch11 -%endif %patch12 +%endif %patch14 %patch18 %patch22 -%patch23 -%patch26 -p1 -%patch27 -p1 -%patch28 -p1 -%patch29 -p1 -%patch30 -p1 -%patch31 -p1 -%patch32 -p1 -%patch33 -p1 %patch34 -p1 %patch35 -p1 %if "%{TARGET}" == "avr" diff --git a/cross-aarch64-binutils.changes b/cross-aarch64-binutils.changes index 6a12f9b..febad5b 100644 --- a/cross-aarch64-binutils.changes +++ b/cross-aarch64-binutils.changes @@ -1,3 +1,60 @@ +------------------------------------------------------------------- +Mon Feb 29 12:49:50 UTC 2016 - rguenther@suse.com + +- Add binutils-2.26-branch.diff, updates to branch head. + * Adds -mrelax-relocations on x86 + * Fixes bso#19698 + +------------------------------------------------------------------- +Mon Feb 1 09:03:02 UTC 2016 - rguenther@suse.com + +- Refresh cross-avr-nesc-as.patch + +------------------------------------------------------------------- +Wed Jan 27 13:12:17 UTC 2016 - rguenther@suse.com + +- Update to binutils 2.26 + * Add --fix-stm32l4xx-629360 to the ARM linker to enable a link-time + workaround for a bug in the bus matrix / memory controller for some of + the STM32 Cortex-M4 based products (STM32L4xx) + * Add a configure option --enable-compressed-debug-sections={all,ld} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Experimental support for linker garbage collection (--gc-sections) + has been enabled for COFF and PE based targets. + * New command line option for ELF targets to compress DWARF debug + sections, --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. + * New command line option, --orphan-handling=[place|warn|error|discard], to + adjust how orphan sections are handled. The default is 'place' which gives + the current behaviour, 'warn' and 'error' issue a warning or error + respectively when orphan sections are found, and 'discard' will discard all + orphan sections. + * Add support for LLVM plugin. + * Add --print-memory-usage option to report memory blocks usage. + * Add --require-defined option, it's like --undefined except the new symbol + must be defined by the end of the link. + * Add a configure option --enable-compressed-debug-sections={all,gas} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + * Add option to objcopy to insert new symbols into a file: + --add-symbol =[
:][,] + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Extend objcopy --compress-debug-sections option to support + --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF + targets. + * Add --update-section option to objcopy. + * Add --output-separator option to strings. +- Includes z13 support, remove 0001-S-390-Add-support-for-IBM-z13.patch, + 0002-S-390-Add-check-for-length-field-operand.patch, + 0003-S-390-Add-more-IBM-z13-instructions.patch, + 0004-S-390-Fixes-for-z13-instructions.patch and + 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch +- Includes fixes in binutils-fix--dynamic-list.patch, + binutils-fix-gold-aarch64.diff, gold-arm64-abi-pagesize.patch + and s390-troo-insn-type.patch +- Refresh s390-pic-dso.diff and binutils-build-as-needed.diff + ------------------------------------------------------------------- Wed Jan 13 08:31:17 UTC 2016 - schwab@suse.de diff --git a/cross-aarch64-binutils.spec b/cross-aarch64-binutils.spec index 12534b8..5fb082f 100644 --- a/cross-aarch64-binutils.spec +++ b/cross-aarch64-binutils.spec @@ -38,7 +38,7 @@ BuildRequires: zlib-devel-static %else BuildRequires: zlib-devel %endif -Version: 2.25.0 +Version: 2.26 Release: 0 # # RUN_TESTS @@ -85,7 +85,7 @@ Source: binutils-%{binutils_version}.tar.bz2 Source1: pre_checkin.sh Source2: README.First-for.SuSE.packagers Source3: baselibs.conf -Patch1: binutils-2.25-branch.diff.gz +Patch: binutils-2.26-branch.diff Patch3: binutils-skip-rpaths.patch Patch4: s390-biarch.diff Patch5: x86-64-biarch.patch @@ -99,15 +99,6 @@ Patch12: s390-pic-dso.diff Patch14: binutils-build-as-needed.diff Patch18: gold-depend-on-opcodes.diff Patch22: binutils-bfd_h.patch -Patch23: binutils-fix-gold-aarch64.diff -Patch26: binutils-fix--dynamic-list.patch -Patch27: 0001-S-390-Add-support-for-IBM-z13.patch -Patch28: 0002-S-390-Add-check-for-length-field-operand.patch -Patch29: 0003-S-390-Add-more-IBM-z13-instructions.patch -Patch30: 0004-S-390-Fixes-for-z13-instructions.patch -Patch31: 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch -Patch32: gold-arm64-abi-pagesize.patch -Patch33: s390-troo-insn-type.patch Patch34: aarch64-common-pagesize.patch Patch35: gold-relocate-tls.patch Patch90: cross-avr-nesc-as.patch @@ -165,8 +156,8 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa %setup -q -n binutils-%{binutils_version} # Patch1 is outside test_vanilla because it's supposed to be the # patch bringing the tarball to the newest upstream version -%patch1 -p1 %if !%{test_vanilla} +%patch -p1 %patch3 %patch4 %patch5 @@ -179,20 +170,11 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa # The MIPS ABI is incompatible with .gnu.hash, so don't # use it there %patch11 -%endif %patch12 +%endif %patch14 %patch18 %patch22 -%patch23 -%patch26 -p1 -%patch27 -p1 -%patch28 -p1 -%patch29 -p1 -%patch30 -p1 -%patch31 -p1 -%patch32 -p1 -%patch33 -p1 %patch34 -p1 %patch35 -p1 %if "%{TARGET}" == "avr" diff --git a/cross-arm-binutils.changes b/cross-arm-binutils.changes index 6a12f9b..febad5b 100644 --- a/cross-arm-binutils.changes +++ b/cross-arm-binutils.changes @@ -1,3 +1,60 @@ +------------------------------------------------------------------- +Mon Feb 29 12:49:50 UTC 2016 - rguenther@suse.com + +- Add binutils-2.26-branch.diff, updates to branch head. + * Adds -mrelax-relocations on x86 + * Fixes bso#19698 + +------------------------------------------------------------------- +Mon Feb 1 09:03:02 UTC 2016 - rguenther@suse.com + +- Refresh cross-avr-nesc-as.patch + +------------------------------------------------------------------- +Wed Jan 27 13:12:17 UTC 2016 - rguenther@suse.com + +- Update to binutils 2.26 + * Add --fix-stm32l4xx-629360 to the ARM linker to enable a link-time + workaround for a bug in the bus matrix / memory controller for some of + the STM32 Cortex-M4 based products (STM32L4xx) + * Add a configure option --enable-compressed-debug-sections={all,ld} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Experimental support for linker garbage collection (--gc-sections) + has been enabled for COFF and PE based targets. + * New command line option for ELF targets to compress DWARF debug + sections, --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. + * New command line option, --orphan-handling=[place|warn|error|discard], to + adjust how orphan sections are handled. The default is 'place' which gives + the current behaviour, 'warn' and 'error' issue a warning or error + respectively when orphan sections are found, and 'discard' will discard all + orphan sections. + * Add support for LLVM plugin. + * Add --print-memory-usage option to report memory blocks usage. + * Add --require-defined option, it's like --undefined except the new symbol + must be defined by the end of the link. + * Add a configure option --enable-compressed-debug-sections={all,gas} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + * Add option to objcopy to insert new symbols into a file: + --add-symbol =[
:][,] + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Extend objcopy --compress-debug-sections option to support + --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF + targets. + * Add --update-section option to objcopy. + * Add --output-separator option to strings. +- Includes z13 support, remove 0001-S-390-Add-support-for-IBM-z13.patch, + 0002-S-390-Add-check-for-length-field-operand.patch, + 0003-S-390-Add-more-IBM-z13-instructions.patch, + 0004-S-390-Fixes-for-z13-instructions.patch and + 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch +- Includes fixes in binutils-fix--dynamic-list.patch, + binutils-fix-gold-aarch64.diff, gold-arm64-abi-pagesize.patch + and s390-troo-insn-type.patch +- Refresh s390-pic-dso.diff and binutils-build-as-needed.diff + ------------------------------------------------------------------- Wed Jan 13 08:31:17 UTC 2016 - schwab@suse.de diff --git a/cross-arm-binutils.spec b/cross-arm-binutils.spec index 24126b3..4f44c97 100644 --- a/cross-arm-binutils.spec +++ b/cross-arm-binutils.spec @@ -38,7 +38,7 @@ BuildRequires: zlib-devel-static %else BuildRequires: zlib-devel %endif -Version: 2.25.0 +Version: 2.26 Release: 0 # # RUN_TESTS @@ -85,7 +85,7 @@ Source: binutils-%{binutils_version}.tar.bz2 Source1: pre_checkin.sh Source2: README.First-for.SuSE.packagers Source3: baselibs.conf -Patch1: binutils-2.25-branch.diff.gz +Patch: binutils-2.26-branch.diff Patch3: binutils-skip-rpaths.patch Patch4: s390-biarch.diff Patch5: x86-64-biarch.patch @@ -99,15 +99,6 @@ Patch12: s390-pic-dso.diff Patch14: binutils-build-as-needed.diff Patch18: gold-depend-on-opcodes.diff Patch22: binutils-bfd_h.patch -Patch23: binutils-fix-gold-aarch64.diff -Patch26: binutils-fix--dynamic-list.patch -Patch27: 0001-S-390-Add-support-for-IBM-z13.patch -Patch28: 0002-S-390-Add-check-for-length-field-operand.patch -Patch29: 0003-S-390-Add-more-IBM-z13-instructions.patch -Patch30: 0004-S-390-Fixes-for-z13-instructions.patch -Patch31: 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch -Patch32: gold-arm64-abi-pagesize.patch -Patch33: s390-troo-insn-type.patch Patch34: aarch64-common-pagesize.patch Patch35: gold-relocate-tls.patch Patch90: cross-avr-nesc-as.patch @@ -165,8 +156,8 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa %setup -q -n binutils-%{binutils_version} # Patch1 is outside test_vanilla because it's supposed to be the # patch bringing the tarball to the newest upstream version -%patch1 -p1 %if !%{test_vanilla} +%patch -p1 %patch3 %patch4 %patch5 @@ -179,20 +170,11 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa # The MIPS ABI is incompatible with .gnu.hash, so don't # use it there %patch11 -%endif %patch12 +%endif %patch14 %patch18 %patch22 -%patch23 -%patch26 -p1 -%patch27 -p1 -%patch28 -p1 -%patch29 -p1 -%patch30 -p1 -%patch31 -p1 -%patch32 -p1 -%patch33 -p1 %patch34 -p1 %patch35 -p1 %if "%{TARGET}" == "avr" diff --git a/cross-avr-binutils.changes b/cross-avr-binutils.changes index 6a12f9b..febad5b 100644 --- a/cross-avr-binutils.changes +++ b/cross-avr-binutils.changes @@ -1,3 +1,60 @@ +------------------------------------------------------------------- +Mon Feb 29 12:49:50 UTC 2016 - rguenther@suse.com + +- Add binutils-2.26-branch.diff, updates to branch head. + * Adds -mrelax-relocations on x86 + * Fixes bso#19698 + +------------------------------------------------------------------- +Mon Feb 1 09:03:02 UTC 2016 - rguenther@suse.com + +- Refresh cross-avr-nesc-as.patch + +------------------------------------------------------------------- +Wed Jan 27 13:12:17 UTC 2016 - rguenther@suse.com + +- Update to binutils 2.26 + * Add --fix-stm32l4xx-629360 to the ARM linker to enable a link-time + workaround for a bug in the bus matrix / memory controller for some of + the STM32 Cortex-M4 based products (STM32L4xx) + * Add a configure option --enable-compressed-debug-sections={all,ld} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Experimental support for linker garbage collection (--gc-sections) + has been enabled for COFF and PE based targets. + * New command line option for ELF targets to compress DWARF debug + sections, --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. + * New command line option, --orphan-handling=[place|warn|error|discard], to + adjust how orphan sections are handled. The default is 'place' which gives + the current behaviour, 'warn' and 'error' issue a warning or error + respectively when orphan sections are found, and 'discard' will discard all + orphan sections. + * Add support for LLVM plugin. + * Add --print-memory-usage option to report memory blocks usage. + * Add --require-defined option, it's like --undefined except the new symbol + must be defined by the end of the link. + * Add a configure option --enable-compressed-debug-sections={all,gas} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + * Add option to objcopy to insert new symbols into a file: + --add-symbol =[
:][,] + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Extend objcopy --compress-debug-sections option to support + --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF + targets. + * Add --update-section option to objcopy. + * Add --output-separator option to strings. +- Includes z13 support, remove 0001-S-390-Add-support-for-IBM-z13.patch, + 0002-S-390-Add-check-for-length-field-operand.patch, + 0003-S-390-Add-more-IBM-z13-instructions.patch, + 0004-S-390-Fixes-for-z13-instructions.patch and + 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch +- Includes fixes in binutils-fix--dynamic-list.patch, + binutils-fix-gold-aarch64.diff, gold-arm64-abi-pagesize.patch + and s390-troo-insn-type.patch +- Refresh s390-pic-dso.diff and binutils-build-as-needed.diff + ------------------------------------------------------------------- Wed Jan 13 08:31:17 UTC 2016 - schwab@suse.de diff --git a/cross-avr-binutils.spec b/cross-avr-binutils.spec index ff4fe23..fcd5f06 100644 --- a/cross-avr-binutils.spec +++ b/cross-avr-binutils.spec @@ -38,7 +38,7 @@ BuildRequires: zlib-devel-static %else BuildRequires: zlib-devel %endif -Version: 2.25.0 +Version: 2.26 Release: 0 # # RUN_TESTS @@ -85,7 +85,7 @@ Source: binutils-%{binutils_version}.tar.bz2 Source1: pre_checkin.sh Source2: README.First-for.SuSE.packagers Source3: baselibs.conf -Patch1: binutils-2.25-branch.diff.gz +Patch: binutils-2.26-branch.diff Patch3: binutils-skip-rpaths.patch Patch4: s390-biarch.diff Patch5: x86-64-biarch.patch @@ -99,15 +99,6 @@ Patch12: s390-pic-dso.diff Patch14: binutils-build-as-needed.diff Patch18: gold-depend-on-opcodes.diff Patch22: binutils-bfd_h.patch -Patch23: binutils-fix-gold-aarch64.diff -Patch26: binutils-fix--dynamic-list.patch -Patch27: 0001-S-390-Add-support-for-IBM-z13.patch -Patch28: 0002-S-390-Add-check-for-length-field-operand.patch -Patch29: 0003-S-390-Add-more-IBM-z13-instructions.patch -Patch30: 0004-S-390-Fixes-for-z13-instructions.patch -Patch31: 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch -Patch32: gold-arm64-abi-pagesize.patch -Patch33: s390-troo-insn-type.patch Patch34: aarch64-common-pagesize.patch Patch35: gold-relocate-tls.patch Patch90: cross-avr-nesc-as.patch @@ -165,8 +156,8 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa %setup -q -n binutils-%{binutils_version} # Patch1 is outside test_vanilla because it's supposed to be the # patch bringing the tarball to the newest upstream version -%patch1 -p1 %if !%{test_vanilla} +%patch -p1 %patch3 %patch4 %patch5 @@ -179,20 +170,11 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa # The MIPS ABI is incompatible with .gnu.hash, so don't # use it there %patch11 -%endif %patch12 +%endif %patch14 %patch18 %patch22 -%patch23 -%patch26 -p1 -%patch27 -p1 -%patch28 -p1 -%patch29 -p1 -%patch30 -p1 -%patch31 -p1 -%patch32 -p1 -%patch33 -p1 %patch34 -p1 %patch35 -p1 %if "%{TARGET}" == "avr" diff --git a/cross-avr-nesc-as.patch b/cross-avr-nesc-as.patch index 530698b..dca758f 100644 --- a/cross-avr-nesc-as.patch +++ b/cross-avr-nesc-as.patch @@ -1,6 +1,8 @@ ---- gas/config/tc-avr-nesc.h -+++ gas/config/tc-avr-nesc.h -@@ -109,8 +109,12 @@ +Index: gas/config/tc-avr-nesc.h +=================================================================== +--- gas/config/tc-avr-nesc.h.orig 2016-02-01 09:58:37.419903606 +0100 ++++ gas/config/tc-avr-nesc.h 2016-02-01 09:58:39.631928732 +0100 +@@ -143,8 +143,12 @@ extern long md_pcrel_from_section (struc would print `12 34 56 78'. The default value is 4. */ #define LISTING_WORD_SIZE 2 @@ -15,9 +17,11 @@ /* An `.lcomm' directive with no explicit alignment parameter will use this macro to set P2VAR to the alignment that a request for ---- gas/expr.c -+++ gas/expr.c -@@ -2165,6 +2165,15 @@ +Index: gas/expr.c +=================================================================== +--- gas/expr.c.orig 2016-02-01 09:58:35.743884569 +0100 ++++ gas/expr.c 2016-02-01 09:58:39.631928732 +0100 +@@ -2342,6 +2342,15 @@ get_symbol_name (char ** ilp_return) ; if (is_name_ender (c)) c = *input_line_pointer++; @@ -31,5 +35,5 @@ + } +#endif } - *--input_line_pointer = 0; - return (c); + else if (c == '"') + { diff --git a/cross-epiphany-binutils.changes b/cross-epiphany-binutils.changes index 6a12f9b..febad5b 100644 --- a/cross-epiphany-binutils.changes +++ b/cross-epiphany-binutils.changes @@ -1,3 +1,60 @@ +------------------------------------------------------------------- +Mon Feb 29 12:49:50 UTC 2016 - rguenther@suse.com + +- Add binutils-2.26-branch.diff, updates to branch head. + * Adds -mrelax-relocations on x86 + * Fixes bso#19698 + +------------------------------------------------------------------- +Mon Feb 1 09:03:02 UTC 2016 - rguenther@suse.com + +- Refresh cross-avr-nesc-as.patch + +------------------------------------------------------------------- +Wed Jan 27 13:12:17 UTC 2016 - rguenther@suse.com + +- Update to binutils 2.26 + * Add --fix-stm32l4xx-629360 to the ARM linker to enable a link-time + workaround for a bug in the bus matrix / memory controller for some of + the STM32 Cortex-M4 based products (STM32L4xx) + * Add a configure option --enable-compressed-debug-sections={all,ld} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Experimental support for linker garbage collection (--gc-sections) + has been enabled for COFF and PE based targets. + * New command line option for ELF targets to compress DWARF debug + sections, --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. + * New command line option, --orphan-handling=[place|warn|error|discard], to + adjust how orphan sections are handled. The default is 'place' which gives + the current behaviour, 'warn' and 'error' issue a warning or error + respectively when orphan sections are found, and 'discard' will discard all + orphan sections. + * Add support for LLVM plugin. + * Add --print-memory-usage option to report memory blocks usage. + * Add --require-defined option, it's like --undefined except the new symbol + must be defined by the end of the link. + * Add a configure option --enable-compressed-debug-sections={all,gas} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + * Add option to objcopy to insert new symbols into a file: + --add-symbol =[
:][,] + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Extend objcopy --compress-debug-sections option to support + --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF + targets. + * Add --update-section option to objcopy. + * Add --output-separator option to strings. +- Includes z13 support, remove 0001-S-390-Add-support-for-IBM-z13.patch, + 0002-S-390-Add-check-for-length-field-operand.patch, + 0003-S-390-Add-more-IBM-z13-instructions.patch, + 0004-S-390-Fixes-for-z13-instructions.patch and + 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch +- Includes fixes in binutils-fix--dynamic-list.patch, + binutils-fix-gold-aarch64.diff, gold-arm64-abi-pagesize.patch + and s390-troo-insn-type.patch +- Refresh s390-pic-dso.diff and binutils-build-as-needed.diff + ------------------------------------------------------------------- Wed Jan 13 08:31:17 UTC 2016 - schwab@suse.de diff --git a/cross-epiphany-binutils.spec b/cross-epiphany-binutils.spec index 2e8bb45..c89213b 100644 --- a/cross-epiphany-binutils.spec +++ b/cross-epiphany-binutils.spec @@ -38,7 +38,7 @@ BuildRequires: zlib-devel-static %else BuildRequires: zlib-devel %endif -Version: 2.25.0 +Version: 2.26 Release: 0 # # RUN_TESTS @@ -85,7 +85,7 @@ Source: binutils-%{binutils_version}.tar.bz2 Source1: pre_checkin.sh Source2: README.First-for.SuSE.packagers Source3: baselibs.conf -Patch1: binutils-2.25-branch.diff.gz +Patch: binutils-2.26-branch.diff Patch3: binutils-skip-rpaths.patch Patch4: s390-biarch.diff Patch5: x86-64-biarch.patch @@ -99,15 +99,6 @@ Patch12: s390-pic-dso.diff Patch14: binutils-build-as-needed.diff Patch18: gold-depend-on-opcodes.diff Patch22: binutils-bfd_h.patch -Patch23: binutils-fix-gold-aarch64.diff -Patch26: binutils-fix--dynamic-list.patch -Patch27: 0001-S-390-Add-support-for-IBM-z13.patch -Patch28: 0002-S-390-Add-check-for-length-field-operand.patch -Patch29: 0003-S-390-Add-more-IBM-z13-instructions.patch -Patch30: 0004-S-390-Fixes-for-z13-instructions.patch -Patch31: 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch -Patch32: gold-arm64-abi-pagesize.patch -Patch33: s390-troo-insn-type.patch Patch34: aarch64-common-pagesize.patch Patch35: gold-relocate-tls.patch Patch90: cross-avr-nesc-as.patch @@ -165,8 +156,8 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa %setup -q -n binutils-%{binutils_version} # Patch1 is outside test_vanilla because it's supposed to be the # patch bringing the tarball to the newest upstream version -%patch1 -p1 %if !%{test_vanilla} +%patch -p1 %patch3 %patch4 %patch5 @@ -179,20 +170,11 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa # The MIPS ABI is incompatible with .gnu.hash, so don't # use it there %patch11 -%endif %patch12 +%endif %patch14 %patch18 %patch22 -%patch23 -%patch26 -p1 -%patch27 -p1 -%patch28 -p1 -%patch29 -p1 -%patch30 -p1 -%patch31 -p1 -%patch32 -p1 -%patch33 -p1 %patch34 -p1 %patch35 -p1 %if "%{TARGET}" == "avr" diff --git a/cross-hppa-binutils.changes b/cross-hppa-binutils.changes index 6a12f9b..febad5b 100644 --- a/cross-hppa-binutils.changes +++ b/cross-hppa-binutils.changes @@ -1,3 +1,60 @@ +------------------------------------------------------------------- +Mon Feb 29 12:49:50 UTC 2016 - rguenther@suse.com + +- Add binutils-2.26-branch.diff, updates to branch head. + * Adds -mrelax-relocations on x86 + * Fixes bso#19698 + +------------------------------------------------------------------- +Mon Feb 1 09:03:02 UTC 2016 - rguenther@suse.com + +- Refresh cross-avr-nesc-as.patch + +------------------------------------------------------------------- +Wed Jan 27 13:12:17 UTC 2016 - rguenther@suse.com + +- Update to binutils 2.26 + * Add --fix-stm32l4xx-629360 to the ARM linker to enable a link-time + workaround for a bug in the bus matrix / memory controller for some of + the STM32 Cortex-M4 based products (STM32L4xx) + * Add a configure option --enable-compressed-debug-sections={all,ld} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Experimental support for linker garbage collection (--gc-sections) + has been enabled for COFF and PE based targets. + * New command line option for ELF targets to compress DWARF debug + sections, --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. + * New command line option, --orphan-handling=[place|warn|error|discard], to + adjust how orphan sections are handled. The default is 'place' which gives + the current behaviour, 'warn' and 'error' issue a warning or error + respectively when orphan sections are found, and 'discard' will discard all + orphan sections. + * Add support for LLVM plugin. + * Add --print-memory-usage option to report memory blocks usage. + * Add --require-defined option, it's like --undefined except the new symbol + must be defined by the end of the link. + * Add a configure option --enable-compressed-debug-sections={all,gas} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + * Add option to objcopy to insert new symbols into a file: + --add-symbol =[
:][,] + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Extend objcopy --compress-debug-sections option to support + --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF + targets. + * Add --update-section option to objcopy. + * Add --output-separator option to strings. +- Includes z13 support, remove 0001-S-390-Add-support-for-IBM-z13.patch, + 0002-S-390-Add-check-for-length-field-operand.patch, + 0003-S-390-Add-more-IBM-z13-instructions.patch, + 0004-S-390-Fixes-for-z13-instructions.patch and + 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch +- Includes fixes in binutils-fix--dynamic-list.patch, + binutils-fix-gold-aarch64.diff, gold-arm64-abi-pagesize.patch + and s390-troo-insn-type.patch +- Refresh s390-pic-dso.diff and binutils-build-as-needed.diff + ------------------------------------------------------------------- Wed Jan 13 08:31:17 UTC 2016 - schwab@suse.de diff --git a/cross-hppa-binutils.spec b/cross-hppa-binutils.spec index be21687..aed7a59 100644 --- a/cross-hppa-binutils.spec +++ b/cross-hppa-binutils.spec @@ -38,7 +38,7 @@ BuildRequires: zlib-devel-static %else BuildRequires: zlib-devel %endif -Version: 2.25.0 +Version: 2.26 Release: 0 # # RUN_TESTS @@ -85,7 +85,7 @@ Source: binutils-%{binutils_version}.tar.bz2 Source1: pre_checkin.sh Source2: README.First-for.SuSE.packagers Source3: baselibs.conf -Patch1: binutils-2.25-branch.diff.gz +Patch: binutils-2.26-branch.diff Patch3: binutils-skip-rpaths.patch Patch4: s390-biarch.diff Patch5: x86-64-biarch.patch @@ -99,15 +99,6 @@ Patch12: s390-pic-dso.diff Patch14: binutils-build-as-needed.diff Patch18: gold-depend-on-opcodes.diff Patch22: binutils-bfd_h.patch -Patch23: binutils-fix-gold-aarch64.diff -Patch26: binutils-fix--dynamic-list.patch -Patch27: 0001-S-390-Add-support-for-IBM-z13.patch -Patch28: 0002-S-390-Add-check-for-length-field-operand.patch -Patch29: 0003-S-390-Add-more-IBM-z13-instructions.patch -Patch30: 0004-S-390-Fixes-for-z13-instructions.patch -Patch31: 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch -Patch32: gold-arm64-abi-pagesize.patch -Patch33: s390-troo-insn-type.patch Patch34: aarch64-common-pagesize.patch Patch35: gold-relocate-tls.patch Patch90: cross-avr-nesc-as.patch @@ -165,8 +156,8 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa %setup -q -n binutils-%{binutils_version} # Patch1 is outside test_vanilla because it's supposed to be the # patch bringing the tarball to the newest upstream version -%patch1 -p1 %if !%{test_vanilla} +%patch -p1 %patch3 %patch4 %patch5 @@ -179,20 +170,11 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa # The MIPS ABI is incompatible with .gnu.hash, so don't # use it there %patch11 -%endif %patch12 +%endif %patch14 %patch18 %patch22 -%patch23 -%patch26 -p1 -%patch27 -p1 -%patch28 -p1 -%patch29 -p1 -%patch30 -p1 -%patch31 -p1 -%patch32 -p1 -%patch33 -p1 %patch34 -p1 %patch35 -p1 %if "%{TARGET}" == "avr" diff --git a/cross-hppa64-binutils.changes b/cross-hppa64-binutils.changes index 6a12f9b..febad5b 100644 --- a/cross-hppa64-binutils.changes +++ b/cross-hppa64-binutils.changes @@ -1,3 +1,60 @@ +------------------------------------------------------------------- +Mon Feb 29 12:49:50 UTC 2016 - rguenther@suse.com + +- Add binutils-2.26-branch.diff, updates to branch head. + * Adds -mrelax-relocations on x86 + * Fixes bso#19698 + +------------------------------------------------------------------- +Mon Feb 1 09:03:02 UTC 2016 - rguenther@suse.com + +- Refresh cross-avr-nesc-as.patch + +------------------------------------------------------------------- +Wed Jan 27 13:12:17 UTC 2016 - rguenther@suse.com + +- Update to binutils 2.26 + * Add --fix-stm32l4xx-629360 to the ARM linker to enable a link-time + workaround for a bug in the bus matrix / memory controller for some of + the STM32 Cortex-M4 based products (STM32L4xx) + * Add a configure option --enable-compressed-debug-sections={all,ld} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Experimental support for linker garbage collection (--gc-sections) + has been enabled for COFF and PE based targets. + * New command line option for ELF targets to compress DWARF debug + sections, --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. + * New command line option, --orphan-handling=[place|warn|error|discard], to + adjust how orphan sections are handled. The default is 'place' which gives + the current behaviour, 'warn' and 'error' issue a warning or error + respectively when orphan sections are found, and 'discard' will discard all + orphan sections. + * Add support for LLVM plugin. + * Add --print-memory-usage option to report memory blocks usage. + * Add --require-defined option, it's like --undefined except the new symbol + must be defined by the end of the link. + * Add a configure option --enable-compressed-debug-sections={all,gas} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + * Add option to objcopy to insert new symbols into a file: + --add-symbol =[
:][,] + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Extend objcopy --compress-debug-sections option to support + --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF + targets. + * Add --update-section option to objcopy. + * Add --output-separator option to strings. +- Includes z13 support, remove 0001-S-390-Add-support-for-IBM-z13.patch, + 0002-S-390-Add-check-for-length-field-operand.patch, + 0003-S-390-Add-more-IBM-z13-instructions.patch, + 0004-S-390-Fixes-for-z13-instructions.patch and + 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch +- Includes fixes in binutils-fix--dynamic-list.patch, + binutils-fix-gold-aarch64.diff, gold-arm64-abi-pagesize.patch + and s390-troo-insn-type.patch +- Refresh s390-pic-dso.diff and binutils-build-as-needed.diff + ------------------------------------------------------------------- Wed Jan 13 08:31:17 UTC 2016 - schwab@suse.de diff --git a/cross-hppa64-binutils.spec b/cross-hppa64-binutils.spec index 7b27e8b..6091afe 100644 --- a/cross-hppa64-binutils.spec +++ b/cross-hppa64-binutils.spec @@ -38,7 +38,7 @@ BuildRequires: zlib-devel-static %else BuildRequires: zlib-devel %endif -Version: 2.25.0 +Version: 2.26 Release: 0 # # RUN_TESTS @@ -85,7 +85,7 @@ Source: binutils-%{binutils_version}.tar.bz2 Source1: pre_checkin.sh Source2: README.First-for.SuSE.packagers Source3: baselibs.conf -Patch1: binutils-2.25-branch.diff.gz +Patch: binutils-2.26-branch.diff Patch3: binutils-skip-rpaths.patch Patch4: s390-biarch.diff Patch5: x86-64-biarch.patch @@ -99,15 +99,6 @@ Patch12: s390-pic-dso.diff Patch14: binutils-build-as-needed.diff Patch18: gold-depend-on-opcodes.diff Patch22: binutils-bfd_h.patch -Patch23: binutils-fix-gold-aarch64.diff -Patch26: binutils-fix--dynamic-list.patch -Patch27: 0001-S-390-Add-support-for-IBM-z13.patch -Patch28: 0002-S-390-Add-check-for-length-field-operand.patch -Patch29: 0003-S-390-Add-more-IBM-z13-instructions.patch -Patch30: 0004-S-390-Fixes-for-z13-instructions.patch -Patch31: 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch -Patch32: gold-arm64-abi-pagesize.patch -Patch33: s390-troo-insn-type.patch Patch34: aarch64-common-pagesize.patch Patch35: gold-relocate-tls.patch Patch90: cross-avr-nesc-as.patch @@ -165,8 +156,8 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa %setup -q -n binutils-%{binutils_version} # Patch1 is outside test_vanilla because it's supposed to be the # patch bringing the tarball to the newest upstream version -%patch1 -p1 %if !%{test_vanilla} +%patch -p1 %patch3 %patch4 %patch5 @@ -179,20 +170,11 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa # The MIPS ABI is incompatible with .gnu.hash, so don't # use it there %patch11 -%endif %patch12 +%endif %patch14 %patch18 %patch22 -%patch23 -%patch26 -p1 -%patch27 -p1 -%patch28 -p1 -%patch29 -p1 -%patch30 -p1 -%patch31 -p1 -%patch32 -p1 -%patch33 -p1 %patch34 -p1 %patch35 -p1 %if "%{TARGET}" == "avr" diff --git a/cross-i386-binutils.changes b/cross-i386-binutils.changes index 6a12f9b..febad5b 100644 --- a/cross-i386-binutils.changes +++ b/cross-i386-binutils.changes @@ -1,3 +1,60 @@ +------------------------------------------------------------------- +Mon Feb 29 12:49:50 UTC 2016 - rguenther@suse.com + +- Add binutils-2.26-branch.diff, updates to branch head. + * Adds -mrelax-relocations on x86 + * Fixes bso#19698 + +------------------------------------------------------------------- +Mon Feb 1 09:03:02 UTC 2016 - rguenther@suse.com + +- Refresh cross-avr-nesc-as.patch + +------------------------------------------------------------------- +Wed Jan 27 13:12:17 UTC 2016 - rguenther@suse.com + +- Update to binutils 2.26 + * Add --fix-stm32l4xx-629360 to the ARM linker to enable a link-time + workaround for a bug in the bus matrix / memory controller for some of + the STM32 Cortex-M4 based products (STM32L4xx) + * Add a configure option --enable-compressed-debug-sections={all,ld} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Experimental support for linker garbage collection (--gc-sections) + has been enabled for COFF and PE based targets. + * New command line option for ELF targets to compress DWARF debug + sections, --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. + * New command line option, --orphan-handling=[place|warn|error|discard], to + adjust how orphan sections are handled. The default is 'place' which gives + the current behaviour, 'warn' and 'error' issue a warning or error + respectively when orphan sections are found, and 'discard' will discard all + orphan sections. + * Add support for LLVM plugin. + * Add --print-memory-usage option to report memory blocks usage. + * Add --require-defined option, it's like --undefined except the new symbol + must be defined by the end of the link. + * Add a configure option --enable-compressed-debug-sections={all,gas} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + * Add option to objcopy to insert new symbols into a file: + --add-symbol =[
:][,] + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Extend objcopy --compress-debug-sections option to support + --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF + targets. + * Add --update-section option to objcopy. + * Add --output-separator option to strings. +- Includes z13 support, remove 0001-S-390-Add-support-for-IBM-z13.patch, + 0002-S-390-Add-check-for-length-field-operand.patch, + 0003-S-390-Add-more-IBM-z13-instructions.patch, + 0004-S-390-Fixes-for-z13-instructions.patch and + 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch +- Includes fixes in binutils-fix--dynamic-list.patch, + binutils-fix-gold-aarch64.diff, gold-arm64-abi-pagesize.patch + and s390-troo-insn-type.patch +- Refresh s390-pic-dso.diff and binutils-build-as-needed.diff + ------------------------------------------------------------------- Wed Jan 13 08:31:17 UTC 2016 - schwab@suse.de diff --git a/cross-i386-binutils.spec b/cross-i386-binutils.spec index e3e961a..7c42020 100644 --- a/cross-i386-binutils.spec +++ b/cross-i386-binutils.spec @@ -38,7 +38,7 @@ BuildRequires: zlib-devel-static %else BuildRequires: zlib-devel %endif -Version: 2.25.0 +Version: 2.26 Release: 0 # # RUN_TESTS @@ -85,7 +85,7 @@ Source: binutils-%{binutils_version}.tar.bz2 Source1: pre_checkin.sh Source2: README.First-for.SuSE.packagers Source3: baselibs.conf -Patch1: binutils-2.25-branch.diff.gz +Patch: binutils-2.26-branch.diff Patch3: binutils-skip-rpaths.patch Patch4: s390-biarch.diff Patch5: x86-64-biarch.patch @@ -99,15 +99,6 @@ Patch12: s390-pic-dso.diff Patch14: binutils-build-as-needed.diff Patch18: gold-depend-on-opcodes.diff Patch22: binutils-bfd_h.patch -Patch23: binutils-fix-gold-aarch64.diff -Patch26: binutils-fix--dynamic-list.patch -Patch27: 0001-S-390-Add-support-for-IBM-z13.patch -Patch28: 0002-S-390-Add-check-for-length-field-operand.patch -Patch29: 0003-S-390-Add-more-IBM-z13-instructions.patch -Patch30: 0004-S-390-Fixes-for-z13-instructions.patch -Patch31: 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch -Patch32: gold-arm64-abi-pagesize.patch -Patch33: s390-troo-insn-type.patch Patch34: aarch64-common-pagesize.patch Patch35: gold-relocate-tls.patch Patch90: cross-avr-nesc-as.patch @@ -165,8 +156,8 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa %setup -q -n binutils-%{binutils_version} # Patch1 is outside test_vanilla because it's supposed to be the # patch bringing the tarball to the newest upstream version -%patch1 -p1 %if !%{test_vanilla} +%patch -p1 %patch3 %patch4 %patch5 @@ -179,20 +170,11 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa # The MIPS ABI is incompatible with .gnu.hash, so don't # use it there %patch11 -%endif %patch12 +%endif %patch14 %patch18 %patch22 -%patch23 -%patch26 -p1 -%patch27 -p1 -%patch28 -p1 -%patch29 -p1 -%patch30 -p1 -%patch31 -p1 -%patch32 -p1 -%patch33 -p1 %patch34 -p1 %patch35 -p1 %if "%{TARGET}" == "avr" diff --git a/cross-ia64-binutils.changes b/cross-ia64-binutils.changes index 6a12f9b..febad5b 100644 --- a/cross-ia64-binutils.changes +++ b/cross-ia64-binutils.changes @@ -1,3 +1,60 @@ +------------------------------------------------------------------- +Mon Feb 29 12:49:50 UTC 2016 - rguenther@suse.com + +- Add binutils-2.26-branch.diff, updates to branch head. + * Adds -mrelax-relocations on x86 + * Fixes bso#19698 + +------------------------------------------------------------------- +Mon Feb 1 09:03:02 UTC 2016 - rguenther@suse.com + +- Refresh cross-avr-nesc-as.patch + +------------------------------------------------------------------- +Wed Jan 27 13:12:17 UTC 2016 - rguenther@suse.com + +- Update to binutils 2.26 + * Add --fix-stm32l4xx-629360 to the ARM linker to enable a link-time + workaround for a bug in the bus matrix / memory controller for some of + the STM32 Cortex-M4 based products (STM32L4xx) + * Add a configure option --enable-compressed-debug-sections={all,ld} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Experimental support for linker garbage collection (--gc-sections) + has been enabled for COFF and PE based targets. + * New command line option for ELF targets to compress DWARF debug + sections, --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. + * New command line option, --orphan-handling=[place|warn|error|discard], to + adjust how orphan sections are handled. The default is 'place' which gives + the current behaviour, 'warn' and 'error' issue a warning or error + respectively when orphan sections are found, and 'discard' will discard all + orphan sections. + * Add support for LLVM plugin. + * Add --print-memory-usage option to report memory blocks usage. + * Add --require-defined option, it's like --undefined except the new symbol + must be defined by the end of the link. + * Add a configure option --enable-compressed-debug-sections={all,gas} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + * Add option to objcopy to insert new symbols into a file: + --add-symbol =[
:][,] + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Extend objcopy --compress-debug-sections option to support + --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF + targets. + * Add --update-section option to objcopy. + * Add --output-separator option to strings. +- Includes z13 support, remove 0001-S-390-Add-support-for-IBM-z13.patch, + 0002-S-390-Add-check-for-length-field-operand.patch, + 0003-S-390-Add-more-IBM-z13-instructions.patch, + 0004-S-390-Fixes-for-z13-instructions.patch and + 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch +- Includes fixes in binutils-fix--dynamic-list.patch, + binutils-fix-gold-aarch64.diff, gold-arm64-abi-pagesize.patch + and s390-troo-insn-type.patch +- Refresh s390-pic-dso.diff and binutils-build-as-needed.diff + ------------------------------------------------------------------- Wed Jan 13 08:31:17 UTC 2016 - schwab@suse.de diff --git a/cross-ia64-binutils.spec b/cross-ia64-binutils.spec index c970734..e93ae05 100644 --- a/cross-ia64-binutils.spec +++ b/cross-ia64-binutils.spec @@ -38,7 +38,7 @@ BuildRequires: zlib-devel-static %else BuildRequires: zlib-devel %endif -Version: 2.25.0 +Version: 2.26 Release: 0 # # RUN_TESTS @@ -85,7 +85,7 @@ Source: binutils-%{binutils_version}.tar.bz2 Source1: pre_checkin.sh Source2: README.First-for.SuSE.packagers Source3: baselibs.conf -Patch1: binutils-2.25-branch.diff.gz +Patch: binutils-2.26-branch.diff Patch3: binutils-skip-rpaths.patch Patch4: s390-biarch.diff Patch5: x86-64-biarch.patch @@ -99,15 +99,6 @@ Patch12: s390-pic-dso.diff Patch14: binutils-build-as-needed.diff Patch18: gold-depend-on-opcodes.diff Patch22: binutils-bfd_h.patch -Patch23: binutils-fix-gold-aarch64.diff -Patch26: binutils-fix--dynamic-list.patch -Patch27: 0001-S-390-Add-support-for-IBM-z13.patch -Patch28: 0002-S-390-Add-check-for-length-field-operand.patch -Patch29: 0003-S-390-Add-more-IBM-z13-instructions.patch -Patch30: 0004-S-390-Fixes-for-z13-instructions.patch -Patch31: 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch -Patch32: gold-arm64-abi-pagesize.patch -Patch33: s390-troo-insn-type.patch Patch34: aarch64-common-pagesize.patch Patch35: gold-relocate-tls.patch Patch90: cross-avr-nesc-as.patch @@ -165,8 +156,8 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa %setup -q -n binutils-%{binutils_version} # Patch1 is outside test_vanilla because it's supposed to be the # patch bringing the tarball to the newest upstream version -%patch1 -p1 %if !%{test_vanilla} +%patch -p1 %patch3 %patch4 %patch5 @@ -179,20 +170,11 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa # The MIPS ABI is incompatible with .gnu.hash, so don't # use it there %patch11 -%endif %patch12 +%endif %patch14 %patch18 %patch22 -%patch23 -%patch26 -p1 -%patch27 -p1 -%patch28 -p1 -%patch29 -p1 -%patch30 -p1 -%patch31 -p1 -%patch32 -p1 -%patch33 -p1 %patch34 -p1 %patch35 -p1 %if "%{TARGET}" == "avr" diff --git a/cross-m68k-binutils.changes b/cross-m68k-binutils.changes index 6a12f9b..febad5b 100644 --- a/cross-m68k-binutils.changes +++ b/cross-m68k-binutils.changes @@ -1,3 +1,60 @@ +------------------------------------------------------------------- +Mon Feb 29 12:49:50 UTC 2016 - rguenther@suse.com + +- Add binutils-2.26-branch.diff, updates to branch head. + * Adds -mrelax-relocations on x86 + * Fixes bso#19698 + +------------------------------------------------------------------- +Mon Feb 1 09:03:02 UTC 2016 - rguenther@suse.com + +- Refresh cross-avr-nesc-as.patch + +------------------------------------------------------------------- +Wed Jan 27 13:12:17 UTC 2016 - rguenther@suse.com + +- Update to binutils 2.26 + * Add --fix-stm32l4xx-629360 to the ARM linker to enable a link-time + workaround for a bug in the bus matrix / memory controller for some of + the STM32 Cortex-M4 based products (STM32L4xx) + * Add a configure option --enable-compressed-debug-sections={all,ld} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Experimental support for linker garbage collection (--gc-sections) + has been enabled for COFF and PE based targets. + * New command line option for ELF targets to compress DWARF debug + sections, --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. + * New command line option, --orphan-handling=[place|warn|error|discard], to + adjust how orphan sections are handled. The default is 'place' which gives + the current behaviour, 'warn' and 'error' issue a warning or error + respectively when orphan sections are found, and 'discard' will discard all + orphan sections. + * Add support for LLVM plugin. + * Add --print-memory-usage option to report memory blocks usage. + * Add --require-defined option, it's like --undefined except the new symbol + must be defined by the end of the link. + * Add a configure option --enable-compressed-debug-sections={all,gas} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + * Add option to objcopy to insert new symbols into a file: + --add-symbol =[
:][,] + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Extend objcopy --compress-debug-sections option to support + --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF + targets. + * Add --update-section option to objcopy. + * Add --output-separator option to strings. +- Includes z13 support, remove 0001-S-390-Add-support-for-IBM-z13.patch, + 0002-S-390-Add-check-for-length-field-operand.patch, + 0003-S-390-Add-more-IBM-z13-instructions.patch, + 0004-S-390-Fixes-for-z13-instructions.patch and + 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch +- Includes fixes in binutils-fix--dynamic-list.patch, + binutils-fix-gold-aarch64.diff, gold-arm64-abi-pagesize.patch + and s390-troo-insn-type.patch +- Refresh s390-pic-dso.diff and binutils-build-as-needed.diff + ------------------------------------------------------------------- Wed Jan 13 08:31:17 UTC 2016 - schwab@suse.de diff --git a/cross-m68k-binutils.spec b/cross-m68k-binutils.spec index f707c40..ff6cf0b 100644 --- a/cross-m68k-binutils.spec +++ b/cross-m68k-binutils.spec @@ -38,7 +38,7 @@ BuildRequires: zlib-devel-static %else BuildRequires: zlib-devel %endif -Version: 2.25.0 +Version: 2.26 Release: 0 # # RUN_TESTS @@ -85,7 +85,7 @@ Source: binutils-%{binutils_version}.tar.bz2 Source1: pre_checkin.sh Source2: README.First-for.SuSE.packagers Source3: baselibs.conf -Patch1: binutils-2.25-branch.diff.gz +Patch: binutils-2.26-branch.diff Patch3: binutils-skip-rpaths.patch Patch4: s390-biarch.diff Patch5: x86-64-biarch.patch @@ -99,15 +99,6 @@ Patch12: s390-pic-dso.diff Patch14: binutils-build-as-needed.diff Patch18: gold-depend-on-opcodes.diff Patch22: binutils-bfd_h.patch -Patch23: binutils-fix-gold-aarch64.diff -Patch26: binutils-fix--dynamic-list.patch -Patch27: 0001-S-390-Add-support-for-IBM-z13.patch -Patch28: 0002-S-390-Add-check-for-length-field-operand.patch -Patch29: 0003-S-390-Add-more-IBM-z13-instructions.patch -Patch30: 0004-S-390-Fixes-for-z13-instructions.patch -Patch31: 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch -Patch32: gold-arm64-abi-pagesize.patch -Patch33: s390-troo-insn-type.patch Patch34: aarch64-common-pagesize.patch Patch35: gold-relocate-tls.patch Patch90: cross-avr-nesc-as.patch @@ -165,8 +156,8 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa %setup -q -n binutils-%{binutils_version} # Patch1 is outside test_vanilla because it's supposed to be the # patch bringing the tarball to the newest upstream version -%patch1 -p1 %if !%{test_vanilla} +%patch -p1 %patch3 %patch4 %patch5 @@ -179,20 +170,11 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa # The MIPS ABI is incompatible with .gnu.hash, so don't # use it there %patch11 -%endif %patch12 +%endif %patch14 %patch18 %patch22 -%patch23 -%patch26 -p1 -%patch27 -p1 -%patch28 -p1 -%patch29 -p1 -%patch30 -p1 -%patch31 -p1 -%patch32 -p1 -%patch33 -p1 %patch34 -p1 %patch35 -p1 %if "%{TARGET}" == "avr" diff --git a/cross-mips-binutils.changes b/cross-mips-binutils.changes index 6a12f9b..febad5b 100644 --- a/cross-mips-binutils.changes +++ b/cross-mips-binutils.changes @@ -1,3 +1,60 @@ +------------------------------------------------------------------- +Mon Feb 29 12:49:50 UTC 2016 - rguenther@suse.com + +- Add binutils-2.26-branch.diff, updates to branch head. + * Adds -mrelax-relocations on x86 + * Fixes bso#19698 + +------------------------------------------------------------------- +Mon Feb 1 09:03:02 UTC 2016 - rguenther@suse.com + +- Refresh cross-avr-nesc-as.patch + +------------------------------------------------------------------- +Wed Jan 27 13:12:17 UTC 2016 - rguenther@suse.com + +- Update to binutils 2.26 + * Add --fix-stm32l4xx-629360 to the ARM linker to enable a link-time + workaround for a bug in the bus matrix / memory controller for some of + the STM32 Cortex-M4 based products (STM32L4xx) + * Add a configure option --enable-compressed-debug-sections={all,ld} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Experimental support for linker garbage collection (--gc-sections) + has been enabled for COFF and PE based targets. + * New command line option for ELF targets to compress DWARF debug + sections, --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. + * New command line option, --orphan-handling=[place|warn|error|discard], to + adjust how orphan sections are handled. The default is 'place' which gives + the current behaviour, 'warn' and 'error' issue a warning or error + respectively when orphan sections are found, and 'discard' will discard all + orphan sections. + * Add support for LLVM plugin. + * Add --print-memory-usage option to report memory blocks usage. + * Add --require-defined option, it's like --undefined except the new symbol + must be defined by the end of the link. + * Add a configure option --enable-compressed-debug-sections={all,gas} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + * Add option to objcopy to insert new symbols into a file: + --add-symbol =[
:][,] + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Extend objcopy --compress-debug-sections option to support + --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF + targets. + * Add --update-section option to objcopy. + * Add --output-separator option to strings. +- Includes z13 support, remove 0001-S-390-Add-support-for-IBM-z13.patch, + 0002-S-390-Add-check-for-length-field-operand.patch, + 0003-S-390-Add-more-IBM-z13-instructions.patch, + 0004-S-390-Fixes-for-z13-instructions.patch and + 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch +- Includes fixes in binutils-fix--dynamic-list.patch, + binutils-fix-gold-aarch64.diff, gold-arm64-abi-pagesize.patch + and s390-troo-insn-type.patch +- Refresh s390-pic-dso.diff and binutils-build-as-needed.diff + ------------------------------------------------------------------- Wed Jan 13 08:31:17 UTC 2016 - schwab@suse.de diff --git a/cross-mips-binutils.spec b/cross-mips-binutils.spec index 2f8712d..5226444 100644 --- a/cross-mips-binutils.spec +++ b/cross-mips-binutils.spec @@ -38,7 +38,7 @@ BuildRequires: zlib-devel-static %else BuildRequires: zlib-devel %endif -Version: 2.25.0 +Version: 2.26 Release: 0 # # RUN_TESTS @@ -85,7 +85,7 @@ Source: binutils-%{binutils_version}.tar.bz2 Source1: pre_checkin.sh Source2: README.First-for.SuSE.packagers Source3: baselibs.conf -Patch1: binutils-2.25-branch.diff.gz +Patch: binutils-2.26-branch.diff Patch3: binutils-skip-rpaths.patch Patch4: s390-biarch.diff Patch5: x86-64-biarch.patch @@ -99,15 +99,6 @@ Patch12: s390-pic-dso.diff Patch14: binutils-build-as-needed.diff Patch18: gold-depend-on-opcodes.diff Patch22: binutils-bfd_h.patch -Patch23: binutils-fix-gold-aarch64.diff -Patch26: binutils-fix--dynamic-list.patch -Patch27: 0001-S-390-Add-support-for-IBM-z13.patch -Patch28: 0002-S-390-Add-check-for-length-field-operand.patch -Patch29: 0003-S-390-Add-more-IBM-z13-instructions.patch -Patch30: 0004-S-390-Fixes-for-z13-instructions.patch -Patch31: 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch -Patch32: gold-arm64-abi-pagesize.patch -Patch33: s390-troo-insn-type.patch Patch34: aarch64-common-pagesize.patch Patch35: gold-relocate-tls.patch Patch90: cross-avr-nesc-as.patch @@ -165,8 +156,8 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa %setup -q -n binutils-%{binutils_version} # Patch1 is outside test_vanilla because it's supposed to be the # patch bringing the tarball to the newest upstream version -%patch1 -p1 %if !%{test_vanilla} +%patch -p1 %patch3 %patch4 %patch5 @@ -179,20 +170,11 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa # The MIPS ABI is incompatible with .gnu.hash, so don't # use it there %patch11 -%endif %patch12 +%endif %patch14 %patch18 %patch22 -%patch23 -%patch26 -p1 -%patch27 -p1 -%patch28 -p1 -%patch29 -p1 -%patch30 -p1 -%patch31 -p1 -%patch32 -p1 -%patch33 -p1 %patch34 -p1 %patch35 -p1 %if "%{TARGET}" == "avr" diff --git a/cross-ppc-binutils.changes b/cross-ppc-binutils.changes index 6a12f9b..febad5b 100644 --- a/cross-ppc-binutils.changes +++ b/cross-ppc-binutils.changes @@ -1,3 +1,60 @@ +------------------------------------------------------------------- +Mon Feb 29 12:49:50 UTC 2016 - rguenther@suse.com + +- Add binutils-2.26-branch.diff, updates to branch head. + * Adds -mrelax-relocations on x86 + * Fixes bso#19698 + +------------------------------------------------------------------- +Mon Feb 1 09:03:02 UTC 2016 - rguenther@suse.com + +- Refresh cross-avr-nesc-as.patch + +------------------------------------------------------------------- +Wed Jan 27 13:12:17 UTC 2016 - rguenther@suse.com + +- Update to binutils 2.26 + * Add --fix-stm32l4xx-629360 to the ARM linker to enable a link-time + workaround for a bug in the bus matrix / memory controller for some of + the STM32 Cortex-M4 based products (STM32L4xx) + * Add a configure option --enable-compressed-debug-sections={all,ld} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Experimental support for linker garbage collection (--gc-sections) + has been enabled for COFF and PE based targets. + * New command line option for ELF targets to compress DWARF debug + sections, --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. + * New command line option, --orphan-handling=[place|warn|error|discard], to + adjust how orphan sections are handled. The default is 'place' which gives + the current behaviour, 'warn' and 'error' issue a warning or error + respectively when orphan sections are found, and 'discard' will discard all + orphan sections. + * Add support for LLVM plugin. + * Add --print-memory-usage option to report memory blocks usage. + * Add --require-defined option, it's like --undefined except the new symbol + must be defined by the end of the link. + * Add a configure option --enable-compressed-debug-sections={all,gas} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + * Add option to objcopy to insert new symbols into a file: + --add-symbol =[
:][,] + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Extend objcopy --compress-debug-sections option to support + --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF + targets. + * Add --update-section option to objcopy. + * Add --output-separator option to strings. +- Includes z13 support, remove 0001-S-390-Add-support-for-IBM-z13.patch, + 0002-S-390-Add-check-for-length-field-operand.patch, + 0003-S-390-Add-more-IBM-z13-instructions.patch, + 0004-S-390-Fixes-for-z13-instructions.patch and + 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch +- Includes fixes in binutils-fix--dynamic-list.patch, + binutils-fix-gold-aarch64.diff, gold-arm64-abi-pagesize.patch + and s390-troo-insn-type.patch +- Refresh s390-pic-dso.diff and binutils-build-as-needed.diff + ------------------------------------------------------------------- Wed Jan 13 08:31:17 UTC 2016 - schwab@suse.de diff --git a/cross-ppc-binutils.spec b/cross-ppc-binutils.spec index 916a803..b708f45 100644 --- a/cross-ppc-binutils.spec +++ b/cross-ppc-binutils.spec @@ -38,7 +38,7 @@ BuildRequires: zlib-devel-static %else BuildRequires: zlib-devel %endif -Version: 2.25.0 +Version: 2.26 Release: 0 # # RUN_TESTS @@ -85,7 +85,7 @@ Source: binutils-%{binutils_version}.tar.bz2 Source1: pre_checkin.sh Source2: README.First-for.SuSE.packagers Source3: baselibs.conf -Patch1: binutils-2.25-branch.diff.gz +Patch: binutils-2.26-branch.diff Patch3: binutils-skip-rpaths.patch Patch4: s390-biarch.diff Patch5: x86-64-biarch.patch @@ -99,15 +99,6 @@ Patch12: s390-pic-dso.diff Patch14: binutils-build-as-needed.diff Patch18: gold-depend-on-opcodes.diff Patch22: binutils-bfd_h.patch -Patch23: binutils-fix-gold-aarch64.diff -Patch26: binutils-fix--dynamic-list.patch -Patch27: 0001-S-390-Add-support-for-IBM-z13.patch -Patch28: 0002-S-390-Add-check-for-length-field-operand.patch -Patch29: 0003-S-390-Add-more-IBM-z13-instructions.patch -Patch30: 0004-S-390-Fixes-for-z13-instructions.patch -Patch31: 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch -Patch32: gold-arm64-abi-pagesize.patch -Patch33: s390-troo-insn-type.patch Patch34: aarch64-common-pagesize.patch Patch35: gold-relocate-tls.patch Patch90: cross-avr-nesc-as.patch @@ -165,8 +156,8 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa %setup -q -n binutils-%{binutils_version} # Patch1 is outside test_vanilla because it's supposed to be the # patch bringing the tarball to the newest upstream version -%patch1 -p1 %if !%{test_vanilla} +%patch -p1 %patch3 %patch4 %patch5 @@ -179,20 +170,11 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa # The MIPS ABI is incompatible with .gnu.hash, so don't # use it there %patch11 -%endif %patch12 +%endif %patch14 %patch18 %patch22 -%patch23 -%patch26 -p1 -%patch27 -p1 -%patch28 -p1 -%patch29 -p1 -%patch30 -p1 -%patch31 -p1 -%patch32 -p1 -%patch33 -p1 %patch34 -p1 %patch35 -p1 %if "%{TARGET}" == "avr" diff --git a/cross-ppc64-binutils.changes b/cross-ppc64-binutils.changes index 6a12f9b..febad5b 100644 --- a/cross-ppc64-binutils.changes +++ b/cross-ppc64-binutils.changes @@ -1,3 +1,60 @@ +------------------------------------------------------------------- +Mon Feb 29 12:49:50 UTC 2016 - rguenther@suse.com + +- Add binutils-2.26-branch.diff, updates to branch head. + * Adds -mrelax-relocations on x86 + * Fixes bso#19698 + +------------------------------------------------------------------- +Mon Feb 1 09:03:02 UTC 2016 - rguenther@suse.com + +- Refresh cross-avr-nesc-as.patch + +------------------------------------------------------------------- +Wed Jan 27 13:12:17 UTC 2016 - rguenther@suse.com + +- Update to binutils 2.26 + * Add --fix-stm32l4xx-629360 to the ARM linker to enable a link-time + workaround for a bug in the bus matrix / memory controller for some of + the STM32 Cortex-M4 based products (STM32L4xx) + * Add a configure option --enable-compressed-debug-sections={all,ld} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Experimental support for linker garbage collection (--gc-sections) + has been enabled for COFF and PE based targets. + * New command line option for ELF targets to compress DWARF debug + sections, --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. + * New command line option, --orphan-handling=[place|warn|error|discard], to + adjust how orphan sections are handled. The default is 'place' which gives + the current behaviour, 'warn' and 'error' issue a warning or error + respectively when orphan sections are found, and 'discard' will discard all + orphan sections. + * Add support for LLVM plugin. + * Add --print-memory-usage option to report memory blocks usage. + * Add --require-defined option, it's like --undefined except the new symbol + must be defined by the end of the link. + * Add a configure option --enable-compressed-debug-sections={all,gas} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + * Add option to objcopy to insert new symbols into a file: + --add-symbol =[
:][,] + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Extend objcopy --compress-debug-sections option to support + --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF + targets. + * Add --update-section option to objcopy. + * Add --output-separator option to strings. +- Includes z13 support, remove 0001-S-390-Add-support-for-IBM-z13.patch, + 0002-S-390-Add-check-for-length-field-operand.patch, + 0003-S-390-Add-more-IBM-z13-instructions.patch, + 0004-S-390-Fixes-for-z13-instructions.patch and + 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch +- Includes fixes in binutils-fix--dynamic-list.patch, + binutils-fix-gold-aarch64.diff, gold-arm64-abi-pagesize.patch + and s390-troo-insn-type.patch +- Refresh s390-pic-dso.diff and binutils-build-as-needed.diff + ------------------------------------------------------------------- Wed Jan 13 08:31:17 UTC 2016 - schwab@suse.de diff --git a/cross-ppc64-binutils.spec b/cross-ppc64-binutils.spec index 76f501d..e84d2bc 100644 --- a/cross-ppc64-binutils.spec +++ b/cross-ppc64-binutils.spec @@ -38,7 +38,7 @@ BuildRequires: zlib-devel-static %else BuildRequires: zlib-devel %endif -Version: 2.25.0 +Version: 2.26 Release: 0 # # RUN_TESTS @@ -85,7 +85,7 @@ Source: binutils-%{binutils_version}.tar.bz2 Source1: pre_checkin.sh Source2: README.First-for.SuSE.packagers Source3: baselibs.conf -Patch1: binutils-2.25-branch.diff.gz +Patch: binutils-2.26-branch.diff Patch3: binutils-skip-rpaths.patch Patch4: s390-biarch.diff Patch5: x86-64-biarch.patch @@ -99,15 +99,6 @@ Patch12: s390-pic-dso.diff Patch14: binutils-build-as-needed.diff Patch18: gold-depend-on-opcodes.diff Patch22: binutils-bfd_h.patch -Patch23: binutils-fix-gold-aarch64.diff -Patch26: binutils-fix--dynamic-list.patch -Patch27: 0001-S-390-Add-support-for-IBM-z13.patch -Patch28: 0002-S-390-Add-check-for-length-field-operand.patch -Patch29: 0003-S-390-Add-more-IBM-z13-instructions.patch -Patch30: 0004-S-390-Fixes-for-z13-instructions.patch -Patch31: 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch -Patch32: gold-arm64-abi-pagesize.patch -Patch33: s390-troo-insn-type.patch Patch34: aarch64-common-pagesize.patch Patch35: gold-relocate-tls.patch Patch90: cross-avr-nesc-as.patch @@ -165,8 +156,8 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa %setup -q -n binutils-%{binutils_version} # Patch1 is outside test_vanilla because it's supposed to be the # patch bringing the tarball to the newest upstream version -%patch1 -p1 %if !%{test_vanilla} +%patch -p1 %patch3 %patch4 %patch5 @@ -179,20 +170,11 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa # The MIPS ABI is incompatible with .gnu.hash, so don't # use it there %patch11 -%endif %patch12 +%endif %patch14 %patch18 %patch22 -%patch23 -%patch26 -p1 -%patch27 -p1 -%patch28 -p1 -%patch29 -p1 -%patch30 -p1 -%patch31 -p1 -%patch32 -p1 -%patch33 -p1 %patch34 -p1 %patch35 -p1 %if "%{TARGET}" == "avr" diff --git a/cross-ppc64le-binutils.changes b/cross-ppc64le-binutils.changes index 6a12f9b..febad5b 100644 --- a/cross-ppc64le-binutils.changes +++ b/cross-ppc64le-binutils.changes @@ -1,3 +1,60 @@ +------------------------------------------------------------------- +Mon Feb 29 12:49:50 UTC 2016 - rguenther@suse.com + +- Add binutils-2.26-branch.diff, updates to branch head. + * Adds -mrelax-relocations on x86 + * Fixes bso#19698 + +------------------------------------------------------------------- +Mon Feb 1 09:03:02 UTC 2016 - rguenther@suse.com + +- Refresh cross-avr-nesc-as.patch + +------------------------------------------------------------------- +Wed Jan 27 13:12:17 UTC 2016 - rguenther@suse.com + +- Update to binutils 2.26 + * Add --fix-stm32l4xx-629360 to the ARM linker to enable a link-time + workaround for a bug in the bus matrix / memory controller for some of + the STM32 Cortex-M4 based products (STM32L4xx) + * Add a configure option --enable-compressed-debug-sections={all,ld} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Experimental support for linker garbage collection (--gc-sections) + has been enabled for COFF and PE based targets. + * New command line option for ELF targets to compress DWARF debug + sections, --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. + * New command line option, --orphan-handling=[place|warn|error|discard], to + adjust how orphan sections are handled. The default is 'place' which gives + the current behaviour, 'warn' and 'error' issue a warning or error + respectively when orphan sections are found, and 'discard' will discard all + orphan sections. + * Add support for LLVM plugin. + * Add --print-memory-usage option to report memory blocks usage. + * Add --require-defined option, it's like --undefined except the new symbol + must be defined by the end of the link. + * Add a configure option --enable-compressed-debug-sections={all,gas} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + * Add option to objcopy to insert new symbols into a file: + --add-symbol =[
:][,] + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Extend objcopy --compress-debug-sections option to support + --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF + targets. + * Add --update-section option to objcopy. + * Add --output-separator option to strings. +- Includes z13 support, remove 0001-S-390-Add-support-for-IBM-z13.patch, + 0002-S-390-Add-check-for-length-field-operand.patch, + 0003-S-390-Add-more-IBM-z13-instructions.patch, + 0004-S-390-Fixes-for-z13-instructions.patch and + 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch +- Includes fixes in binutils-fix--dynamic-list.patch, + binutils-fix-gold-aarch64.diff, gold-arm64-abi-pagesize.patch + and s390-troo-insn-type.patch +- Refresh s390-pic-dso.diff and binutils-build-as-needed.diff + ------------------------------------------------------------------- Wed Jan 13 08:31:17 UTC 2016 - schwab@suse.de diff --git a/cross-ppc64le-binutils.spec b/cross-ppc64le-binutils.spec index 2fb8bdc..8e7ddb5 100644 --- a/cross-ppc64le-binutils.spec +++ b/cross-ppc64le-binutils.spec @@ -38,7 +38,7 @@ BuildRequires: zlib-devel-static %else BuildRequires: zlib-devel %endif -Version: 2.25.0 +Version: 2.26 Release: 0 # # RUN_TESTS @@ -85,7 +85,7 @@ Source: binutils-%{binutils_version}.tar.bz2 Source1: pre_checkin.sh Source2: README.First-for.SuSE.packagers Source3: baselibs.conf -Patch1: binutils-2.25-branch.diff.gz +Patch: binutils-2.26-branch.diff Patch3: binutils-skip-rpaths.patch Patch4: s390-biarch.diff Patch5: x86-64-biarch.patch @@ -99,15 +99,6 @@ Patch12: s390-pic-dso.diff Patch14: binutils-build-as-needed.diff Patch18: gold-depend-on-opcodes.diff Patch22: binutils-bfd_h.patch -Patch23: binutils-fix-gold-aarch64.diff -Patch26: binutils-fix--dynamic-list.patch -Patch27: 0001-S-390-Add-support-for-IBM-z13.patch -Patch28: 0002-S-390-Add-check-for-length-field-operand.patch -Patch29: 0003-S-390-Add-more-IBM-z13-instructions.patch -Patch30: 0004-S-390-Fixes-for-z13-instructions.patch -Patch31: 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch -Patch32: gold-arm64-abi-pagesize.patch -Patch33: s390-troo-insn-type.patch Patch34: aarch64-common-pagesize.patch Patch35: gold-relocate-tls.patch Patch90: cross-avr-nesc-as.patch @@ -165,8 +156,8 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa %setup -q -n binutils-%{binutils_version} # Patch1 is outside test_vanilla because it's supposed to be the # patch bringing the tarball to the newest upstream version -%patch1 -p1 %if !%{test_vanilla} +%patch -p1 %patch3 %patch4 %patch5 @@ -179,20 +170,11 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa # The MIPS ABI is incompatible with .gnu.hash, so don't # use it there %patch11 -%endif %patch12 +%endif %patch14 %patch18 %patch22 -%patch23 -%patch26 -p1 -%patch27 -p1 -%patch28 -p1 -%patch29 -p1 -%patch30 -p1 -%patch31 -p1 -%patch32 -p1 -%patch33 -p1 %patch34 -p1 %patch35 -p1 %if "%{TARGET}" == "avr" diff --git a/cross-rx-binutils.changes b/cross-rx-binutils.changes index 6a12f9b..febad5b 100644 --- a/cross-rx-binutils.changes +++ b/cross-rx-binutils.changes @@ -1,3 +1,60 @@ +------------------------------------------------------------------- +Mon Feb 29 12:49:50 UTC 2016 - rguenther@suse.com + +- Add binutils-2.26-branch.diff, updates to branch head. + * Adds -mrelax-relocations on x86 + * Fixes bso#19698 + +------------------------------------------------------------------- +Mon Feb 1 09:03:02 UTC 2016 - rguenther@suse.com + +- Refresh cross-avr-nesc-as.patch + +------------------------------------------------------------------- +Wed Jan 27 13:12:17 UTC 2016 - rguenther@suse.com + +- Update to binutils 2.26 + * Add --fix-stm32l4xx-629360 to the ARM linker to enable a link-time + workaround for a bug in the bus matrix / memory controller for some of + the STM32 Cortex-M4 based products (STM32L4xx) + * Add a configure option --enable-compressed-debug-sections={all,ld} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Experimental support for linker garbage collection (--gc-sections) + has been enabled for COFF and PE based targets. + * New command line option for ELF targets to compress DWARF debug + sections, --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. + * New command line option, --orphan-handling=[place|warn|error|discard], to + adjust how orphan sections are handled. The default is 'place' which gives + the current behaviour, 'warn' and 'error' issue a warning or error + respectively when orphan sections are found, and 'discard' will discard all + orphan sections. + * Add support for LLVM plugin. + * Add --print-memory-usage option to report memory blocks usage. + * Add --require-defined option, it's like --undefined except the new symbol + must be defined by the end of the link. + * Add a configure option --enable-compressed-debug-sections={all,gas} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + * Add option to objcopy to insert new symbols into a file: + --add-symbol =[
:][,] + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Extend objcopy --compress-debug-sections option to support + --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF + targets. + * Add --update-section option to objcopy. + * Add --output-separator option to strings. +- Includes z13 support, remove 0001-S-390-Add-support-for-IBM-z13.patch, + 0002-S-390-Add-check-for-length-field-operand.patch, + 0003-S-390-Add-more-IBM-z13-instructions.patch, + 0004-S-390-Fixes-for-z13-instructions.patch and + 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch +- Includes fixes in binutils-fix--dynamic-list.patch, + binutils-fix-gold-aarch64.diff, gold-arm64-abi-pagesize.patch + and s390-troo-insn-type.patch +- Refresh s390-pic-dso.diff and binutils-build-as-needed.diff + ------------------------------------------------------------------- Wed Jan 13 08:31:17 UTC 2016 - schwab@suse.de diff --git a/cross-rx-binutils.spec b/cross-rx-binutils.spec index 9845aa7..b65b27e 100644 --- a/cross-rx-binutils.spec +++ b/cross-rx-binutils.spec @@ -38,7 +38,7 @@ BuildRequires: zlib-devel-static %else BuildRequires: zlib-devel %endif -Version: 2.25.0 +Version: 2.26 Release: 0 # # RUN_TESTS @@ -85,7 +85,7 @@ Source: binutils-%{binutils_version}.tar.bz2 Source1: pre_checkin.sh Source2: README.First-for.SuSE.packagers Source3: baselibs.conf -Patch1: binutils-2.25-branch.diff.gz +Patch: binutils-2.26-branch.diff Patch3: binutils-skip-rpaths.patch Patch4: s390-biarch.diff Patch5: x86-64-biarch.patch @@ -99,15 +99,6 @@ Patch12: s390-pic-dso.diff Patch14: binutils-build-as-needed.diff Patch18: gold-depend-on-opcodes.diff Patch22: binutils-bfd_h.patch -Patch23: binutils-fix-gold-aarch64.diff -Patch26: binutils-fix--dynamic-list.patch -Patch27: 0001-S-390-Add-support-for-IBM-z13.patch -Patch28: 0002-S-390-Add-check-for-length-field-operand.patch -Patch29: 0003-S-390-Add-more-IBM-z13-instructions.patch -Patch30: 0004-S-390-Fixes-for-z13-instructions.patch -Patch31: 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch -Patch32: gold-arm64-abi-pagesize.patch -Patch33: s390-troo-insn-type.patch Patch34: aarch64-common-pagesize.patch Patch35: gold-relocate-tls.patch Patch90: cross-avr-nesc-as.patch @@ -165,8 +156,8 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa %setup -q -n binutils-%{binutils_version} # Patch1 is outside test_vanilla because it's supposed to be the # patch bringing the tarball to the newest upstream version -%patch1 -p1 %if !%{test_vanilla} +%patch -p1 %patch3 %patch4 %patch5 @@ -179,20 +170,11 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa # The MIPS ABI is incompatible with .gnu.hash, so don't # use it there %patch11 -%endif %patch12 +%endif %patch14 %patch18 %patch22 -%patch23 -%patch26 -p1 -%patch27 -p1 -%patch28 -p1 -%patch29 -p1 -%patch30 -p1 -%patch31 -p1 -%patch32 -p1 -%patch33 -p1 %patch34 -p1 %patch35 -p1 %if "%{TARGET}" == "avr" diff --git a/cross-s390-binutils.changes b/cross-s390-binutils.changes index 6a12f9b..febad5b 100644 --- a/cross-s390-binutils.changes +++ b/cross-s390-binutils.changes @@ -1,3 +1,60 @@ +------------------------------------------------------------------- +Mon Feb 29 12:49:50 UTC 2016 - rguenther@suse.com + +- Add binutils-2.26-branch.diff, updates to branch head. + * Adds -mrelax-relocations on x86 + * Fixes bso#19698 + +------------------------------------------------------------------- +Mon Feb 1 09:03:02 UTC 2016 - rguenther@suse.com + +- Refresh cross-avr-nesc-as.patch + +------------------------------------------------------------------- +Wed Jan 27 13:12:17 UTC 2016 - rguenther@suse.com + +- Update to binutils 2.26 + * Add --fix-stm32l4xx-629360 to the ARM linker to enable a link-time + workaround for a bug in the bus matrix / memory controller for some of + the STM32 Cortex-M4 based products (STM32L4xx) + * Add a configure option --enable-compressed-debug-sections={all,ld} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Experimental support for linker garbage collection (--gc-sections) + has been enabled for COFF and PE based targets. + * New command line option for ELF targets to compress DWARF debug + sections, --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. + * New command line option, --orphan-handling=[place|warn|error|discard], to + adjust how orphan sections are handled. The default is 'place' which gives + the current behaviour, 'warn' and 'error' issue a warning or error + respectively when orphan sections are found, and 'discard' will discard all + orphan sections. + * Add support for LLVM plugin. + * Add --print-memory-usage option to report memory blocks usage. + * Add --require-defined option, it's like --undefined except the new symbol + must be defined by the end of the link. + * Add a configure option --enable-compressed-debug-sections={all,gas} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + * Add option to objcopy to insert new symbols into a file: + --add-symbol =[
:][,] + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Extend objcopy --compress-debug-sections option to support + --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF + targets. + * Add --update-section option to objcopy. + * Add --output-separator option to strings. +- Includes z13 support, remove 0001-S-390-Add-support-for-IBM-z13.patch, + 0002-S-390-Add-check-for-length-field-operand.patch, + 0003-S-390-Add-more-IBM-z13-instructions.patch, + 0004-S-390-Fixes-for-z13-instructions.patch and + 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch +- Includes fixes in binutils-fix--dynamic-list.patch, + binutils-fix-gold-aarch64.diff, gold-arm64-abi-pagesize.patch + and s390-troo-insn-type.patch +- Refresh s390-pic-dso.diff and binutils-build-as-needed.diff + ------------------------------------------------------------------- Wed Jan 13 08:31:17 UTC 2016 - schwab@suse.de diff --git a/cross-s390-binutils.spec b/cross-s390-binutils.spec index 0074a71..03d88ac 100644 --- a/cross-s390-binutils.spec +++ b/cross-s390-binutils.spec @@ -38,7 +38,7 @@ BuildRequires: zlib-devel-static %else BuildRequires: zlib-devel %endif -Version: 2.25.0 +Version: 2.26 Release: 0 # # RUN_TESTS @@ -85,7 +85,7 @@ Source: binutils-%{binutils_version}.tar.bz2 Source1: pre_checkin.sh Source2: README.First-for.SuSE.packagers Source3: baselibs.conf -Patch1: binutils-2.25-branch.diff.gz +Patch: binutils-2.26-branch.diff Patch3: binutils-skip-rpaths.patch Patch4: s390-biarch.diff Patch5: x86-64-biarch.patch @@ -99,15 +99,6 @@ Patch12: s390-pic-dso.diff Patch14: binutils-build-as-needed.diff Patch18: gold-depend-on-opcodes.diff Patch22: binutils-bfd_h.patch -Patch23: binutils-fix-gold-aarch64.diff -Patch26: binutils-fix--dynamic-list.patch -Patch27: 0001-S-390-Add-support-for-IBM-z13.patch -Patch28: 0002-S-390-Add-check-for-length-field-operand.patch -Patch29: 0003-S-390-Add-more-IBM-z13-instructions.patch -Patch30: 0004-S-390-Fixes-for-z13-instructions.patch -Patch31: 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch -Patch32: gold-arm64-abi-pagesize.patch -Patch33: s390-troo-insn-type.patch Patch34: aarch64-common-pagesize.patch Patch35: gold-relocate-tls.patch Patch90: cross-avr-nesc-as.patch @@ -165,8 +156,8 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa %setup -q -n binutils-%{binutils_version} # Patch1 is outside test_vanilla because it's supposed to be the # patch bringing the tarball to the newest upstream version -%patch1 -p1 %if !%{test_vanilla} +%patch -p1 %patch3 %patch4 %patch5 @@ -179,20 +170,11 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa # The MIPS ABI is incompatible with .gnu.hash, so don't # use it there %patch11 -%endif %patch12 +%endif %patch14 %patch18 %patch22 -%patch23 -%patch26 -p1 -%patch27 -p1 -%patch28 -p1 -%patch29 -p1 -%patch30 -p1 -%patch31 -p1 -%patch32 -p1 -%patch33 -p1 %patch34 -p1 %patch35 -p1 %if "%{TARGET}" == "avr" diff --git a/cross-s390x-binutils.changes b/cross-s390x-binutils.changes index 6a12f9b..febad5b 100644 --- a/cross-s390x-binutils.changes +++ b/cross-s390x-binutils.changes @@ -1,3 +1,60 @@ +------------------------------------------------------------------- +Mon Feb 29 12:49:50 UTC 2016 - rguenther@suse.com + +- Add binutils-2.26-branch.diff, updates to branch head. + * Adds -mrelax-relocations on x86 + * Fixes bso#19698 + +------------------------------------------------------------------- +Mon Feb 1 09:03:02 UTC 2016 - rguenther@suse.com + +- Refresh cross-avr-nesc-as.patch + +------------------------------------------------------------------- +Wed Jan 27 13:12:17 UTC 2016 - rguenther@suse.com + +- Update to binutils 2.26 + * Add --fix-stm32l4xx-629360 to the ARM linker to enable a link-time + workaround for a bug in the bus matrix / memory controller for some of + the STM32 Cortex-M4 based products (STM32L4xx) + * Add a configure option --enable-compressed-debug-sections={all,ld} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Experimental support for linker garbage collection (--gc-sections) + has been enabled for COFF and PE based targets. + * New command line option for ELF targets to compress DWARF debug + sections, --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. + * New command line option, --orphan-handling=[place|warn|error|discard], to + adjust how orphan sections are handled. The default is 'place' which gives + the current behaviour, 'warn' and 'error' issue a warning or error + respectively when orphan sections are found, and 'discard' will discard all + orphan sections. + * Add support for LLVM plugin. + * Add --print-memory-usage option to report memory blocks usage. + * Add --require-defined option, it's like --undefined except the new symbol + must be defined by the end of the link. + * Add a configure option --enable-compressed-debug-sections={all,gas} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + * Add option to objcopy to insert new symbols into a file: + --add-symbol =[
:][,] + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Extend objcopy --compress-debug-sections option to support + --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF + targets. + * Add --update-section option to objcopy. + * Add --output-separator option to strings. +- Includes z13 support, remove 0001-S-390-Add-support-for-IBM-z13.patch, + 0002-S-390-Add-check-for-length-field-operand.patch, + 0003-S-390-Add-more-IBM-z13-instructions.patch, + 0004-S-390-Fixes-for-z13-instructions.patch and + 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch +- Includes fixes in binutils-fix--dynamic-list.patch, + binutils-fix-gold-aarch64.diff, gold-arm64-abi-pagesize.patch + and s390-troo-insn-type.patch +- Refresh s390-pic-dso.diff and binutils-build-as-needed.diff + ------------------------------------------------------------------- Wed Jan 13 08:31:17 UTC 2016 - schwab@suse.de diff --git a/cross-s390x-binutils.spec b/cross-s390x-binutils.spec index 9e0e5d6..8f41fbf 100644 --- a/cross-s390x-binutils.spec +++ b/cross-s390x-binutils.spec @@ -38,7 +38,7 @@ BuildRequires: zlib-devel-static %else BuildRequires: zlib-devel %endif -Version: 2.25.0 +Version: 2.26 Release: 0 # # RUN_TESTS @@ -85,7 +85,7 @@ Source: binutils-%{binutils_version}.tar.bz2 Source1: pre_checkin.sh Source2: README.First-for.SuSE.packagers Source3: baselibs.conf -Patch1: binutils-2.25-branch.diff.gz +Patch: binutils-2.26-branch.diff Patch3: binutils-skip-rpaths.patch Patch4: s390-biarch.diff Patch5: x86-64-biarch.patch @@ -99,15 +99,6 @@ Patch12: s390-pic-dso.diff Patch14: binutils-build-as-needed.diff Patch18: gold-depend-on-opcodes.diff Patch22: binutils-bfd_h.patch -Patch23: binutils-fix-gold-aarch64.diff -Patch26: binutils-fix--dynamic-list.patch -Patch27: 0001-S-390-Add-support-for-IBM-z13.patch -Patch28: 0002-S-390-Add-check-for-length-field-operand.patch -Patch29: 0003-S-390-Add-more-IBM-z13-instructions.patch -Patch30: 0004-S-390-Fixes-for-z13-instructions.patch -Patch31: 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch -Patch32: gold-arm64-abi-pagesize.patch -Patch33: s390-troo-insn-type.patch Patch34: aarch64-common-pagesize.patch Patch35: gold-relocate-tls.patch Patch90: cross-avr-nesc-as.patch @@ -165,8 +156,8 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa %setup -q -n binutils-%{binutils_version} # Patch1 is outside test_vanilla because it's supposed to be the # patch bringing the tarball to the newest upstream version -%patch1 -p1 %if !%{test_vanilla} +%patch -p1 %patch3 %patch4 %patch5 @@ -179,20 +170,11 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa # The MIPS ABI is incompatible with .gnu.hash, so don't # use it there %patch11 -%endif %patch12 +%endif %patch14 %patch18 %patch22 -%patch23 -%patch26 -p1 -%patch27 -p1 -%patch28 -p1 -%patch29 -p1 -%patch30 -p1 -%patch31 -p1 -%patch32 -p1 -%patch33 -p1 %patch34 -p1 %patch35 -p1 %if "%{TARGET}" == "avr" diff --git a/cross-sparc-binutils.changes b/cross-sparc-binutils.changes index 6a12f9b..febad5b 100644 --- a/cross-sparc-binutils.changes +++ b/cross-sparc-binutils.changes @@ -1,3 +1,60 @@ +------------------------------------------------------------------- +Mon Feb 29 12:49:50 UTC 2016 - rguenther@suse.com + +- Add binutils-2.26-branch.diff, updates to branch head. + * Adds -mrelax-relocations on x86 + * Fixes bso#19698 + +------------------------------------------------------------------- +Mon Feb 1 09:03:02 UTC 2016 - rguenther@suse.com + +- Refresh cross-avr-nesc-as.patch + +------------------------------------------------------------------- +Wed Jan 27 13:12:17 UTC 2016 - rguenther@suse.com + +- Update to binutils 2.26 + * Add --fix-stm32l4xx-629360 to the ARM linker to enable a link-time + workaround for a bug in the bus matrix / memory controller for some of + the STM32 Cortex-M4 based products (STM32L4xx) + * Add a configure option --enable-compressed-debug-sections={all,ld} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Experimental support for linker garbage collection (--gc-sections) + has been enabled for COFF and PE based targets. + * New command line option for ELF targets to compress DWARF debug + sections, --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. + * New command line option, --orphan-handling=[place|warn|error|discard], to + adjust how orphan sections are handled. The default is 'place' which gives + the current behaviour, 'warn' and 'error' issue a warning or error + respectively when orphan sections are found, and 'discard' will discard all + orphan sections. + * Add support for LLVM plugin. + * Add --print-memory-usage option to report memory blocks usage. + * Add --require-defined option, it's like --undefined except the new symbol + must be defined by the end of the link. + * Add a configure option --enable-compressed-debug-sections={all,gas} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + * Add option to objcopy to insert new symbols into a file: + --add-symbol =[
:][,] + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Extend objcopy --compress-debug-sections option to support + --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF + targets. + * Add --update-section option to objcopy. + * Add --output-separator option to strings. +- Includes z13 support, remove 0001-S-390-Add-support-for-IBM-z13.patch, + 0002-S-390-Add-check-for-length-field-operand.patch, + 0003-S-390-Add-more-IBM-z13-instructions.patch, + 0004-S-390-Fixes-for-z13-instructions.patch and + 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch +- Includes fixes in binutils-fix--dynamic-list.patch, + binutils-fix-gold-aarch64.diff, gold-arm64-abi-pagesize.patch + and s390-troo-insn-type.patch +- Refresh s390-pic-dso.diff and binutils-build-as-needed.diff + ------------------------------------------------------------------- Wed Jan 13 08:31:17 UTC 2016 - schwab@suse.de diff --git a/cross-sparc-binutils.spec b/cross-sparc-binutils.spec index 81acdcc..9405159 100644 --- a/cross-sparc-binutils.spec +++ b/cross-sparc-binutils.spec @@ -38,7 +38,7 @@ BuildRequires: zlib-devel-static %else BuildRequires: zlib-devel %endif -Version: 2.25.0 +Version: 2.26 Release: 0 # # RUN_TESTS @@ -85,7 +85,7 @@ Source: binutils-%{binutils_version}.tar.bz2 Source1: pre_checkin.sh Source2: README.First-for.SuSE.packagers Source3: baselibs.conf -Patch1: binutils-2.25-branch.diff.gz +Patch: binutils-2.26-branch.diff Patch3: binutils-skip-rpaths.patch Patch4: s390-biarch.diff Patch5: x86-64-biarch.patch @@ -99,15 +99,6 @@ Patch12: s390-pic-dso.diff Patch14: binutils-build-as-needed.diff Patch18: gold-depend-on-opcodes.diff Patch22: binutils-bfd_h.patch -Patch23: binutils-fix-gold-aarch64.diff -Patch26: binutils-fix--dynamic-list.patch -Patch27: 0001-S-390-Add-support-for-IBM-z13.patch -Patch28: 0002-S-390-Add-check-for-length-field-operand.patch -Patch29: 0003-S-390-Add-more-IBM-z13-instructions.patch -Patch30: 0004-S-390-Fixes-for-z13-instructions.patch -Patch31: 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch -Patch32: gold-arm64-abi-pagesize.patch -Patch33: s390-troo-insn-type.patch Patch34: aarch64-common-pagesize.patch Patch35: gold-relocate-tls.patch Patch90: cross-avr-nesc-as.patch @@ -165,8 +156,8 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa %setup -q -n binutils-%{binutils_version} # Patch1 is outside test_vanilla because it's supposed to be the # patch bringing the tarball to the newest upstream version -%patch1 -p1 %if !%{test_vanilla} +%patch -p1 %patch3 %patch4 %patch5 @@ -179,20 +170,11 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa # The MIPS ABI is incompatible with .gnu.hash, so don't # use it there %patch11 -%endif %patch12 +%endif %patch14 %patch18 %patch22 -%patch23 -%patch26 -p1 -%patch27 -p1 -%patch28 -p1 -%patch29 -p1 -%patch30 -p1 -%patch31 -p1 -%patch32 -p1 -%patch33 -p1 %patch34 -p1 %patch35 -p1 %if "%{TARGET}" == "avr" diff --git a/cross-sparc64-binutils.changes b/cross-sparc64-binutils.changes index 6a12f9b..febad5b 100644 --- a/cross-sparc64-binutils.changes +++ b/cross-sparc64-binutils.changes @@ -1,3 +1,60 @@ +------------------------------------------------------------------- +Mon Feb 29 12:49:50 UTC 2016 - rguenther@suse.com + +- Add binutils-2.26-branch.diff, updates to branch head. + * Adds -mrelax-relocations on x86 + * Fixes bso#19698 + +------------------------------------------------------------------- +Mon Feb 1 09:03:02 UTC 2016 - rguenther@suse.com + +- Refresh cross-avr-nesc-as.patch + +------------------------------------------------------------------- +Wed Jan 27 13:12:17 UTC 2016 - rguenther@suse.com + +- Update to binutils 2.26 + * Add --fix-stm32l4xx-629360 to the ARM linker to enable a link-time + workaround for a bug in the bus matrix / memory controller for some of + the STM32 Cortex-M4 based products (STM32L4xx) + * Add a configure option --enable-compressed-debug-sections={all,ld} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Experimental support for linker garbage collection (--gc-sections) + has been enabled for COFF and PE based targets. + * New command line option for ELF targets to compress DWARF debug + sections, --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. + * New command line option, --orphan-handling=[place|warn|error|discard], to + adjust how orphan sections are handled. The default is 'place' which gives + the current behaviour, 'warn' and 'error' issue a warning or error + respectively when orphan sections are found, and 'discard' will discard all + orphan sections. + * Add support for LLVM plugin. + * Add --print-memory-usage option to report memory blocks usage. + * Add --require-defined option, it's like --undefined except the new symbol + must be defined by the end of the link. + * Add a configure option --enable-compressed-debug-sections={all,gas} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + * Add option to objcopy to insert new symbols into a file: + --add-symbol =[
:][,] + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Extend objcopy --compress-debug-sections option to support + --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF + targets. + * Add --update-section option to objcopy. + * Add --output-separator option to strings. +- Includes z13 support, remove 0001-S-390-Add-support-for-IBM-z13.patch, + 0002-S-390-Add-check-for-length-field-operand.patch, + 0003-S-390-Add-more-IBM-z13-instructions.patch, + 0004-S-390-Fixes-for-z13-instructions.patch and + 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch +- Includes fixes in binutils-fix--dynamic-list.patch, + binutils-fix-gold-aarch64.diff, gold-arm64-abi-pagesize.patch + and s390-troo-insn-type.patch +- Refresh s390-pic-dso.diff and binutils-build-as-needed.diff + ------------------------------------------------------------------- Wed Jan 13 08:31:17 UTC 2016 - schwab@suse.de diff --git a/cross-sparc64-binutils.spec b/cross-sparc64-binutils.spec index 830e203..45f85ce 100644 --- a/cross-sparc64-binutils.spec +++ b/cross-sparc64-binutils.spec @@ -38,7 +38,7 @@ BuildRequires: zlib-devel-static %else BuildRequires: zlib-devel %endif -Version: 2.25.0 +Version: 2.26 Release: 0 # # RUN_TESTS @@ -85,7 +85,7 @@ Source: binutils-%{binutils_version}.tar.bz2 Source1: pre_checkin.sh Source2: README.First-for.SuSE.packagers Source3: baselibs.conf -Patch1: binutils-2.25-branch.diff.gz +Patch: binutils-2.26-branch.diff Patch3: binutils-skip-rpaths.patch Patch4: s390-biarch.diff Patch5: x86-64-biarch.patch @@ -99,15 +99,6 @@ Patch12: s390-pic-dso.diff Patch14: binutils-build-as-needed.diff Patch18: gold-depend-on-opcodes.diff Patch22: binutils-bfd_h.patch -Patch23: binutils-fix-gold-aarch64.diff -Patch26: binutils-fix--dynamic-list.patch -Patch27: 0001-S-390-Add-support-for-IBM-z13.patch -Patch28: 0002-S-390-Add-check-for-length-field-operand.patch -Patch29: 0003-S-390-Add-more-IBM-z13-instructions.patch -Patch30: 0004-S-390-Fixes-for-z13-instructions.patch -Patch31: 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch -Patch32: gold-arm64-abi-pagesize.patch -Patch33: s390-troo-insn-type.patch Patch34: aarch64-common-pagesize.patch Patch35: gold-relocate-tls.patch Patch90: cross-avr-nesc-as.patch @@ -165,8 +156,8 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa %setup -q -n binutils-%{binutils_version} # Patch1 is outside test_vanilla because it's supposed to be the # patch bringing the tarball to the newest upstream version -%patch1 -p1 %if !%{test_vanilla} +%patch -p1 %patch3 %patch4 %patch5 @@ -179,20 +170,11 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa # The MIPS ABI is incompatible with .gnu.hash, so don't # use it there %patch11 -%endif %patch12 +%endif %patch14 %patch18 %patch22 -%patch23 -%patch26 -p1 -%patch27 -p1 -%patch28 -p1 -%patch29 -p1 -%patch30 -p1 -%patch31 -p1 -%patch32 -p1 -%patch33 -p1 %patch34 -p1 %patch35 -p1 %if "%{TARGET}" == "avr" diff --git a/cross-spu-binutils.changes b/cross-spu-binutils.changes index 6a12f9b..febad5b 100644 --- a/cross-spu-binutils.changes +++ b/cross-spu-binutils.changes @@ -1,3 +1,60 @@ +------------------------------------------------------------------- +Mon Feb 29 12:49:50 UTC 2016 - rguenther@suse.com + +- Add binutils-2.26-branch.diff, updates to branch head. + * Adds -mrelax-relocations on x86 + * Fixes bso#19698 + +------------------------------------------------------------------- +Mon Feb 1 09:03:02 UTC 2016 - rguenther@suse.com + +- Refresh cross-avr-nesc-as.patch + +------------------------------------------------------------------- +Wed Jan 27 13:12:17 UTC 2016 - rguenther@suse.com + +- Update to binutils 2.26 + * Add --fix-stm32l4xx-629360 to the ARM linker to enable a link-time + workaround for a bug in the bus matrix / memory controller for some of + the STM32 Cortex-M4 based products (STM32L4xx) + * Add a configure option --enable-compressed-debug-sections={all,ld} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Experimental support for linker garbage collection (--gc-sections) + has been enabled for COFF and PE based targets. + * New command line option for ELF targets to compress DWARF debug + sections, --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. + * New command line option, --orphan-handling=[place|warn|error|discard], to + adjust how orphan sections are handled. The default is 'place' which gives + the current behaviour, 'warn' and 'error' issue a warning or error + respectively when orphan sections are found, and 'discard' will discard all + orphan sections. + * Add support for LLVM plugin. + * Add --print-memory-usage option to report memory blocks usage. + * Add --require-defined option, it's like --undefined except the new symbol + must be defined by the end of the link. + * Add a configure option --enable-compressed-debug-sections={all,gas} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + * Add option to objcopy to insert new symbols into a file: + --add-symbol =[
:][,] + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Extend objcopy --compress-debug-sections option to support + --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF + targets. + * Add --update-section option to objcopy. + * Add --output-separator option to strings. +- Includes z13 support, remove 0001-S-390-Add-support-for-IBM-z13.patch, + 0002-S-390-Add-check-for-length-field-operand.patch, + 0003-S-390-Add-more-IBM-z13-instructions.patch, + 0004-S-390-Fixes-for-z13-instructions.patch and + 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch +- Includes fixes in binutils-fix--dynamic-list.patch, + binutils-fix-gold-aarch64.diff, gold-arm64-abi-pagesize.patch + and s390-troo-insn-type.patch +- Refresh s390-pic-dso.diff and binutils-build-as-needed.diff + ------------------------------------------------------------------- Wed Jan 13 08:31:17 UTC 2016 - schwab@suse.de diff --git a/cross-spu-binutils.spec b/cross-spu-binutils.spec index 5db33cc..33dcf12 100644 --- a/cross-spu-binutils.spec +++ b/cross-spu-binutils.spec @@ -38,7 +38,7 @@ BuildRequires: zlib-devel-static %else BuildRequires: zlib-devel %endif -Version: 2.25.0 +Version: 2.26 Release: 0 # # RUN_TESTS @@ -85,7 +85,7 @@ Source: binutils-%{binutils_version}.tar.bz2 Source1: pre_checkin.sh Source2: README.First-for.SuSE.packagers Source3: baselibs.conf -Patch1: binutils-2.25-branch.diff.gz +Patch: binutils-2.26-branch.diff Patch3: binutils-skip-rpaths.patch Patch4: s390-biarch.diff Patch5: x86-64-biarch.patch @@ -99,15 +99,6 @@ Patch12: s390-pic-dso.diff Patch14: binutils-build-as-needed.diff Patch18: gold-depend-on-opcodes.diff Patch22: binutils-bfd_h.patch -Patch23: binutils-fix-gold-aarch64.diff -Patch26: binutils-fix--dynamic-list.patch -Patch27: 0001-S-390-Add-support-for-IBM-z13.patch -Patch28: 0002-S-390-Add-check-for-length-field-operand.patch -Patch29: 0003-S-390-Add-more-IBM-z13-instructions.patch -Patch30: 0004-S-390-Fixes-for-z13-instructions.patch -Patch31: 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch -Patch32: gold-arm64-abi-pagesize.patch -Patch33: s390-troo-insn-type.patch Patch34: aarch64-common-pagesize.patch Patch35: gold-relocate-tls.patch Patch90: cross-avr-nesc-as.patch @@ -165,8 +156,8 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa %setup -q -n binutils-%{binutils_version} # Patch1 is outside test_vanilla because it's supposed to be the # patch bringing the tarball to the newest upstream version -%patch1 -p1 %if !%{test_vanilla} +%patch -p1 %patch3 %patch4 %patch5 @@ -179,20 +170,11 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa # The MIPS ABI is incompatible with .gnu.hash, so don't # use it there %patch11 -%endif %patch12 +%endif %patch14 %patch18 %patch22 -%patch23 -%patch26 -p1 -%patch27 -p1 -%patch28 -p1 -%patch29 -p1 -%patch30 -p1 -%patch31 -p1 -%patch32 -p1 -%patch33 -p1 %patch34 -p1 %patch35 -p1 %if "%{TARGET}" == "avr" diff --git a/cross-x86_64-binutils.changes b/cross-x86_64-binutils.changes index 6a12f9b..febad5b 100644 --- a/cross-x86_64-binutils.changes +++ b/cross-x86_64-binutils.changes @@ -1,3 +1,60 @@ +------------------------------------------------------------------- +Mon Feb 29 12:49:50 UTC 2016 - rguenther@suse.com + +- Add binutils-2.26-branch.diff, updates to branch head. + * Adds -mrelax-relocations on x86 + * Fixes bso#19698 + +------------------------------------------------------------------- +Mon Feb 1 09:03:02 UTC 2016 - rguenther@suse.com + +- Refresh cross-avr-nesc-as.patch + +------------------------------------------------------------------- +Wed Jan 27 13:12:17 UTC 2016 - rguenther@suse.com + +- Update to binutils 2.26 + * Add --fix-stm32l4xx-629360 to the ARM linker to enable a link-time + workaround for a bug in the bus matrix / memory controller for some of + the STM32 Cortex-M4 based products (STM32L4xx) + * Add a configure option --enable-compressed-debug-sections={all,ld} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Experimental support for linker garbage collection (--gc-sections) + has been enabled for COFF and PE based targets. + * New command line option for ELF targets to compress DWARF debug + sections, --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. + * New command line option, --orphan-handling=[place|warn|error|discard], to + adjust how orphan sections are handled. The default is 'place' which gives + the current behaviour, 'warn' and 'error' issue a warning or error + respectively when orphan sections are found, and 'discard' will discard all + orphan sections. + * Add support for LLVM plugin. + * Add --print-memory-usage option to report memory blocks usage. + * Add --require-defined option, it's like --undefined except the new symbol + must be defined by the end of the link. + * Add a configure option --enable-compressed-debug-sections={all,gas} to + decide whether DWARF debug sections should be compressed by default. + * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + * Add option to objcopy to insert new symbols into a file: + --add-symbol =[
:][,] + * Add support for the ARC EM/HS, and ARC600/700 architectures. + * Extend objcopy --compress-debug-sections option to support + --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF + targets. + * Add --update-section option to objcopy. + * Add --output-separator option to strings. +- Includes z13 support, remove 0001-S-390-Add-support-for-IBM-z13.patch, + 0002-S-390-Add-check-for-length-field-operand.patch, + 0003-S-390-Add-more-IBM-z13-instructions.patch, + 0004-S-390-Fixes-for-z13-instructions.patch and + 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch +- Includes fixes in binutils-fix--dynamic-list.patch, + binutils-fix-gold-aarch64.diff, gold-arm64-abi-pagesize.patch + and s390-troo-insn-type.patch +- Refresh s390-pic-dso.diff and binutils-build-as-needed.diff + ------------------------------------------------------------------- Wed Jan 13 08:31:17 UTC 2016 - schwab@suse.de diff --git a/cross-x86_64-binutils.spec b/cross-x86_64-binutils.spec index 7d363e9..bed157f 100644 --- a/cross-x86_64-binutils.spec +++ b/cross-x86_64-binutils.spec @@ -38,7 +38,7 @@ BuildRequires: zlib-devel-static %else BuildRequires: zlib-devel %endif -Version: 2.25.0 +Version: 2.26 Release: 0 # # RUN_TESTS @@ -85,7 +85,7 @@ Source: binutils-%{binutils_version}.tar.bz2 Source1: pre_checkin.sh Source2: README.First-for.SuSE.packagers Source3: baselibs.conf -Patch1: binutils-2.25-branch.diff.gz +Patch: binutils-2.26-branch.diff Patch3: binutils-skip-rpaths.patch Patch4: s390-biarch.diff Patch5: x86-64-biarch.patch @@ -99,15 +99,6 @@ Patch12: s390-pic-dso.diff Patch14: binutils-build-as-needed.diff Patch18: gold-depend-on-opcodes.diff Patch22: binutils-bfd_h.patch -Patch23: binutils-fix-gold-aarch64.diff -Patch26: binutils-fix--dynamic-list.patch -Patch27: 0001-S-390-Add-support-for-IBM-z13.patch -Patch28: 0002-S-390-Add-check-for-length-field-operand.patch -Patch29: 0003-S-390-Add-more-IBM-z13-instructions.patch -Patch30: 0004-S-390-Fixes-for-z13-instructions.patch -Patch31: 0005-S-390-z13-use-GNU-attribute-to-indicate-vector-ABI.patch -Patch32: gold-arm64-abi-pagesize.patch -Patch33: s390-troo-insn-type.patch Patch34: aarch64-common-pagesize.patch Patch35: gold-relocate-tls.patch Patch90: cross-avr-nesc-as.patch @@ -165,8 +156,8 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa %setup -q -n binutils-%{binutils_version} # Patch1 is outside test_vanilla because it's supposed to be the # patch bringing the tarball to the newest upstream version -%patch1 -p1 %if !%{test_vanilla} +%patch -p1 %patch3 %patch4 %patch5 @@ -179,20 +170,11 @@ echo "make check will return with %{make_check_handling} in case of testsuite fa # The MIPS ABI is incompatible with .gnu.hash, so don't # use it there %patch11 -%endif %patch12 +%endif %patch14 %patch18 %patch22 -%patch23 -%patch26 -p1 -%patch27 -p1 -%patch28 -p1 -%patch29 -p1 -%patch30 -p1 -%patch31 -p1 -%patch32 -p1 -%patch33 -p1 %patch34 -p1 %patch35 -p1 %if "%{TARGET}" == "avr" diff --git a/gold-arm64-abi-pagesize.patch b/gold-arm64-abi-pagesize.patch deleted file mode 100644 index 043c7fa..0000000 --- a/gold-arm64-abi-pagesize.patch +++ /dev/null @@ -1,40 +0,0 @@ -Index: binutils-2.25.0/gold/aarch64.cc -=================================================================== ---- binutils-2.25.0.orig/gold/aarch64.cc -+++ binutils-2.25.0/gold/aarch64.cc -@@ -790,7 +790,7 @@ const Target::Target_info Target_aarch64 - '\0', // wrap_char - "/lib/ld.so.1", // program interpreter - 0x400000, // default_text_segment_address -- 0x1000, // abi_pagesize (overridable by -z max-page-size) -+ 0x10000, // abi_pagesize (overridable by -z max-page-size) - 0x1000, // common_pagesize (overridable by -z common-page-size) - false, // isolate_execinstr - 0, // rosegment_gap -@@ -817,7 +817,7 @@ const Target::Target_info Target_aarch64 - '\0', // wrap_char - "/lib/ld.so.1", // program interpreter - 0x400000, // default_text_segment_address -- 0x1000, // abi_pagesize (overridable by -z max-page-size) -+ 0x10000, // abi_pagesize (overridable by -z max-page-size) - 0x1000, // common_pagesize (overridable by -z common-page-size) - false, // isolate_execinstr - 0, // rosegment_gap -@@ -844,7 +844,7 @@ const Target::Target_info Target_aarch64 - '\0', // wrap_char - "/lib/ld.so.1", // program interpreter - 0x400000, // default_text_segment_address -- 0x1000, // abi_pagesize (overridable by -z max-page-size) -+ 0x10000, // abi_pagesize (overridable by -z max-page-size) - 0x1000, // common_pagesize (overridable by -z common-page-size) - false, // isolate_execinstr - 0, // rosegment_gap -@@ -871,7 +871,7 @@ const Target::Target_info Target_aarch64 - '\0', // wrap_char - "/lib/ld.so.1", // program interpreter - 0x400000, // default_text_segment_address -- 0x1000, // abi_pagesize (overridable by -z max-page-size) -+ 0x10000, // abi_pagesize (overridable by -z max-page-size) - 0x1000, // common_pagesize (overridable by -z common-page-size) - false, // isolate_execinstr - 0, // rosegment_gap diff --git a/s390-pic-dso.diff b/s390-pic-dso.diff index 78b0304..1e84414 100644 --- a/s390-pic-dso.diff +++ b/s390-pic-dso.diff @@ -1,24 +1,15 @@ Index: bfd/elf32-s390.c =================================================================== ---- bfd/elf32-s390.c.orig 2013-09-20 16:04:50.000000000 +0200 -+++ bfd/elf32-s390.c 2013-09-20 16:10:02.000000000 +0200 -@@ -2707,15 +2707,36 @@ elf_s390_relocate_section (bfd *output_b - unresolved_reloc = FALSE; - break; - -- case R_390_8: -- case R_390_16: -- case R_390_32: - case R_390_PC16: - case R_390_PC12DBL: - case R_390_PC16DBL: +--- bfd/elf32-s390.c.orig 2016-01-25 09:51:06.000000000 +0100 ++++ bfd/elf32-s390.c 2016-01-27 15:24:52.947115619 +0100 +@@ -2782,6 +2782,27 @@ elf_s390_relocate_section (bfd *output_b case R_390_PC24DBL: case R_390_PC32DBL: case R_390_PC32: + /* This is strictly required only for PC32DBL, which + is not handled by ld.so, but let's be helpful to the user also + in the other cases. */ -+ if (info->shared ++ if (bfd_link_pic (info) + && !SYMBOL_REFERENCES_LOCAL (info, h) + && (input_section->flags & SEC_ALLOC) != 0 + && (input_section->flags & SEC_READONLY) != 0 @@ -28,17 +19,14 @@ Index: bfd/elf32-s390.c + || ELF_ST_VISIBILITY (h->other) != STV_PROTECTED)) + { + (*_bfd_error_handler) -+ (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"), ++ (_("%B: relocation %s against `%s' can not be used when " ++ "making a shared object; recompile with -fPIC"), + input_bfd, elf_howto_table[r_type].name, + h->root.root.string); + bfd_set_error (bfd_error_bad_value); + return FALSE; + } -+ /* Fall through. */ + -+ case R_390_8: -+ case R_390_16: -+ case R_390_32: if (h != NULL && s390_is_ifunc_symbol_p (h) - && h->def_regular) + && h->def_regular diff --git a/s390-troo-insn-type.patch b/s390-troo-insn-type.patch deleted file mode 100644 index d180cce..0000000 --- a/s390-troo-insn-type.patch +++ /dev/null @@ -1,154 +0,0 @@ -From c46eb7b88a1261bc079bfbe2339060152bdf3527 Mon Sep 17 00:00:00 2001 -From: Andreas Krebbel -Date: Wed, 14 Oct 2015 10:58:41 +0200 -Subject: [PATCH] S/390: Fix instruction type of troo, trot, trto, and trtt. - -opcodes/ChangeLog: - -2015-10-14 Andreas Krebbel - - * s390-opc.c: Fix comment. - * s390-opc.txt: Change instruction type for troo, trot, trto, and - trtt to RRF_U0RER since the second parameter does not need to be a - register pair. - -gas/testsuite/ChangeLog: - -2015-10-14 Andreas Krebbel - - * gas/s390/esa-g5.d: Use odd GPR for the second operand. - * gas/s390/esa-g5.s: Likewise. - * gas/s390/esa-z9-109.d: Likewise. - * gas/s390/esa-z9-109.s: Likewise. ---- - gas/testsuite/gas/s390/esa-g5.d | 8 ++++---- - gas/testsuite/gas/s390/esa-g5.s | 8 ++++---- - gas/testsuite/gas/s390/esa-z9-109.d | 16 ++++++++-------- - gas/testsuite/gas/s390/esa-z9-109.s | 16 ++++++++-------- - opcodes/s390-opc.c | 2 +- - opcodes/s390-opc.txt | 8 ++++---- - 6 files changed, 29 insertions(+), 29 deletions(-) - -Index: binutils-2.25.0/gas/testsuite/gas/s390/esa-g5.d -=================================================================== ---- binutils-2.25.0.orig/gas/testsuite/gas/s390/esa-g5.d -+++ binutils-2.25.0/gas/testsuite/gas/s390/esa-g5.d -@@ -464,11 +464,11 @@ Disassembly of section .text: - .*: 01 ff [ ]*trap2 - .*: b2 ff 5f ff [ ]*trap4 4095\(%r5\) - .*: b2 a5 00 69 [ ]*tre %r6,%r9 --.*: b9 93 00 68 [ ]*troo %r6,%r8 --.*: b9 92 00 68 [ ]*trot %r6,%r8 -+.*: b9 93 00 69 [ ]*troo %r6,%r9 -+.*: b9 92 00 69 [ ]*trot %r6,%r9 - .*: dd ff 5f ff af ff [ ]*trt 4095\(256,%r5\),4095\(%r10\) --.*: b9 91 00 68 [ ]*trto %r6,%r8 --.*: b9 90 00 68 [ ]*trtt %r6,%r8 -+.*: b9 91 00 69 [ ]*trto %r6,%r9 -+.*: b9 90 00 69 [ ]*trtt %r6,%r9 - .*: 93 00 5f ff [ ]*ts 4095\(%r5\) - .*: b2 35 5f ff [ ]*tsch 4095\(%r5\) - .*: f3 58 5f ff af ff [ ]*unpk 4095\(6,%r5\),4095\(9,%r10\) -Index: binutils-2.25.0/gas/testsuite/gas/s390/esa-g5.s -=================================================================== ---- binutils-2.25.0.orig/gas/testsuite/gas/s390/esa-g5.s -+++ binutils-2.25.0/gas/testsuite/gas/s390/esa-g5.s -@@ -458,11 +458,11 @@ foo: - trap2 - trap4 4095(%r5) - tre %r6,%r9 -- troo %r6,%r8 -- trot %r6,%r8 -+ troo %r6,%r9 -+ trot %r6,%r9 - trt 4095(256,%r5),4095(%r10) -- trto %r6,%r8 -- trtt %r6,%r8 -+ trto %r6,%r9 -+ trtt %r6,%r9 - ts 4095(%r5) - tsch 4095(%r5) - unpk 4095(6,%r5),4095(9,%r10) -Index: binutils-2.25.0/gas/testsuite/gas/s390/esa-z9-109.d -=================================================================== ---- binutils-2.25.0.orig/gas/testsuite/gas/s390/esa-z9-109.d -+++ binutils-2.25.0/gas/testsuite/gas/s390/esa-z9-109.d -@@ -6,12 +6,12 @@ - Disassembly of section .text: - - .* : --.*: b9 93 f0 68 [ ]*troo %r6,%r8,15 --.*: b9 93 00 68 [ ]*troo %r6,%r8 --.*: b9 92 f0 68 [ ]*trot %r6,%r8,15 --.*: b9 92 00 68 [ ]*trot %r6,%r8 --.*: b9 91 f0 68 [ ]*trto %r6,%r8,15 --.*: b9 91 00 68 [ ]*trto %r6,%r8 --.*: b9 90 f0 68 [ ]*trtt %r6,%r8,15 --.*: b9 90 00 68 [ ]*trtt %r6,%r8 -+.*: b9 93 f0 69 [ ]*troo %r6,%r9,15 -+.*: b9 93 00 69 [ ]*troo %r6,%r9 -+.*: b9 92 f0 69 [ ]*trot %r6,%r9,15 -+.*: b9 92 00 69 [ ]*trot %r6,%r9 -+.*: b9 91 f0 69 [ ]*trto %r6,%r9,15 -+.*: b9 91 00 69 [ ]*trto %r6,%r9 -+.*: b9 90 f0 69 [ ]*trtt %r6,%r9,15 -+.*: b9 90 00 69 [ ]*trtt %r6,%r9 - .*: b2 2b 00 69 [ ]*sske %r6,%r9 -Index: binutils-2.25.0/gas/testsuite/gas/s390/esa-z9-109.s -=================================================================== ---- binutils-2.25.0.orig/gas/testsuite/gas/s390/esa-z9-109.s -+++ binutils-2.25.0/gas/testsuite/gas/s390/esa-z9-109.s -@@ -1,13 +1,13 @@ - .text - foo: -- troo %r6,%r8,15 -- troo %r6,%r8 -- trot %r6,%r8,15 -- trot %r6,%r8 -- trto %r6,%r8,15 -- trto %r6,%r8 -- trtt %r6,%r8,15 -- trtt %r6,%r8 -+ troo %r6,%r9,15 -+ troo %r6,%r9 -+ trot %r6,%r9,15 -+ trot %r6,%r9 -+ trto %r6,%r9,15 -+ trto %r6,%r9 -+ trtt %r6,%r9,15 -+ trtt %r6,%r9 - # z9-109 z/Architecture mode extended sske with an additional parameter - # make sure the old version still works for esa - sske %r6,%r9 -Index: binutils-2.25.0/opcodes/s390-opc.c -=================================================================== ---- binutils-2.25.0.orig/opcodes/s390-opc.c -+++ binutils-2.25.0/opcodes/s390-opc.c -@@ -372,7 +372,7 @@ const struct s390_operand s390_operands[ - #define INSTR_RRF_FEFERU 4, { FE_24,FE_16,R_28,U4_20,0,0 } /* e.g. rrxtr */ - #define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. sske */ - #define INSTR_RRF_U0RER 4, { RE_24,R_28,U4_16,0,0,0 } /* e.g. trte */ --#define INSTR_RRF_U0RERE 4, { RE_24,RE_28,U4_16,0,0,0 } /* e.g. troo */ -+#define INSTR_RRF_U0RERE 4, { RE_24,RE_28,U4_16,0,0,0 } /* e.g. cu24 */ - #define INSTR_RRF_00RR 4, { R_24,R_28,0,0,0,0 } /* e.g. clrtne */ - #define INSTR_RRF_UUFR 4, { F_24,U4_16,R_28,U4_20,0,0 } /* e.g. cdgtra */ - #define INSTR_RRF_UUFER 4, { FE_24,U4_16,R_28,U4_20,0,0 } /* e.g. cxfbra */ -Index: binutils-2.25.0/opcodes/s390-opc.txt -=================================================================== ---- binutils-2.25.0.orig/opcodes/s390-opc.txt -+++ binutils-2.25.0/opcodes/s390-opc.txt -@@ -767,10 +767,10 @@ b9aa lptea RRF_RURR2 "load page-table-en - # z9-109 conditional sske facility, sske instruction entered twice - b22b sske RRF_U0RR "set storage key extended" z9-109 zarch optparm - # z9-109 etf2-enhancement facility, instructions entered twice --b993 troo RRF_U0RERE "translate one to one" z9-109 esa,zarch optparm --b992 trot RRF_U0RERE "translate one to two" z9-109 esa,zarch optparm --b991 trto RRF_U0RERE "translate two to one" z9-109 esa,zarch optparm --b990 trtt RRF_U0RERE "translate two to two" z9-109 esa,zarch optparm -+b993 troo RRF_U0RER "translate one to one" z9-109 esa,zarch optparm -+b992 trot RRF_U0RER "translate one to two" z9-109 esa,zarch optparm -+b991 trto RRF_U0RER "translate two to one" z9-109 esa,zarch optparm -+b990 trtt RRF_U0RER "translate two to two" z9-109 esa,zarch optparm - # z9-109 etf3-enhancement facility, some instructions entered twice - b9b1 cu24 RRF_U0RERE "convert utf-16 to utf-32" z9-109 zarch optparm - b2a6 cu21 RRF_U0RERE "convert utf-16 to utf-8" z9-109 zarch optparm